WO2022047587A1 - Low temperature bonding of microdevice integration into a system substrate - Google Patents

Low temperature bonding of microdevice integration into a system substrate Download PDF

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Publication number
WO2022047587A1
WO2022047587A1 PCT/CA2021/051218 CA2021051218W WO2022047587A1 WO 2022047587 A1 WO2022047587 A1 WO 2022047587A1 CA 2021051218 W CA2021051218 W CA 2021051218W WO 2022047587 A1 WO2022047587 A1 WO 2022047587A1
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WO
WIPO (PCT)
Prior art keywords
microdevice
substrate
pads
electrode
layer
Prior art date
Application number
PCT/CA2021/051218
Other languages
French (fr)
Inventor
Gholamreza Chaji
Ehsanollah FATHI
Hossein Zamani Siboni
Lauren LESERGENT
David Hwang
Pranav GAVIRNENI
Original Assignee
Vuereal Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vuereal Inc. filed Critical Vuereal Inc.
Priority to CN202180050106.0A priority Critical patent/CN116096667A/en
Priority to US18/043,628 priority patent/US20230395560A1/en
Publication of WO2022047587A1 publication Critical patent/WO2022047587A1/en

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    • B81—MICROSTRUCTURAL TECHNOLOGY
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations

Definitions

  • the present disclosure relates to the integration of microdevices into a system substrate as well as integrating vertical microdevices into a substrate.
  • the invention further relates to providing misalignment adjustment in microdevices.
  • the system substrate may comprise micro light emitting diodes (LEDs), Organic LEDs, sensors, solid state devices, integrated circuits, (micro-electro-mechanical systems) MEMS, and/or other electronic components.
  • LEDs micro light emitting diodes
  • Other embodiments are related to patterning and placing of microdevices in respect to the pixel arrays to optimize the microdevice utilizations in selective transfer processes.
  • the receiving substrate may be, but is not limited to, a printed circuit board (PCB), thin film transistor backplane, integrated circuit substrate, or, in one case of optical microdevices such as LEDs, a component of a display, for example a driving circuitry backplane.
  • microdevice donor substrate and receiver substrate can be used in combination with different transfer technology including but not limited to pick and place with different mechanisms (e.g. electrostatic transfer head, elastomer transfer head), or direct transfer mechanism such as dual function pads and more.
  • the invention relates to a bonding process of a microdevice into a system substrate where the system substrate has at least one pad for coupling to a microdevice and part of the pad on the system substrate or microdevice is shielded by a dielectric layer.
  • the invention relates to providing a method to minimize misalignment defects in microdevices, the method comprising, having a microdevice made of a stack of semiconductor layers, having active layers that are sandwiched between doped layers, coupling doped layers to ohmic layers, coupling the ohmic layers to a first and second electrodes, placing the microdevice on a first substrate, having a first bonding layer between the microdevice and the substrate, forming a planarization layer on the substrate and the microdevice, opening a VIA in the planarization on top of the microdevice; and making a third electrode larger than the VIA.
  • the present invention relates to a method to integrate vertical microdevices into a system substrate the method comprising, covering a sidewall of a microdevice with a first dielectric, covering a top surface of microdevice with a second dielectric, and creating a first VIA opening on the second dielectrics.
  • the bottom side of the microdevice may be covered by a third dielectric and a second VIA opening is created in the third dielectric.
  • FIG. 1A shows a donor setup where a donor substrate has microdevices and a housing structure holds the microdevices.
  • FIG. IB shows a transferred microdevice into a system substrate.
  • FIG. 1C shows a microdevice integrated into the system substrate after the curing process.
  • FIG’s. 2A and 2B show a microdevice made of a stack of semiconductor layers.
  • FIG. 3 shows a microdevice made of a stack of semiconductor layers with an additional VIA.
  • FIG. 4 shows the integration of vertical microdevices into the system substrate.
  • microdevices are transferred from a donor substrate into a system backplane where the microdevices connection pads are adhered to a pad on the system substrate at a temperature that is below the melting point of the materials on the pads of system substrate and microdevice pads.
  • the system substrate with integrated microdevices is heated to a temperature to form an alloy between the pads material on the system substrate and microdevice connection pads.
  • a material is filled around the pads of the microdevice or pads of system substrate prior to the alloying process.
  • the filler materials can be cured first or cured at the same time to eliminate the dispersion/expansion of pad materials during the alloying process and as such eliminates possible shorting between pads or other components.
  • At least part of the pads on system substrate or microdevice is separated from other areas by a shield structure.
  • the fence can be polymer or other types of materials.
  • FIG. 1A shows a donor setup 100.
  • the donor substrate 102 can have microdevices 104.
  • a housing structure 108 can protect and hold the microdevices 104.
  • the microdevices 104 can have connections that are formed as pads 106-a and 106-b. The pads are conductive and may have one or more types of materials.
  • the microdevices 104 can be coupled to the donor substrate 102 directly or through other/extra layers 110.
  • the extra layers 110 can be the release layers.
  • the system substrate 112 can include some backplane layers 114 forming either driving circuitry or just connection.
  • Pads 116-a and 116-b can be formed on the substrate 114 that provides connection between backplane layers and to the microdevice 104 after integration.
  • the system substrate pads 116-a and 116-b on the substrate 114 can be composed of a single material or multiple materials (such as Indium, Thin, polymers or In/ Au, In/Ag, In/Cu, etc.).
  • FIG. IB shows a transferred microdevice 104 into a system substrate 112. the microdevice pads 104-a and 104-b and the system substrates pads 116-a and 116-b are in contact.
  • the contact between microdevice pads and system substrate pads is formed at a temperature below the temperature needed to form an alloy or mixed the pads materials.
  • the pad area will expand and may cause unwanted shorts. With transferring microdevices at low temperature, this issue is resolved. However, the bonding is not strong enough.
  • at least a part of the system substrate or microdevice pads that may expand and cause shorts is also shielded by a layer 122.
  • the shield layer 122 can cover everywhere or a confined area.
  • the shield layer 122 can be formed before the integration of the microdevice 104 into system substrate 112 or after the transfer of the microdevice.
  • the shield layer 122 also can be used as an adhesive layer for integrating microdevices into the system substrate.
  • the setup can be cured at higher temperatures to increase the strength of the bonding. As during this process, no pressure is applied to the microdevices 104, the system substrate pads will not expand. Furthermore, the shield layer 122 can prevent the short.
  • the shield layer 122 can be a polymer or dielectric layer.
  • the shield layer curing can happen at the same time as the pads curing. The shield can be separated from the system substrate pads or connected to them in some areas.
  • FIG. 1C shows a microdevice 104 integrated into the system substrate 112 after the curing process. As it can be seen, the pads formed one structure 124-a and 124-b.
  • the invention relates to providing a method to minimize misalignment defects in microdevices, the method comprising, having a microdevice made of a stack of semiconductor layers, having active layers that are sandwiched between doped layers, coupling doped layers to ohmic layers, coupling the ohmic layers to a first and second electrodes, placing the microdevice on a first substrate, having a first bonding layer between the microdevice and the substrate, forming a planarization layer on the substrate and the microdevice, opening a VIA in the planarization on top of the microdevice; and making a third electrode larger than the VIA.
  • a microdevice 200 (an optoelectronic device made of a stack of semiconductor layers) where active layers are sandwiched between the doped layers and ohmic layers.
  • the ohmic layers can be the same as electrode layers 202, and 204.
  • the ohmic layer in the microdevice 200 is smaller than the surface of other layers.
  • the electrodes 202, and 204 are larger than the ohmic layer.
  • the microdevice 200 is placed on a substrate 212.
  • a planarization layer 208 is formed on the substrate 212 and the microdevice 200.
  • a VIA is open in the planarization layer 208 on top of the microdevice 200.
  • the electrode layer 202 is larger than the VIA so that the misalignment is not causing the defect.
  • the electrode 210 is covering the VIA to couple to the microdevice and connect the microdevice into a signal.
  • the electrode 210 can be transparent to allow the light generated by microdevice 200 to go through the electrode 210.
  • electrode 210 can be reflective (or opaque).
  • the electrode 210 can be larger than the microdevice 200 so that it does not light profile of the device 200 due to misalignment between microdevice 200 and the electrode 210.
  • There can be misalignment by placing the microdevice 200 on the substrate 212.
  • the electrode 210 can be larger than the microdevice at least in one direction and the size difference can be the sum of all misalignments.
  • the electrode 210 can be part of a backplane 240 that is formed on top of the planarization layer 208.
  • the backplane 240 can include driving circuits for controlling the microdevice 200.
  • the circuits can be made of thin film transistors or CMOS or other types of semiconductors.
  • the backplane may include a dielectric or buffer layer 208-2 separating passivation/planarization layer 208 from the rest of the backplane 240.
  • the microdevice 200 is bonded to another substrate 220 using bonding layer 218.
  • the substrate 212 is removed from the device and other layers.
  • the buffer layer 216 can be removed or left on the structure.
  • a dielectric layer can be deposited on the surface on top of the microdevice or the buffer layer 216.
  • a VIA through the dielectric layer or the buffer layer 216 is formed to provide access to the electrode 204.
  • the VIA can go through the bonding layer 206, or the bonding layer can be removed.
  • the VIA can be smaller than the 204.
  • the electrode 218 can be transparent to allow the light to pass through. In another case, the electrode 218 can be opaque or reflective. In this case, the electrode 218 can be larger than the device and extended over the edge of the device at least from one point. This allows it to accommodate misalignment without compromising the light profile.
  • the support layer can be part of the substrate. Or it can be the final substrate after the substrate 220 is removed.
  • Microdevices can be microLED or sensors or MEMS or OLEDs or etc.
  • a system substrate consists of a substrate and a backplane circuitry which controls the microdevices by biasing the microdevices.
  • This embodiment relates to a method to integrate vertical microdevices into a system substrate the method comprising, covering a sidewall of a microdevice with a first dielectric, covering a top surface of microdevice with a second dielectric, and creating a first VIA opening on the second dielectrics.
  • the bottom side of the microdevice may be covered by a third dielectric and a second VIA opening is created in the third dielectric
  • microdevices can be in different forms such as vertical where at least one contact is at the top and one contact is at the bottom surface of the device.
  • FIG. 4 shows an embodiment that simplifies the integration of vertical microdevices into the system substrate.
  • Microdevice 400 can have a dielectric 402 covering the sidewall.
  • Another dielectric 404-1 covering the top surface of the device 400.
  • another dielectric 404-2 covering the bottom surface of the device 400.
  • the dielectrics 404-1, 404-2, and 402 can be the same layers or different.
  • the dielectric layers can be developed using ALD (Atomic layer deposition), PECVD (Plasma-enhanced chemical vapor deposition), sputtering or other methods.
  • the material used for the dielectric can be organic such as polyamide, BCB(Benzocyclobutene), or inorganic such as SiN, SiO2, etc.
  • a pad 406 is formed on the bottom surface of the device 400.
  • a dielectric shell 408 can be developed which is surrounding the pads.
  • the dielectric shell 408 can be adhesive.
  • the system substrate 420 can have backplane circuit 422 on the top surface of the backplane.
  • the backplane circuitry can be coupled to a second pad 424.
  • a second shell 426 is formed to surround the pad 424.
  • the second shell 426 can be adhesive. At least one dimension associated with the area of the shell 426 is larger than the one dimension of the microdevice 400.
  • the pad 406 of the microdevice 400 is coupled to the pad 424 of the system substrate 120.
  • the shields 406 and 424 are also bonded protecting the pads such that shields are also bonded to encapsulate the coupled bonds.
  • an electrode 428 can form on top of the device 400 to couple the top side through VIA 410 to the backplane 422.
  • the electrode can be transparent, reflector or opaque.
  • it can be patterned in rows or columns. In another related case, it can form a common electrode for a set of microdevices on the system substrate.
  • the shield can be only on system substrate or microdevice or both. There can be a gap between the pads and shield. In another case, the shield and the pads are connected physically.
  • the combined height of the shields can be the same as the combined height of the pads. If the combined height of either pad or shield is higher than that of the other one, the taller structure needs to be deformed during the bonding to provide coupling of the other structure.

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Abstract

This disclosure is related to integrating microdevices into a system substrate. In particular the microdevices are transferred from a donor substrate into a system backplane where the microdevices connection pads are adhered to a pads on the system substrate at a temperature that is below the melting point of the materials on the pads of the system substrate and microdevice pads. The present disclosure also relates to integrating vertical microdevices into a system substrate. The system substrate can have a backplane circuit as well. The integration covers the microdevices with dielectrics and couples the backplane through a VIA. The disclosure further relates to a method and structure of microdevice or optoelectronic devices that allows for misalignment adjustment. The microdevices comprise a stack of semiconductor layers that in configuration with electrodes, substrate, VIA's and size factors minimize misalignment.

Description

Low TEMPERATURE BONDING OF MICRODEVICE INTEGRATION
INTO A SYSTEM SUBSTRATE
FIELD OF THE INVENTION
[0001] The present disclosure relates to the integration of microdevices into a system substrate as well as integrating vertical microdevices into a substrate. The invention further relates to providing misalignment adjustment in microdevices.
BRIEF SUMMARY
[0002] A few embodiments of this description are related to integration of microdevices into the system substrate. The system substrate may comprise micro light emitting diodes (LEDs), Organic LEDs, sensors, solid state devices, integrated circuits, (micro-electro-mechanical systems) MEMS, and/or other electronic components. Other embodiments are related to patterning and placing of microdevices in respect to the pixel arrays to optimize the microdevice utilizations in selective transfer processes. The receiving substrate may be, but is not limited to, a printed circuit board (PCB), thin film transistor backplane, integrated circuit substrate, or, in one case of optical microdevices such as LEDs, a component of a display, for example a driving circuitry backplane. The patterning of microdevice donor substrate and receiver substrate can be used in combination with different transfer technology including but not limited to pick and place with different mechanisms (e.g. electrostatic transfer head, elastomer transfer head), or direct transfer mechanism such as dual function pads and more. [0003] In one embodiment, the invention relates to a bonding process of a microdevice into a system substrate where the system substrate has at least one pad for coupling to a microdevice and part of the pad on the system substrate or microdevice is shielded by a dielectric layer.
[0004] In one embodiment the invention relates to providing a method to minimize misalignment defects in microdevices, the method comprising, having a microdevice made of a stack of semiconductor layers, having active layers that are sandwiched between doped layers, coupling doped layers to ohmic layers, coupling the ohmic layers to a first and second electrodes, placing the microdevice on a first substrate, having a first bonding layer between the microdevice and the substrate, forming a planarization layer on the substrate and the microdevice, opening a VIA in the planarization on top of the microdevice; and making a third electrode larger than the VIA.
[0005] The present invention relates to a method to integrate vertical microdevices into a system substrate the method comprising, covering a sidewall of a microdevice with a first dielectric, covering a top surface of microdevice with a second dielectric, and creating a first VIA opening on the second dielectrics. The bottom side of the microdevice may be covered by a third dielectric and a second VIA opening is created in the third dielectric.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The foregoing and other advantages of the disclosure will become apparent upon reading the following detailed description and upon reference to the drawings.
[0007] FIG. 1A shows a donor setup where a donor substrate has microdevices and a housing structure holds the microdevices.
[0008] FIG. IB shows a transferred microdevice into a system substrate.
[0009] FIG. 1C shows a microdevice integrated into the system substrate after the curing process.
[0010] FIG’s. 2A and 2B show a microdevice made of a stack of semiconductor layers.
[0011] FIG. 3 shows a microdevice made of a stack of semiconductor layers with an additional VIA.
[0012] FIG. 4 shows the integration of vertical microdevices into the system substrate.
[0013] The present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations as have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims. DETAILED DESCRIPTION
[0014] In one embodiment, microdevices are transferred from a donor substrate into a system backplane where the microdevices connection pads are adhered to a pad on the system substrate at a temperature that is below the melting point of the materials on the pads of system substrate and microdevice pads.
[0015] In a related embodiment, the system substrate with integrated microdevices is heated to a temperature to form an alloy between the pads material on the system substrate and microdevice connection pads.
[0016] In yet another related embodiment, a material is filled around the pads of the microdevice or pads of system substrate prior to the alloying process. The filler materials can be cured first or cured at the same time to eliminate the dispersion/expansion of pad materials during the alloying process and as such eliminates possible shorting between pads or other components.
[0017] In another embodiment case, at least part of the pads on system substrate or microdevice is separated from other areas by a shield structure. The fence can be polymer or other types of materials.
[0018] FIG. 1A shows a donor setup 100. The donor substrate 102 can have microdevices 104. In one case, a housing structure 108 can protect and hold the microdevices 104. The microdevices 104 can have connections that are formed as pads 106-a and 106-b. The pads are conductive and may have one or more types of materials. The microdevices 104 can be coupled to the donor substrate 102 directly or through other/extra layers 110. The extra layers 110 can be the release layers. There can be a system substrate 112. The system substrate 112, can include some backplane layers 114 forming either driving circuitry or just connection. Pads 116-a and 116-b can be formed on the substrate 114 that provides connection between backplane layers and to the microdevice 104 after integration. The system substrate pads 116-a and 116-b on the substrate 114 can be composed of a single material or multiple materials (such as Indium, Thin, polymers or In/ Au, In/Ag, In/Cu, etc.).
[0019] FIG. IB shows a transferred microdevice 104 into a system substrate 112. the microdevice pads 104-a and 104-b and the system substrates pads 116-a and 116-b are in contact. The contact between microdevice pads and system substrate pads is formed at a temperature below the temperature needed to form an alloy or mixed the pads materials. In some cases, if the system substrate or microdevice pads are heated up at high temperature (melting) and under pressure, the pad area will expand and may cause unwanted shorts. With transferring microdevices at low temperature, this issue is resolved. However, the bonding is not strong enough. In another related case, at least a part of the system substrate or microdevice pads that may expand and cause shorts is also shielded by a layer 122. The shield layer 122 can cover everywhere or a confined area. The shield layer 122 can be formed before the integration of the microdevice 104 into system substrate 112 or after the transfer of the microdevice. The shield layer 122 also can be used as an adhesive layer for integrating microdevices into the system substrate. The setup can be cured at higher temperatures to increase the strength of the bonding. As during this process, no pressure is applied to the microdevices 104, the system substrate pads will not expand. Furthermore, the shield layer 122 can prevent the short. The shield layer 122 can be a polymer or dielectric layer. The shield layer curing can happen at the same time as the pads curing. The shield can be separated from the system substrate pads or connected to them in some areas.
[0020] FIG. 1C shows a microdevice 104 integrated into the system substrate 112 after the curing process. As it can be seen, the pads formed one structure 124-a and 124-b.
Embodiments of Figures 2 and 3
[0021] In this description, the terms "optoelectronic device" and "microdevice" are used interchangeably. However, it is clear to one skilled in the art that the embodiments described here are independent of the device size.
[0022] In one embodiment the invention relates to providing a method to minimize misalignment defects in microdevices, the method comprising, having a microdevice made of a stack of semiconductor layers, having active layers that are sandwiched between doped layers, coupling doped layers to ohmic layers, coupling the ohmic layers to a first and second electrodes, placing the microdevice on a first substrate, having a first bonding layer between the microdevice and the substrate, forming a planarization layer on the substrate and the microdevice, opening a VIA in the planarization on top of the microdevice; and making a third electrode larger than the VIA.
[0023] In FIG’s. 2 A and 2B a microdevice 200 (an optoelectronic device made of a stack of semiconductor layers) where active layers are sandwiched between the doped layers and ohmic layers. There can be other electrodes 202, and 204 coupled to the ohmic layers. The ohmic layers can be the same as electrode layers 202, and 204.
[0024] In another case, the ohmic layer in the microdevice 200 is smaller than the surface of other layers. Here, the electrodes 202, and 204 are larger than the ohmic layer. There can be a dielectric layer covering the ohmic layer and there is an opening in the dielectric that allows the electrodes 202, and 204 to be coupled to the ohmic layers. The microdevice 200 is placed on a substrate 212. There can be a bonding layer 206 holding the microdevice onto the substrate 212. There can be a buffer/release layer 214 on top of the substrate and another buffer layer 216 on top of the layer 214.
[0025] A planarization layer 208 is formed on the substrate 212 and the microdevice 200. A VIA is open in the planarization layer 208 on top of the microdevice 200. The electrode layer 202 is larger than the VIA so that the misalignment is not causing the defect. [0026] The electrode 210 is covering the VIA to couple to the microdevice and connect the microdevice into a signal. The electrode 210 can be transparent to allow the light generated by microdevice 200 to go through the electrode 210.
[0027] In one case electrode 210 can be reflective (or opaque). In that case, the electrode 210 can be larger than the microdevice 200 so that it does not light profile of the device 200 due to misalignment between microdevice 200 and the electrode 210. There can be misalignment by placing the microdevice 200 on the substrate 212. There can be misalignment in patterning of the electrode 210. The electrode 210 can be larger than the microdevice at least in one direction and the size difference can be the sum of all misalignments.
[0028] The electrode 210 can be part of a backplane 240 that is formed on top of the planarization layer 208. The backplane 240 can include driving circuits for controlling the microdevice 200. The circuits can be made of thin film transistors or CMOS or other types of semiconductors. The backplane may include a dielectric or buffer layer 208-2 separating passivation/planarization layer 208 from the rest of the backplane 240.
[0029] In FIG. 3 the microdevice 200 is bonded to another substrate 220 using bonding layer 218. There can be a dielectric layer between the bonding layer 206 and electrode 210. The substrate 212 is removed from the device and other layers. The buffer layer 216 can be removed or left on the structure. A dielectric layer can be deposited on the surface on top of the microdevice or the buffer layer 216.
[0030] A VIA through the dielectric layer or the buffer layer 216 is formed to provide access to the electrode 204. The VIA can go through the bonding layer 206, or the bonding layer can be removed. The VIA can be smaller than the 204. The electrode 218 can be transparent to allow the light to pass through. In another case, the electrode 218 can be opaque or reflective. In this case, the electrode 218 can be larger than the device and extended over the edge of the device at least from one point. This allows it to accommodate misalignment without compromising the light profile.
[0031] There can be a thick support layer formed on top of the structure in the previous figure before bonding to the second substrate 220. The support layer can be part of the substrate. Or it can be the final substrate after the substrate 220 is removed.
[0032] In another case, there can be more than one electrode at the top or bottom of the microdevice, or there can be an electrode at the bottom where the microdevice is bonded to it.
Embodiments of Figure 4
[0033] Microdevices can be microLED or sensors or MEMS or OLEDs or etc. A system substrate consists of a substrate and a backplane circuitry which controls the microdevices by biasing the microdevices.
[0034] This embodiment relates to a method to integrate vertical microdevices into a system substrate the method comprising, covering a sidewall of a microdevice with a first dielectric, covering a top surface of microdevice with a second dielectric, and creating a first VIA opening on the second dielectrics. The bottom side of the microdevice may be covered by a third dielectric and a second VIA opening is created in the third dielectric
[0035] The microdevices can be in different forms such as vertical where at least one contact is at the top and one contact is at the bottom surface of the device.
[0036] The challenge with vertical microdevice integration into system substrate is the post processing to create contact to the top layer. [0037] Figure 4 shows an embodiment that simplifies the integration of vertical microdevices into the system substrate. Microdevice 400 can have a dielectric 402 covering the sidewall. Another dielectric 404-1 covering the top surface of the device 400. And there can be another dielectric 404-2 covering the bottom surface of the device 400. The dielectrics 404-1, 404-2, and 402 can be the same layers or different. There is a VIA opening 410 on the top dielectric 404-1. If there is a dielectric 404-2 on the bottom surface of the device, there is a VIA opening 412 in that dielectric 404-2. The dielectric layers can be developed using ALD (Atomic layer deposition), PECVD (Plasma-enhanced chemical vapor deposition), sputtering or other methods. The material used for the dielectric can be organic such as polyamide, BCB(Benzocyclobutene), or inorganic such as SiN, SiO2, etc.
[0038] A pad 406 is formed on the bottom surface of the device 400. A dielectric shell 408 can be developed which is surrounding the pads. The dielectric shell 408 can be adhesive.
[0039] The system substrate 420 can have backplane circuit 422 on the top surface of the backplane. The backplane circuitry can be coupled to a second pad 424. A second shell 426 is formed to surround the pad 424. The second shell 426 can be adhesive. At least one dimension associated with the area of the shell 426 is larger than the one dimension of the microdevice 400.
[0040] The pad 406 of the microdevice 400 is coupled to the pad 424 of the system substrate 120. During the bonding process to couple the pads, the shields 406 and 424 are also bonded protecting the pads such that shields are also bonded to encapsulate the coupled bonds. After this process an electrode 428 can form on top of the device 400 to couple the top side through VIA 410 to the backplane 422. The electrode can be transparent, reflector or opaque.
[0041] In one case, it can be patterned in rows or columns. In another related case, it can form a common electrode for a set of microdevices on the system substrate.
[0042] The shield can be only on system substrate or microdevice or both. There can be a gap between the pads and shield. In another case, the shield and the pads are connected physically. The combined height of the shields can be the same as the combined height of the pads. If the combined height of either pad or shield is higher than that of the other one, the taller structure needs to be deformed during the bonding to provide coupling of the other structure.
[0043] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims.

Claims

CLAIMS WHAT IS CLAIMED IS:
1. A bonding process of a microdevice into a system substrate where the system substrate has at least one pad for coupling to a microdevice and part of the pad on the system substrate or microdevice is shielded by a dielectric layer.
2. The bonding process of claim 1, wherein the dielectric layer is separated from the pads.
3. The bonding process of claim 1, wherein the dielectric shield is also adhesive.
4. The bonding process of claim 1, the microdevice pads and the system substrates pads are in a contact wherein the contact between microdevice pads and system substrate pads is formed at a temperature below the temperature needed to form an alloy.
5. The bonding process of claim 4, wherein the microdevice pads and the system substrate pads are annealed at higher temperatures after a bonding of the microdevice pads and the system substrates is transferred.
6. The bonding process of claim 1, wherein a housing structure holds the microdevices and microdevices have connections that are formed as microdevice pads.
7. The bonding process of claim 6, wherein the microdevice pads are conductive and are composed of one or more types of material.
8. The bonding process of claim 7, wherein the microdevices are coupled to a donor substrate directly or through release layers.
9. The bonding process of claim 8, wherein the system substrate includes backplane layers forming either a driving circuitry or just a connection.
10. The bonding process of claim 9, wherein the system substrate pads provide connection between backplane layers and to the microdevice after integration.
11. The bonding process of claim 9, wherein the system substrate pads are composed of a single material or multiple materials.
12. The bonding process of claim 1, wherein the system substrate pads are heated up at high temperature and under pressure expanding a system substrate pad area.
13. The bonding process of claim 1, wherein the dielectric layer is formed before the integration of the microdevice.
14. The bonding process of claim 4, wherein the microdevice pads and the system substrate pads become one structure after curing.
15. A method to minimize misalignment defects in microdevices, the method comprising: having a microdevice made of a stack of semiconductor layers; having active layers are sandwiched between doped layers; coupling doped layers to ohmic layers; coupling the ohmic layers to a first and second electrodes; placing the microdevice on a first substrate; having a first bonding layer between the microdevice and the substrate; forming a planarization layer on the substrate and the microdevice; opening a VIA on in the planarization on top of the microdevice; and making a third electrode larger than the VIA.
16. The method of claim 15, wherein the ohmic layers can be the same as electrode layers.
17. The method of claim 15, wherein the ohmic layer is smaller than surfaces of other layers.
18. The method of claim 17, wherein the first and second electrodes are larger than the ohmic layer.
19. The method of claim 18, covering the ohmic layer with a dielectric layer and having an opening in the dielectric allowing the first and second electrodes to be coupled to the ohmic layer.
20. The method of claim 19, covering the VIA with the third electrode to couple to the microdevice and connect the microdevice into a signal.
21. The method of claim 20, wherein the third electrode is transparent.
22. The method of claim 20, wherein the third electrode is reflective or opaque.
23. The method of claim 21, wherein the third electrode is larger than the microdevice.
24. The method of claim 23, wherein the third electrode is larger than the microdevice and a size difference is a sum of all misalignments, due to placing the microdevice on the substrate and in patterning of the third electrode.
25. The method of claim 24, wherein the third electrode is part of a backplane formed on top of the planarization layer.
26. The method of claim 15, the method comprising further: placing the microdevice on a second substrate; having a second bonding layer between the microdevice and the substrate; having a bonding layer between the second bonding layer; removing the first substrate and other layers; having a second dielectric layer between the second bonding layer and a fourth electrode; and forming a second VIA to provide access to the second electrode.
27. The method of claim 26, wherein the second VIA is through the second dielectric layer of a buffer layer.
28. The method of claim 26, wherein the second VIA goes through the second bonding layer.
29. The method of claim 26, wherein a third dielectric layer is deposited on the surface on top of the microdevice or the buffer layer.
30. The method of claim 28, wherein the second VIA is smaller than the second electrode.
31. The method of claim 28, wherein the fourth electrode is transparent.
32. The method of claim 28, wherein the fourth electrode is reflective or opaque.
33. The method of claim 28, wherein the fourth electrode is larger than the microdevice and extends over an edge of the microdevice at least from one point to accommodate misalignment.
34. A method to integrate vertical microdevices into a system substrate the method comprising: covering a sidewall of a microdevice with a first dielectric; covering a top surface of microdevice with a second dielectric; and creating a first VIA opening on the second dielectrics.
35. The method of claim 34, wherein the bottom side of the microdevice is covered by a third dielectric and a second VIA opening is created in the third dielectric.
36. The method of claim 34, wherein the dielectrics are the same or different layers.
37. The method of claim 35, where in the dielectrics layers are developed using ALD, PECVD, or sputtering and a material used for the dielectrics is organic such as polyamide, BCB, or inorganic such as SiN or SiO2.
38. The method of claim 34, further comprising forming a first pad on the bottom surface of the microdevice
39. The method of claim 38, further developing a dielectric shell surrounding the pad.
40. The method of claim 37, wherein the dielectric shell is adhesive.
41. The method of claim 34, wherein the system substrate has a backplane circuit formed directly or indirectly on the top surface of the substrate.
42. The method of claim 39, further comprising coupling the backplane circuitry to a second pad.
43. The method of claim 40, further comprising forming a second shell to surround the second pad.
44. The method of claim 41, wherein the shell is adhesive.
45. The method of claim 41, wherein at least one dimension associated with the area of the second shell is larger than the one dimension of the microdevice.
46. The method of claim 41, wherein the first pad is coupled to the second pad.
47. The method of claim 44, wherein shields are also bonded to encapsulate the coupled bonds.
48. The method of claim 45, further comprising an electrode coupling the top surface of the microdevice through the VIA to the backplane.
49. The method of claim 44, wherein the electrode is either transparent, reflector or opaque.
PCT/CA2021/051218 2020-09-02 2021-09-02 Low temperature bonding of microdevice integration into a system substrate WO2022047587A1 (en)

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US8502389B2 (en) * 2011-08-08 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS image sensor and method for forming the same
US20160111386A1 (en) * 2014-10-16 2016-04-21 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
CA2921737A1 (en) * 2016-02-25 2017-08-25 Reza Rc Chaji Micro device integration into system substrate
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US8502389B2 (en) * 2011-08-08 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS image sensor and method for forming the same
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