WO2022042354A1

WO2022042354A1 - Chip packaging process and packaging chip

Info

Publication number: WO2022042354A1
Application number: PCT/CN2021/112780
Authority: WO
Inventors: 于上家; 陈建超; 詹新明; 胡光华
Original assignee: 青岛歌尔微电子研究院有限公司
Priority date: 2020-08-27
Filing date: 2021-08-16
Publication date: 2022-03-03
Also published as: CN111968949B; CN111968949A

Abstract

Disclosed in the present application are a chip packaging process and a packaging chip, the chip packaging process comprising the following steps: providing a substrate, a first chip, and a second chip, and attaching the first chip to the substrate; forming a plastic packaging layer on the substrate, the plastic packaging layer plastic-packaging the first chip; processing the plastic packaging layer on a side facing away from the substrate, so as to expose the first chip on a side facing away from the substrate; and attaching the second chip on a side of the first chip facing away from the substrate.

Description

Chip packaging process and packaging chips

This application claims the priority of the Chinese patent application filed on August 27, 2020, the application number is 202010884926.7, and the title is "Chip Packaging Process and Packaging Chips", which is hereby incorporated by reference in its entirety.

technical field

The present application relates to the technical field of semiconductor packaging, and in particular, to a chip packaging process and a packaging chip.

Background technique

For the stacked integrated package chips produced by the related package on package technology, after the chips are attached to the substrate, plastic sealing is performed, and then a substrate adapter plate is set on the plastic sealing layer, and then the substrate adapter plate is re-attached. Chips are placed to realize an integrated package structure of multiple chips in the vertical direction, which makes full use of the vertical space, and inevitably, the thickness of the package body will increase.

technical problem

The main purpose of the present application is to propose a chip packaging process and a packaged chip, aiming at improving the related problem of the large thickness of the integrated packaged chip.

technical solutions

In order to achieve the above purpose, the chip packaging process proposed by the present application includes the following steps:

providing a substrate, a first chip and a second chip, and attaching the first chip on the substrate;

forming a plastic encapsulation layer on the substrate, and the plastic encapsulation layer encapsulates the first chip;

processing the side of the plastic encapsulation layer facing away from the substrate to expose the side of the first chip facing away from the substrate;

The second chip is attached to the side of the first chip facing away from the substrate.

In one embodiment, the step of processing the side of the plastic encapsulation layer facing away from the substrate to expose the side of the first chip facing away from the substrate includes:

grinding the side of the plastic sealing layer facing away from the substrate, so that the surface of the side of the ground first chip facing away from the substrate and the surface of the plastic sealing layer facing away from the substrate are on the same plane to expose the side of the first chip facing away from the substrate.

The plastic sealing layer corresponding to the position of the first chip is ground, and the side of the first chip facing away from the substrate is exposed.

In one embodiment, after performing the step of exposing the side of the first chip away from the substrate, the chip packaging process further includes:

etching the side of the first chip facing away from the substrate, so that the distance between the surface of the ground side of the first chip facing away from the substrate and the substrate is smaller than the distance between the surface of the first chip facing away from the substrate and the substrate facing away from the plastic sealing layer The distance between one side surface of the substrate and the substrate.

In one embodiment, after the step of processing the side of the plastic encapsulation layer facing away from the substrate to expose the side of the first chip facing away from the substrate, the chip packaging process further includes: include:

A circuit layer is formed on the side of the plastic packaging layer facing away from the substrate, the substrate is electrically connected to the circuit layer through a wire bonding chip, and the second chip is electrically connected to the circuit layer through a bonding wire.

In one embodiment, the step of forming a circuit layer on the side of the plastic encapsulation layer facing away from the substrate includes:

forming a seed layer on the side of the plastic encapsulation layer facing away from the substrate; and

The circuit layer is formed on the side of the plastic encapsulation layer facing away from the substrate.

In one embodiment, the plastic sealing layer is an organic metal compound modified plastic sealing compound, and the side of the plastic sealing layer facing away from the substrate is activated by laser irradiation to form the seed layer.

In an embodiment, before performing the step of activating the side of the plastic encapsulation layer facing away from the substrate by laser irradiation to form the seed layer, the method further includes:

A mask layer is applied on the side of the plastic sealing layer facing away from the substrate, and the mask layer is provided with a light-transmitting portion corresponding to the circuit pattern of the circuit layer.

In one embodiment, the step of electrically connecting the substrate to the circuit layer through a wire bonding chip includes:

A wire-bonding chip is provided, the wire-bonding chip is electrically connected to the substrate, the wire-bonding chip is plastic-sealed by the plastic sealing layer, and the wire-bonding chip has conductive posts, and the plastic sealing layer is ground to make the conductive posts Exposing, electrically connecting the conductive post with the circuit layer; or

A wire-bonding chip is provided, the wire-bonding chip is electrically connected to the substrate, the wire-bonding chip is plastic-sealed by the plastic sealing layer, the wire-bonding chip has conductive posts, and the plastic sealing layer is drilled so that the The conductive posts are exposed, and conductors are filled in the drilled holes, and the conductive posts are electrically connected to the circuit layer through the conductors.

In one embodiment, the wire bonding chip is electrically connected to the substrate through connecting wires, and the wire bonding chip is electrically connected to the circuit layer.

In one embodiment, after performing the step of electrically connecting the second chip with the circuit layer through bonding wires, the chip packaging process further includes:

A third chip is provided, and the third chip is attached to the circuit layer.

In one embodiment, after the step of providing a third chip and flip-chip attaching the third chip to the circuit layer, the chip packaging process further includes:

Secondary plastic sealing is performed on the side of the plastic sealing layer facing away from the substrate, so as to perform plastic sealing of the second chip, the third chip and the circuit layer.

The present application also proposes a packaged chip, comprising:

substrate;

a plastic encapsulation layer, disposed on the substrate, and a accommodating portion is recessed on the side of the plastic encapsulation layer facing away from the substrate;

a first chip, which is attached to the substrate and located in the plastic encapsulation layer, and the side of the first chip facing away from the substrate is communicated with the accommodating portion; and

The second chip is disposed in the accommodating portion and attached to the side of the first chip facing away from the substrate.

In one embodiment, the packaged chip further includes:

a wire bonding chip, which is arranged on the plastic sealing layer and is electrically connected to the substrate;

bonding wires, electrically connected to the second chip; and

The circuit layer is arranged on the side of the plastic sealing layer facing away from the substrate, the wire bonding chip is electrically connected to the circuit layer, and the second chip is electrically connected to the circuit layer through the bonding wire.

beneficial effect

The technical solution of the present application is to expose the back of the first chip by grinding after the first chip is plastic-sealed. When the second chip is placed on the back of the first chip, the distance between the substrate and the second chip is reduced. , to reduce the thickness of the overall chip after encapsulation.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to the structures shown in these drawings without any creative effort.

FIG. 1 is a schematic flowchart of an embodiment of a chip packaging process of the present application;

FIG. 2 is a schematic flowchart of an embodiment of grinding a plastic sealing layer of the present application;

FIG. 3 is a schematic flowchart of another embodiment of grinding the plastic sealing layer of the present application;

FIG. 4 is a schematic flowchart of etching the first chip according to an embodiment of the present application

FIG. 5 is a schematic flowchart of an embodiment of step S50 of the present application;

FIG. 6 is a schematic flowchart of forming a circuit layer according to an embodiment of the present application;

7 is a schematic flowchart of an embodiment of the connection between the substrate and the circuit layer of the present application;

8 is a schematic flowchart of another embodiment of the connection between the substrate and the circuit layer of the present application;

FIG. 9 is a schematic flowchart of an embodiment of step S60 of the present application;

10 is a schematic structural diagram of an embodiment of a packaged chip of the present application;

FIG. 11 is a schematic flowchart of forming a packaged chip according to an embodiment of the present application;

FIG. 12 is a schematic flowchart of forming a packaged chip according to another embodiment of the present application.

Description of reference numbers:

标号 label	名称 name	标号 label	名称 name
10 10	基板 substrate	201 201	打线芯片 wire chip
202 202	连接导线 connecting wires	21 twenty one	导电柱 Conductive pillar
22 twenty two	导体 conductor	30 30	锡球 Solder balls
40 40	第一芯片 first chip	50 50	塑封层 Plastic layer
51 51	种子层 seed layer	52 52	掩膜层 mask layer
53 53	容置部 accommodating part	60 60	第二芯片 second chip
61 61	焊线 welding wire	70 70	第三芯片 third chip
80 80	激光设备 Laser equipment

The realization, functional characteristics and advantages of the purpose of the present application will be further described with reference to the accompanying drawings in conjunction with the embodiments.

Embodiments of the present invention

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) involved in the embodiments of the present application, the directional indications are only used to explain a certain posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly.

In addition, if there are descriptions related to "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only for the purpose of description, and should not be construed as indicating or implying Its relative importance or implicitly indicates the number of technical features indicated. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In addition, the technical solutions between the various embodiments can be combined with each other, but must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of such technical solutions does not exist. , is not within the scope of protection claimed in this application.

Referring to FIG. 1, the present application proposes a chip packaging process, including the following steps:

S10 : providing the substrate 10 , the first chip 40 and the second chip 60 , and attaching the first chip 40 on the substrate 10 .

Circuits are provided on the substrate 10 , and mounting positions corresponding to the first chips 40 are provided on the substrate 10 , and the mounting positions have connection contacts for connecting the circuits in the substrate 10 . The first chip 40 can be flip-chip mounted on the substrate 10, so that the pins or connection contacts of the first chip 40 are disposed toward the substrate 10, and the first chip 40 is mounted on the corresponding substrate 10. After the mounting position, the first chip 40 is connected to the connection contacts of the mounting position, so that the circuit between the first chip 40 and the substrate 10 is conducted. The end face of the first chip 40 facing away from the substrate 10 is its back. The first chip 40 may be a flip chip. Chip Die), the solder balls 30 are connected to the connection contacts on the substrate 10 to realize the mounting of the first chip 40 .

S20 : forming a plastic encapsulation layer 50 on the substrate 10 , and the plastic encapsulation layer 50 encapsulates the first chip 40 in plastic.

The plastic encapsulation layer 50 is formed on the substrate 10 by using a plastic encapsulation material, and the first chip 40 is encapsulated in the plastic encapsulation layer 50 .

S30 : Process the side of the plastic sealing layer 50 facing away from the substrate 10 to expose the side of the first chip 40 facing away from the substrate 10 .

After the first chip 40 is plastic-sealed, the plastic-sealing layer is processed so that the plastic-sealing layer 50 on the side of the first chip 40 facing away from the substrate 10 is removed, so that the first chip 40 is removed. The side of 40 facing away from the base 10 forms a space that can be used for accommodating the second chip 60 .

S40 : Attach the second chip 60 to the side of the first chip 40 facing away from the substrate 10 .

Please refer to FIG. 10 , by grinding the plastic sealing layer 50 , the side of the first chip 40 facing away from the substrate is exposed, and the back of the second chip 60 is attached to the first chip 40 On the side facing away from the substrate, the connection contacts of the second chip 60 are arranged away from the substrate 10 .

When the second chip 60 is attached to the back of the first chip 40 , the second chip 60 , the plastic sealing layer 50 and the substrate 10 form a package body. Compared with the existing method of directly mounting the second chip 60 on the surface of the plastic sealing layer 50 after the plastic packaging is completed, the second chip 60 faces away from the substrate after grinding and etching. The distance between one side of the 10 and the substrate 10 is relatively reduced, thereby reducing the overall thickness of the package body.

When the chip is packaged, the thickness of the chip itself accounts for a large part of the overall thickness of the generated package. By flip-chip mounting the first chip 40 on the substrate 10, the backside of the first chip 40 can be utilized. space to make full use of the internal space of the package. When the second chip 60 is placed on the first chip 40, the distance between the chips can be reduced, the overall thickness of the package body can be reduced, the SIP (System In a Package, system-in-package) packaging space can be reduced, and the The SIP is more miniaturized; since the proportion of the first chip 40 in the total thickness of the package can be reduced, the space for attaching the second chip 60 can be relatively more, and more chips can be integrated in the plastic package to achieve higher density requirements.

When forming the plastic sealing layer 50 , a bonding wire or the like may be provided on the substrate 10 as a connecting structure, and part of the connecting structure is plastic-sealed in the plastic sealing layer 50 , and part of the connecting structure protrudes from the plastic sealing layer 50 and is connected with the first plastic sealing layer 50 . The two chips 60 are electrically connected, so that the second chip 60 and the substrate 10 are electrically connected through a connection structure, so as to realize the mutual conduction between the first chip 40 and the second chip 60 . The conduction between the second chip 60 and the substrate 10 may also be achieved in other manners.

Referring to FIG. 2, in an embodiment of the present application, the step S30 includes:

S310 : grinding the side of the plastic sealing layer 50 facing away from the substrate 10 so that the ground surface of the first chip 40 facing away from the substrate 10 and the plastic sealing layer 50 facing away from the substrate One side of the surface of the first chip 40 is on the same plane, so that the side of the first chip 40 facing away from the substrate 10 is exposed.

Please refer to FIG. 11 , when the side of the plastic sealing layer 50 facing away from the substrate 10 is ground, since the first chip 40 is plastically sealed in the plastic sealing layer 50 , the plastic sealing layer 50 can be The entire surface of the first chip 40 is ground to reduce the overall thickness of the plastic encapsulation layer 50 until the backside of the first chip 40 is exposed.

By grinding the whole of the plastic sealing layer 50 , the positioning of the grinding process can be facilitated, and the control of the grinding process can be facilitated. Due to the overall grinding of the plastic encapsulation layer 50, the distance between the end face of the plastic encapsulation layer 50 facing away from the substrate 10 and the substrate 10 is reduced. The thickness of the overall structure formed by mounting is also relatively reduced. For example, when a rewiring layer is formed on the plastic packaging layer 50 and a circuit layer is formed, the distance between the circuit layer and the substrate 10 is reduced, and when the chip is mounted on the circuit layer again, the thickness of the formed package body is reduced. little. For the method of grinding the side of the plastic sealing layer 50 facing away from the substrate 10, reference may be made to the prior art.

Referring to FIG. 3, in another embodiment of the present application, the step S30 includes:

S320 : Grinding the plastic encapsulation layer 50 corresponding to the position of the first chip 40 to expose the side of the first chip 40 facing away from the substrate 10 .

Please refer to FIG. 12 , when grinding the plastic encapsulation layer 50 , only the plastic encapsulation layer 50 corresponding to the first chip 40 is ground, so that the plastic encapsulation layer 50 is formed on the plastic encapsulation layer 50 which is opposite to the back of the first chip 40 . Corresponding to the concave portion until the back of the first chip 40 is exposed, the concave portion is the accommodating portion 53 for accommodating the second chip 60 . Since only the plastic encapsulation layer 50 corresponding to the first chip 40 is ground during grinding, the required grinding area is relatively reduced, thereby reducing the grinding workload.

In this embodiment, the surface of the plastic sealing layer 50 facing away from the substrate 10 may be ground as a whole first, and after the overall thickness of the plastic sealing layer 50 is reduced, the first chip 40 is The plastic sealing layer 50 corresponding to the position continues to be ground until the backside of the first chip 40 is exposed. At this time, the overall thickness of the plastic sealing layer 50 is reduced. When the second chip 60 is placed on the back of the first chip 40 and a rewiring layer is formed on the plastic sealing layer 50, the resulting The overall thickness of the package body is reduced.

Referring to FIG. 4, in an embodiment of the present application, after step S30 is performed, the chip packaging process further includes:

S330 : Etch the side of the first chip 40 facing away from the substrate 10 , so that the distance between the surface of the ground side of the first chip 40 facing away from the substrate 10 and the substrate 10 It is smaller than the distance between the side surface of the plastic sealing layer 50 facing away from the substrate 10 and the substrate 10 .

Please refer to FIG. 11 and FIG. 12 , the backside of the first chip 40 is etched with hydrofluoric acid, so that the side of the first chip 40 facing away from the substrate 10 is between the substrate 10 . The distance between them decreases, so that at the position where the first chip 40 is located, the depth of the accommodating portion 53 increases. When the first chip 40 is etched, it is preferable not to affect the internal circuit of the first chip 40 . When the second chip 60 is attached to the back of the first chip 40, the distance between the side of the second chip 60 facing away from the substrate 10 and the substrate 10 is relatively reduced, thereby reducing the distance between the second chip 60 and the substrate 10. The overall thickness of the small package.

The etching thickness of the first chip 40 may be between 0 and 1000 microns. Taking a flip chip as an example for the first chip 40, the thickness of the flip chip after grinding is usually 50 to 500 microns, while the thickness of the flip chip is usually 50 to 500 microns. The thickness of the circuits in is usually around 10 microns. By reducing the overall thickness of the first chip 40 , a larger accommodating space can be provided for the second chip 60 . The etching thickness of the first chip 40 can be determined according to the specific conditions of the first chip 40 , and it is preferable that the internal circuit of the first chip 40 is not affected.

In this embodiment, the surface of the plastic sealing layer 50 facing away from the substrate 10 may be ground as a whole first, and after the overall thickness of the plastic sealing layer 50 is reduced, the first chip 40 is The plastic encapsulation layer 50 corresponding to the position continues to be ground until the backside of the first chip 40 is exposed. Then, step S330 is performed to etch the back of the first chip 40 to reduce the thickness of the first chip 40 .

Referring to FIG. 5, in an embodiment of the present application, after step S30 is performed, the chip packaging process further includes:

S50 : forming a circuit layer on the side of the plastic encapsulation layer 50 facing away from the substrate 10 , the substrate 10 is electrically connected to the circuit layer through the wire bonding chip 201 , and the second chip 60 is connected to the circuit layer through the bonding wire 61 . The circuit layers are electrically connected.

Please refer to FIG. 11 and FIG. 12 in combination, the second chip 60 and the circuit layer form a second-layer circuit structure. The wire bonding chip 201 is used to connect the substrate 10 and the circuit layer to each other, and the first chip 40 is attached to the substrate 10 to realize the circuit layer and the first chip 40 mutual conduction. The bonding wire 61 is used to realize the conduction between the second chip 60 and the circuit layer, and thus can be in conduction with the first chip 40 .

By forming the circuit layer, the circuit layer can be used for conduction between the second chip 60 and the first chip 40 , so that it is not necessary to provide a separate adapter board, so as to improve the performance of the existing package. The problem of increasing the overall thickness of the package caused by the arrangement of the adapter plate.

The wire bonding chip 201 is electrically connected to the substrate 10 through the connecting wires 202 , and the wire bonding chip 201 is electrically connected to the circuit layer. The wire bonding chip 201 can be used to connect the circuit layer and the substrate 10, and also has its own chip function.

Since the thickness of the wire-bonding chip 201 after grinding is usually 30 to 500 microns, the thickness of the internal circuit is usually 10 microns. By using the wire-bonding chip 201, the function of the chip itself can be played. Plastic body to improve the packing density of SIP. The connecting wire 202 can also be a bonding wire. As shown in the figure, there are only two first chips 40 and one wire bonding chip 201 , which are only partial structures of the plastic package. In actual processing, a plurality of the first chips 40 may be placed on the substrate 10 . and the wire bonding chip 201, which are not limited here.

Referring to FIG. 6 , in an embodiment of the present application, the step of forming a circuit layer on the side of the plastic encapsulation layer 50 facing away from the substrate 10 includes:

S510 : forming a seed layer 51 on the side of the plastic sealing layer 50 facing away from the substrate 10 .

S511 : forming the circuit layer on the side of the plastic sealing layer 50 facing away from the substrate 10 .

Please refer to FIG. 11 and FIG. 12 in combination. When the circuit layer is formed, the circuit pattern is first etched, and the seed layer 51 forms the circuit pattern. By forming the seed layer 51, when the circuit layer is formed, the bonding force between the circuit layer and the plastic encapsulation layer 50 can be improved, and the quality of the package body can be improved.

When the electroless plating process is adopted, according to the principle of redox reaction, a strong reducing agent is used in a solution containing metal ions to deposit metal ions on the surface of the seed layer 51 to form the pattern of the circuit layer.

During the electroless plating process, in order to improve the circuit flatness after electroless plating, the surface of the side of the plastic encapsulation layer 50 facing away from the substrate 10 may be ground first. In the process of grinding to form the accommodating portion 53 , the plastic sealing layer 50 may also be ground simultaneously.

When electroplating is used, a copper seed layer 51 needs to be formed for conduction when forming the copper circuit. When the power supply is applied between the copper (anode) and the silicon wafer (cathode), the copper in the anode reacts and converts into copper ions and electrons, and the cathode also reacts, and the copper ions on the surface of the seed layer 51 near the cathode combine with the electrons to form a plating Copper on the surface of the seed layer 51 to form a circuit, thereby forming the circuit layer.

In this embodiment, optionally, the plastic sealing layer 50 is an organic metal compound modified plastic sealing compound, and the side of the plastic sealing layer 50 facing away from the substrate 10 is activated by laser irradiation to form the seed layer 51 . The organometallic compound modified plastic sealant contains metal ions, and after being irradiated by a laser, the ions can be released to form a conductive seed layer 51 .

Since the seed layer 51 can be formed on the surface of the plastic encapsulation layer 50 by laser irradiation generated by the laser device 80 , the subsequent circuit layer fabrication can be facilitated, and at the same time, there is no need to provide a device on the plastic encapsulation layer 50 for conducting the first chip 40 and the The adapter plate of the second chip 60 further reduces the overall thickness of the plastic package.

In order to form a circuit pattern, in this embodiment, optionally, before performing the step of activating the side of the plastic encapsulation layer 50 facing away from the substrate 10 by laser irradiation to form the seed layer 51 A mask layer 52 is applied to the side of the layer 50 facing away from the substrate 10 , and the mask layer 52 is provided with a light-transmitting portion corresponding to the circuit pattern of the circuit layer. The mask layer 52 is used to block the laser light, so that the laser light can only be irradiated on the plastic sealing layer 50 according to a preset position. The light-transmitting portion is used for laser light to pass through, so that the laser light can act on the surface of the plastic sealing layer 50 facing away from the substrate 10 to form the seed layer 51 . Since the light-transmitting portion is consistent with the circuit pattern of the circuit layer, the pattern of the seed layer 51 formed after laser irradiation is the same as the circuit pattern of the circuit layer.

Referring to FIG. 7, in an embodiment of the present application, the step of electrically connecting the substrate 10 to the circuit layer through a wire bonding chip includes:

S520: Provide a wire bonding chip, the wire bonding chip is electrically connected to the substrate 10, the plastic sealing layer 50 plastic-encapsulates the wire bonding chip, the wire bonding chip has conductive posts 21, the plastic sealing layer 50 is ground, so that the conductive pillars 21 are exposed, and the conductive pillars 21 are electrically connected to the circuit layer;

Please refer to FIG. 11 , one end of the wire bonding chip is connected to the circuit of the substrate 10 , and the conductive pillars 21 of the wire bonding chip are disposed in a direction away from the substrate 10 . During the overall grinding of the plastic encapsulation layer 50 according to step S310 , the side of the conductive pillar 21 away from the substrate 10 is exposed. When the circuit layer is fabricated, the formed circuit layer is connected to one end of the conductive pillar 21 away from the substrate 10 , so that the wire bonding chip and the circuit layer are connected to each other.

Referring to FIG. 8 , in another embodiment of the present application, the step of electrically connecting the substrate 10 to the circuit layer through a wire bonding chip includes:

S530 : providing a wire bonding chip, the wire bonding chip is electrically connected to the substrate 10 , the plastic sealing layer 50 plastic-encapsulates the wire bonding chip, the wire bonding chip has conductive posts 21 , and the plastic sealing layer 50 is plastic-sealed. Drill holes to expose the conductive pillars 21 , fill conductors 22 in the drilled holes, and electrically connect the conductive pillars 21 to the circuit layer through the conductors 22 .

Please refer to FIG. 12 , one end of the conductive column 21 is connected to the wire bonding chip, and the other end of the conductive column 21 faces the side surface of the plastic sealing layer 50 away from the substrate 10 . When the plastic sealing layer 50 is ground according to step S320 , an accommodating portion 53 corresponding to the position of the first chip 40 is formed in the plastic sealing layer 50 . Then, the plastic encapsulation layer 50 is drilled to expose one end of the conductive pillar 21 away from the substrate 10 . Conductors 22 are filled in the drilled holes, and when the circuit layer is fabricated, the conductors 22 in the drilled holes are connected to the circuit layer, so that the wire bonding chip and the circuit layer are connected to each other. .

The plastic sealing layer 50 may also be drilled first to form the conductors 22 , and then the accommodating portion 53 is formed in the plastic sealing layer 50 . Can also be done at the same time.

When the circuit layer is formed by an electroless plating process, the entire surface of the side surface of the plastic sealing layer 50 facing away from the substrate 10 may be ground as a whole to reduce the overall thickness of the plastic sealing layer 50 and at the same time make the It is easier to form a stable, high-quality circuit layer on the surface of the plastic encapsulation layer 50 . Then, the plastic sealing layer 50 is ground to form the accommodating portion 53 , and the plastic sealing layer 50 is drilled to form the conductor 22 .

The conductor 22 can be made of a metal substance, or a material capable of having electrical conductivity such as conductive glue.

Referring to FIG. 9, in an embodiment of the present application, after performing the step of electrically connecting the second chip 60 with the circuit layer through the bonding wire 61, the chip packaging process further includes:

S60: Provide a third chip 70, and attach the third chip 70 to the circuit layer.

Please refer to FIG. 10 , the third chip 70 is located on the side of the circuit layer facing away from the substrate 10 , and the end face of the third chip 70 facing away from the circuit layer is its back. The third chip 70 can be flip-chip mounted on the circuit layer. When the package body is further processed, the backside of the third chip 70 can be etched with reference to the manufacturing method of the first chip 40 . , and further chips can be mounted on the third chip 70 .

Since the second chip 60 is electrically connected to the circuit layer through the bonding wire 61 , the second chip 60 can be electrically connected to the third chip 70 . Since the circuit layer is connected to the substrate 10 through the wire bonding chip, the third chip 70 and the substrate 10 can be connected to each other. There is no need to dispose an adapter plate on the plastic encapsulation layer 50 to communicate with the third chip 70 and the first chip 40 , thereby reducing the thickness of the plastic encapsulation.

Please refer to FIG. 11 and FIG. 12 , when the surface of the plastic sealing layer 50 facing away from the substrate 10 is ground and the accommodating portion 53 is formed by etching the first chip 40 , When the second chip 60 is mounted, since the distance between the side of the second chip 60 facing away from the substrate 10 and the substrate 10 is relatively reduced, and the circuit layer is connected to the substrate 10 The distance between them is reduced, so that the thickness of the package body is reduced. After the third chip 70 is mounted, the distance between the side surface of the third chip 70 facing away from the substrate 10 and the substrate 10 is also reduced. relatively reduced.

The flip-chip mounting of the third chip 70 on the substrate 10 means that the pins or connection contacts of the third chip 70 are disposed toward the substrate 10, and the third chip 70 is mounted on the corresponding After the mounting position, the third chip 70 is connected to the connection contacts of the mounting position, so that the circuit of the third chip 70 and the substrate 10 is conducted. The end face of the third chip 70 facing away from the substrate 10 is its back. The third chip 70 can also be a flip chip, and the solder balls 30 of the third chip 70 are connected to the connection contacts on the substrate 10 to realize the installation of the third chip 70

Referring to FIG. 9, in an embodiment of the present application, after performing the steps of providing a third chip 70 and flip-chip attaching the third chip 70 to the circuit layer, the chip packaging process further includes:

S70: Perform secondary plastic encapsulation on the side of the plastic encapsulation layer 50 facing away from the substrate 10 to encapsulate the second chip 60, the third chip 70 and the circuit layer.

Please refer to FIG. 11 and FIG. 12 in combination, after the secondary plastic packaging is performed, the third chip 70 , the second chip 60 and the first chip 40 form an integral plastic packaging body. After the plastic packaging is completed, the surface of the plastic packaging body facing away from the substrate 10 may be ground by referring to step S310 or step S320 , and further chips are mounted on the third chip 70 again. Since no adapter plate is provided in the package body, the overall thickness of the package body can be reduced.

After the secondary plastic packaging is performed, the conductive pillars 21 may be arranged on the second chip 60. When the circuit layer is fabricated again on the surface of the plastic packaging body formed by the secondary plastic packaging that faces away from the substrate 10, the second The conductive pillars 21 on the chip 60 realize the conduction of the circuit layers.

The present application also provides an embodiment of a packaged chip.

Referring to FIG. 10, the packaged chip includes: a substrate 10; a plastic sealing layer 50 disposed on the substrate 10; The chip 40 is flip-chip mounted on the substrate 10 and located in the plastic sealing layer 50 , and the side of the first chip 40 facing away from the substrate 10 is communicated with the accommodating portion 53 ; Two chips 60 are disposed in the accommodating portion 53 and attached to the side of the first chip 40 facing away from the substrate 10 .

The plastic encapsulation layer 50 may use an organic metal compound to modify the plastic encapsulation material, and the first chip 40 is encapsulated by the plastic encapsulation layer 50 . The first chip 40 may be a flip chip.

The substrate 10 is provided with a circuit layer, a mounting position for mounting the chip is provided on the substrate 10, and the mounting position is provided with connecting contacts such as pads connecting the circuit layer, the first When the chip 40 is mounted on the substrate 10 , it is in conduction with the substrate 10 . The side surface of the first chip 40 facing away from the substrate 10 is its back.

The accommodating portion 53 is a concave portion disposed on the side surface of the plastic sealing layer 50 facing away from the substrate 10 . The accommodating portion 53 corresponds to the position of the first chip 40 , so that the The back of the first chip 40 is exposed. The second chip 60 is disposed in the accommodating portion 53 . Compared with the method of directly mounting the second chip 60 on the side of the plastic sealing layer 50 facing away from the substrate 10 , the method described in this embodiment is adopted, the second chip 60 and the substrate are The distance between 10 is reduced, thereby reducing the thickness of the entire plastic package.

Referring to FIG. 11 , when the accommodating portion 53 is fabricated, the surface of the plastic layer 50 facing away from the substrate 10 may be ground as a whole to expose the back of the first chip 40 . The backside of the first chip 40 is etched to form the accommodating portion 53 .

Referring to FIG. 12 , the plastic sealing layer 50 at the position corresponding to the first chip 40 may also be ground, so that the plastic sealing layer 50 forms an accommodating portion corresponding to the position of the first chip 40 . 53, until the back of the first chip 40 is exposed.

Referring to FIGS. 11 and 12 , the surface of the plastic sealing layer 50 facing away from the substrate 10 may be ground as a whole first, so as to reduce the overall thickness of the plastic sealing layer 50 . Then, the plastic sealing layer 50 at the position corresponding to the first chip 40 is ground until the backside of the first chip 40 is exposed. Then, the back of the first chip 40 is etched to reduce the thickness of the first chip 40 and correspondingly increase the depth of the accommodating portion 53, and the second chip 60 is placed on the The backside of the first chip 40 after etching.

Referring to FIG. 10 , in an embodiment of the present application, the packaged chip further includes: a wire bonding chip, which is disposed on the plastic sealing layer 50 and is electrically connected to the substrate 10 ; a bonding wire 61 is connected to the first The two chips 60 are electrically connected; and the circuit layer is disposed on the side of the plastic encapsulation layer 50 facing away from the substrate 10 , and the end of the wire bonding chip away from the substrate 10 is electrically connected to the circuit layer, and the first The two chips 60 are electrically connected to the circuit layer through the bonding wires 61 .

The wire bonding chip is used to connect the circuit of the substrate 10 and the circuit layer. When the second chip 60 is electrically connected to the circuit layer through the bonding wire 61 , the second chip 60 can also be implemented. The interconnection with the substrate 10 is conducted. Since the first chip 40 is attached to the substrate 10 , the second chip 60 can be electrically connected to the first substrate 10 .

The wire bonding chip 201 may be a wire bonding chip 201 attached to the substrate 10 , the wire bonding chip 201 is electrically connected to the substrate 10 through bonding wires, and the wire bonding chip 201 is connected to the substrate 10 through a conductive column 21 . The circuit layers are electrically connected. Since the wire bonding chip 201 itself has its chip function, more chips can be integrated in the plastic package while the substrate 10 and the circuit layer are conducting, so as to improve the integration degree of the plastic package.

After the circuit layer is fabricated, a third chip 70 can be flip-chip attached on the circuit layer, and then the packaged chip is subjected to secondary plastic sealing. After the secondary plastic encapsulation is completed, the accommodating portion 53 corresponding to the position of the third chip 70 can be set, or the third chip 70 can be continuously etched, and the back of the third chip 70 can be pasted again. set the chip.

By arranging the circuit layer, the mutual conduction between the second chip 60 and the substrate 10 can be achieved, and there is no need to install an existing transfer board on the plastic package again, thereby reducing the size of the packaged chip. the overall thickness. Since the second chip 60 is placed on the back of the first chip 40, or after the first chip 40 is etched, the thickness of the first chip 40 is reduced and the second chip 40 is then mounted. The chip 60 makes the space occupied by the second chip 60 in the thickness direction of the packaged chip smaller, which helps to reduce the thickness of the packaged chip.

The above descriptions are only optional embodiments of the present application, and are not intended to limit the patent scope of the present application. Under the inventive concept of the present application, any equivalent structural transformations made by using the contents of the description and drawings of the present application, or direct/indirect Applications in other related technical fields are included in the scope of patent protection of this application.

Claims

A chip packaging process, comprising the following steps:

providing a substrate, a first chip and a second chip, and attaching the first chip on the substrate;

forming a plastic encapsulation layer on the substrate, and the plastic encapsulation layer encapsulates the first chip;

processing the side of the plastic encapsulation layer facing away from the substrate to expose the side of the first chip facing away from the substrate;

The second chip is attached to the side of the first chip facing away from the substrate.
The chip packaging process according to claim 1, wherein the step of processing the side of the plastic packaging layer facing away from the substrate to expose the side of the first chip facing away from the substrate comprises the following steps: :

grinding the side of the plastic sealing layer facing away from the substrate, so that the surface of the side of the ground first chip facing away from the substrate and the surface of the plastic sealing layer facing away from the substrate are on the same plane to expose the side of the first chip facing away from the substrate.
The chip packaging process according to claim 1, wherein the step of processing the side of the plastic packaging layer facing away from the substrate to expose the side of the first chip facing away from the substrate comprises the following steps: :

The plastic sealing layer corresponding to the position of the first chip is ground, and the side of the first chip facing away from the substrate is exposed.
The chip packaging process according to any one of claims 1 to 3, wherein after performing the step of exposing the side of the first chip away from the substrate, the chip packaging process further comprises:

etching the side of the first chip facing away from the substrate, so that the distance between the surface of the ground side of the first chip facing away from the substrate and the substrate is smaller than the distance between the surface of the first chip facing away from the substrate and the substrate facing away from the plastic sealing layer The distance between one side surface of the substrate and the substrate.
The chip packaging process according to claim 1, wherein after the step of processing the side of the plastic encapsulation layer facing away from the substrate to expose the side of the first chip facing away from the substrate , the chip packaging process further includes:

A circuit layer is formed on the side of the plastic packaging layer facing away from the substrate, the substrate is electrically connected to the circuit layer through a wire bonding chip, and the second chip is electrically connected to the circuit layer through a bonding wire.
The chip packaging process according to claim 5, wherein the step of forming a circuit layer on the side of the plastic packaging layer facing away from the substrate comprises:

forming a seed layer on the side of the plastic encapsulation layer facing away from the substrate; and

The circuit layer is formed on the side of the plastic encapsulation layer facing away from the substrate.
The chip packaging process according to claim 6 , wherein the plastic sealing layer is an organic metal compound modified plastic sealing compound, and a side of the plastic sealing layer facing away from the substrate is activated by laser irradiation to form the seed layer.
The chip packaging process according to claim 7, wherein before performing the step of activating the side of the plastic sealing layer facing away from the substrate by laser irradiation to form the seed layer, further comprising:

A mask layer is applied on the side of the plastic sealing layer facing away from the substrate, and the mask layer is provided with a light-transmitting portion corresponding to the circuit pattern of the circuit layer.
The chip packaging process according to any one of claims 5 to 8, wherein the step of electrically connecting the substrate with the circuit layer through a wire bonding chip comprises:

A wire-bonding chip is provided, the wire-bonding chip is electrically connected to the substrate, the wire-bonding chip is plastic-sealed by the plastic sealing layer, and the wire-bonding chip has conductive posts, and the plastic sealing layer is ground to make the conductive posts Exposing, electrically connecting the conductive post with the circuit layer; or

A wire-bonding chip is provided, the wire-bonding chip is electrically connected to the substrate, the wire-bonding chip is plastic-sealed by the plastic sealing layer, the wire-bonding chip has conductive posts, and the plastic sealing layer is drilled so that the The conductive posts are exposed, and conductors are filled in the drilled holes, and the conductive posts are electrically connected to the circuit layer through the conductors.
The chip packaging process according to any one of claims 5 to 8, wherein the wire bonding chip is electrically connected to the substrate through connecting wires, and the wire bonding chip is electrically connected to the circuit layer.
The chip packaging process according to any one of claims 5 to 8, wherein after performing the step of electrically connecting the second chip with the circuit layer through bonding wires, the chip packaging process further comprises:

A third chip is provided, and the third chip is attached to the circuit layer.
The chip packaging process according to claim 11, wherein after performing the step of providing a third chip and flip-chip attaching the third chip to the circuit layer, the chip packaging process further comprises:

Secondary plastic sealing is performed on the side of the plastic sealing layer facing away from the substrate, so as to perform plastic sealing of the second chip, the third chip and the circuit layer.
A packaged chip, comprising:

substrate;

a plastic encapsulation layer, disposed on the substrate, and a accommodating portion is recessed on the side of the plastic encapsulation layer facing away from the substrate;

a first chip, which is attached to the substrate and located in the plastic encapsulation layer, and the side of the first chip facing away from the substrate is communicated with the accommodating portion; and

The second chip is disposed in the accommodating portion and attached to the side of the first chip facing away from the substrate.
The packaged chip of claim 13, wherein the packaged chip further comprises:

a wire bonding chip, which is arranged on the plastic sealing layer and is electrically connected to the substrate;

bonding wires, electrically connected to the second chip; and

The circuit layer is arranged on the side of the plastic sealing layer facing away from the substrate, the wire bonding chip is electrically connected to the circuit layer, and the second chip is electrically connected to the circuit layer through the bonding wire.