WO2022041582A1 - 一种驱动电路和驱动方法 - Google Patents

一种驱动电路和驱动方法 Download PDF

Info

Publication number
WO2022041582A1
WO2022041582A1 PCT/CN2020/136586 CN2020136586W WO2022041582A1 WO 2022041582 A1 WO2022041582 A1 WO 2022041582A1 CN 2020136586 W CN2020136586 W CN 2020136586W WO 2022041582 A1 WO2022041582 A1 WO 2022041582A1
Authority
WO
WIPO (PCT)
Prior art keywords
output
module
threshold
sampling circuit
circuit
Prior art date
Application number
PCT/CN2020/136586
Other languages
English (en)
French (fr)
Inventor
雷述宇
Original Assignee
宁波飞芯电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202010895358.0A external-priority patent/CN114122891A/zh
Priority claimed from CN202010895674.8A external-priority patent/CN114124078A/zh
Application filed by 宁波飞芯电子科技有限公司 filed Critical 宁波飞芯电子科技有限公司
Priority to US18/042,751 priority Critical patent/US20230297034A1/en
Publication of WO2022041582A1 publication Critical patent/WO2022041582A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/185—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using dielectric elements with variable dielectric constant, e.g. ferro-electric capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval

Definitions

  • the present disclosure relates to the field of driving circuits, and in particular, to a driving circuit and a driving method.
  • the rise/fall times of signals propagating between the CPU and chipset often vary due to one or more external influences. These effects include variations in silicon strength caused by process, voltage and/or temperature conditions present on a large number of dies. Uncompensated supply voltage variations can also cause rise/fall time variations. If not addressed, these changes will adversely affect system performance. For example, if the rise/fall times are too slow, timing failures can occur. Conversely, if the rise/fall times are too fast, signal integrity and reliability issues may arise due to large reflections and overshoot/undershoot effects.
  • active light source detection type systems such as laser-based ranging systems, driving The laser source emits a wave with a specific waveform is the key to detection, but the accuracy of the waveform depends largely on the precise control of the rise time and fall time.
  • Rise time is the time it takes for a digital logic circuit to transition from a low logic level to a high logic level (e.g. "0" to “1")
  • fall time is the time it takes to transition from a high logic level to a low logic level ( For example, “1” to “0”).
  • the need to know that the pulse rise and fall times (rising and falling edges) are within specification is the basis for using pulses in measurement and test applications.
  • the degree to which the pulse rise and/or fall time affects the device under test performance depends on the nature of the device and the type of test to be performed.
  • pulse generators do not provide independent self-contained verification of rise and fall times, nor do they provide independent automatic self-contained adjustment of rise and fall times.
  • Such equipment typically requires the use of an external oscilloscope and an automatic test equipment controller or trained operator to perform pulse rise and fall time verification.
  • the purpose of the present disclosure is to provide a driving circuit and a driving method in view of the above-mentioned deficiencies in the prior art, so as to solve the problem that in the related art, the precise control of the waveform of the transmitting end or the inability to achieve a more accurate output of the ranging results The problem.
  • an embodiment of the present disclosure provides a driving circuit, characterized in that it includes:
  • the target waveform conversion part is configured to convert the target waveform information into a current or voltage signal
  • the converted current or voltage signal is output to the first sampling circuit and the second sampling circuit;
  • the operation module outputs an action instruction according to the output results of the first sampling circuit and the second sampling circuit;
  • the TDC module outputs the time parameter of the counting interval according to the action instruction output by the operation module.
  • the current or voltage signal converted from the target waveform includes a rising edge and a falling edge
  • the time parameter of the counting interval output by the TDC module is at least the total time of the rising edge and/or the falling edge. part.
  • the first sampling circuit has a first output threshold
  • the second sampling circuit has a second output threshold
  • the first output threshold is smaller than the second output threshold
  • the drive circuit further includes a first output threshold and a second output threshold adjustment module, the first output threshold and the second output threshold adjustment module include an adjustable resistor, and the resistance value of the adjustable resistor determines the desired value.
  • the first output threshold and the second output threshold, and the adjustable resistance includes a first adjustable resistance and a second adjustable resistance.
  • the driving circuit further includes a third threshold value and a fourth threshold value, the resistance value of the first adjustable resistor is determined according to the third threshold value; the second adjustable resistor value is determined according to the fourth threshold value resistance value; the third threshold value is smaller than the fourth threshold value.
  • the driving circuit further includes a first switch and a second switch.
  • the resistance value of the first adjustable resistor is determined according to the third threshold value; when the second switch is closed, the resistance value of the second adjustable resistor is determined by the fourth threshold value.
  • the resistance value of the first adjustable resistor can be adjusted until the level of the first jump module jumps, and the first adjustable resistor can be determined.
  • the resistance value of the second adjustable resistor can be determined by adjusting the resistance value of the second adjustable resistor until the level of the second jump module jumps.
  • the first hopping module and/or the second hopping module is an even number of inverters or an even number of inverters.
  • the resistance value of the adjustable resistor of the threshold adjustment module is adjusted in at least one of the following ways:
  • the operation module includes an OR operation unit, and the OR operation unit outputs an action instruction according to the output results of the first sampling circuit and the second sampling circuit.
  • the driving circuit further includes a latching module, and the latching module latches the time parameter of the count interval output by the TDC module according to the action instruction output by the operation module.
  • the present disclosure also provides a driving method implemented by using the driving circuit of the first aspect, including:
  • the target waveform conversion part is configured to convert the target waveform information into a current or voltage signal
  • the converted current or voltage signal is output to the first sampling circuit and the second sampling circuit;
  • the operation module outputs an action instruction according to the output results of the first sampling circuit and the second sampling circuit;
  • the TDC module outputs the time parameter of the counting interval according to the action instruction output by the operation module.
  • the current or voltage signal converted from the target waveform includes a rising edge and a falling edge
  • the time parameter of the counting interval output by the TDC module is at least the total time of the rising edge and/or the falling edge. part.
  • the first sampling circuit has a first output threshold
  • the second sampling circuit has a second output threshold
  • the first output threshold is smaller than the second output threshold
  • the operation module includes an OR operation unit, and the OR operation unit outputs an action instruction according to the output results of the first sampling circuit and the second sampling circuit.
  • the first output threshold and the second output threshold adjustment module include an adjustable resistor, and the resistance value of the adjustable resistor determines the first output Threshold and second output threshold, the adjustable resistance includes a first adjustable resistance and a second adjustable resistance.
  • it further includes a third threshold value and a fourth threshold value, and the resistance value of the first adjustable resistor is determined according to the third threshold value; the resistance value of the second adjustable resistor is determined according to the fourth threshold value; The third threshold is smaller than the fourth threshold.
  • a first switch and a second switch are also included.
  • the resistance value of the first adjustable resistor is determined according to a third threshold value; when the second switch is closed, the resistance value of the second adjustable resistor is determined by a fourth threshold value.
  • a latch module is further included, and the latch module latches the time parameter of the count interval output by the TDC module according to the action instruction output by the operation module.
  • an embodiment of the present disclosure provides a driving circuit, which is characterized by comprising: a target waveform conversion unit configured to convert target waveform information into a current or voltage signal; the converted current or voltage signal; output to the first sampling circuit and the second sampling circuit; an arithmetic module, the arithmetic module outputs an action instruction according to the output results of the first sampling circuit and the second sampling circuit; the TDC module, according to the output of the arithmetic module The time parameter of the action command output count interval.
  • the present disclosure can convert the target waveform into a voltage or current signal, and process the voltage or current signal converted from the target waveform through two sampling circuits, and use the processing result to obtain the time value of the counting interval. Compared with the traditional circuit, no reference is used. Or the reference signal, and the design of the comparator is not used to ensure the simplicity, high efficiency, and greater achievability of the circuit.
  • FIG. 1 is a schematic diagram of a typical pulse waveform commonly used in the prior art
  • FIG. 2 is a schematic diagram of a driving circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another driving circuit provided by the present disclosure.
  • FIG. 4 is a schematic diagram of a driving circuit provided by the present disclosure.
  • FIG. 5 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another driving circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another driving circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a chip modularization provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of storage of time information obtained by a TDC according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a circuit operation implementation provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of implementing sine wave driving by using the present disclosure according to an embodiment of the present disclosure.
  • Fig. 12 is a schematic diagram that can be used to accurately obtain the rising edge and falling edge time in TOF ranging to correct ranging accuracy according to an embodiment of the present disclosure.
  • T represents a pulse in a cycle
  • Tr represents a rise time
  • Th represents a high retention time
  • TF represents a fall time
  • T1 represents a low retention time
  • one pulse period T Tr+Th+Tf+Tl. If the trigger level of the input pulse input is used to measure the different times of the input pulse, a typical time measurement system with low cost test equipment can detect the rising transition or falling edge of the input pulse.
  • a measurement system with an input pulse of time 0.1V (corresponding to the voltage level at the 10% point of 1V) and an amplitude of 0.9V (the voltage level corresponding to the 90% point of 1V) when the trigger level is 1V can be measured
  • the rise time (Tr) and fall time (Tf) of the input pulse are of course not limited to the use of these two thresholds, 15% and 85%, 20% and 80% can also be used.
  • 20% and 80% are more optimally selected as the set thresholds.
  • the current is used as the sampling data. Similar to the result of taking the voltage as the data of the rising edge and the falling edge, this is not limited to the specific implementation process.
  • FIG. 2 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a driving circuit provided by an embodiment of the present disclosure.
  • the waveform is the requirement of light and light waves.
  • the power requirements of the laser driving operation can be obtained through the waveform conversion module, for example, the power requirements of the laser driving operation can be obtained from the waveform requirements, and then the power requirements can be converted into current requirements. Voltage can also be used. Taking current as an example here has an effect that is easy to achieve. For example, the same current can be divided into different channels by using a current mirror, which realizes the mirror copy of the current signal.
  • the copied multiple currents also provide a prerequisite for setting different thresholds for the currents of different circuits, which can save the traditional use of slope comparison signals or comparators.
  • the current here is two-way. Taking 20% of the target current and 80% of the target current as an example, the resistance of the first circuit R1 is set according to the value that can make the jump module jump at 20% of the highest current, wherein The jump module can be an even number of inverters.
  • the IDAC first outputs 20% of the target current as the first current threshold, then closes the switch S1, and adjusts the value of the adjustable resistor R1 so that the value of R1 at the moment when the output of buffer1 jumps is the follow-up value. The value used in calibrating and determining waveforms.
  • the IDAC outputs 80% of the target current as the second current threshold, then closes the switch S2, and adjusts the value of the adjustable resistor R2 so that the value of R2 at the moment when the output of buffer2 transitions is the value used in subsequent calibration and determination of the waveform
  • the jumping module may be an even number of inverters, which is also an example of an implementation manner and does not limit the specific implementation of the module.
  • the two jumping modules are buffer1 and buffer2 in FIG. 1 .
  • FIG. 3 is a schematic diagram of the structure of another driving circuit provided by the present disclosure, the current magnitude Itarget corresponding to the target optical power can be obtained through APC calibration; 0.2Itarget and 0.8Itarget are calculated according to Itarget, Adjustment, take 80% and 20% as an example to illustrate, close S1, adjust IDAC to 0.2Itarget/1000 (In the circuit design, the gain from Isense to Itarget is 1000), adjust the resistance of R1 (from small to large), when buffer1 outputs When it jumps from low level to high level, stop the adjustment of R1 through EN1, and keep the current output value of R1. Similarly, open S1, close S2, adjust IDAC to 0.8Itarget/1000, and adjust the resistance of R2 (from small to large).
  • the circuit can work as follows, open S2, close S0, the Sensor drives the driver chip to drive the laser through LVDS, and buffer1 outputs when the sampling current rises to 0.2Itarget/1000 Jump from low level to high level, XOR output high level, start TDC and start counting, this time is marked as t0, when the sampling current rises to 0.8Itarget/1000, the output of buffer2 jumps from low level to high level If it is flat, the XOR output jumps to a low level. This time is marked as t1. At this time, the counter data is latched into the register. Similarly, for the falling edge, when the current drops to 0.8Itarget/1000, the buffer2 outputs a low level.
  • XOR outputs a high level, and this moment is marked as t2.
  • buffer1 outputs a low level, and XOR outputs a low level.
  • This moment is marked as t3, and the TDC is stopped and the count result is latched into the register.
  • the thresholds are not limited to 20% and 80%.
  • the threshold correction can also be arranged in different time periods, such as power-on calibration before power-on. A fixed time period or a random time period can be selected during operation, and an adaptive time period can also be arranged during use. For example, adaptive calibration is arranged in the gap of the interval time during the use of the driving power supply, which is not limited here.
  • FIG. 4 is a schematic diagram of a driving circuit provided by the present disclosure.
  • the adjustable resistors in this embodiment are not limited to 2 circuits, but may be N circuits, where N is greater than or equal to 1.
  • This embodiment is an extension of the embodiment provided in FIG. 2 , and the principle for determining each adjustable resistance is the same as that provided by the embodiment shown in FIG. 2 , which will not be repeated here.
  • FIG. 5 is a schematic structural diagram of a driving circuit provided by an embodiment of the present disclosure.
  • a system driven by an active laser source detection is used as an example.
  • the waveform is required by the light wave, which can be obtained by
  • the waveform conversion module for example, obtains the power requirements of the laser driving operation from the waveform requirements, and then converts the power requirements into current requirements.
  • the converted waveform microcurrent waveform is used as an example to illustrate, but the actual implementation is not limited to current, and can also be used Voltage, taking current as an example here has an effect that is easy to achieve.
  • the same current can be divided into different channels by using a current mirror, which realizes the mirror copy of the current signal.
  • the current is converted into a voltage without using an additional resistance, which simplifies the circuit.
  • the copied multi-channel current also provides a prerequisite for setting different thresholds for the current of different circuits, which can save the traditional complex implementation schemes such as using a slope comparison signal or a comparator. .
  • the currents here are two circuits, and the thresholds of the two circuits are defined by the resistors R1 and R2 of the two circuits.
  • the resistance of the first circuit R1 can make the jumping module in the The 20% value of the highest current is set by jumping, and the jumping module can be an even number of inverters, and the resistance of the second circuit R2 is set according to the value that can make the jumping module jump at 80% of the highest current, wherein
  • the jumping module can be an even number of inverters, which is also an example of an implementation method and does not limit the specific implementation of the module.
  • the two jumping modules are buffer1 and buffer2 in FIG. 1 .
  • the result is calculated by the operation unit, the XOR in Figure 1 or the operation module, through which the operation module can output the action commands under different thresholds of the two circuits, the TDC can start or end the timing under the action command, and the timing results are processed.
  • Latching optionally, for a traditional trapezoidal wave, the result of the TDC count can be used to obtain the rising edge and/or falling edge time.
  • the TDC running time ensures that the entire circuit design will not generate large power consumption due to the long working time of the high-precision TDC.
  • FIG. 6 is a schematic structural diagram of another driving circuit provided by the present disclosure, which is different from FIG. 2 in that an adaptive threshold setting scheme is added in this embodiment, and the threshold can be adjusted through the use of variable resistors. Therefore, different action instructions can be obtained according to the adjusted threshold, and the scene can also be adaptively adjusted.
  • the current size Itarget corresponding to the target optical power can be obtained through APC calibration; 0.2Itarget and 0.8Itarget are calculated according to Itarget, and the resistance value of the adjustable resistor is first adjusted, here 80% and 20 % as an example to illustrate, close S1, adjust IDAC to 0.2Itarget/1000 (In the circuit design, the gain from Isense to Itarget is 1000), adjust the resistance of R1 (from small to large), when the output of buffer1 jumps from low to high Stop the adjustment of R1 through EN1 and keep the current output value of R1.
  • open S1, close S2, adjust IDAC to 0.8Itarget/1000, adjust the resistance of R2 (from small to large), when buffer2 outputs a low level
  • the adjustment of R2 is stopped through EN2, and the current output value of R2 is maintained.
  • the confirmation of the resistance value of the adjustable resistor under low current is realized, which ensures that the energy consumption during the whole adjustment process is small. , and also rationalizes the power consumption of the entire drive module.
  • the circuit can work as follows, open S2, close S0, the Sensor drives the driver chip to drive the laser through LVDS, and buffer1 outputs when the sampling current rises to 0.2Itarget/1000 Jump from low level to high level, XOR output high level, start TDC and start counting, this time is marked as t0, when the sampling current rises to 0.8Itarget/1000, the output of buffer2 jumps from low level to high level If it is flat, the XOR output jumps to a low level. This time is marked as t1. At this time, the counter data is latched into the register. Similarly, for the falling edge, when the current drops to 0.8Itarget/1000, the buffer2 outputs a low level.
  • XOR outputs a high level, and this moment is marked as t2.
  • buffer1 outputs a low level, and XOR outputs a low level.
  • This moment is marked as t3, and the TDC is stopped and the count result is latched into the register.
  • This working process is similar to the working process in Figure 2, and is described here from the perspective of the driving scheme in the driving chip.
  • the above thresholds are not limited to 20% and 80%, and the threshold correction can also be arranged at different times. period, such as power-on calibration before power-on, fixed time or random time period can be selected during equipment operation, or adaptive time period can be arranged during use, for example, adaptive calibration can be arranged in the interval of driving power supply use. , which is not limited here.
  • FIG. 7 is a schematic structural diagram of another driving circuit provided by an embodiment of the present disclosure, which is the same as the working principle of FIG. 2 and FIG. 3 , and will not be described in detail here.
  • the current mirror here can divide the current into For the structure of more than two channels, it can adaptively drive the transmission of non-traditional waveforms and the calibration adjustment in the process, such as sine wave, we can set multiple calibration points in half wave or 1/4 band, such as setting 3, 4, 5 or 6 multiple correction points, and then realize the accurate correction of the driving current, so that the driving chip can output accurate driving energy, and complete the efficient and accurate driving target of the driving circuit.
  • Two points can be set in the specific work.
  • An OR operation is performed between the two points to determine the relative interval time between the two points, and it is not limited here to specifically perform an OR operation between the two points.
  • the laser source is optimally selected as a diode-type light-emitting source, such as a vertical cavity surface diode emitter VCSEL, and the driving module needs to be optically based on power light waveforms, etc.
  • the characteristic requires the output of accurate driving power. For example, for the traditional trapezoidal pulse wave, it will become crucial to accurately obtain the rising edge and falling edge time of the waveform. For example, use the APC calibration illustrated in Figure 3 to obtain the current requirement corresponding to the target waveform.
  • the actual current is connected to the drive circuit module in the form of feedback, so that the entire drive chip has the function of automatically calibrating and correcting the emitted light, so that the system will not need an external separate sampling device to convert the rising edge and falling edge time of the current. Precise positioning ensures that the waveform emitted by the laser source driven by the entire driver chip is always in an accurate effect.
  • FIG. 9 is a schematic diagram of storage of time information obtained by a TDC provided by an embodiment of the present disclosure; when the TDC measures a rising edge or a falling edge or other wave calibration time period information, the measurement result needs to be stored, and here after the TDC Take the 8-bit TDC output as an example, when the TDC outputs the rising edge time, it outputs the converted 8-bit binary code segment, and the register also receives the 8-bit storage code segment.
  • the register also The identification information code segment may optionally be included, which is not limited here. For example, under the premise of the information obtained in FIG. rising edge time and falling edge time.
  • FIG. 10 is a schematic diagram of a circuit operation implementation provided by an embodiment of the present disclosure.
  • the current magnitude Itarget corresponding to the target optical power is obtained, that is, the target optical waveform is converted into a current demand, and the variable resistance value is adjusted to maintain the realization
  • the thresholds of the two sampling circuits are set, and the target waveform includes a rising edge phase and a falling edge phase. Therefore, in order to accurately drive the light-emitting unit to output the correct waveform, it is necessary to accurately obtain the rising edge and falling edge time.
  • the jump module 1buffer1 When the threshold value of the first sampling circuit When it is reached, the jump module 1buffer1 outputs a high level, and the second threshold has not yet been reached, so the OR operation result through the operation unit will be true, and the subsequent circuit will work at this time, that is, the TDC at this time starts to count, and as the When the time increases, the threshold value of the second sampling circuit is also reached. At this time, the false value result of 0 can be obtained through the OR operation of the operation module. At this time, the counter will stop working, so the time of the rising edge will be obtained, and the time of the falling edge and the rising edge will be obtained. The time is similar and will not be described in detail here.
  • FIG. 11 is a schematic diagram of implementing sine wave driving using the present disclosure provided by an embodiment of the present disclosure; here, six sampling points are set in a 1/4 wavelength range as an example, but the zero point is generally not calibrated, so the actual sampling point is required. For 5 points, use a current mirror or similar device to achieve multi-channel signal replication, and then perform OR operation on any two channels to determine a plurality of relative time information, and use the obtained time information to complete the calibration of the driving device. Here It is also not limited that 5 or more sampling points can be set in the half-wave cycle to complete the calibration.
  • FIG. 12 is a schematic diagram that can be used to accurately obtain the rising edge and falling edge time in TOF ranging to correct ranging accuracy according to an embodiment of the present disclosure.
  • ranging there are also problems due to uncertainty of the rising edge or the falling edge. Causes the phenomenon that the distance measurement has a certain error. Therefore, in the scenario that requires high-precision detection, using the similar principle of the present disclosure to obtain the accurate rising edge and/or falling edge time, and completing the calibration of the accurate detection is also an application of the present disclosure. , the acquisition principle will not be described in detail here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Electronic Switches (AREA)

Abstract

一种驱动电路，包括：目标波形转化部，配置成将目标波形信息转化为电流或电压信号；转化后的所述电流或电压信号输出至第一采样电路和第二采样电路；运算模块，所述运算模块依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令；TDC模块，依照所述运算模块输出的动作指令输出计数区间的时间参数。通过该电路可以自动地获取到预定区间的时间信息，例如上升沿或者下降沿的时间信息，从而可用于校准发射或者在飞行时间测距方案中校准最终的测距结果，使得发射源发射光波形更准确或者测距结果更准确。

Description

一种驱动电路和驱动方法
相关申请的交叉引用
本公开要求于2020年08月31日提交中国专利局的申请号为CN202010895674.8、名称为“一种驱动电路和驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
本公开要求于2020年08月31日提交中国专利局的申请号为CN202010895358.0、名称为“一种驱动电路及方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及驱动电路领域，具体而言，涉及一种驱动电路和驱动方法。
背景技术
由于一个或多个外部影响，在CPU和芯片组之间传播的信号的上升/下降时间通常会变化。这些影响包括由大量管芯上存在的工艺，电压和/或温度条件引起的硅强度的变化。未补偿的电源电压变化也会导致上升/下降时间变化。如果不加以解决，这些变化将对系统性能产生不利影响。例如，如果上升/下降时间太慢，则可能发生定时故障。相反，如果上升/下降时间太快，则可能由于大反射和过冲/下冲效应而出现信号完整性和可靠性问题，对于主动光源探测类型系统，例如以激光为光源的测距系统，驱动激光源发射特定波形的波是探测的关键，然而波形是否准确很大程度上取决于上升时间和下降时间的准确控制。
上升时间是指数字逻辑电路从低逻辑电平转换为高逻辑电平(例如“0”到“1”)的时间，下降时间是从高逻辑电平转换到低逻辑电平所需的时间(例如，“1”到“0”)。需要知道脉冲上升和下降时间(上升沿和下降沿)在规范范围内是在测量和测试应用中使用脉冲的基础。脉冲上升和/或下降时间对测试性能下所需器件的影响程度取决于器件的性质和要执行的测试类型。
大多数脉冲发生器不提供单独的上升和下降时间自包含验证，也不提供独立的上升和下降时间自动自包含调整。这种设备通常要求使用外部示波器和自动测试设备控制器或经过培训的操作员执行脉冲上升和下降时间验证。
该解决方案的一个缺点是需要示波器(额外费用)以及自动测试控制器(专用计算机和软件)或训练有素的操作员。第二个缺点是上升和下降时间电路的操作可能受操作温度 或元件老化的影响，并且可能需要连续或频繁的校正。如果需要相对复杂的测量或程序来调整这些效果，则用户可能会发现调整不方便并且在不太理想的条件下操作仪器。
另外在TOF测距过程中由于存在上升时间和下降时间，利用飞行时间所确认的被探测物距离将有一定偏差，为了获得更精确的探测结果也需要一种能够获得上升时间和下降时间的方法。
为了解决以上问题，亟需一种能够快速准确地确定被驱动的光源准确工作的波形，以实现精确探测电路和方法，并且能够实现与发射端驱动集成在一起，实现具有自检测以及校准校正的激光发射端。
发明内容
本公开的目的在于，针对上述现有技术中的不足，提供一种驱动电路和驱动方法，以便解决相关技术中，不能够对于发射端波形的精确控制或测距结果不能够实现更精确的输出的问题。
为实现上述目的，本公开实施例采用的技术方案如下：
第一方面，本公开实施例提供了一种驱动电路，其特征在于，包括：
目标波形转化部，配置成将目标波形信息转化为电流或电压信号；
转化后的所述电流或电压信号输出至第一采样电路和第二采样电路；
运算模块，所述运算模块依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令；
TDC模块，依照所述运算模块输出的动作指令输出计数区间的时间参数。
可选的，所述目标波形转化后的电流或电压信号包含上升沿和下降沿，所述TDC模块输出的计数区间的时间参数为所述上升沿和/或所述下降沿的总时间的至少部分。
可选的，所述第一采样电路具有第一输出阈值，所述第二采样电路具有第二输出阈值，且所述第一输出阈值小于所述第二输出阈值。
可选的，所述驱动电路还包含第一输出阈值和第二输出阈值调整模块，所述第一输出阈值和第二输出阈值调整模块包含可调电阻，所述可调电阻的电阻值确定所述第一输出阈值和第二输出阈值，所述可调电阻包括第一可调节电阻和第二可调节电阻。
可选的，所述驱动电路还包括第三阈值和第四阈值，根据所述第三阈值来确定所述第一可调节电阻的电阻值；根据第四阈值来确定所述第二可调节电阻的电阻值；所述第三阈值小于所述第四阈值。
可选的，所述驱动电路还包括第一开关和第二开关。当所述第一开关闭合时，根据第 三阈值确定所述第一可调节电阻的电阻值；当所述第二开关闭合时，第四阈值确定所述第二可调节电阻的电阻值。
可选的，所述驱动电路当输出第三阈值时，调节所述第一可调节电阻的电阻值直到第一跳变模块的电平发生跳变时，即可确定所述第一可调节电阻的电阻值；当输出第四阈值时，调节所述第二可调节电阻的电阻值直到第二跳变模块的电平发生跳变时，即可确定所述第二可调节电阻的电阻值。
可选的，所述第一跳变模块和/或所述第二跳变模块为偶数个反相器为偶数个反相器。
可选的，所述阈值调整模块的可调电阻的电阻值至少按照如下之一的方式调整：
开机标定、预设时间段调整以及自适应调整等等。
可选地，所述运算模块包含抑或运算单元，所述抑或运算单元依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令。
可选地，所述驱动电路还包含锁存模块，所述锁存模块锁存所述TDC模块依照所述运算模块输出的动作指令输出计数区间的时间参数。
第二方面，本公开还提供一种使用第一方面的驱动电路实现的驱动方法，包括：
目标波形转化部，配置成将目标波形信息转化为电流或电压信号；
转化后的所述电流或电压信号输出至第一采样电路和第二采样电路；
运算模块，所述运算模块依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令；
TDC模块，依照所述运算模块输出的动作指令输出计数区间的时间参数。
可选的，所述目标波形转化后的电流或电压信号包含上升沿和下降沿，所述TDC模块输出的计数区间的时间参数为所述上升沿和/或所述下降沿的总时间的至少部分。
可选的，所述第一采样电路具有第一输出阈值，所述第二采样电路具有第二输出阈值，且所述第一输出阈值小于所述第二输出阈值。
可选的，所述运算模块包含抑或运算单元，所述抑或运算单元依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令。
可选的，还包含第一输出阈值和第二输出阈值调整模块，所述第一输出阈值和第二输出阈值调整模块包含可调电阻，所述可调电阻的电阻值确定所述第一输出阈值和第二输出阈值，所述可调电阻包括第一可调节电阻和第二可调节电阻。
可选的，还包括第三阈值和第四阈值，根据所述第三阈值来确定所述第一可调节电阻的电阻值；根据第四阈值来确定所述第二可调节电阻的电阻值；所述第三阈值小于所述第四阈值。
可选地，还包括第一开关和第二开关。当所述第一开关闭合时，根据第三阈值确定所述第一可调节电阻的电阻值；当所述第二开关闭合时，第四阈值确定所述第二可调节电阻的电阻值。
可选地，还包含锁存模块，所述锁存模块锁存所述TDC模块依照所述运算模块输出的动作指令输出计数区间的时间参数。
本公开的有益效果是：本公开实施例提供一种驱动电路，其特征在于，包括：目标波形转化部，配置成将目标波形信息转化为电流或电压信号；转化后的所述电流或电压信号输出至第一采样电路和第二采样电路；运算模块，所述运算模块依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令；TDC模块，依照所述运算模块输出的动作指令输出计数区间的时间参数。本公开可以将目标波形转化为电压或电流信号，并通过两个采样电路对于目标波形转化的电压或电流信号进行处理，利用处理结果获得计数区间的时间值，与传统的电路相比不使用基准或者参考信号，也不采用比较器设计保证了电路的简便性、高效性和电路的可实现性更强的效果。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为现有技术中一种常用的典型的脉冲波形示意图；
图2为本公开实施例提供的一种驱动电路的示意图；
图3为本公开提供的另一种驱动电路的结构示意图；
图4为本公开提供的一种驱动电路示意图；
图5为本公开实施例提供的一种驱动电路的结构示意图；
图6为本公开实施例提供的另一种驱动电路的结构示意图；
图7为本公开实施例提供的又一种驱动电路的结构示意图；
图8为本公开实施例提供的一种芯片模块化示意图；
图9为本公开实施例提供的一种TDC获取的时间信息的存储示意图；
图10为本公开实施例提供的一种电路运算实现示意图；
图11为本公开实施例提供的一种利用本公开实现正弦波驱动的示意图；
图12为本公开实施例提供的一种可使用在TOF测距中准确获取上升沿和下降沿时间 以校正测距精度的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。
图1为现有技术中一种常用的典型的脉冲波形示意图，T表示在一个周期中的脉冲，Tr表示上升时间，和Th表示高的保留时间，TF表示下降时间，Tl表示低的保持时间，因此一个脉冲周期T＝Tr+Th+Tf+Tl。如果输入的脉冲输入的触发电平来测量输入脉冲的不同时间具有低成本的测试设备的典型时间测量系统能够检测输入脉冲的上升转变还是下降沿。例如，输入触发电平1V时的时间0.1V的输入脉冲(对应于1V的10％点处电压电平)的测量系统和0.9V(电压电平对应于1V的90％点)的振幅可以测量输入脉冲的上升时间(Tr)和下降时间(Tf)，当然也不限于使用这两个阈值，也可以使用15％和85％，20％和80％，经过最终探索为了保证TDC运行的时间充足保证获得的精度较高，另一方面也为了尽可能减少TDC运行时间保证电路的功耗低等等，因此此处更优地选择20％和80％作为设定阈值，当然以电流为采样数据与以电压为数据的上升沿和下降沿的结果相似，此处也不限定于具体实现过程。
图2为本公开实施例提供的一种驱动电路的示意图。如图2所示为本公开实施例提供的一种驱动电路的结构示意图，在本公开提供的实现方案中，此处以被驱动的为主动激光源探测的系统为例，其中波形为光光波要求，可以通过波形转化模块，例如由波形要求获得激光器驱动工作的功率要求，再将功率要求转化为电流要求，此处以转化后的波形微电流波形为例进行说明，但实际实现并不限于电流，也可以使用电压，此处以电流为示例具有易于实现的效果，例如利用电流镜可以将相同的电流分为不同的几路，这样实现了对于电流信号的镜像复制，也是由于该特性可以实现了直接利用镜像的电流而不使用额外电阻转化为电压，简化了电路，另外复制的多路电流也为不同电路的电流设置不同阈值提供了前提，可以省却传统的使用斜坡对比信号或者比较器等等复杂的实现方案。此处的电流为两路，此处以目标电流的20％和目标电流的80％为例，第一电路R1的电阻按照可以使跳变模块在最高电流的20％值发生跳变来设置，其中跳变模块可以为偶数个反向器，IDAC首先输出目标电流的20％作为第一电流阈值，然后闭合开关S1，调节可调节电阻R1的值使得buffer1的输出发生跳变时刻R1的值就是后续在校准和确定波形中使用的值。同理IDAC输出目标电流的80％作为第二电流阈值，然后闭合开关S2，调节可调节电阻R2的 值使得buffer2的输出发生跳变时刻R2的值就是后续在校准和确定波形中使用的值，其中跳变模块可以为偶数个反向器，此处也是一种实现方式的示例说明并不限定具体的模块实现方式，两个跳变模块为图1中的buffer1和buffer2。
图3为本公开提供的另一种驱动电路的结构示意图，可以通过APC校准，得到目标光功率对应的电流大小Itarget；根据Itarget计算出0.2Itarget和0.8Itarget，首先对于可调电阻的阻值进行调整，此处以80％和20％为例进行说明，将S1闭合，调整IDAC至0.2Itarget/1000(电路设计中Isense到Itarget增益为1000)，调节R1电阻(由小到大)，当buffer1输出由低电平跳变为高电平时通过EN1停止R1的调节，并保持R1当前输出值，同理，断开S1，闭合S2，调整IDAC至0.8Itarget/1000，调节R2电阻(由小到大)，当buffer2输出低电平跳变为高电平时通过EN2停止R2的调节，并保持R2当前输出值，通过该调整步骤，实现了在低电流下对于可调电阻阻值的确认，保证了整个调整过程中能耗较小，也合理化了整个驱动模块的功耗。当可变电阻的阻值被保持固定化之后，该电路可以按照如下的方式工作，断开S2，闭合S0，Sensor通过LVDS驱动Driver芯片驱动激光器，当采样电流上升到0.2Itarget/1000时buffer1输出由低电平跳变为高电平，XOR输出高电平，启动TDC并开始计数，此时刻记为t0，当采样电流上升到0.8Itarget/1000时buffer2输出由低电平跳变为高电平，XOR输出跳变为低电平，此时刻记为t1，此时将计数器数据锁存到寄存器中，同理，对于下降沿，电流先下降到0.8Itarget/1000时buffer2输出低电平，XOR输出高电平，此时刻记为t2，电流下降到0.2Itarget/1000时buffer1输出低电平，XOR输出低电平，此时刻记为t3，停止TDC并将计数结果锁存到寄存器中，此处以驱动芯片内的驱动方案角度进行描述，当然上述阈值并不限定于一定为20％和80％，对于阈值的校正也可以安排在不同的时间段，例如在开机之前进行开机标定，在设备运行中可以选择固定时间或者随机时间段，也可以在使用过程中进行自适应时间段安排，例如驱动电源使用中间隔时间的空隙中安排自适应校准，此处也不进行限定。
图4为本公开提供的一种驱动电路示意图，与图2实施列的差别在于本实施列的可调节电阻不限于2路，可以是N路，N大于等于1。本实施列是图2提供的实施列的一种扩展情况，每个可调节电阻的确定原理和图2实施列提供的原理相同，这里就不再赘述。
图5为本公开实施例提供的一种驱动电路的结构示意图，在本公开提供的实现方案中，此处以被驱动的为主动激光源探测的系统为例，其中波形为光光波要求，可以通过波形转化模块，例如由波形要求获得激光器驱动工作的功率要求，再将功率要求转化为电流要求，此处以转化后的波形微电流波形为例进行说明，但实际实现并不限于电流，也可以使用电压，此处以电流为示例具有易于实现的效果，例如利用电流镜可以将相同的电流分为不同 的几路，这样实现了对于电流信号的镜像复制，也是由于该特性可以实现了直接利用镜像的电流而不使用额外电阻转化为电压，简化了电路，另外复制的多路电流也为不同电路的电流设置不同阈值提供了前提，可以省却传统的使用斜坡对比信号或者比较器等等复杂的实现方案。结合图1，此处的电流为两路，通过两路的电阻R1和R2来限定两路的阈值，此处以80％和20％为例，第一电路R1的电阻按照可以使跳变模块在最高电流的20％值发生跳变来设置，其中跳变模块可以为偶数个反向器，第二电路R2的电阻按照可以使跳变模块在最高电流的80％值发生跳变来设置，其中跳变模块可以为偶数个反向器，此处也是一种实现方式的示例说明并不限定具体的模块实现方式，两个跳变模块为图1中的buffer1和buffer2，两个跳变模块的的结果通过运算单元进行运算，图1中的XOR抑或运算模块，通过该运算模块可以输出两个电路不同阈值下的动作指令，TDC可以在该动作指令下开始或者结束计时，并将计时结果进行锁存，可选地，对于传统梯形波，此时可以利用该TDC计数的结果实现对于上升沿和/或下降沿时间的获取，为了保证计时的准确性，需要保证TDC的计时精度，例如本公开可以使用50皮秒级别的计时器来进行计时操作，当然也可以采用其他类似的皮秒级计数器保证计时准确性，此处并不限定，通过运算模块的动作指令保证了皮秒级精度的TDC运行时间，进而确保了整个电路设计不会因为高精度的TDC工作时间较长而产生较大的功耗。
图6为本公开提供的另一种驱动电路的结构示意图，和图2不同在于，在本实施例中增加了自适应阈值设定方案，通过可变电阻的使用，进而对于阈值可以进行调整，从而依据调整后的阈值获得不同的动作指令，也能对于场景进行适应性调整。与图2产生波形机理类似，可以通过APC校准，得到目标光功率对应的电流大小Itarget；根据Itarget计算出0.2Itarget和0.8Itarget，首先对于可调电阻的阻值进行调整，此处以80％和20％为例进行说明，将S1闭合，调整IDAC至0.2Itarget/1000(电路设计中Isense到Itarget增益为1000)，调节R1电阻(由小到大)，当buffer1输出由低电平跳变为高电平时通过EN1停止R1的调节，并保持R1当前输出值，同理，断开S1，闭合S2，调整IDAC至0.8Itarget/1000，调节R2电阻(由小到大)，当buffer2输出低电平跳变为高电平时通过EN2停止R2的调节，并保持R2当前输出值，通过该调整步骤，实现了在低电流下对于可调电阻阻值的确认，保证了整个调整过程中能耗较小，也合理化了整个驱动模块的功耗。当可变电阻的阻值被保持固定化之后，该电路可以按照如下的方式工作，断开S2，闭合S0，Sensor通过LVDS驱动Driver芯片驱动激光器，当采样电流上升到0.2Itarget/1000时buffer1输出由低电平跳变为高电平，XOR输出高电平，启动TDC并开始计数，此时刻记为t0，当采样电流上升到0.8Itarget/1000时buffer2输出由低电平跳变为高电平，XOR输出跳变为低电平，此时刻记为 t1，此时将计数器数据锁存到寄存器中，同理，对于下降沿，电流先下降到0.8Itarget/1000时buffer2输出低电平，XOR输出高电平，此时刻记为t2，电流下降到0.2Itarget/1000时buffer1输出低电平，XOR输出低电平，此时刻记为t3，停止TDC并将计数结果锁存到寄存器中，这一工作过程和图2的工作过程类似，此处以驱动芯片内的驱动方案角度进行描述，当然上述阈值并不限定于一定为20％和80％，对于阈值的校正也可以安排在不同的时间段，例如在开机之前进行开机标定，在设备运行中可以选择固定时间或者随机时间段，也可以在使用过程中进行自适应时间段安排，例如驱动电源使用中间隔时间的空隙中安排自适应校准，此处也不进行限定。
图7为本公开实施例提供的又一种驱动电路的结构示意图，与图2和图3的工作原理相同，此处不再详细赘述，需要说明的是，此处的电流镜可以将电流分为多于两路的结构，这样可以适应性驱动非传统波形的特殊波形的发射和过程中的校准调整，例如正弦波，我们可以在半波或者1/4波段设置多个校正点，例如设置3、4、5或6等等多个校正点，进而实现驱动电流的精确校正，进而使得驱动芯片输出精确的驱动能量，完成驱动电路的高效准确驱动目标，在具体工作中可以设置两个点之间进行抑或运算进而确定两个点之间的相对间隔时间，此处也不限定具体哪两个点之间抑或运算。
图8为本公开实施例提供的一种芯片模块化示意图；激光源最优地选择为二极管类型的发光源，例如可以为垂直腔面二极管发射器VCSEL，驱动模块需要依照功率光波形等等光学特性要求输出准确的驱动功率，例如对于传统的梯形脉冲波，准确获得波形的上升沿和下降沿时间将变得至关重要，例如使用图3所阐述的APC校准获得目标波形对应的电流需求，再将实际电流以反馈形式接入驱动电路模块中，这样整个驱动芯片就具有了自动校准校对发射光的功能，这样系统将不需要外部单独的采样设备对转化后的电流上升沿和下降沿时间进行精确定位，保证了整个驱动芯片驱动激光源发射的波形始终处于准确的效果。
图9为本公开实施例提供的一种TDC获取的时间信息的存储示意图；当TDC测量到上升沿或下降沿或者其他波校对时间段信息之后需要对测量的结果进行存储，此处以在TDC之后连接寄存器REG为例，以8位的TDC输出为例，当TDC输出上升沿时间时，其输出的是转化之后的8位二进制码段，寄存器也以8位的存储码段接收，当然寄存器也可以可选地包含识别信息码段，此处不限定，例如可以在图3获得的信息结果前提下按照Tr＝t1-t0，Tf＝t3-t2,T＝t2-t0，如此可获得精确的上升沿时间和下降沿时间。
图10为本公开实施例提供的一种电路运算实现示意图；通过APC校准，得到目标光功率对应的电流大小Itarget，也就是将目标光波形转化为电流需求，利用可变电阻阻值调整保持实现两个采样电路的阈值设定，目标的波形包含上升沿阶段和下降沿阶段，所以为 了准确驱动发光单元输出正确的波形，需要准确获得上升沿和下降沿的时间，当第一采样电路的阈值达到时，跳变模块1buffer1输出高电平，此时第二阈值还未达到，所以通过运算单元的抑或运算结果将为真，此时后续电路工作，也就是此时的TDC开始计数，随着时间的增加第二采样电路的阈值也达到，此时通过运算模块的抑或运算可以得到0的假值结果，此时计数器将停止工作，如此将获得上升沿的时间，获得下降沿时间与上升沿时间类似，此处不再详细赘述。
图11为本公开实施例提供的一种利用本公开实现正弦波驱动的示意图；此处以1/4波长范围内设置六个采样点为例，但是0点一般不进行校对，因此实际需要采样的为5个点，利用电流镜或者类似装置实现多路的信号复制，再通过任意两路进行抑或运算确定多个相对的时间信息，利用获得的时间信息可以完成对于驱动装置的校准校对，此处也不限定也可以在半波周期设置5个或者多个采样点进而完成校准。
图12为本公开实施例提供的一种可使用在TOF测距中准确获取上升沿和下降沿时间以校正测距精度的示意图，在测距过程中也存在由于上升沿或者下降沿不确定而造成测距具有一定误差的现象，因而对于需要高精度探测的场景下，利用本公开类似的原理获取到准确的上升沿和/或下降沿时间，完成精确探测的校准也是本公开的一种应用，此处不再详细赘述获取原理。
需要说明的是，在本文中，诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换和/或改进等，均应包含在本公开的保护范围之内。应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换和/或改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种驱动电路，其特征在于，包括：
    目标波形转化部，配置成将目标波形信息转化为电流或电压信号；
    转化后的所述电流或电压信号输出至第一采样电路和第二采样电路；
    运算模块，所述运算模块依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令；
    TDC模块，依照所述运算模块输出的动作指令输出计数区间的时间参数。
  2. 根据权利要求1所述的驱动电路，其特征在于，所述目标波形转化后的电流或电压信号包含上升沿和下降沿，所述TDC模块输出的计数区间的时间参数为所述上升沿和/或所述下降沿的总时间的至少部分。
  3. 根据权利要求1所述的驱动电路，其特征在于，所述第一采样电路具有第一输出阈值，所述第二采样电路具有第二输出阈值，且所述第一输出阈值小于所述第二输出阈值。
  4. 根据权利要求3所述的驱动电路，其特征在于，所述运算模块包含第一跳变模块和第二跳变模块，当所述第一采样电路达到第一输出阈值时，所述第一跳变模块电平跳变；当所述第二采样电路达到第二输出阈值时，所述第二跳变模块电平跳变。
  5. 根据权利要求3所述的驱动电路，其特征在于，所述驱动电路还包含第一输出阈值和第二输出阈值调整模块，所述第一输出阈值和第二输出阈值调整模块包含可调电阻，所述可调电阻的电阻值确定所述第一输出阈值和第二输出阈值，所述可调电阻包括第一可调节电阻和第二可调节电阻。
  6. 根据权利要求5所述的驱动电路，其特征在于，所述驱动电路还包括第三阈值和第四阈值，根据所述第三阈值来确定所述第一可调节电阻的电阻值；根据第四阈值来确定所述第二可调节电阻的电阻值；所述第三阈值小于所述第四阈值。
  7. 根据权利要求6所述的驱动电路，其特征在于，所述驱动电路还包括第一开关和第二开关；当所述第一开关闭合时，根据第三阈值确定所述第一可调节电阻的电阻值；当所述第二开关闭合时，第四阈值确定所述第二可调节电阻的电阻值。
  8. 根据权利要求5所述的驱动电路，其特征在于，所述驱动电路当输出第三阈值时，调节所述第一可调节电阻的电阻值直到第一跳变模块的电平发生跳变时，即能确定所述第一可调节电阻的电阻值；当输出第四阈值时，调节所述第二可调节电阻的电阻值直到第二跳变模块的电平发生跳变时，即能确定所述第二可调节电阻的电阻值。
  9. 根据权利要求4所述的驱动电路，其特征在于，所述第一跳变模块和/或所述第二跳变模块为偶数个反相器为偶数个反相器。
  10. 根据权利要求5所述的驱动电路，其特征在于，所述阈值调整模块的可调电阻的电阻值至少按照如下之一的方式调整：
    开机标定、预设时间段调整以及自适应调整。
  11. 根据权利要求1所述的驱动电路，其特征在于，所述运算模块包含抑或运算单元，所述抑或运算单元依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令。
  12. 根据权利要求1所述的驱动电路，其特征在于，所述驱动电路还包含锁存模块，所述锁存模块锁存所述TDC模块依照所述运算模块输出的动作指令输出计数区间的时间参数。
  13. 一种使用权利要求1所述的驱动电路实现的驱动方法，其特征在于，包括：
    目标波形转化部，配置成将目标波形信息转化为电流或电压信号；
    转化后的所述电流或电压信号输出至第一采样电路和第二采样电路；
    运算模块，所述运算模块依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令；
    TDC模块，依照所述运算模块输出的动作指令输出计数区间的时间参数。
  14. 根据权利要求13所述的驱动方法，其特征在于，所述目标波形转化后的电流或电压信号包含上升沿和下降沿，所述TDC模块输出的计数区间的时间参数为所述上升沿和/或所述下降沿的总时间的至少部分。
  15. 根据权利要求13所述的驱动方法，其特征在于，所述第一采样电路具有第一输出阈值，所述第二采样电路具有第二输出阈值，且所述第一输出阈值小于所述第二输出阈值。
  16. 根据权利要求13所述的驱动方法，其特征在于，所述运算模块包含抑或运算单元，所述抑或运算单元依照所述第一采样电路和所述第二采样电路的输出结果输出动作指令。
  17. 根据权利要求15所述的驱动方法，其特征在于，还包含第一输出阈值和第二输出阈值调整模块，所述第一输出阈值和第二输出阈值调整模块包含可调电阻，所述可调电阻的电阻值确定所述第一输出阈值和第二输出阈值，所述可调电阻包括第一可调节电阻和第二可调节电阻。
  18. 根据权利要求15所述的驱动方法，其特征在于，还包括第三阈值和第四阈值，根据所述第三阈值来确定所述第一可调节电阻的电阻值；根据第四阈值来确定所述第二可调节电阻的电阻值；所述第三阈值小于所述第四阈值。
  19. 根据权利要求16所述的驱动方法，其特征在于，还包括第一开关和第二开关；当所述第一开关闭合时，根据第三阈值确定所述第一可调节电阻的电阻值；当所述第二开关闭合时，第四阈值确定所述第二可调节电阻的电阻值。
  20. 根据权利要求13所述的驱动方法，其特征在于，还包含锁存模块，所述锁存模块锁存所述TDC模块依照所述运算模块输出的动作指令输出计数区间的时间参数。
PCT/CN2020/136586 2020-08-31 2020-12-15 一种驱动电路和驱动方法 WO2022041582A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/042,751 US20230297034A1 (en) 2020-08-31 2020-12-15 Drive circuit and drive method

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN202010895674.8 2020-08-31
CN202010895358.0A CN114122891A (zh) 2020-08-31 2020-08-31 一种驱动电路及方法
CN202010895358.0 2020-08-31
CN202010895674.8A CN114124078A (zh) 2020-08-31 2020-08-31 一种驱动电路和驱动方法

Publications (1)

Publication Number Publication Date
WO2022041582A1 true WO2022041582A1 (zh) 2022-03-03

Family

ID=80352520

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/136586 WO2022041582A1 (zh) 2020-08-31 2020-12-15 一种驱动电路和驱动方法

Country Status (2)

Country Link
US (1) US20230297034A1 (zh)
WO (1) WO2022041582A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116609578A (zh) * 2023-07-06 2023-08-18 深圳柯力三电科技有限公司 一种高精度数字电流传感器及其测试方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030076251A1 (en) * 2001-10-19 2003-04-24 Deepnarayan Gupta Superconducting dual function digitizer
CN201795819U (zh) * 2010-06-10 2011-04-13 宁波大学 一种时差法超声流量计静态漂移抑制模型
CN103825612A (zh) * 2014-01-17 2014-05-28 电子科技大学 基于时间数字转换器的采样时钟失配后台校正方法
CN110708047A (zh) * 2019-08-29 2020-01-17 上海御渡半导体科技有限公司 一种基于tdc芯片测量高速比较器精度的结构及方法
CN111474571A (zh) * 2020-05-29 2020-07-31 明峰医疗系统股份有限公司 基于SiPM的PET探测器前端电路在线自检装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030076251A1 (en) * 2001-10-19 2003-04-24 Deepnarayan Gupta Superconducting dual function digitizer
CN201795819U (zh) * 2010-06-10 2011-04-13 宁波大学 一种时差法超声流量计静态漂移抑制模型
CN103825612A (zh) * 2014-01-17 2014-05-28 电子科技大学 基于时间数字转换器的采样时钟失配后台校正方法
CN110708047A (zh) * 2019-08-29 2020-01-17 上海御渡半导体科技有限公司 一种基于tdc芯片测量高速比较器精度的结构及方法
CN111474571A (zh) * 2020-05-29 2020-07-31 明峰医疗系统股份有限公司 基于SiPM的PET探测器前端电路在线自检装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116609578A (zh) * 2023-07-06 2023-08-18 深圳柯力三电科技有限公司 一种高精度数字电流传感器及其测试方法
CN116609578B (zh) * 2023-07-06 2024-04-16 深圳柯力三电科技有限公司 一种高精度数字电流传感器及其测试方法

Also Published As

Publication number Publication date
US20230297034A1 (en) 2023-09-21

Similar Documents

Publication Publication Date Title
US5082363A (en) Optical distance measuring apparatus and method using light projection pulses
TWI661211B (zh) 距離感測裝置及其方法
US11397249B2 (en) Light detection device and electronic apparatus comprising a reverse bias voltage adjustment in accordance with a pulse number output by a first SPAD array
US10302747B2 (en) Distance measuring apparatus, electronic device, method for measuring distance, and recording medium
US5262837A (en) Laser range finder
CA2475850A1 (en) Apparatus and method for measurement of dynamic laser signals
CN111157976B (zh) 一种异步高精度可调的激光距离选通信号设计方法
JPH1123709A (ja) 距離測定装置
WO2022041582A1 (zh) 一种驱动电路和驱动方法
CN114047498A (zh) 激光发射功率调整方法、装置、激光雷达及存储介质
CN114124078A (zh) 一种驱动电路和驱动方法
US20100157279A1 (en) Distance Measuring Apparatus and Control Method Thereof
CN110646804B (zh) 基于双脉冲激光信号的脉冲时刻鉴别电路
JP2018040656A (ja) 距離測定装置
CN111854679B (zh) 一种激光测距望远镜及其测距电路、方法、设备和介质
CN212324424U (zh) 一种数字式时钟的秒脉冲发生装置及测量系统
CN115480234A (zh) 电压校准方法、电路、激光雷达系统及存储介质
CN114122891A (zh) 一种驱动电路及方法
US20240183953A1 (en) Tdc apparatus, distance measuring apparatus and correction method
JP3961428B2 (ja) 測距装置
WO2019139744A1 (en) Laser distance sensing using prior measurement information
JPH11352226A (ja) 高精度測距装置
KR20200082418A (ko) 지능형 라이다 장치
CN111580121B (zh) 一种基于SiPM信号摆幅的测距方法及装置
JP2004053250A (ja) 発光タイミング検出方法、発光タイミング検出装置、及び測距装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20951248

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20951248

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20951248

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28-09-2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20951248

Country of ref document: EP

Kind code of ref document: A1