WO2022041158A1 - 一种多芯片封装结构、交换机 - Google Patents

一种多芯片封装结构、交换机 Download PDF

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Publication number
WO2022041158A1
WO2022041158A1 PCT/CN2020/112293 CN2020112293W WO2022041158A1 WO 2022041158 A1 WO2022041158 A1 WO 2022041158A1 CN 2020112293 W CN2020112293 W CN 2020112293W WO 2022041158 A1 WO2022041158 A1 WO 2022041158A1
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WIPO (PCT)
Prior art keywords
switch chip
chip
switch
interface
data
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PCT/CN2020/112293
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English (en)
French (fr)
Inventor
杜文华
张帆
刘永志
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/112293 priority Critical patent/WO2022041158A1/zh
Priority to EP20950828.2A priority patent/EP4195617A4/en
Priority to CN202080104690.9A priority patent/CN116250220A/zh
Publication of WO2022041158A1 publication Critical patent/WO2022041158A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/66—Layer 2 routing, e.g. in Ethernet based MAN's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric

Definitions

  • the present application relates to the field of chip technology, and in particular, to a multi-chip packaging structure and a switch.
  • a switch is a network device for forwarding electrical signals or optical signals.
  • the switch is provided with multiple interfaces, and data transmission can be realized through any one of the multiple interfaces.
  • the most common switches are Ethernet switches that transmit data over Ethernet.
  • the interface of the switch can be directly connected to the host.
  • the switch can connect multiple pairs of interfaces at the same time, so that each pair of hosts that communicate with each other can transmit data without collision.
  • the switch is provided with a switch chip, and the exchange capacity of the switch chip can determine the data exchange capability of the switch.
  • the switching capabilities of switches required by different types of users are also different. As a result, it is necessary to manufacture switch chips with corresponding switching capabilities according to the needs of different users, which is not conducive to reducing production costs.
  • the embodiments of the present application provide a multi-chip packaging structure and a switch, which are used to solve the problem of high manufacturing cost that switches with different switching capabilities need to be prepared with switch chips with corresponding switching capabilities.
  • a multi-chip packaging structure includes a package substrate and at least a plurality of switch chips disposed on the package substrate.
  • the switch chip includes at least two network interfaces, and at least one chip-to-chip D2D interface.
  • the switch chip is used for accessing the network through at least two network interfaces, and sending and receiving data with the network.
  • the switch chip is also used for connecting with one other switch chip through each D2D interface in the at least one D2D interface, and sending and receiving data between them.
  • the switch chip is further configured to forward data received from the at least two network interfaces or the at least one D2D interface to at least one of the at least two network interfaces and the at least one D2D interface.
  • the switching bandwidth of the switch chip is the actual switching bandwidth of the switch.
  • the D2D interface of the switch chip may be in a vacant state without being electrically connected with other chips.
  • the actual switching bandwidth of the switch is the sum of the switching bandwidths of the internal switch chips. In this way, in the solution provided by the embodiment of the present application, in order to obtain switches with different switching bandwidths, it is not necessary to separately manufacture corresponding switch chips for different switching bandwidths.
  • the switching bandwidth of the multi-chip packaging structure can be made the sum of the switching bandwidths of all switch chips in the multi-chip packaging structure, so that the switching bandwidth of the entire switch can be made larger, for example, it can reach 50Tbps, 100 Tbps or even larger .
  • the switch chip further includes control logic, and the control logic is used for: acquiring purpose information of the received data from the received data. Then, the sending port is determined according to the purpose information, and the sending port includes at least one D2D interface and at least two network interfaces in the current switch chip, and then the received data is sent through the sending port. Therefore, the switch chip can realize the data forwarding and exchange process.
  • the multiple switch chips include a source switch chip and a destination switch chip.
  • the control logic of the source switch chip is further used to: determine at least one sending path between the source switch chip and the destination switch chip, queue and cache the received data, and send the data to the destination switch chip. Send a scheduling request.
  • the control logic of the destination switch chip is also used to: generate the scheduling result according to the scheduling request and the bandwidth of the destination switch chip; the control logic of the source switch chip is also used for : According to the scheduling result, the received data is dequeued from the queue, and the received data is sent to the destination switch chip through at least one sending path.
  • multiple switch chips can exchange data between multiple electrically connected switch chips by sending scheduling requests, generating scheduling results, and sending data according to the scheduling results.
  • the multi-chip package structure includes four switch chips.
  • Each switch chip includes two D2D interfaces for connecting with the D2D interfaces of the other two switch chips respectively.
  • the four switch chips are electrically connected in sequence. In this way, the two switch chips that are electrically connected to each other are adjacent to each other, so the length of the metal leads used to electrically connect the two adjacent switch chips together may not be too long, so that the signal transmission efficiency can be improved.
  • the source switch chip is adjacent to the destination switch chip.
  • the control logic of the source switch chip is specifically used to: determine a sending path, and send the received data to the destination switch chip through the sending path; wherein, the sending path includes: from the source switch chip to the destination switch chip. In this way, data forwarding between adjacent switch chips can be implemented through the above-mentioned sending paths.
  • an intermediate switch chip is spaced between the source switch chip and the destination switch chip.
  • the control logic of the source switch chip is specifically used to: determine a sending path, and send the received data to the destination switch chip through the sending path; wherein, the sending path includes: from the source switch chip, through the intermediate switch chip to the destination switch chip.
  • a first intermediate switch chip is spaced between the source switch chip and the destination switch chip
  • a second intermediate switch chip is spaced between the source switch chip and the destination switch chip. an intermediate switch chip; wherein the first direction and the second direction are opposite.
  • the control logic of the source switch chip is specifically used to: determine the first sending path, and send a part of the received data to the destination switch chip through the first sending path.
  • the first sending path includes: from the source switch chip to the destination switch chip through the first intermediate switch chip.
  • the determined second sending path sends another part of the received data to the destination switch chip through the second sending path.
  • the second sending path includes: from the source switch chip to the destination switch chip through the second intermediate switch chip.
  • the switch chip further includes a switch buffer unit and a transmission link.
  • the exchange buffer unit is used for executing the above-mentioned control logic of sending the scheduling request, generating the scheduling result, and sending data according to the scheduling result.
  • the transmission link is electrically connected with the D2D interface and the switching buffer unit, and the transmission link is used for sending and receiving data between the D2D interface and the switching buffer unit, as well as between different D2D interfaces. Data exchanged between multiple switch chips can be transmitted through a transmission link.
  • the transmission link includes a first link and a second link.
  • the first link includes a first receiver MAC interface, a first buffer, and a first transmitter MAC interface that are electrically connected in sequence.
  • the first receiving end MAC interface and the first transmitting end MAC interface are respectively electrically connected with the two D2D interfaces of the switch chip.
  • the first receiving end MAC interface and the first buffer are also electrically connected with the switching buffer unit.
  • the MAC interfaces of the first receiving end and the MAC of the first transmitting end of the plurality of switch chips in the switch are electrically connected in sequence, so that the first links of the plurality of switch chips can be electrically connected, so that the data of the plurality of switch chips can be electrically connected.
  • the transmission can take place in different switch chips through the first link.
  • the data buffered in the first buffer can be queued in the first buffer in a FIFO manner, and sent to the first sending end MAC interface of the switch chip, so as to avoid data from the first receiving end MAC interface and Data conflict for output cache processing unit.
  • the transmission direction of data in the second link is opposite to the transmission direction of data in the first link.
  • the second link includes a second receiver MAC interface, a second buffer, and a second transmitter MAC interface that are electrically connected in sequence.
  • the second receiving end MAC interface and the second transmitting end MAC interface are respectively electrically connected to the two D2D interfaces of the switch chip.
  • the second receiver MAC interface and the second buffer are also electrically connected to the switching buffer unit.
  • the technical effects of the second link and the second buffer can be obtained in the same way, which will not be repeated here.
  • the transmission direction of data in the second link is opposite to the transmission direction of data in the first link, when data is forwarded between non-adjacent switch chips in the switch, a part of the data traffic can be transmitted along the first link.
  • the other part of the traffic can be forwarded along the second link to improve the data transmission efficiency.
  • the four switch chips are arranged in a 2 ⁇ 2 matrix.
  • the first links of the four switch chips are electrically connected end to end in a ring shape.
  • the second links of the four switch chips are electrically connected end to end in a ring shape.
  • one switch chip can be electrically connected to its left (or right) and the other switch chip on the upper (or lower) side through the first link and the second link. Since the two switch chips that are electrically connected to each other are adjacent to each other, the length of the metal leads used to electrically connect the two adjacent switch chips together may not be too long, so that the signal transmission efficiency can be improved.
  • the switch chip further includes a forwarding processing unit, a third receiving end MAC interface, and a third transmitting end MAC interface.
  • the forwarding processing unit is configured to execute the above control logic for data forwarding. For example, according to the source address of the data from the network interface, the destination address of the data is obtained, and the data is written into the exchange buffer unit.
  • the forwarding processing unit can read the source MAC address in the header of the data packet, then read the destination MAC address in the header of the data packet, and search the MAC address table for the destination MAC address. corresponding interface.
  • the forwarding processing unit can read the source IP address in the packet header, and then read the destination IP address in the packet header, and search the IP address table for the destination IP address.
  • the forwarding processing unit is electrically connected with the network interface and the switching buffer unit. The forwarding processing unit is used for reading data from the switching buffer unit and sending it to the network interface.
  • the forwarding processing unit needs to change the source MAC address and the destination MAC address in the packet header to complete the Layer 2 encapsulation.
  • the third receiver MAC interface is electrically connected to the network interface and the forwarding processing unit, and is used for transmitting data from the network interface to the forwarding processing unit.
  • the third sending end MAC interface is electrically connected with the network interface and the forwarding processing unit, and is used for transmitting data from the forwarding processing unit to the network interface.
  • the multi-chip packaging structure Multi-chip packaging structure
  • the multi-chip packaging structure is optional, in the multi-chip packaging structure, the switching bandwidth of any two switch chips is the same. In this way, only one type of switch chip needs to be produced, and the number of switch chips in the switch needs to be set according to the switching bandwidth requirements of the switch, and multiple switch chips with the same switching bandwidth can be electrically connected through their respective D2D interfaces. A series of switches with different switching bandwidths can be obtained to reduce costs.
  • the multi-chip package structure further includes a plurality of optical modules disposed on the package substrate and located on the same side as the switch chip.
  • the switch can have an optical interface with a larger switching bandwidth.
  • the switch includes a circuit board and any one of the above-mentioned multi-chip packaging structures disposed on the circuit board.
  • the switch has the same technical effect as the switch chip provided in the foregoing embodiment, which is not repeated here.
  • a switch in yet another aspect of the embodiments of the present application, includes a circuit board and at least two of the above-mentioned multi-chip packaging structures disposed on the circuit board.
  • the D2D interfaces of all switch chips on the circuit board are electrically connected end to end in sequence.
  • the switch has the same technical effect as the switch chip provided in the foregoing embodiment, which is not repeated here.
  • any two switch chips have the same switching bandwidth.
  • the switching bandwidth of the switch can be the sum of the switching bandwidths of all switch chips in the switch, so that the switching bandwidth of the entire switch can be made larger, for example, 50Tbps, 100Tbps or even larger.
  • FIG. 1 is a schematic structural diagram of a switching network according to an embodiment of the present application.
  • Fig. 2 is a kind of structural schematic diagram of the switch in Fig. 1;
  • Fig. 3a is a kind of structural schematic diagram of the multi-chip package structure in Fig. 2;
  • Fig. 3b is another structural schematic diagram of the multi-chip package structure in Fig. 2;
  • FIG. 4 is another structural schematic diagram of the multi-chip package structure in FIG. 2;
  • Fig. 5 is another kind of structural schematic diagram of the switch in Fig. 1;
  • FIG. 6 is another structural schematic diagram of the multi-chip package structure in FIG. 2;
  • FIG. 7 is another structural schematic diagram of the multi-chip package structure in FIG. 2;
  • FIG. 8 is a schematic structural diagram of a switch chip provided by an embodiment of the present application.
  • FIG. 9 is another schematic structural diagram of a switch chip provided by an embodiment of the present application.
  • FIG. 10a is a schematic structural diagram of the electrical connection of a plurality of switch chips as shown in FIG. 9;
  • FIG. 10b is another schematic structural diagram of the electrical connection of a plurality of switch chips as shown in FIG. 9;
  • FIG. 11 is a flowchart of data forwarding of a switch provided by an embodiment of the present application.
  • 01-switching network 10-switch; 11-electronic equipment; 101-Ethernet interface; 20-multi-chip package structure; 201-package substrate; 12-circuit board; 202-switch chip; 30-network interface; 31-D2D 100-ring bus; 203-light engine; 40-SWB; 41-transmission link; 401-IB; 402-EB; 411-first link; 412-second link; 51-first buffer ; 52 - Second buffer.
  • first”, second, etc. are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implying the number of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • orientation terms such as “upper”, “lower”, “left” and “right” are defined relative to the orientation in which the components in the drawings are schematically placed, and it should be understood that these directional terms are Relative notions, they are used for relative description and clarification, which may vary accordingly depending on the orientation in which components are placed in the figures.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary.
  • electrical connection can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • the switching network 01 may include at least one switch 10 and a plurality of electronic devices 11 electrically connected to the switch.
  • the above-mentioned electronic device 11 may be a server, a computer, a mobile terminal, a data storage device, a network component, a network device, a router, a switch, and the like.
  • Each electronic device 11 in the above-mentioned switching network 01 may be electrically connected to one or more Ethernet interfaces 101 of the switch 10 through an Ethernet (ethernet) transmission line.
  • the above-mentioned switch 10 can provide packet forwarding between multiple physical Ethernet interfaces 101, so that each electronic device 11 in the switching network 01 can be electrically connected to each other through the switch 10, and communicate with each other. .
  • the switch 10 provided in this embodiment of the present application may include a circuit board 12 , such as a printed circuit board (PCB), and at least one chip package (package) disposed on the circuit board 12 ) structure 20.
  • the multi-chip package structure 20 may include a package substrate 201 and at least one switch die (die or chiplet) 202 disposed on the package substrate 201 .
  • any switch chip 202 in the multi-chip package structure 20 may include at least two network interfaces 30 and at least one die-to-die (D2D) interface 31 .
  • the above-mentioned network interface 30 and D2D interface 31 are used as physical layer interfaces of an open system interconnection reference model (OSI model).
  • OSI model open system interconnection reference model
  • the switch chip 202 is used for accessing a network (eg, Ethernet) through the above-mentioned at least two network interfaces 30 , and sending and receiving data with the network.
  • a network eg, Ethernet
  • the above-mentioned network interface 30 may be electrically connected to the physical Ethernet interface 101 shown in FIG. 1 , and the network interface 30 may receive data sent by each electronic device 11 in the Ethernet. Alternatively, the network interface 30 may transmit data to the respective electronic devices 11 described above.
  • the above-mentioned network interface 30 may be a serializer/deserializer (serializer-deserializer, SerDes) interface.
  • SerDes serializer-deserializer
  • the above-mentioned network interface 30 may be a SerDes interface, a very short reach (very short reach, VSR) interface for connecting a chip with a pluggable optical module.
  • VSR very short reach
  • one switch chip 202 may include at least one D2D interface 31 and at least two network interfaces 30 .
  • One switch chip 202 is connected to another switch chip through each D2D interface 31 of the at least one D2D interface 31, and is connected to two Ethernet interfaces 101 of the switch 10 through two network interfaces 30, respectively.
  • the switch chip 202 is configured to be connected to one other switch chip 202 through each D2D interface 31 of the at least one D2D interface 31, and to send and receive data between each other.
  • the switch chip 202 is further configured to forward data received from the at least two network interfaces 30 or the at least one D2D interface 31 to at least one of the at least two network interfaces 30 and the at least one D2D interface 31 .
  • one switch chip 202 includes one D2D interface 31 and two network interfaces 30 .
  • data from different network interfaces 30 can exchange data with other switch chips 202 through the D2D interface 31, and send and receive data with the ports of at least two receivers and external networks.
  • the D2D interface 31 can be used to electrically connect the two switch chips 202, that is, die to die.
  • the D2D interface 31 may be a SerDes interface, for example, the D2D may be an ultra-short reach (extreme short reach, XSR) interface in the SerDes interface for realizing electrical connection between chips, and the XSR interfaces are made between
  • the length of the traces on the PCB 12 can be 0 to 50 mm.
  • the D2D interface 31 may also be a parallel interface, for example, an advanced interface bus (AIB).
  • AIB advanced interface bus
  • the switch chip 202 may include a processor, and a forwarding processing unit in the processor may be used to execute control logic.
  • the control logic is used to obtain the purpose information of the received data from the data received by the network interface 30 or the D2D interface 31 .
  • the destination information may be the destination address of the received data.
  • the above-mentioned control logic can be used to determine the sending port according to the purpose information.
  • the sending port includes the at least one D2D interface 31 and the at least two network interfaces 30 in the current switch chip.
  • the above-mentioned control logic is further configured to send the received data through the above-mentioned sending port, so as to realize the data forwarding process.
  • the chip packaging structure 20 may be one in which the plurality of switch chips 202 are directly disposed on the packaging substrate, Multi-chip module (MCM) structure.
  • MCM Multi-chip module
  • the chip packaging structure 20 may be a 2.5D packaging structure in which a plurality of switch chips 202 are disposed on an interposer using a chip on wafer on substrate (COWOS) technology.
  • COWOS chip on wafer on substrate
  • the chip package structure 20 may be a fan-out package (FOP) technology in which multiple switch chips 202 are disposed on a redistribution layer (RDL). Fan-out package structure.
  • FOP fan-out package
  • the above-mentioned chip packaging structure 20 may be provided with connectors in the packaging substrate, and a plurality of switch chips 202 disposed on the packaging substrate are electrically connected through the connectors, an embedded multi-die interconnect bridge. interconnect bridge, EMIB) package structure.
  • EMIB embedded multi-die interconnect bridge
  • the switching bandwidth of any two switch chips on the same PCB 12 may be the same, for example, both 12.8Tpbs.
  • the setting manner of the plurality of switch chips 202 in the switch 10 will be described by way of example.
  • the switching bandwidth of the switch 10 in this application is used to measure the total data switching capability of the switch 10 .
  • the switching bandwidth of the switch 10 is 50 Tbps
  • the data transfer rate of the switch 10 is 50 megabits per second.
  • Switch 10 may include a multi-chip package structure 20 as shown in FIG. 4 .
  • the multi-chip package structure 20 may include four switch chips located on the same package substrate 201, which are switch chip 202-A, switch chip 202-B, switch chip 202-C and switch chip 202-D.
  • the switch chip 202-A, the switch chip 202-B, the switch chip 202 in the multi-chip package structure 20 -C and the switch chip 202-D may both be chips with a switching bandwidth of 12.8Tbps prepared by a 7nm (minimum line width of a transistor in a chip) chip preparation process.
  • the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the D2D interface 31 of the switch chip 202-D in the multi-chip package structure 20 are electrically connected one by one to form a ring bus. 100.
  • the D2D interface 31 of the switch chip 202-A is electrically connected to the D2D interface 31 of the switch chip 202-B.
  • the D2D interface 31 of the switch chip 202-B is electrically connected to the D2D interface 31 of the switch chip 202-C.
  • the D2D interface 31 of the switch chip 202-C is electrically connected to the D2D interface 31 of the switch chip 202-D.
  • the switch chip 202-A serving as the source switch chip can The switch chip 202-B of the destination switch chip sends data.
  • the switch chip 202-A which is the source switch chip, is sent to the destination switch chip.
  • the switch chip 202-C sends data
  • the data sent by the switch chip 202-A may be transmitted to the switch chip 202-C after passing through the switch chip 202-B as the first intermediate switch chip in a clockwise direction.
  • the data sent by the switch chip 202-A may be transmitted to the switch chip 202-C after passing through the switch chip 202-D as the second intermediate switch chip in a counterclockwise direction.
  • part of the data sent by the switch chip 202-A serving as the source switch chip may pass through the switch chip 202-B serving as the first intermediate switch chip in a clockwise direction, and then be transferred to the switch chip 202-C.
  • Another part of the above data may be transmitted to the switch chip 202-C after passing through the switch chip 202-D as the second intermediate switch chip in a counterclockwise direction.
  • the D2D interface 31 of any one of the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the switch chip 202-D may be a 128L-112G-XSR interface.
  • the 128L-112G-XSR interface represents 128 lanes of XSR interfaces, and the data transmission rate of each XSR interface is 112Gbps.
  • the above-mentioned transmission link can be used to carry the 12.8Tbps Ethernet traffic of each switch chip when transmitting data in one direction, such as receiving data or sending data.
  • the packet header of the data transmitted has an address, and the address needs to occupy some bytes.
  • scheduling instructions and scheduling results related to the data also need to be transmitted between the D2D interfaces 31 of the above-mentioned multiple switch chips.
  • the scheduling instruction and the scheduling result also need to occupy some bytes. Therefore, the above-mentioned traffic for internal consumption may be used to transmit data-related addresses, scheduling instructions, and scheduling results.
  • the margin of the traffic transmitted by the D2D interface 31 of each switch chip may be the switching bandwidth of the switch chip, for example, about 10% of 12.8 Tbps.
  • the D2D interface 31 of any switch chip can not only receive data, but also send data. Therefore, when two adjacent electrically connected D2D interfaces 31 send and receive data at the same time, the bidirectional bandwidth of the formed transmission link is two 14.3 Tbps.
  • any switch chip can be used as a source switch chip and can also be used as a destination switch chip at the same time. When four switch chips on the ring bus 100 receive and send data at the same time, the bandwidth of the transmission link formed on the ring bus 100 may be 8 (2 ⁇ 4) 14.3 Tbps. At this time, each D2D interface 31 in the multi-chip package structure 20 is in a state of sending and receiving data.
  • the total switching bandwidth actually embodied by the switch 10 externally is the sum of the switching bandwidths of the switch chips 202 inside it.
  • the switch 10 make the switch 10 have a wire-speed non-blocking switching capability of 51.2Tbps, and the switching bandwidth is greater than the preset switching bandwidth of the switch 10 (eg, 50Tbps).
  • the vertical projection shape of the switch chip 202 on the packaging substrate 201 or the PCB in the embodiment of the present application may be a rectangle or a square, which is not limited in the embodiment of the present application.
  • the switch chip 202-A and the switch chip 202-B are , the short side L1 of any one of the switch chip 202-C and the switch chip 202-D may be 25.5mm, and the long side L2 may be 27.5mm.
  • the vertical projection of the switch chip on the packaging substrate 201 or the PCB is a rectangle as an example.
  • the network interface 30 of any one of the switch chip 202-A, switch chip 202-B, switch chip 202-C and switch chip 202-D may be a 64L-112G-VSR interface, or a 128L interface -112G-VSR interface.
  • the 64L-112G-VSR interface represents 64 VSR interfaces, and the data transmission rate of each VSR interface is 112Gbps.
  • the 128L-112G-VSR interface represents 128 VSR interfaces, and the data transmission rate of each VSR interface is 112Gbps.
  • the bandwidth of the one-way data transmission of the network interface 30 can be set according to the size of the transmission traffic of the electronic device 11 electrically connected to the network interface 30, which is not limited in this application.
  • the preset switching bandwidth of the switch 10 is 50Tbps.
  • the switch 10 may include two multi-chip packaging structures, which are respectively the multi-chip packaging structure 20a and the multi-chip packaging structure 20b shown in FIG. 5 .
  • each multi-chip package structure may include two switch chips.
  • the multi-chip package structure 20a includes a switch chip 202-A and a switch chip 202-D
  • the multi-chip package structure 20b includes a switch chip 202-B and a switch chip 202-C.
  • the switching bandwidth of any two switch chips in each multi-chip package structure can be the same.
  • the switching bandwidth of any two switch chips may be the same. In this way, the switching bandwidths of all switch chips in the switch 10 can be equal.
  • the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the switch chip 202-D may all be chips with a switching bandwidth of 12.8Tbps prepared by using a 7nm chip preparation process.
  • the D2D interfaces 31 of all the switch chips are electrically connected end to end to form a ring bus 100 .
  • the D2D interface 31 of the switch chip 202-A in the multi-chip package structure 20a is electrically connected to the D2D interface 31 of the switch chip 202-B.
  • the D2D interface 31 of the switch chip 202-B in the multi-chip package structure 20a is electrically connected to the D2D interface 31 of the switch chip 202-C in the multi-chip package structure 20b.
  • the D2D interface 31 of the switch chip 202-C in the multi-chip package structure 20b is electrically connected to the D2D interface 31 of the switch chip 202-D in the multi-chip package structure 20a.
  • the preset switching bandwidths of the switches 10 in Example 1 and Example 2 are both 50Tbps, and the switches 10 each include four switch chips (switch chip 202-A, switch chip 202-B, switch chip 202-C). and switch chips 202-D), and the switching bandwidth of each switch chip is 12.8Tbps.
  • the difference is that, in Example 1, all four switch chips are packaged in the same multi-chip package structure 20 . In this way, the total power consumption of the above-mentioned multi-chip package structure may exceed 1000W, which is relatively large.
  • Example 2 the above four switch chips are packaged in the multi-chip package structure 20a and the multi-chip package structure 20b respectively, so that each multi-chip package structure is packaged with two switch chips, so that each multi-chip package structure can be packaged with two switch chips.
  • the power consumption of the chip packaging structure is reduced by half, for example, to about 500W.
  • the switching bandwidth of the switch chip 202 is the actual switching bandwidth of the switch 10 .
  • the D2D interface 31 of the switch chip 202 may be in a vacant state without being electrically connected to other chips.
  • the actual switching bandwidth of the switch 10 is the sum of the switching bandwidths of the switch chips 202 in the switch 10 .
  • the switch 10 when the switch 10 is provided with two switch chips 202 (12.8Tbps), the actual switching bandwidth of the switch 10 is 25.6Tbps (2 ⁇ 12.8Tbps). Alternatively, when the switch 10 is provided with three switch chips 202 (12.8Tbps), the actual switching bandwidth of the switch 10 is 38.4Tbps (3 ⁇ 12.8Tbps). Alternatively, when the switch 10 is provided with four switch chips 202 (12.8Tbps), the actual switching bandwidth of the switch 10 is 51.2Tbps (4 ⁇ 12.8Tbps).
  • the manner of setting the remaining number of switch chips 202 in the switch 10 is the same as that described above, and will not be repeated here.
  • the above-mentioned plurality of switch chips 202 may be packaged in the same multi-chip package structure in the manner of Example 1. Alternatively, it can also be encapsulated in different multi-chip package structures in the manner of Example 2.
  • the preset switching bandwidth of the switch 10 is 50 Tbps to illustrate the setting manner of the switch chip 202 in the switch 10 as an example.
  • the setting manner of the switch 10 having other preset switching bandwidths will be illustrated by way of example.
  • Switch 10 may include a multi-chip package structure 20 .
  • the multi-chip package structure 20 may include four switch chips located on the same package substrate 201 , which are respectively the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the switch chip 202-C as shown in FIG. 4 .
  • Switch chip 202-D is the switch chip located on the same package substrate 201 , which are respectively the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the switch chip 202-C as shown in FIG. 4 .
  • Switch chip 202-D Switch chip 202-D.
  • the switch chip 202-A, the switch chip 202-B, the switch chip 202 in the multi-chip package structure 20 -C and the switch chip 202-D may both be chips with a switching bandwidth of 25.6 Tbps prepared by a 5nm (minimum line width of transistors in the chip) chip preparation process.
  • the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the D2D interface 31 of the switch chip 202-D in the multi-chip package structure 20 are electrically connected end to end to form a ring bus 100 .
  • the D2D interface 31 of any one of the switch chip 202-A, switch chip 202-B, switch chip 202-C and switch chip 202-D may be a 256L-112G-XSR interface.
  • the 256L-112G-XSR interface represents 256 XSR interfaces, and the data transmission rate of each XSR interface is 112Gbps.
  • the above-mentioned transmission link can be used to carry the 25.6Tbps Ethernet traffic of each switch chip when receiving data or sending data.
  • the network interface 30 of any one of the switch chip 202-A, switch chip 202-B, switch chip 202-C and switch chip 202-D may be a 128L-112G-VSR interface.
  • the above four switch chips are packaged in the same multi-chip package structure 20 .
  • the total power consumption of the multi-chip package structure 20 may exceed 2000W, and the total power consumption is relatively large. Therefore, in order to reduce the power consumption of a single multi-chip package structure, the above-mentioned four switch chips can be packaged in two different multi-chip package structures. Each switch chip can further reduce the power consumption of each multi-chip package structure by half, for example, to about 1000W.
  • the multi-chip package structure 20 in the above-mentioned example 1, example 2 and example 3 is described by taking only the switch chip 202 encapsulated as an example.
  • other components in addition to the switch chip 202 provided in the multi-chip package structure 20, other components may also be encapsulated.
  • the structure of the multi-chip package structure 20 in which other components are encapsulated and the switch 10 having the multi-chip package structure 20 will be described below.
  • At least one multi-chip package structure 20 in the switch 10 is not only packaged with the switch chip 202 shown in FIG. 6 , but also packaged with a plurality of optical engines (OEs) 203 .
  • the above-mentioned multiple OEs 203 and the switch chip 202 are disposed on the same side of the package substrate 201 , and signal interconnection can be realized through the package substrate 201 .
  • each OE203 can be used as at least one optical interface for connecting with the optical fiber.
  • the OE203 is also used to receive the optical signal in the optical fiber and convert the optical signal into an electrical signal.
  • the electrical signal output by the switch chip 202 is received by the packaging substrate 201, and the electrical signal is converted into an optical signal and transmitted to the above-mentioned optical fiber, so that the optical signal can be sent, received and processed.
  • Switch 10 may include a multi-chip package structure 20 .
  • the multi-chip package structure 20 may include four switch chips located on the same package substrate 201, which are the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the switch chip 202-B as shown in FIG. Switch chip 202-D.
  • the switching bandwidth of any one of the above switch chips may be 25.6Tbps.
  • the foregoing switch chip 202-A, switch chip 202-B, switch chip 202-C and switch chip 202-D are electrically connected end to end in sequence through the respective D2D interfaces 31 as described above, and will not be repeated here.
  • the shape of the vertical projection of any one of the above switch chips on the packaging substrate 201 or the PCB may be a square.
  • the length of any side of any one of the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the switch chip 202-D may be 26 mm.
  • 32 OEs 203 may also be encapsulated in the above-mentioned multi-chip package structure 20 .
  • the exchange bandwidth of each optical interface is 800Gbps
  • 32 OEs 203 may also be encapsulated in the above-mentioned multi-chip package structure 20 .
  • the exchange bandwidth of each optical interface is 400Gbps
  • 64 OEs 203 may be encapsulated in the above-mentioned multi-chip package structure 20 .
  • the switching bandwidth of each optical interface is 400G
  • the structure of the switch chip 202 in any of the foregoing embodiments is shown in FIG. 8 , and the switch chip 202 may include a transmission link 41 and a processor for executing control logic.
  • the processor includes a switch buffer unit (SWB) 40 as shown in FIG. 8 .
  • SWB switch buffer unit
  • the transmission link 41 is electrically connected to the D2D interface 31 and the SWB 40 , and the transmission link 41 is used for the transmission of data sent and received between the D2D interface 31 , the SWB 40 and different D2D interfaces 31 .
  • the data in the SWB 40 of the source switch chip can be transmitted to the D2D interface 31 of the source switch chip 202 through the transmission link 41, so as to be sent to the D2D interface 31 of the destination switch chip through the D2D interface 31.
  • the data can also be transmitted to the SWB 40 of the destination switch chip through the transmission link 41 .
  • SWB 40 is used to execute the following control logic.
  • the control logic executed by the SWB 40 of the source switch chip is further used to: determine at least one sending path between the source switch chip and the destination switch chip, and queue the received data. cache, and send a scheduling request to the destination switch chip.
  • control logic executed by the SWB 40 of the destination switch chip is further used to generate a scheduling result according to the scheduling request and the bandwidth of the destination switch chip.
  • control logic executed by the SWB 40 of the source switch chip is further used to: dequeue the received data from the queue according to the scheduling result, and send the received data to the destination switch chip through at least one sending path.
  • the above-mentioned SWB 40 may include an input buffer processing unit (ingress buffer, IB) 401 and an output buffer processing unit (egress buffer, EB) 402 that are electrically connected.
  • the IB401 is electrically connected to the network interface 30 .
  • the IB401 is used to determine at least one sending path between the source switch chip and the destination switch chip, queue and buffer the data from the network interface 30 in the form of a virtual output queue (VOQ), and send it to the EB402 of the destination switch chip.
  • VOQ virtual output queue
  • the EB402 is electrically connected to the transmission link 41 and the network interface 30.
  • the EB402 is used to receive scheduling requests sent by multiple source switch chips, generate multiple scheduling results according to the bandwidth, and send the multiple scheduling results to the IB401 of the multiple source switch chips respectively.
  • the IB401 of the source switch chip receives the above scheduling result, it can dequeue the data packet from the VOQ queue of the IB401 according to the scheduling result, and send the received data to the EB402 of the destination switch chip through at least one transmission path.
  • the EB402 of the target switch chip is also used for buffering the data from the source switch chip to be sent to the network interface 30 of the destination switch chip.
  • the above-mentioned transmission link 41 may include a first link 411 and a second link 412 .
  • the transmission direction of data in the second link 412 (the direction shown by the arrow in FIG. 9 ) is opposite to the transmission direction of the data in the first link 411 (the direction shown by the arrow in FIG. 9 ).
  • the first links 411 of all the switch chips 202 are electrically connected end to end in sequence
  • the second links 412 of all the switch chips 202 are electrically connected end to end in sequence.
  • the switch 10 has four switch chips, which are the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the switch chip 202-D which are electrically connected end to end in sequence.
  • the switch chip 202-A is the source switch chip for sending data
  • the switch chip 202-C is the destination switch chip for receiving data
  • a part of the traffic of the data sent by the switch chip 202-A can pass along each switch chip In the first link 411 (solid arrow in FIG. 10a ) of , the transmission goes through the switch chip 202-B to the switch chip 202-C along the arrow.
  • switch chip 202-A may be transmitted along the arrow through switch chip 202-D to switch chip 202-C in the second link 412 of each switch chip (dotted arrow in Figure 10a) , so that the data transmission efficiency can be improved.
  • the above-mentioned four switch chips in the same multi-chip package structure 20, such as switch chip 202-A, switch chip 202-B, switch chip 202-C and switch Chips 202-D may be arranged in a 2x2 matrix.
  • the switch chip 202-A, the switch chip 202-B, the switch chip 202-C and the first link 411 (solid arrow in FIG. 10b ) of the switch chip 202-D are electrically connected in a ring shape.
  • the switch chip 202-A, the switch chip 202-B, the switch chip 202-C, and the second link 412 of the switch chip 202-D (dotted arrows in FIG. 10b ) end in sequence and are electrically connected in a ring shape.
  • a switch chip such as the switch chip 202-A
  • the paths 412 are electrically connected together. Since the two switch chips that are electrically connected to each other, for example, the switch chip 202-A and the switch chip 202-B (or, the switch chip 202-D) are adjacent to each other, the metal used to electrically connect the adjacent two switch chips together
  • the length of the lead wire may not be too long, so that the transmission efficiency of the signal can be improved.
  • the above-mentioned first link 411 may include a first MAC interface (hereinafter referred to as MAC-Rx1) and a first transmitting end MAC interface (hereinafter referred to as MAC-Tx1).
  • the MAC-Rx1 is electrically connected to the MAC-Tx1 and the EB402.
  • the D2D interface 31 of each switch chip 202 may include a D2D-Rx1 for receiving signals and a D2D-Tx1 for transmitting signals, and the above-mentioned D2D-Rx1 and D2D-Tx1 are connected to the first link as shown in FIG. 9 . 411 Electrical connection.
  • the switch 10 includes at least two switch chips, for example, as shown in FIG. 10a
  • the MAC-Rx1 of the switch chip 202-B passes through its own D2D interface (for example, D2D-Rx1)
  • another switch chip such as the D2D interface (eg D2D-Tx1) of the switch chip 202-A
  • the MAC-Rx1 of the switch chip 202-B is used to write data from the D2D interface (eg D2D-Rx1) to the EB402 of the switch chip 202-B, or send the data to the MAC-Tx1 of the switch chip 202-B.
  • the MAC-Tx1 of the switch chip 202-B is electrically connected to the EB 402, and passes through the D2D interface (eg, D2D-Tx1) of the switch chip 202-B and another switch chip, such as the switch chip 202-C
  • the D2D interface (for example, D2D-Rx1) of the switch chip 202-C is electrically connected to the MAC-Rx1 of the switch chip 202-C.
  • the MAC-Tx1 of the switch chip 202-B is also electrically connected to the MAC-Rx1 of the switch chip 202-B, the MAC-Tx1 of the switch chip 202-B is used to connect the MAC-Rx1 from the switch chip 202-B or The data of the EB 402 of the switch chip 202-B is sent to the D2D interface (eg D2D-Tx1) of the switch chip 202-B.
  • D2D interface eg D2D-Tx1
  • the first link 411 further includes a first buffer (buffer, BF) 51 .
  • the first buffer 51 is electrically connected to the MAC-Rx1 , the MAC-Tx1 and the EB402 of the switch chip 202 .
  • the first buffer 51 is used for buffering the data sent from the MAC-Rx1 and the EB402 in the same switch chip 202 to the MAC-Tx1. In this way, the data buffered in the first buffer 51 can be queued in the first buffer 51 in a first-in-first-out (FIFO) manner, and sent to the MAC-Tx1.
  • FIFO first-in-first-out
  • the second link 412 may include a second receiver MAC interface (hereinafter referred to as MAC-Rx2) and a second transmitter MAC interface (hereinafter referred to as MAC-Tx2).
  • MAC-Rx2 a second receiver MAC interface
  • MAC-Tx2 a second transmitter MAC interface
  • the MAC-Rx2 is electrically connected to the MAC-Tx2 and the EB402.
  • the MAC-Rx1 and MAC-Tx1 in the first link 411 and the MAC-Rx2 and MAC-Tx2 in the second link 412 may use a standard Ethernet protocol, or a customized simplified protocol may be used. standard.
  • the D2D interface 31 of each switch chip 202 may further include a D2D-Rx2 for receiving signals and a D2D-Tx2 for transmitting signals.
  • Road 412 is electrically connected.
  • the switch 10 includes at least two switch chips, two adjacent switch chips, such as the MAC-Rx2 of the switch chip 202-B shown in FIG. 10a , pass through its own D2D interface (eg, D2D-Rx2) And another switch chip, such as the D2D interface (eg D2D-Tx2) of the switch chip 202-C, is electrically connected with the MAC-Tx2 of the switch chip 202-C.
  • the MAC-Rx2 of the switch chip 202-B is used to write data from the D2D interface (eg, D2D-Rx2) to the EB 402, or send the data to the MAC-Tx2 of the switch chip 202-B.
  • D2D interface eg, D2D-Rx2
  • the MAC-Tx2 of the switch chip 202-B is electrically connected to the EB 402, and passes through the D2D interface (eg D2D-Tx2) of the switch chip 202-B and another switch chip, such as the switch chip 202-A
  • the D2D interface (for example, D2D-Rx2) of the switch chip 202-A is electrically connected to the MAC-Rx2 of the switch chip 202-A.
  • the MAC-Tx2 of the switch chip 202-B is also electrically connected to the MAC-Rx2 of the switch chip 202-B, the MAC-Tx2 of the switch chip 202-B is used to connect the MAC-Rx2 from the switch chip 202-B or The data of the EB 402 of the switch chip 202-B is sent to the D2D interface (eg D2D-Tx2) of the switch chip 202-B.
  • D2D interface eg D2D-Tx2
  • the second link 412 further includes a second buffer 52 .
  • the second buffer 52 is electrically connected to the MAC-Rx2 , the MAC-Tx2 and the EB402 of the switch chip 202 .
  • the second buffer 52 is used for buffering the data sent by the MAC-Rx2 and the EB402 in the same switch chip 202 to the MAC-Tx2. In this way, the data buffered in the second buffer 52 can be queued in the second buffer 52 in a FIFO manner and sent to the MAC-Tx2.
  • the network interface 30 of the switch chip 202 may include a VSR-Rx for receiving a signal and a VSR-Tx for sending a signal as shown in FIG. 9 .
  • the switch chip 202 further includes a third receiver MAC interface (hereinafter referred to as MAC-Rx3) and a third transmitter MAC interface (hereinafter referred to as MAC-Tx3).
  • MAC-Rx3 and MAC-Tx3 can use standard Ethernet protocols.
  • the forwarding processing unit in the processor of the switch chip 202 may include an upstream forwarding processing unit (ingress pipeline, IPP) and a downstream forwarding processing unit (egress pipeline, EPP) as shown in FIG. 9 .
  • the MAC-Rx3 is electrically connected to the network interface (eg, VSR-Rx) and the IPP.
  • the MAC-Rx3 is used as the interface of the data link layer to transmit the data from the VSR-Rx to the IPP.
  • the IPP is also electrically connected to the SWB 40.
  • the IPP is used to obtain the destination address of the data from the VSR-Rx according to the source address, and write the data to the local SWB40. Specifically, when the VSR-Rx receives the data packet and transmits it to the IPP through the MAC-Rx3.
  • the IPP can read the source MAC address in the packet header, then read the destination MAC address in the packet header, and look up the corresponding destination MAC address in the MAC address table Interface.
  • the switch chip 202 performs Layer 3 forwarding, the IPP can read the source IP address in the packet header, then read the destination IP address in the packet header, and search the IP address table for the destination MAC address. address the corresponding interface.
  • the EPP is electrically connected to the MAC-Tx3 and the SWB 40 .
  • This EPP is used to read data from SWB40 and send it to MAC-Tx3.
  • the switch chip 202 performs Layer 3 forwarding, the EPP needs to change the source MAC address and the destination MAC address in the packet header to complete the Layer 2 encapsulation.
  • the MAC-Tx3 is also electrically connected to a network interface (eg, MR-Tx). The MAC-Tx3 is used as the interface of the data link layer for future data transmission of the EPP to the MR-Tx.
  • the data exchange capacity of IB401 and EB402 in SWB40 of any switch chip 202 in the switch 10 may both be 12.8Tbps (abbreviated as 12.8T in the figure).
  • IPPs can be set to be electrically connected to the IB401
  • MAC-Rx3s can be set, and one MAC-Rx3 is electrically connected to one IPP, so that each interface can process data with a capacity of 3.2Tbps (abbreviated in the figure). is 3.2T).
  • each interface can process data with a capacity of 3.2Tbps (abbreviated as 3.2T in the figure). ).
  • the forwarding process is illustrated with an example.
  • the data forwarding process may include S101 to S103 as shown in FIG. 11 .
  • the switch chip 202-A when data is forwarded in the same switch chip in the switch 10, for example, the switch chip 202-A, the destination switch chip and one of the source switch chips are both the switch chip 202-A.
  • the source switch chip performs data caching.
  • the switch chip 202-A shown in FIG. 9 is used as one of the source switch chips, and the data output by each IPP can be transmitted to the IB 401 of the switch chip 202-A.
  • the IB401 can buffer data from multiple IPPs in the VOQ queue.
  • one VOQ queue in IB401 corresponds to one priority of one MAC-Tx3 of one switch chip.
  • the destination switch chip performs scheduling, and the scheduling result is sent to the source switch chip.
  • the IB 401 of the switch chip 202-A will send a scheduling request to the EB 402 of the switch chip 202-A.
  • the switch chip 202-A is used as the destination switch chip, the EB 402 of the switch chip 202-A receives the scheduling request sent by the IB 401 of the switch chip 202-A.
  • the EB 402 of the switch chip 202-A can also receive other source switch chips, such as the switch chip 202-B, the switch chip 202-C, and the IB 401 of the switch chip 202-D through the above-mentioned transmission link 41 (as shown in FIG. 9 ).
  • the EB 402 of the switch chip 202-A generates a plurality of scheduling results according to the bandwidth (for example, 12.8T) to perform scheduling, and sends the scheduling results to the IB 401 of each of the above-mentioned source switch chips.
  • the EB402 of the destination switch chip generates multiple scheduling results according to the bandwidth (for example, 12.8T), and sends the scheduling results to the IB401 of each source switch chip mentioned above, which refers to the scheduling request received by the EB402 of the destination switch chip It may be larger than the bandwidth (for example, 12.8T).
  • the sending capacity of the EB402 is only 12.8T, so the scheduling result sent by the EB402 each time will not be greater than 12.8T, and the excess bandwidth will be sent in batches in the EB402.
  • the source switch chip forwards the data to the destination switch chip.
  • the IB 401 of the switch chip 202-A which is the source switch chip
  • receives the scheduling result sent by the EB 402 of the switch chip 202-A which is the destination switch chip
  • the IB 401 of the switch chip 202-A can make the data according to the scheduling result.
  • the packet is dequeued from the VOQ queue of the IB 401 and sent to the EB 402 of the switch chip 202-A.
  • the EB402 can send the data packet to the corresponding MAC-Tx3 through the EPP, and finally send the data packet to the electronic device 11 electrically connected to the MR-TX through the MR-TX, so as to complete the data forwarding.
  • the EB402 of the switch chip 202 can also use FIFO to cache the data to be sent to one MAC-Tx3 according to the scheduling result. .
  • the above description is given by taking an example that data is forwarded in the same switch chip in the switch 10, for example, in the switch chip 202-A.
  • the switch chip 202-A A in the process of forwarding data by the switch 10, when the switch chip 202-A forwards the data to the switch chip 202-B adjacent to the switch chip 202-A, the switch chip 202-A A can be used as one of the source switch chips, and the switch chip 202-B can be used as the destination switch chip.
  • the data forwarding process of the switch 10 is still as shown in FIG. 11 .
  • S101 is executed first, so that in the switch chip 202-A, the data output by each IPP can be cached in the switch chip 202- which is the source switch chip.
  • the sending path may include: from the switch chip 202-A as the source switch chip to the switch chip 202-B as the destination switch chip .
  • the IB 401 of the switch chip 202-A as the source switch chip shown in FIG. 10a will communicate with the switch as the destination switch chip through the first link 411 (solid arrow in FIG. 10a )
  • the EB 402 of the chip 202-B sends a scheduling request.
  • the EB402 of the switch chip 202-B receives the scheduling request sent by the IB401 of the switch chip 202-A.
  • the EB 402 of the switch chip 202-B can also receive other source switch chips, such as the switch chip 202-B, the switch chip 202-C, and the IB 401 of the switch chip 202-D through the first link 411 or the second link.
  • the EB402 of the switch chip 202-B serving as the destination switch chip generates a plurality of scheduling results according to the bandwidth (for example, 12.8T), and sends the scheduling results to the IB401 of each of the above-mentioned source switch chips.
  • the IB401 of the switch chip 202-A serving as the source switch chip receives the scheduling result sent by the EB402 of the switch chip 202-B
  • the IB401 of the switch chip 202-A can make the data packets from the The data is dequeued from the VOQ queue of the IB401, and the data can be sent to the EB402 of the switch chip 202-B through the first link 411 through the above-mentioned sending path.
  • the data dequeued by the IB 401 of the switch chip 202-A may be sent to the first buffer 51 of the switch chip 202-A through the EB 402 of the switch chip 202-A.
  • the first buffer 51 can use FIFO to buffer the data and output it to the switch chip 202- A's MAC-Tx1.
  • the switch chip 202-B which is electrically connected to the MAC-Tx1 of the switch chip 202-A, receives the data to the EB402 of the switch chip 202-B through the MAC-Rx1 of the switch chip 202-B, and the EB402 can send the data through the EPP.
  • the packet is sent to the MAC-Tx3 corresponding to the switch chip 202-B, or buffered once in the EB402 of the switch chip 202-B.
  • the switch chip 202-A when the switch chip 202-A forwards the data to the switch chip 202-C, the switch chip 202-A may serve as one of the source switch chips , the switch chip 202-C is used as the destination switch chip.
  • the switch chip 202-B when data is transmitted in the first reverse direction (eg, clockwise), a switch chip 202-B as a first intermediate switch chip is spaced between the switch chip 202-A and the switch chip 202-C.
  • a switch chip 202-D when data is transmitted in the second direction (eg, counterclockwise), a switch chip 202-D as a second intermediate switch chip is spaced between the switch chip 202-A and the switch chip 202-C.
  • the data forwarding process of the switch 10 is still as shown in FIG. 11 .
  • S101 is executed first, so that in the switch chip 202-A, the data output by each IPP can be cached in the switch chip 202- which is the source switch chip.
  • the first transmission path that can be determined by the IB 401 in the switch chip 202-A, which is the source switch chip may include: from the switch chip 202-A, which is the source switch chip, through the first intermediate switch chip, which is the first intermediate switch chip.
  • the switch chip 202-B is the destination switch chip 202-B.
  • the IB 401 of the switch chip 202-A as the source switch chip shown in FIG. 10a will pass through the first link 411 (solid arrow in FIG. 10a ) and pass through the switch chip 202-B A scheduling request is sent to the EB 402 of the switch chip 202-C.
  • the EB402 of the switch chip 202-C serving as the destination switch chip receives the scheduling request sent by the IB401 of the switch chip 202-A.
  • the EB 402 of the switch chip 202-C can also receive other source switch chips, such as the switch chip 202-B, the switch chip 202-C, and the IB 401 of the switch chip 202-D through the first link 411 or the second link. 412 A scheduling request sent to the EB 402 of the switch chip 202-C.
  • the EB 402 of the switch chip 202-C generates multiple scheduling results according to the bandwidth, and sends the scheduling results to the IB 401 of each of the above-mentioned source switch chips.
  • the IB401 of the switch chip 202-A serving as the source switch chip receives the scheduling result sent by the EB402 of the switch chip 202-C
  • the IB401 of the switch chip 202-A can make the data packets from the The IB401 is dequeued from the VOQ queue.
  • the data may be sent to the EB 402 of the switch chip 202-C through the switch chip 202-B through the first link 411 (solid arrow in FIG. 10a ) through the above-mentioned first sending path.
  • the IB 401 in the switch chip 202-A may determine a second sending path, and the second sending path may be: from the switch chip 202-A, through the second intermediate switch
  • the switch chip 202-D of the chip reaches the switch chip 202-B as the destination switch chip, the data sending process is the same as that described above, and details are not repeated here.
  • S101 is executed, and the IB 401 in the switch chip 202-A serving as the source switch chip can simultaneously determine the first sending path and the second sending path.
  • the IB 401 of the switch chip 202-A as the source switch chip shown in FIG. 10a will pass through the first link 411 (solid arrow in FIG. 10a ) and pass through the switch chip 202-B A scheduling request is sent to the EB 402 of the switch chip 202-C.
  • the IB 401 of the switch chip 202-A may send the scheduling request to the EB 402 of the switch chip 202-C via the switch chip 202-D through the second link 412 (dotted arrow in FIG. 10a).
  • the EB402 of the switch chip 202-C serving as the destination switch chip receives the scheduling request sent by the IB401 of the switch chip 202-A.
  • the EB 402 of the switch chip 202-C can also receive other source switch chips, such as the switch chip 202-B, the switch chip 202-C, and the IB 401 of the switch chip 202-D through the first link 411 or the second link. 412 A scheduling request sent to the EB 402 of the switch chip 202-C.
  • the EB 402 of the switch chip 202-C generates multiple scheduling results according to the bandwidth, and sends the scheduling results to the IB 401 of each of the above-mentioned source switch chips.
  • the IB401 of the switch chip 202-A serving as the source switch chip receives the scheduling result sent by the EB402 of the switch chip 202-C
  • the IB401 of the switch chip 202-A can make the data packets from the The IB401 is dequeued from the VOQ queue.
  • a part of the data is sent to the EB 402 of the switch chip 202-C through the switch chip 202-B through the first link 411 (solid arrow in FIG. 10a ) through the above-mentioned first sending path.
  • another part of the data is sent to the destination switch chip 202-C through the switch chip 202-D through the second link 412 (solid arrow in FIG. 10a ) through the above-mentioned second transmission path.
  • the function of the second buffer 52 in the second link 412 is similar to that of the first buffer 51 , and details are not repeated here.
  • the EB 402 of the switch chip 202-C may send the data packet to the MAC-Tx3 corresponding to the switch chip 202-C through EPP, or perform a cache in the EB 402 of the switch chip 202-C.

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Abstract

本申请实施例提供一种多芯片封装结构、交换机，涉及一种多芯片封装结构、交换机，用于解决不同交换能力的交换机，需要制备相应交换容量的交换机芯片，导致制作成本较高的问题。该多芯片封装结构包括封装基板以及设置于封装基板上的多个交换机芯片。交换机芯片包括至少两个网络接口，以及至少一个芯片到芯片D2D接口。交换机芯片用于通过至少两个网络接口接入网络，且与网络之间收发数据。交换机芯片还用于通过至少一个D2D接口中的每个D2D接口与一个其他的交换机芯片相连，在彼此之间收发数据。交换机芯片还用于将接收自至少两个网络接口或至少一个D2D接口的数据，转发至至少两个网络接口和至少一个D2D接口中的至少一个接口。

Description

一种多芯片封装结构、交换机 技术领域
本申请涉及芯片技术领域，尤其涉及一种多芯片封装结构、交换机。
背景技术
交换机(switch)是一种用于转发电信号或者光信号的网络设备，交换机上设置有多个接口，可以通过多个接口中的任一个接口实现数据的传输。最常见的交换机基于以太网传输数据的以太网交换机。交换机的接口可以直接与主机相连。交换机可以同时连通多对接口，使得每一对相互通信的主机之间进行无碰撞地传输数据。
交换机中设置有交换机芯片，交换机芯片的交换容量可以决定交换机的数据交换能力。交换机芯片的交换容量越大，交换机的数据交换能力越高，交换机可以设置的端口数量越多，其连接的主机的数量也会多。然而，不同类型的用户所需要的交换机的交换能力也有所不同，这样一来，需要根据不同用户的需求，制作具有相应交换容量的交换机芯片，从而不利于降低生产成本。
发明内容
本申请实施例提供一种多芯片封装结构、交换机，用于解决不同交换能力的交换机，需要制备相应交换容量的交换机芯片，导致制作成本较高的问题。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的一方面，提供一种多芯片封装结构。该多芯片封装结构包括封装基板以及设置于封装基板上的至少多个交换机芯片。交换机芯片包括至少两个网络接口，以及至少一个芯片到芯片D2D接口。交换机芯片用于通过至少两个网络接口接入网络，且与网络之间收发数据。交换机芯片还用于通过至少一个D2D接口中的每个D2D接口与一个其他的交换机芯片相连，在彼此之间收发数据。交换机芯片还用于将接收自至少两个网络接口或至少一个D2D接口的数据，转发至至少两个网络接口和至少一个D2D接口中的至少一个接口。在此情况下，当交换机中设置有一个交换机芯片时，该交换机芯片的交换带宽即为交换机的实际交换带宽。此时，该交换机芯片的D2D接口可以处于空置的状态，而不与其他芯片进行电连接。当交换机中设置多个交换带宽相同，且通过各自的D2D接口可以依次首尾电连接的交换机芯片时，该交换机的实际交换带宽为其内部的各个交换机芯片的交换带宽之和。这样一来，本申请实施例提供的方案中，为了得到交换带宽不同的交换机，无需针对不同的交换带宽单独制作对应的交换机芯片。而只需要生产一种交换机芯片，并根据交换机交换带宽的需求，设置交换机中交换机芯片的数量，并将多个交换带宽相同的交换机芯片，通过各自的D2D接口电连接，就可以得到一系列的交换带宽不同的交换机，达到降低成本的目的。并且，同一个多芯片封装结构中，所有交换机芯片的D2D接口依次首尾电连接。这样一来，可以使得多芯片封装结构的交换带宽为该多芯片封装结构中所有交换机芯片的交换带宽之和，从而可以使得整个交换机的交换带宽更大，例如可以达到50Tbps、100 Tbps甚至更大。
可选的，交换机芯片还包括控制逻辑，控制逻辑用于：从接收的数据中获取接收的数据的目的信息。然后，根据目的信息确定发送端口，发送端口包括当前的交换机芯片中的至少一个D2D接口和至少两个网络接口，再将接收的数据通过发送端口发送。从而可以使得交换机芯片实现数据的转发和交换过程。
可选的，多个交换机芯片包括源交换机芯片和目的交换机芯片。源交换机芯片根据目的信息确定发送端口之后，源交换机芯片的控制逻辑还用于：确定源交换机芯片和目的交换机芯片之间的至少一条发送路径，对接收的数据进行排队缓存，并向目的交换机芯片发送调度请求。此外，在目的交换机芯片将接收的数据通过发送端口发送之前，目的交换机芯片的控制逻辑还用于：根据调度请求以及目的交流换机芯片的带宽生成调度结果；源交换机芯片的控制逻辑还用于：根据调度结果，使得接收的数据从队列中出队，将接收的数据通过至少一条发送路径，发送至目的交换机芯片。这样一来，多个交换机芯片之间可以通过发送调度请求、生成调度结果以及根据调度结果发送数据，从而实现多个电连接的交换机芯片之间的数据交换。
可选的，多芯片封装结构包括四个交换机芯片。每个交换机芯片包括两个D2D接口，用于分别与其他两个交换机芯片的D2D接口相连接。四个交换机芯片依次收尾电连接。这样一来，彼此电连接的两个交换机芯片相邻，所以用于将相邻两个交换机芯片电连接在一起的金属引线的长度可以不用太长，从而能够提高信号的传输效率。
可选的，源交换机芯片与目的交换机芯片相邻。源交换机芯片的控制逻辑具体用于：确定的一条发送路径，将接收的数据通过发送路径，发送至目的交换机芯片；其中，发送路径包括：从源交换机芯片到目的交换机芯片。这样一来，通过上述发送路径可以实现相邻交换机芯片之间的数据转发。
可选的，四个交换机芯片中，源交换机芯片和目的交换机芯片之间间隔有一个中间交换机芯片。源交换机芯片的控制逻辑具体用于：确定的一条发送路径，将接收的数据通过发送路径，发送至目的交换机芯片；其中，发送路径包括：从源交换机芯片，经过中间交换机芯片到目的交换机芯片。这样一来，通过上述第一发送路径可以实现间隔设置的两个交换机芯片之间的数据转发。
可选的，四个交换机芯片中，沿第一方向，源交换机芯片和目的交换机芯片之间间隔有第一中间交换机芯片，沿第二方向，源交换机芯片和目的交换机芯片之间间隔有第二中间交换机芯片；其中，第一方向和第二方向相反。源交换机芯片的控制逻辑具体用于：确定的第一发送路径，将接收的数据的一部分通过第一发送路径，发送至目的交换机芯片。其中，第一发送路径包括：从源交换机芯片，经过第一中间交换机芯片到目的交换机芯片。确定的第二发送路径，将接收的数据的另一部分通过第二发送路径，发送至目的交换机芯片。其中，第二发送路径包括：从源交换机芯片，经过第二中间交换机芯片到目的交换机芯片。这样一来，由于第一发送路径和第二发送路径的数据传输方向相反，因此当交换机中不相邻的交换机芯片之间进行数据转发时，一部分数据的流量可以沿第一发送路径进行传输，另一部分的流量可以沿第二发送路径进行转发，提高数据的传输效率。
可选的，所述交换机芯片还包括交换缓存单元以及传输链路。其中，交换缓存单 元用于执行上述发送调度请求、生成调度结果以及根据调度结果发送数据的控制逻辑。传输链路与D2D接口以及交换缓存单元电连接，传输链路用于D2D接口与交换缓存单元之间，以及不同D2D接口之间收发数据。多个交换机芯片之间交换的数据可以通过传输链路进行传输。
可选的，传输链路包括第一链路和第二链路。第一链路包括依次电连接的第一接收端媒体访问控制MAC接口、第一缓冲器以及第一发送端MAC接口。第一接收端MAC接口和第一发送端MAC接口与交换机芯片的两个D2D接口分别电连接。第一接收端MAC接口、第一缓冲器还与交换缓存单元电连接。这样一来，交换机中的多个交换机芯片的第一接收端MAC接口、第一发送端MAC依次电连接，从而可以将多个交换机芯片的第一链路电连接，使得多个交换机芯片的数据可以通过第一链路在不同的交换机芯片中进行传输。并且，缓存于第一缓冲器中的数据可以采用FIFO的方式在第一缓冲器中进行排队，并发送至该交换机芯片的第一发送端MAC接口，从而可以避免来自第一接收端MAC接口以及输出缓存处理单元的数据发生冲突。此外，第二链路中数据的传输方向与第一链路中数据的传输方向相反。第二链路包括依次电连接的第二接收端MAC接口、第二缓冲器以及第二发送端MAC接口。第二接收端MAC接口和第二发送端MAC接口与交换机芯片的两个D2D接口分别电连接。第二接收端MAC接口和第二缓冲器还与交换缓存单元电连接。第二链路和第二缓冲器的技术效果同理可得，此处不再赘述。此外，由于第二链路中数据的传输方向与第一链路中数据的传输方向相反，因此当交换机中不相邻的交换机芯片之间进行数据转发时，一部分数据的流量可以沿第一链路进行传输，另一部分的流量可以沿第二链路进行转发，提高数据的传输效率。
可选的，四个交换机芯片以2×2矩阵形式进行排列。多芯片封装结构中，四个交换机芯片的第一链路依次首尾电连接呈环状。四个交换机芯片的第二链路依次首尾电连接呈环状。这样一来，一个交换机芯片可以与其左边(或右边)，以及上边(或下边)的另一个交换机芯片通过第一链路、第二链路电连接在一起。由于彼此电连接的两个交换机芯片相邻，所以用于将相邻两个交换机芯片电连接在一起的金属引线的长度可以不用太长，从而能够提高信号的传输效率。
可选的，交换机芯片还包括转发处理单元、第三接收端MAC接口以及第三发送端MAC接口。转发处理单元用于执行上述数据转发的控制逻辑。例如根据来自网络接口的数据的源地址，获取其目的地址，并将数据写入至交换缓存单元。当交换机芯片执行二层转发时，该转发处理单元可以读取数据包包头中的源MAC地址，再读取该数据包包头中的目的MAC地址，并在MAC地址表中查找与该目的MAC地址相应的接口。或者，当交换机芯片执行三层转发时，该转发处理单元可以读取数据包包头中的源IP地址，再读取该数据包包头中的目的IP地址，并在IP地址表中查找与该目的MAC地址相应的接口。此外，转发处理单元与网络接口、交换缓存单元电连接。该转发处理单元用于对从交换缓存单元中读取数据并发送至网络接口。当交换机芯片进行三层转发时，转发处理单元需要改变数据包包头中的源MAC地址以及目的MAC地址，以完成二层封装。第三接收端MAC接口与网络接口和转发处理单元电连接，用于将来自所述网络接口的数据传输至转发处理单元。第三发送端MAC接口与网络 接口和转发处理单元电连接，用于将来自转发处理单元的数据传输至网络接口。
可选的，多芯片封装结构多芯片封装结构多芯片封装结构多芯片封装结构可选的，多芯片封装结构中，任意两个交换机芯片的交换带宽相同。这样一来，只需要生产一种交换机芯片，并根据交换机交换带宽的需求，设置交换机中交换机芯片的数量，并将多个交换带宽相同的交换机芯片，通能过各自的D2D接口电连接，就可以得到一系列的交换带宽不同的交换机，达到降低成本的目的。
可选的，多芯片封装结构还包括多个光模块设置于封装基板上，且与交换机芯片位于同一侧。这样一来，通过将光模块和交换机芯片封装在同一个多芯片封装结构中，可以使得交换机具有更大交换带宽的光接口。
本申请实施例的另一方面，提供一种交换机。该交换机包括电路板以及设置于电路板上的上所述的任意一种多芯片封装结构。该交换机具有与前述实施例提供的交换机芯片相同的技术效果，此处不再赘述。
本申请实施例的又一方面，提供一种交换机。该交换机包括电路板以及设置于电路板上的至少两个如上所述的多芯片封装结构。该电路板上所有的交换机芯片的D2D接口依次首尾电连接。该交换机具有与前述实施例提供的交换机芯片相同的技术效果，此处不再赘述。
可选的，同一电路板上，任意两个交换机芯片的交换带宽相同。这样一来，可以使得交换机的交换带宽为该交换机中所有交换机芯片的交换带宽之和，从而可以使得整个交换机的交换带宽更大，例如可以达到50Tbps、100Tbps甚至更大。
附图说明
图1为本申请实施例提供的一种交换网络的结构示意图；
图2为图1中交换机的一种结构示意图；
图3a为图2中多芯片封装结构的一种结构示意图；
图3b为图2中多芯片封装结构的另一种结构示意图；
图4为图2中多芯片封装结构的另一种结构示意图；
图5为图1中交换机的另一种结构示意图；
图6为图2中多芯片封装结构的另一种结构示意图；
图7为图2中多芯片封装结构的另一种结构示意图；
图8为本申请实施例提供的交换机芯片的一种结构示意图；
图9为本申请实施例提供的交换机芯片的另一种结构示意图；
图10a为多个如图9所示的交换机芯片电连接的一种结构示意图；
图10b为多个如图9所示的交换机芯片电连接的另一种结构示意图；
图11为本申请实施例提供的交换机的数据转发流程图。
附图标记：
01-交换网络；10-交换机；11-电子设备；101-以太网接口；20-多芯片封装结构；201-封装基板；12-电路板；202-交换机芯片；30-网络接口；31-D2D接口；100-环形总线；203-光引擎；40-SWB；41-传输链路；401-IB；402-EB；411-第一链路；412-第二链路；51-第一缓冲器；52-第二缓冲器。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。
此外，本申请中，“上”、“下”、“左”以及“右”等方位术语是相对于附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以通过中间媒介进行间接的电性连接。
本申请实施例提供的交换网络01如图1所示，可以包括至少一个交换机10以及与该交换机电连接的多个电子设备11。上述电子设备11可以为服务器、计算机、移动终端、数据存储装置、网络组件、网络装置、路由器、交换机等。上述交换网络01中的各个电子设备11可以通过以太网(ethernet)传输线电连接到交换机10的一个或多个以太网接口101上。在此情况下，上述交换机10可以提供多个物理以太网接口101间的报文转发，以使得交换网络01中的各个电子设备11可以通过交换机10实现彼此电连接，并实现彼此之间的通信。
在本申请实施例提供的上述交换机10，如图2所示，可以包括电路板12，例如印刷电路板(printed circuit board，PCB)，以及设置于该电路板12上的至少一个芯片封装(package)结构20。该多芯片封装结构20可以包括封装基板(substrate)201，以及设置于该封装基板201上的至少一个交换机芯片(die或chiplet)202。
本申请实施例中，该多芯片封装结构20中的任意一个交换机芯片202如图3a所示，可以包括至少两个网络接口30和至少一个芯片到芯片(die-to-die，D2D)接口31。上述网络接口30和D2D接口31作为开放式系统互联通信参考模型(open system interconnection reference model，OSI model)的物理层接口。
其中，交换机芯片202用于通过上述至少两个网络接口30接入网络(例如以太网)，且与网络之间收发数据。例如，上述网络接口30可以与图1所示的物理以太网接口101电连接，网络接口30可以接收以太网中的各个电子设备11发送的数据。或者，网络接口30可以将数据发送至上述各个电子设备11。
示例的，上述网络接口30可以为串行器/解串器(serializer-deserializer，SerDes)接口。例如，上述网络接口30可以为SerDes接口中，用于将芯片与可插拔的光模块相连接的甚短距离(very short reach，VSR)接口。以下为了方便说明，附图中均是以网络接口采用VSR接口为例进行举例。
在本发明实施例中，一个交换机芯片202中可以包括至少一个D2D接口31和至少两个网络接口30。一个交换芯片202通过至少一个D2D接口31中的每个D2D接口 31与其他的一个交换机芯片相连，而通过两个网络接口30分别与交换机10的两个太网接口101相连。交换机芯片202用于通过至少一个D2D接口31中的每个D2D接口31与一个其他的交换机芯片202相连，在彼此之间收发数据。此外，交换机芯片202还用于将接收自至少两个网络接口30或至少一个D2D接口31的数据，转发至至少两个网络接口30和至少一个D2D接口31中的至少一个接口。
为了方便说明，以下均是以一个交换机芯片202包括一个D2D接口31和两个网络接口30为例。在此情况下，来自不同网络接口30的数据，可以通过D2D接口31与其他的交换机芯片202交换数据，并与至少两个接收机的端口与外部网络收发数据。
由此可知，D2D接口31可以用于将两个交换机芯片202之间电连接，即die to die。本申请实施例中，D2D接口31可以为SerDes接口，例如，D2D可以为SerDes接口中，用于实现芯片间电连接的超短距(extreme short reach，XSR)接口，该XSR接口之间制作于PCB12上的走线长度可以为0～50mm。或者，D2D接口31还可以为并行接口，例如，高级接口总线(advanced interface bus，AIB)。
基于此，本申请实施例提供的交换机芯片202可以包括处理器，该处理器中的转发处理单元可以用于执行控制逻辑。该控制逻辑用于从网络接口30或D2D接口31接收的数据中获取该接收的数据的目的信息。例如，该目的信息可以为接收的数据的目的地址。然后，上述控制逻辑可以用于根据该目的信息确定发送端口。其中，发送端口包括当前的交换机芯片中的上述至少一个D2D接口31和上述至少两个网络接口30。接下来，上述控制逻辑还用于将接收的数据通过上述发送端口发送，从而实现数据转发过程。
需要说明的是，本申请实施例中，当芯片封装结构20中封装有多个交换机芯片202时，该芯片封装结构20可以为将多个交换机芯片202直接设置于封装基板(substrate)上的，多芯片合封(multi-chip module，MCM)结构。或者，芯片封装结构20可以为采用包含硅载板的封装(chip on wafer on substrate，COWOS)技术，将多个交换机芯片202设置于转接板(interposer)上的2.5D封装结构。又或者，在另一些实施例中，上述芯片封装结构20可以为采用扇出型封装(fan out package，FOP)技术，将多个交换机芯片202设置于重布线层(redistribution layer，RDL)上的扇出型封装结构。又或者，上述芯片封装结构20可以为在封装基板中设置连接器，并通过连接器将多个设置于封装基板上的交换机芯片202电连接的，嵌入式多芯片互连桥接(embedded multi-die interconnect bridge，EMIB)封装结构。
在此基础上，当交换机10包括至少两个交换机芯片，例如，如图3b所示的交换机芯片202a和交换机芯片202b时，同一PCB12上的任意两个交换机芯片的交换带宽可以相同，例如均为12.8Tpbs。以下根据交换机10的交换带宽的不同需求，对该交换机10内多个交换机芯片202的设置方式进行举例说明。
需要说明的是，本申请中交换机10的交换带宽用于衡量交换机10总的数据交换能力。例如，当交换机10的交换带宽为50Tbps时，交换机10的数据传输速率为每秒50兆位。
示例一
本示例中，交换机10预设的交换带宽为50Tbps。交换机10可以包括一个如图4 所示的多芯片封装结构20。此时，该多芯片封装结构20可以包括位于同一个封装基板201上的四个交换机芯片，分别为交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D。
在此情况下，为了使得交换机10的实际交换带宽可以达到上述预设的交换带宽(例如，50Tbps)，该多芯片封装结构20中的交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D，可以均为采用7nm(芯片中晶体管的最小线宽)芯片制备工艺制备的交换带宽为12.8Tbps的芯片。
基于此，多芯片封装结构20中的交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D的D2D接口31依次首尾(one by one)电连接形成一个环形总线100。例如，交换机芯片202-A的D2D接口31与交换机芯片202-B的D2D接口31电连接。交换机芯片202-B的D2D接口31与交换机芯片202-C的D2D接口31电连接。交换机芯片202-C的D2D接口31与交换机芯片202-D的D2D接口31电连接。
在本申请的一些实施例中，在用于发送数据的源交换机芯片和用于接收数据的目的交换机芯片相邻的情况下，例如，作为源交换机芯片的交换机芯片202-A，可以直接向作为目的交换机芯片的交换机芯片202-B发送数据。或者，在本申请的另一些实施例中，在源交换机芯片和目的交换机芯片之间间隔有中间交换机芯片的情况下，例如，作为源交换机芯片的交换机芯片202-A，向作为目的交换机芯片的交换机芯片202-C发送数据时，交换机芯片202-A发送的数据可以沿顺时针的方向，经过作为第一中间交换机芯片的交换机芯片202-B后，传递至交换机芯片202-C。或者，交换机芯片202-A发送的数据可以沿逆时针的方向，经过作为第二中间交换机芯片的交换机芯片202-D后，传递至交换机芯片202-C。又或者，作为源交换机芯片的交换机芯片202-A发送数据的一部分可以沿顺时针的方向，通过作为第一中间交换机芯片的交换机芯片202-B后，传递至交换机芯片202-C。上述数据的另一部分可以沿逆时针的方向，通过作为第二中间交换机芯片的交换机芯片202-D后，传递至交换机芯片202-C。
上述交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D中任意一个交换机芯片的D2D接口31可以为128L-112G-XSR接口。其中，128L-112G-XSR接口表示的是128路(lane)XSR接口，每一路XSR接口的数据传输速率为112Gbps。这样一来，相邻两个电连接的D2D接口31之间形成的传输电路单向传输数据的带宽为14.3Tbps(128×112＝14.3Tbps)。此时，上述传输链路可以在单向传输数据，例如接收数据，或者发送数据时用于承载每个交换机芯片的12.8Tbps的以太网流量。并且，剩余的流量1.5Tbps(14.3Tbps-12.8Tbps＝1.5Tbps)，可以用于内部消耗(over header)。
需要说明的是，多个交换机芯片的D2D接口31之间，传输的数据其包头上带有地址，该地址需要占用一些字节。此外，上述多个交换机芯片的D2D接口31之间除了传输数据以外，还需要传输与该数据相关的调度指令以及调度结果。该调度指令以及调度结果同样需要占用一些字节。因此，上述用于内部消耗的流量可以是用于传输与数据相关的地址、调度指令以及调度结果。示例的，每个交换机芯片的D2D接口31传输流量的余量可以为该交换机芯片的交换带宽，例如12.8Tbps的10％左右。上述 与数据相关的地址、调度指令以及调度结果会在之后对实施例中进行详细的说明。
然而，上述环形总线100上，任意一个交换机芯片的D2D接口31即可以接收数据，又可以发送数据。因此相邻两个电连接的D2D接口31同时收发数据时，形成的传输链路双向带宽为2个14.3Tbps。此外，环形总线100上，任意一个交换机芯片即可以作为源交换机芯片，同时也可以作为目的交换机芯片。当环形总线100上的4个交换机芯片同时接受和发送数据时，上述环形总线100上形成的传输链路的带宽可以为8(2×4)个14.3Tbps。此时，多芯片封装结构20中每个D2D接口31均处于收发数据的状态。
考虑到交换机10内部形成的上述传输链路的带宽具有加速比，所以交换机10对外实际体现的总的交换带宽，为其内部的各个交换机芯片202的交换带宽之和。例如，4个14.3Tbps，即51.2Tbps(4×14.3＝51.2Tbps)的交换带宽，使得该交换机10具有51.2Tbps的线速无阻塞交换能力，且该交换带宽大于交换机10的预设的交换带宽(例如，50Tbps)。
此外，本申请实施例中的交换机芯片202在封装基板201或者PCB上的垂直投影的形状可以为长方形或者正方形，本申请实施例对此不作限定。以交换机芯片202在封装基板201或者PCB上的垂直投影的形状可以为长方形为例，示例的，如图4所示，该多芯片封装结构20中，交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D中的任意一个交换机芯片的短边L1可以为25.5mm，长边L2可以为27.5mm。以下为了方便说明，大部分实施例是以上述交换机芯片在封装基板201或者PCB上的垂直投影的形状为长方形为例进行的说明。
此外，示例的，上述交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D中任意一个交换机芯片的网络接口30可以为64L-112G-VSR接口，或者，128L-112G-VSR接口。其中，64L-112G-VSR接口表示的是64路VSR接口，每一路VSR接口的数据传输速率为112Gbps。此时，网络接口30的单向数据传输的带宽为7.168Tbps(64×112＝7.168Tbps)。
此外，128L-112G-VSR接口表示的是128路VSR接口，每一路VSR接口的数据传输速率为112Gbps。此时，网络接口30的单向数据传输的带宽为14.3Tbps(128×112＝14.3Tbps)。网络接口30的单向数据传输的带宽可以根据与该网络接口30电连接的电子设备11传输流量的大小进行设定，本申请对此不作限定。
示例二
本示例中，交换机10预设的交换带宽为50Tbps。交换机10可以包括两个多芯片封装结构，分别为如图5所示的多芯片封装结构20a和多芯片封装结构20b。其中，每个多芯片封装结构可以包括两个交换机芯片。例如，多芯片封装结构20a中包括交换机芯片202-A和交换机芯片202-D，多芯片封装结构20b中包括交换机芯片202-B和交换机芯片202-C。
此外，每个多芯片封装结构中的任意两个交换机芯片的交换带宽可以相同。并且，不同多芯片封装结构之间，任意两个交换机芯片的交换带宽可以相同。这样一来，交换机10中所有交换机芯片的交换带宽可以均相等。在此情况下，上述交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D，可以均为采用 7nm芯片制备工艺制备的交换带宽为12.8Tbps的芯片。
并且，交换机10中的电路板12上，所有的交换机芯片的D2D接口31依次首尾电连接形成一个环形总线100。例如，多芯片封装结构20a中的交换机芯片202-A的D2D接口31与交换机芯片202-B的D2D接口31电连接。多芯片封装结构20a中的交换机芯片202-B的D2D接口31与多芯片封装结构20b中的交换机芯片202-C的D2D接口31电连接。多芯片封装结构20b中的交换机芯片202-C的D2D接口31与多芯片封装结构20a中的交换机芯片202-D的D2D接口31电连接。
由上述可知，示例一和示例二中的交换机10预设的交换带宽均为50Tbps，该交换机10均包括四个交换机芯片(换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D)，且每个交换机芯片的交换带宽均为12.8Tbps。不同之处在于，示例一中，四个交换机芯片均合封于在同一个多芯片封装结构20中。这样一来，上述多芯片封装结构的总功耗可能会超过1000W，总功耗较大。示例二中，上述四个交换机芯片，两两分别合封于多芯片封装结构20a和多芯片封装结构20b中，使得每个多芯片封装结构中封装有两个交换机芯片，进而可以使得每个多芯片封装结构的功耗降低一半，例如降低至500W左右。
综上所述，当交换机10中设置有一个交换机芯片202时，该交换机芯片202的交换带宽，例如12.8Tbps，即为交换机10的实际交换带宽。此时，该交换机芯片202的D2D接口31可以处于空置的状态，而不与其他芯片进行电连接。当交换机10中设置多个交换带宽相同，且通过各自的D2D接口31依次首尾电连接的交换机芯片202时，该交换机10的实际交换带宽为其内部的各个交换机芯片202的交换带宽之和。
例如，当交换机10中设置有两个交换机芯片202(12.8Tbps)时，该交换机10的实际交换带宽为25.6Tbps(2×12.8Tbps)。或者，当交换机10中设置有三个交换机芯片202(12.8Tbps)时，该交换机10的实际交换带宽为38.4Tbps(3×12.8Tbps)。或者，当交换机10中设置有四个交换机芯片202(12.8Tbps)时，该交换机10的实际交换带宽为51.2Tbps(4×12.8Tbps)。
交换机10中设置其余数量的交换机芯片202的方式同上所述，此处不再赘述。其中，当交换机10中设置有多个交换机芯片202时，上述多个交换机芯片202可以采用示例一的方式均合封于同一个多芯片封装结构中。或者，也可以采用示例二的方式合封于不同的多芯片封装结构中。
这样一来，本申请实施例提供的方案中，为了得到交换带宽不同的交换机10，无需针对不同的交换带宽单独制作对应的交换机芯片。而只需要生产一种交换机芯片202(例如，交换带宽为12.8Tbps)，根据交换机10交换带宽的需求，设置交换机10中交换机芯片202的数量。然后，将多个交换带宽相同的交换机芯片202采用上述方式依次首尾电连接，就可以得到一系列的交换带宽不同的交换机10，达到降低成本的目的。
上述是以交换机10预设的交换带宽为50Tbps为例，对该交换机10中交换机芯片202的设置方式进行的举例说明。以下对具有其他预设的交换带宽的交换机10的设置方式进行举例说明。
示例三
本示例中，交换机10预设的交换带宽为100Tbps。交换机10可以包括一个多芯片封装结构20。此时，该多芯片封装结构20可以包括位于同一个封装基板201上的四个交换机芯片，分别为如图4所示的交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D。
在此情况下，为了使得交换机10的实际交换带宽可以达到上述预设的交换带宽(例如，100Tbps)，该多芯片封装结构20中的交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D，可以均为采用5nm(芯片中晶体管的最小线宽)芯片制备工艺制备的交换带宽为25.6Tbps的芯片。这样一来，4个25.6Tbps的交换机芯片的总的交换带宽为4×25.6Tbps(4×25.6＝102.4Tbps)，可以大于预设的交换带宽(例如，100Tbps)。
同理，多芯片封装结构20中的交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D的D2D接口31依次首尾电连接形成一个环形总线100。
本示例中，上述交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D中任意一个交换机芯片的D2D接口31可以为256L-112G-XSR接口。其中，256L-112G-XSR接口表示的是256路XSR接口，每一路XSR接口的数据传输速率为112Gbps。这样一来，相邻两个电连接的D2D接口31之间形成的传输电路单向带宽为28.6Tbps(256×112＝28.6Tbps)。此时，上述传输链路可以在接收数据，或者发送数据时用于承载每个交换机芯片的25.6Tbps的以太网流量。并且，剩余的流量3Tbps(28.6Tbps-25.6Tbps＝3Tbps)，可以用于上述内部消耗。
此外，示例的，上述交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D中任意一个交换机芯片的网络接口30可以为128L-112G-VSR接口。
同理，上述将四个交换机芯片均合封于在同一个多芯片封装结构20中。这样一来，该多芯片封装结构20的总功耗可能会超过2000W，总功耗较大。因此为了降低单个多芯片封装结构的功耗，可以上述四个交换机芯片，两两分别合封于两个不同的多芯片封装结构中，同上所述可以使得每个多芯片封装结构中封装有两个交换机芯片，进而可以使得每个多芯片封装结构的功耗降低一半，例如降低至1000W左右。
上述示例一、示例二以及示例三中的多芯片封装结构20中均是以只合封有交换机芯片202为例进行的说明。在本申请的另一些实施例中，上述多芯片封装结构20中除了设置有交换机芯片202以外，还可以合封其他部件。以下对合封有其他部件的多芯片封装结构20以及具有该多芯片封装结构20的交换机10的结构进行说明。
示例四
本示例中，交换机10中的至少一个多芯片封装结构20中，不仅封装有如图6所示的交换机芯片202，还封装有多个光引擎(optical engine，OE)203。在此情况下，上述多个OE203与交换机芯片202设置于封装基板201的同一侧，可以通过封装基板201实现信号互联。
其中，每一个OE203可以作为至少一个光接口用于与光纤连接。该OE203还用于接收光纤中的光信号，并将该光信号转换成电信号。并且，通过封装基板201接收 交换机芯片202输出的电信号，并将该电信号转换成光信号，传输至上述光纤中，从而可以进行光信号的收发和处理。
示例的，如图7所示，交换机10预设的交换带宽为100Tbps。交换机10可以包括一个多芯片封装结构20。同理，该多芯片封装结构20可以包括位于同一个封装基板201上的四个交换机芯片，分别为如图7所示的交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D。上述任意一个交换机芯片的交换带宽可以为25.6Tbps。上述交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D通过各自的D2D接口31依次首尾电连接的方式同上所述，此处不再赘述。
本示例中，上述任意一个交换机芯片在封装基板201或者PCB上的垂直投影的形状可以为正方形。示例的，该多芯片封装结构20中，交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D中的任意一个交换机芯片的任意一边的边长可以为26mm。
此外，在本申请的一些实施例中，上述多芯片封装结构20中还可以合封有32个OE203。在一个OE203作为4个光接口，且每个光接口的交换带宽为800Gbps时，一个OE203的交换带宽为3.2Tbps(4×800Gbps＝3.2Tbps)。在此情况下，该交换机10可以具有128个(32×4＝128个)交换带宽为800Gbps的光接口。
或者，在本申请的另一些实施例中，上述多芯片封装结构20中还可以合封有32个OE203。在一个OE203作为8个光接口，且每个光接口的交换带宽为400Gbps时，一个OE203的交换带宽为3.2Tbps(8×400Gbps＝3.2Tbps)。在此情况下，该交换机10可以具有128个(32×8＝256个)交换带宽为400Gbps的光接口。
又或者，在本申请的另一些实施例中，上述多芯片封装结构20中还可以合封有64个OE203。在一个OE203作为4个光接口，且每个光接口的交换带宽为400G时，一个OE203的交换带宽为1.6Tbps(4×400Gbps＝1.6Tbps)。在此情况下，该交换机10可以具有128个(64×4＝256个)交换带宽为400Gbps的光接口。
需要说明的是，上述仅仅是对多芯片封装结构20中合封的OE203的数量和其交换带宽的举例说明，其它示例在此不再一一赘述。
[根据细则91更正 04.09.2020]　
由上述可知，通过在交换机10的多芯片封装结构20中设置多个交换机芯片202，且交换机10中的各个交换机芯片202可以通过D2D接口31电连接，可以使得交换机10的交换带宽达到50Tbps、100Tbps甚至更大。而目前采用7nm(芯片中晶体管的最小线宽)芯片制备工艺制备的交换机芯片，其能够达到的最佳交换带宽为25Tbps，因此本申请实施例提供的交换机10能够获得更大的交换带宽，有利于提升交换机10的性能。
上述任意一个实施例中的交换机芯片202的结构如图8所示，该交换机芯片202可以包括传输链路41以及用于执行控制逻辑的处理器。该处理器包括如图8所示的交换缓存单元(switch buffer，SWB)40。
其中，传输链路41与D2D接口31以及SWB40电连接，传输链路41用于D2D接口31、SWB40以及不同D2D接口31之间收发数据的传输。这样一来，源交换机芯片的SWB40中的数据，可以通过传输链路41传输至该源交换机芯片202的D2D接 口31，以通过该D2D接口31发送至目的交换机芯片的D2D接口31。此外，当目的交换机芯片的D2D接口31接收到源交换机芯片202输出的数据后，该数据也可以通过传输链路41传输至目的交换机芯片的SWB40中。
此外，SWB40用于执行以下控制逻辑。示例的，源交换机芯片根据目的信息确定发送端口之后，源交换机芯片的SWB40所执行的控制逻辑还用于：确定源交换机芯片和目的交换机芯片之间的至少一条发送路径，对接收的数据进行排队缓存，并向目的交换机芯片发送调度请求。
此外，在目的交换机芯片将接收的数据通过发送端口发送之前，目的交换机芯片的SWB40所执行的控制逻辑还用于：根据调度请求以及目的交流换机芯片的带宽生成调度结果。并且，源交换机芯片的SWB40所执行的控制逻辑还用于：根据调度结果，使得接收的数据从队列中出队，将接收的数据通过至少一条发送路径，发送至目的交换机芯片。
在此基础上，上述SWB40如图9所示，可以包括电连接的输入缓存处理单元(ingress buffer，IB)401和输出缓存处理单元(egress buffer，EB)402。其中，IB401与网络接口30电连接。IB401用于确定源交换机芯片和目的交换机芯片之间的至少一条发送路径，对来自网络接口30的数据采用虚拟输出队列(virtual output queue，VOQ)的方式排队缓存，并向目的交换机芯片的EB402发送调度请求。
EB402与传输链路41和网络接口30电连接，EB402用于接收多个源交换机芯片发送的调度请求，并根据带宽生成多个调度结果，将多个调度结果分别发送至多个源交换机芯片的IB401。当源交换机芯片的IB401接收到上述调度结果后，可以根据调度结果，使得数据包从IB401的VOQ队列中出队，将接收的数据通过至少一条发送路径，发送至目的交换机芯片的EB402。在此基础上，目标交换机芯片的EB402还用于对来自源交换机芯片的即将发送至目的交换机芯片的网络接口30的数据进行缓存。
此外，如图9所示，上述传输链路41可以包括第一链路411和第二链路412。其中，第二链路412中数据的传输方向(如图9中箭头所示的方向)与第一链路411中数据的传输方向(如图9中箭头所示的方向)相反。此外，交换机10中，所有交换机芯片202的第一链路411依次首尾电连接，并且所有交换机芯片202的第二链路412依次首尾电连接。
例如，如图10a所示，在交换机10具有四个交换机芯片，分别为依次首尾电连接的交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D的情况下，当交换机芯片202-A为用于发送数据的源交换机芯片，交换机芯片202-C为用于接收数据的目的交换机芯片时，该交换机芯片202-A发送数据的一部分流量可以沿每个交换机芯片的第一链路411(图10a中的实线箭头)中，沿箭头经过交换机芯片202-B传输至交换机芯片202-C。此外，交换机芯片202-A发送数据的另一部分流量可以在每个交换机芯片的第二链路412(图10a中的虚线箭头)中，沿箭头经过交换机芯片202-D传输至交换机芯片202-C，从而可以提高数据的传输效率。
在本申请的一些实施例中，如图10b所示，同一个多芯片封装结构20中的上述四个交换机芯片，例如交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D可以以2×2矩阵形式进行排列。交换机芯片202-A，交换机芯片202-B， 交换机芯片202-C以及交换机芯片202-D的第一链路411(图10b中的实线箭头)依次收尾电连接呈环状。交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D的第二链路412(图10b中的虚线箭头)依次收尾电连接呈环状。
这样一来，一个交换机芯片，例如交换机芯片202-A可以与其左边(或右边)的交换机芯片202-B，以及下边(或上边)的交换机芯片202-D通过第一链路411、第二链路412电连接在一起。由于彼此电连接的两个交换机芯片，例如交换机芯片202-A与交换机芯片202-B(或者，交换机芯片202-D)相邻，所以用于将相邻两个交换机芯片电连接在一起的金属引线(图中未示出)的长度可以不用太长，从而能够提高信号的传输效率。
示例的，如图9所示，上述第一链路411可以包括第一MAC接口(以下简称MAC-Rx1)和第一发送端MAC接口(以下简称MAC-Tx1)。其中，MAC-Rx1与MAC-Tx1以及EB402电连接。在此情况下，每个交换机芯片202的D2D接口31可以包括用于接收信号的D2D-Rx1和发送信号的D2D-Tx1，上述D2D-Rx1和D2D-Tx1如图9所示与第一链路411电连接。
基于此，当交换机10包括至少两个交换机芯片时，相邻的两个交换机芯片，例如如图10a所示，交换机芯片202-B的MAC-Rx1通过其自身的D2D接口(例如D2D-Rx1)以及另一个交换机芯片，例如交换机芯片202-A的D2D接口(例如D2D-Tx1)，与该交换机芯片202-A的MAC-Tx1电连接。上述交换机芯片202-B的MAC-Rx1用于将来自D2D接口(例如D2D-Rx1)的数据写入至交换机芯片202-B的EB402，或者发送至交换机芯片202-B的MAC-Tx1。
此外，如图10a所示，交换机芯片202-B的MAC-Tx1与EB402电连接，并通过交换机芯片202-B的D2D接口(例如D2D-Tx1)以及另一个交换机芯片，例如交换机芯片202-C的D2D接口(例如D2D-Rx1)，与交换机芯片202-C的MAC-Rx1电连接。由于交换机芯片202-B的MAC-Tx1还与交换机芯片202-B的MAC-Rx1电连接，因此，该交换机芯片202-B的MAC-Tx1用于将来自交换机芯片202-B的MAC-Rx1或者交换机芯片202-B的EB402的数据发送至该交换机芯片202-B的D2D接口(例如D2D-Tx1)。
此外，由上述可知，如图9所示，同一个交换机芯片202中，MAC-Tx1会接收来自MAC-Rx1以及EB402的数据。因此，为了避免来自MAC-Rx1以及EB402的数据发生冲突，该第一链路411还包括第一缓冲器(buffer，BF)51。该第一缓冲器51与交换机芯片202的MAC-Rx1、MAC-Tx1以及EB402电连接。第一缓冲器51用于将同一个交换机芯片202中MAC-Rx1以及EB402发送至MAC-Tx1的数据进行缓存。这样一来，缓存于第一缓冲器51中的数据可以采用先进先出(first In first out，FIFO)的方式在第一缓冲器51中进行排队，并发送至MAC-Tx1。
同理，如图9所示，第二链路412可以包括第二接收端MAC接口(以下简称MAC-Rx2)和第二发送端MAC接口(以下简称MAC-Tx2)。同一个交换机芯片202中，MAC-Rx2与MAC-Tx2以及EB402电连接。
需要说明的是，第一链路411中的MAC-Rx1与MAC-Tx1，以及与第二链路412中的MAC-Rx2与MAC-Tx2可以采用标准以太网协议，也可以采用自定义的简化标准。
在此情况下，每个交换机芯片202的D2D接口31还可以包括用于接收信号的D2D-Rx2和发送信号的D2D-Tx2，上述D2D-Rx2和D2D-Tx2如图9所示与第二链路412电连接。基于此，当交换机10包括至少两个交换机芯片时，相邻的两个交换机芯片，例如如图10a所示的交换机芯片202-B的MAC-Rx2通过其自身的D2D接口(例如D2D-Rx2)以及另一个交换机芯片，例如交换机芯片202-C的D2D接口(例如D2D-Tx2)，与该交换机芯片202-C的MAC-Tx2电连接。上述交换机芯片202-B的MAC-Rx2用于将来自D2D接口(例如D2D-Rx2)的数据写入至EB402，或者发送至交换机芯片202-B的MAC-Tx2。
此外，如图10a所示，交换机芯片202-B的MAC-Tx2与EB402电连接，并通过交换机芯片202-B的D2D接口(例如D2D-Tx2)以及另一个交换机芯片，例如交换机芯片202-A的D2D接口(例如D2D-Rx2)，与交换机芯片202-A的MAC-Rx2电连接。由于交换机芯片202-B的MAC-Tx2还与交换机芯片202-B的MAC-Rx2电连接，因此，该交换机芯片202-B的MAC-Tx2用于将来自交换机芯片202-B的MAC-Rx2或者交换机芯片202-B的EB402的数据发送至该交换机芯片202-B的D2D接口(例如D2D-Tx2)。
此外，由上述可知，如图9所示，同一个交换机芯片202中，MAC-Tx2会接收来自MAC-Rx2以及EB402的数据。因此，为了避免来自MAC-Rx2以及EB402的数据发生冲突，该第二链路412还包括第二缓冲器52。该第二缓冲器52与交换机芯片202的MAC-Rx2、MAC-Tx2以及EB402电连接。第二缓冲器52用于将同一个交换机芯片202中MAC-Rx2以及EB402发送至MAC-Tx2的数据进行缓存。这样一来，缓存于第二缓冲器52中的数据可以采用FIFO的方式在第二缓冲器52中进行排队，并发送至MAC-Tx2。
在此基础上，本申请实施例提供的交换机芯片202的网络接口30可以包括如图9所示的用于接收信号的VSR-Rx和发送信号的VSR-Tx。此外，上述交换机芯片202还包括第三接收端MAC接口(以下简称MAC-Rx3)以及第三发送端MAC接口(以下简称MAC-Tx3)。MAC-Rx3和MAC-Tx3可以采用标准以太网协议。此外，交换机芯片202的处理器中的转发处理单元可以包括如图9所示的上行转发处理单元(ingress pipeline，IPP)、下行转发处理单元(egress pipeline，EPP)。
其中，MAC-Rx3与网络接口(例如，VSR-Rx)和IPP电连接。该MAC-Rx3作为数据链路层的接口用于将来自VSR-Rx的数据传输至IPP。该IPP还与SWB40电连接。IPP用于根据来自VSR-Rx的数据的源地址，获取其目的地址，并将数据写入至本地的SWB40。具体的，当VSR-Rx接收到数据包，并通过MAC-Rx3传输至IPP。当交换机芯片202执行二层转发时，该IPP可以读取数据包包头中的源MAC地址，再读取该数据包包头中的目的MAC地址，并在MAC地址表中查找与该目的MAC地址相应的接口。或者，当交换机芯片202执行三层转发时，该IPP可以读取数据包包头中的源IP地址，再读取该数据包包头中的目的IP地址，并在IP地址表中查找与该目的MAC地址相应的接口。
此外，如图9所示，EPP与MAC-Tx3以及SWB40电连接。该EPP用于对从SWB40中读取数据并发送至MAC-Tx3。当交换机芯片202进行三层转发时，EPP需要改变数 据包包头中的源MAC地址以及目的MAC地址，以完成二层封装。此外，MAC-Tx3还与网络接口(例如，MR-Tx)电连接。该MAC-Tx3作为数据链路层的接口用于将来EPP的数据传输至MR-Tx。
示例的，该交换机10中任意一个交换机芯片202的SWB40中的IB401以及EB402的数据交换容量可以均为12.8Tbps(图中简写为12.8T)。在此情况下，可以设置四个IPP分别该IB401电连接，并设置四个MAC-Rx3，一个MAC-Rx3与一个IPP电连接，使得每一路接口可以处理数据的容量为3.2Tbps(图中简写为3.2T)。同理，设置四个EPP分别该EB402电连接，并设置四个MAC-Tx3，一个MAC-Tx3与一个EPP电连接，使得每一路接口可以处理数据的容量为3.2Tbps(图中简写为3.2T)。
以下以图10a所示的交换机10的结构为例，对交换机10中四个依次首尾相接的交换机芯片202-A，交换机芯片202-B，交换机芯片202-C以及交换机芯片202-D的数据转发过程进行举例说明。该数据转发过程可以包括如图11所示的S101～S103。
在本申请的一些实施例中，当数据在交换机10中的同一个交换机芯片，例如交换机芯片202-A中进行数据转发时，目的交换机芯片与其中一个源交换机芯片均为交换机芯片202-A。
S101、源交换机芯片进行数据缓存。
具体的，图9所示的交换机芯片202-A作为其中一个源交换机芯片，其各个IPP输出的数据可以传输至交换机芯片202-A的IB401中。IB401可以对来自多个IPP的数据缓存于VOQ队列中。
需要说明的是，IB401中一个VOQ队列与一个交换机芯片的一个MAC-Tx3的一个优先级对应。例如，当交换机10包括如图4所示的四个交换机芯片，且每个交换机芯片具有32个MAC-Tx3，每个MAC-Tx3具有8个优先级时，每个交换机芯片的IB401中可以设置1024个(4×32×8＝1024个)VOQ队列。
S102、目的交换机芯片执行调度，调度结果发给源交换机芯片。
具体的，该交换机芯片202-A作为源交换机芯片时，该交换机芯片202-A的IB401会向该交换机芯片202-A的EB402发送调度请求。该交换机芯片202-A作为目的交换机芯片时，交换机芯片202-A的EB402接收交换机芯片202-A的IB401发送的调度请求。此外，交换机芯片202-A的EB402还可以接收其余的源交换机芯片，例如交换机芯片202-B、交换机芯片202-C以及交换机芯片202-D的IB401通过上述传输链路41(如图9所示)发送至交换机芯片202-A的EB402的调度请求。交换机芯片202-A的EB402根据带宽(例如，12.8T)生成多个调度结果，以执行调度，并将调度结果发送至上述各个源交换机芯片的IB401。
需要说明的是，目的交换机芯片的EB402根据带宽(例如，12.8T)生成多个调度结果，并将调度结果发送至上述各个源交换机芯片的IB401是指，目的交换机芯片的EB402接收到的调度请求可能会大于带宽(例如，12.8T)，该EB402的发送能力只有12.8T，所以EB402每次发送的调度结果不会大于12.8T，超出带宽部分会在EB402中分批次发送。
S103、源交换机芯片转发数据给目的交换机芯片。
具体的，当作为源交换机芯片的交换机芯片202-A的IB401接收到作为目的交换 机芯片的交换机芯片202-A的EB402发送的调度结果后，交换机芯片202-A的IB401可以根据调度结果，使得数据包从该IB401的VOQ队列中出队，并发送至交换机芯片202-A的EB402。该EB402可以通过EPP将数据包发送至对应的MAC-Tx3，并最终通过MR-TX发送至与该MR-TX电连接的电子设备11中，以完成数据的转发。
基于此，为了避免EB402向同一个MAC-Tx3发送的数据发生冲突，该交换机芯片202的EB402还可以根据调度结果，对即将发送至通能过一个MAC-Tx3的数据，采用FIFO的方式进行缓存。
上述是以数据在交换机10中的同一个交换机芯片，例如交换机芯片202-A中进行数据转发为例进行的说明。在本申请的另一个实施例中，交换机10在转发数据的过程中，当交换机芯片202-A将数据转发至与该交换机芯片202-A相邻的交换机芯片202-B时，交换机芯片202-A可以作为其中一个源交换机芯片，交换机芯片202-B作为目的交换机芯片。
在此情况下，交换机10的数据转发过程仍然如图11所示，具体的，首先执行S101，使得交换机芯片202-A中，各个IPP输出的数据可以缓存于作为源交换机芯片的交换机芯片202-A中IB401的多个VOQ队列中。此时，作为源交换机芯片的交换机芯片202-A中IB401可以确定的一条发送路径，该发送路径可以包括：从作为源交换机芯片的交换机芯片202-A到作为目的交换机芯片的交换机芯片202-B。
接下来，在执行S102的过程中，图10a所示的作为源交换机芯片的交换机芯片202-A的IB401会通过第一链路411(图10a中的实线箭头)向作为目的交换机芯片的交换机芯片202-B的EB402发送调度请求。交换机芯片202-B的EB402接收交换机芯片202-A的IB401发送的调度请求。此外，交换机芯片202-B的EB402还可以接收其余的源交换机芯片，例如交换机芯片202-B、交换机芯片202-C以及交换机芯片202-D的IB401通过上述第一链路411或第二链路412发送至交换机芯片202-B的EB402的调度请求。作为目的交换机芯片的交换机芯片202-B的EB402根据带宽(例如，12.8T)生成多个调度结果，并将调度结果发送至上述各个源交换机芯片的IB401。
接下来，执行上述S103，作为源交换机芯片的交换机芯片202-A的IB401接收到交换机芯片202-B的EB402发送的调度结果后，交换机芯片202-A的IB401可以根据调度结果，使得数据包从该IB401的VOQ队列中出队，将该数据可以通过上述发送路径，由第一链路411发送至交换机芯片202-B的EB402。其中，由交换机芯片202-A的IB401出队的数据可以经过交换机芯片202-A的EB402发送至交换机芯片202-A的第一缓冲器51。此时，当交换机芯片202-A的MAC-Rx1接收到的数据也发送至第一缓冲器51时，该第一缓冲器51可以采用FIFO的方式对数据进行缓存，并输出至交换机芯片202-A的MAC-Tx1。
然后，与交换机芯片202-A的MAC-Tx1电连接的交换机芯片202-B，通过该交换机芯片202-B的MAC-Rx1将数据接收至交换机芯片202-B的EB402，EB402可以通过EPP将数据包发送至交换机芯片202-B对应的MAC-Tx3，或者在交换机芯片202-B的EB402中进行一次缓存。
或者，在本申请的另一个实施例中，交换机10在转发数据的过程中，当交换机芯片202-A将数据转发至交换机芯片202-C时，交换机芯片202-A可以作为其中一个源 交换机芯片，交换机芯片202-C作为目的交换机芯片。此时，如图10b所示，沿第一反向(例如顺时针)传输数据时，交换机芯片202-A和交换机芯片202-C之间间隔有作为第一中间交换机芯片的交换机芯片202-B。或者，沿第二方向(例如逆时针)传输数据时，交换机芯片202-A和交换机芯片202-C之间间隔有作为第二中间交换机芯片的交换机芯片202-D。
在此情况下，交换机10的数据转发过程仍然如图11所示，具体的，首先执行S101，使得交换机芯片202-A中，各个IPP输出的数据可以缓存于作为源交换机芯片的交换机芯片202-A中IB401的多个VOQ队列中。此时，作为源交换机芯片的交换机芯片202-A中IB401可以确定的第一发送路径，该第一发送路径可以包括：从作为源交换机芯片的交换机芯片202-A，经过作为第一中间交换机芯片的交换机芯片202-B到作为目的交换机芯片的交换机芯片202-B。
接下来，在执行S102的过程中，图10a所示的作为源交换机芯片的交换机芯片202-A的IB401会通过第一链路411(图10a中的实线箭头)，经过交换机芯片202-B向该交换机芯片202-C的EB402发送调度请求。
然后，作为目的交换机芯片的交换机芯片202-C的EB402接收交换机芯片202-A的IB401发送的调度请求。此外，交换机芯片202-C的EB402还可以接收其余的源交换机芯片，例如交换机芯片202-B、交换机芯片202-C以及交换机芯片202-D的IB401通过上述第一链路411或第二链路412发送至交换机芯片202-C的EB402的调度请求。交换机芯片202-C的EB402根据带宽生成多个调度结果，并将调度结果发送至上述各个源交换机芯片的IB401。
接下来，执行上述S103，作为源交换机芯片的交换机芯片202-A的IB401接收到交换机芯片202-C的EB402发送的调度结果后，交换机芯片202-A的IB401可以根据调度结果，使得数据包从该IB401的VOQ队列中出队。将该数据可以通过上述第一发送路径，由第一链路411(图10a中的实线箭头)，经过交换机芯片202-B发送至交换机芯片202-C的EB402。
或者，在本申请的另一些实施例中，执行S101，交换机芯片202-A中IB401可以确定第二发送路径，该第二发送路径可以为：从交换机芯片202-A，经过作为第二中间交换机芯片的交换机芯片202-D到作为目的交换机芯片的交换机芯片202-B时，数据的发送过程同上所述，此处不再赘述。
又或者，在本申请的另一些实施例中，执行S101，作为源交换机芯片的交换机芯片202-A中IB401可以同时确定出第一发送路径和第二发送路径。接下来，在执行S102的过程中，图10a所示的作为源交换机芯片的交换机芯片202-A的IB401会通过第一链路411(图10a中的实线箭头)，经过交换机芯片202-B向该交换机芯片202-C的EB402发送调度请求。或者，交换机芯片202-A的IB401可以通过第二链路412(图10a中的虚线箭头)，经过交换机芯片202-D向该交换机芯片202-C的EB402发送调度请求。
然后，作为目的交换机芯片的交换机芯片202-C的EB402接收交换机芯片202-A的IB401发送的调度请求。此外，交换机芯片202-C的EB402还可以接收其余的源交换机芯片，例如交换机芯片202-B、交换机芯片202-C以及交换机芯片202-D的IB401 通过上述第一链路411或第二链路412发送至交换机芯片202-C的EB402的调度请求。交换机芯片202-C的EB402根据带宽生成多个调度结果，并将调度结果发送至上述各个源交换机芯片的IB401。
接下来，执行上述S103，作为源交换机芯片的交换机芯片202-A的IB401接收到交换机芯片202-C的EB402发送的调度结果后，交换机芯片202-A的IB401可以根据调度结果，使得数据包从该IB401的VOQ队列中出队。将该数据的一部分通过上述第一发送路径，由第一链路411(图10a中的实线箭头)，经过交换机芯片202-B发送至交换机芯片202-C的EB402。此外，将该数据的另一部分通过上述第二发送路径，由第二链路412(图10a中的实线箭头)，经过交换机芯片202-D发送至作为目的交换机芯片的交换机芯片202-C的EB402。其中，第二链路412中的第二缓冲器52的作用与第一缓冲器51的作用同理可得，此处不再赘述。
接下来，交换机芯片202-C的EB402可以通过EPP将数据包发送至交换机芯片202-C对应的MAC-Tx3，或者在交换机芯片202-C的EB402中进行一次缓存。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种多芯片封装结构，其特征在于，包括封装基板以及设置于所述封装基板上的多个交换机芯片，所述交换机芯片包括至少两个网络接口，以及至少一个芯片到芯片D2D接口，
    所述交换机芯片用于通过所述至少两个网络接口接入网络，且与所述网络之间收发数据；
    所述交换机芯片还用于通过所述至少一个D2D接口中的每个D2D接口与一个其他的交换机芯片相连，在彼此之间收发数据；
    所述交换机芯片还用于将接收自所述至少两个网络接口或所述至少一个D2D接口的数据，转发至所述至少两个网络接口和所述至少一个D2D接口中的至少一个接口。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述交换机芯片还包括控制逻辑，所述控制逻辑用于：
    从接收的数据中获取所述接收的数据的目的信息；
    根据所述目的信息确定发送端口，所述发送端口包括当前的交换机芯片中的所述至少一个D2D接口和所述至少两个网络接口；
    将所述接收的数据通过所述发送端口发送。
  3. 根据权利要求2所述的芯片封装结构，其特征在于，所述多个交换机芯片包括源交换机芯片和目的交换机芯片；
    所述源交换机芯片根据所述目的信息确定发送端口之后，所述源交换机芯片的控制逻辑还用于：确定所述源交换机芯片和所述目的交换机芯片之间的至少一条发送路径，对所述接收的数据进行排队缓存，并向所述目的交换机芯片发送调度请求；
    在目的交换机芯片将所述接收的数据通过所述发送端口发送之前，所述目的交换机芯片的控制逻辑还用于：根据所述调度请求以及所述目的交流换机芯片的带宽生成调度结果；所述源交换机芯片的控制逻辑还用于：根据所述调度结果，使得所述接收的数据从队列中出队，将所述接收的数据通过所述至少一条发送路径，发送至所述目的交换机芯片。
  4. 根据权利要求3所述的芯片封装结构，其特征在于，所述多芯片封装结构包括四个所述交换机芯片；每个所述交换机芯片包括两个所述D2D接口，用于分别与其他两个交换机芯片的D2D接口相连接；四个所述交换机芯片依次收尾电连接。
  5. 根据权利要求4所述的芯片封装结构，其特征在于，所述源交换机芯片与所述目的交换机芯片相邻；
    所述源交换机芯片的控制逻辑具体用于：确定的一条所述发送路径，将所述接收的数据通过所述发送路径，发送至所述目的交换机芯片；其中，所述发送路径包括：从所述源交换机芯片到所述目的交换机芯片。
  6. 根据权利要求4所述的芯片封装结构，其特征在于，四个所述交换机芯片中，所述源交换机芯片和所述目的交换机芯片之间间隔有一个中间交换机芯片；
    所述源交换机芯片的控制逻辑具体用于：确定的一条所述发送路径，将所述接收的数据通过所述发送路径，发送至所述目的交换机芯片；其中，所述发送路径包括： 从所述源交换机芯片，经过所述中间交换机芯片到所述目的交换机芯片。
  7. 根据权利要求4所述的芯片封装结构，其特征在于，四个所述交换机芯片中，沿第一方向，所述源交换机芯片和所述目的交换机芯片之间间隔有第一中间交换机芯片，沿第二方向，所述源交换机芯片和所述目的交换机芯片之间间隔有第二中间交换机芯片；其中，所述第一方向和所述第二方向相反；
    所述源交换机芯片的控制逻辑具体用于：确定的第一发送路径，将所述接收的数据的一部分通过所述第一发送路径，发送至所述目的交换机芯片；其中，所述第一发送路径包括：从所述源交换机芯片，经过所述第一中间交换机芯片到所述目的交换机芯片；
    确定的第二发送路径，将所述接收的数据的另一部分通过所述第二发送路径，发送至所述目的交换机芯片；其中，所述第二发送路径包括：从所述源交换机芯片，经过所述第二中间交换机芯片到所述目的交换机芯片。
  8. 根据权利要求4-7任一项所述的芯片封装结构，其特征在于，所述交换机芯片还包括：
    交换缓存单元，用于执行所述控制逻辑；
    传输链路；所述传输链路与所述D2D接口以及所述交换缓存单元电连接，所述传输链路用于所述D2D接口与所述交换缓存单元之间，以及不同D2D接口之间收发数据。
  9. 根据权利要求8所述的多芯片封装结构，其特征在于，所述传输链路包括：
    第一链路；所述第一链路包括依次电连接的第一接收端媒体访问控制MAC接口、第一缓冲器以及第一发送端MAC接口；所述第一接收端MAC接口和所述第一发送端MAC接口与所述交换机芯片的两个D2D接口分别电连接；所述第一接收端MAC接口、所述第一缓冲器还与所述交换缓存单元电连接；
    第二链路，所述第二链路中数据的传输方向与所述第一链路中数据的传输方向相反；所述第二链路包括依次电连接的第二接收端MAC接口、第二缓冲器以及第二发送端MAC接口；所述第二接收端MAC接口和所述第二发送端MAC接口与所述交换机芯片的两个D2D接口分别电连接；所述第二接收端MAC接口和所述第二缓冲器还与所述交换缓存单元电连接。
  10. 根据权利要求9所述的多芯片封装结构，其特征在于，四个所述交换机芯片以2×2矩阵形式进行排列；所述多芯片封装结构中，四个所述交换机芯片的所述第一链路依次首尾电连接呈环状；四个所述交换机芯片的所述第二链路依次首尾电连接呈环状。
  11. 根据权利要求2所述的多芯片封装结构，其特征在于，所述交换机芯片还包括：
    转发处理单元，用于执行所述控制逻辑；
    第三接收端MAC接口，与所述网络接口和所述转发处理单元电连接，用于将来自所述网络接口的数据传输至所述转发处理单元；
    第三发送端MAC接口，与所述网络接口和所述转发处理单元电连接，用于将来自所述转发处理单元的数据传输至所述网络接口。
  12. 根据权利要求1所述的多芯片封装结构，其特征在于，所述多芯片封装结构中，任意两个所述交换机芯片的交换带宽相同。
  13. 根据权利要求1-12任一项所述的多芯片封装结构，其特征在于，所述多芯片封装结构还包括多个光模块设置于所述封装基板上，且与所述交换机芯片位于同一侧。
  14. 一种交换机，其特征在于，包括电路板，以及设置于所述电路板上的如权利要求1-13任一项所述的多芯片封装结构。
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