WO2022038349A1

WO2022038349A1 - Differential impedance to voltage converter circuit and system

Info

Publication number: WO2022038349A1
Application number: PCT/GB2021/052129
Authority: WO
Inventors: Alberto GOMEZ SAIZ; Giovanni ROVERE; Faisal AWQATI
Original assignee: Crypto Quantique Limited
Priority date: 2020-08-18
Filing date: 2021-08-17
Publication date: 2022-02-24
Also published as: GB2598118B; GB202012901D0; GB2598118A

Abstract

A differential impedance to voltage converter (600) is described herein. Some examples describe a differential impedance to voltage converter circuit having multiple feedbacks (602, 604) and cross-coupled connections (606, 608). Some examples describe a differential impedance to voltage converter circuit having an offset storage mode and an impedance to voltage conversion mode. A system for converting impedance to voltage is also described.

Description

DIFFERENTIAL IMPEDANCE TO VOLTAGE CONVERTER CIRCUIT AND SYSTEM

TECHNICAL FIELD

[0001] The present disclosure relates generally to impedance to voltage conversion. In particular, the present disclosure relates to differential impedance to voltage conversion.

BACKGROUND

[0002] An operational amplifier arranged in a circuit as a transimpedance amplifier facilitates the measurement of the impedance of an input. Figure 1A illustrates a known transimpedance amplifier 100 having a single input V_P, which is connected to the inverting input of the operational amplifier, and a single output V_0UT. The non-inverting input of the operational amplifier is connected to a reference voltage, such as ground. There is a feedback loop from the output of the operational amplifier to the non-inverting input which has a resistance R_f 106. The operational amplifier 110 is an ideal operational amplifier which therefore has infinite open loop gain, infinite input impedance such that no current flows into either input terminal, zero output impedance, infinite bandwidth and zero input offset voltage. Due to the infinite input impedance, the current all flows through resistor R_f and so the voltage V_0UT = -Rfl^ Thus, the output of the transimpedance amplifier 110 can be used to calculate the input current I_± and consequently the impedance of the input. However, it does not produce an output based on the difference between the impedance of two inputs, as the transimpedance amplifier only receives one input. [0003] An operational amplifier can be arranged in a circuit as a differential amplifier which receives two inputs. Figure 1 B illustrates a typical differential transimpedance amplifier circuit 150. This circuit amplifies the difference between two input voltages. The operational amplifier 160 is an ideal operational amplifier, as explained above in relation to Figure 1A. The first input to the circuit has current I_INP and voltage V_INP 152 and is connected to the non-inverting input of the operational amplifier 160. The second input to the circuit has current I_INN and voltage V_INN 154 and is connected to the inverting input of the operational amplifier 160. The first and second outputs of the operational amplifier 160 have voltages V_OUTP 162 and V_OUTN 164 respectively. The first and second outputs of the operational amplifier 160 are fed back to the inverting input via resistors R_± 156 and R₂ 158 respectively. The following equation applies to the differential transimpedance amplifier circuit 150 when R = R^R- -

^OUTP ⁼ IlNpR ^an QUTN ⁼ I/NN

^OUTP ~ QUTN ⁼ ( INP ~ IINN )

[0004] The equation above illustrates the purpose of the differential transimpedance amplifier circuit 150 of Figure 1 B, which is to amplify, using R, the difference between the input currents to produce a differential output voltage. However, as shown in the above equation, the differential output voltage depends on the input differential current but not on the input differential voltage. Hence, it is not suitable to measure the input differential impedance, as this requires the output to be based on the input differential voltage. This is because the differential impedance of the input Z_INDIF is based on the input differential voltage, as shown in the following equation.

[0005] It is an object of embodiments of the invention to at least mitigate one or more of the problems of the prior art.

SUMMARY

[0006] Given two devices under test (DUTs), one may seek to measure the difference in impedance of each DUT. To do this, it is required to convert the difference in impedance of each DUT into a voltage suitable for further processing or digitization. In order to convert the difference in impedance between two inputs into a voltage, one naive approach would be to apply a first voltage across both DUTs and duplicate the transimpedance amplifier of Figure 1A so that a first current generated by the first DUT can be input into the inverting input of one of the operational amplifiers and a second input current generated by the second DUT can be input into the inverting input of another operational amplifier. The reference voltage (shown as ground in figure 1A) connected to the non-inverting input of the operational amplifier 110 of Figure 1A can be connected to the non-inverting input of both operational amplifiers to ensure the DUT impedances at the inverting inputs are subjected to the same voltage of the noninverting input. This configuration will be referred to as the dual transimpedance amplifier configuration. The outputs of the operational amplifiers would then theoretically provide a conversion into voltage, and possible amplification, of the difference in current between the first and second currents and consequently provide the difference in impedance.

[0007] However, when receiving input currents where the difference in magnitude between the currents is substantially smaller than the magnitude of the input currents, the outputs of the operational amplifiers would not be large enough to effectively provide the difference between the input currents. This is because the outputs of the dual transimpedance amplifier would be a function of the difference in current between the inputs (i.e. the differential mode) and the amount of current that is the same in both inputs (i.e. the common mode) and both the differential mode and the common mode are subject to the same amplification. Thus, for input currents where the common mode of the input currents is substantially larger than the differential mode, the amplifier outputs saturate before the differential output voltage is large enough to be further processed or digitized. [0008] Moreover, the fabrication constraints of on-chip resistors and capacitors puts a limit on the achievable transimpedance values (both common mode and differential mode) of the dual transimpedance amplifier configuration, for example, by imposing a limit on the value of the resistors and capacitors. The intrinsic noise of the components used in the dual transimpedance amplifier configuration, particularly the mismatch of components and noise, also puts a limit on achievable differential mode transimpedance values. These limitations inhibit the achievement of measurements of differential impedances which generate small (e.g. sub-picoampere scale) differential currents in integrated circuits.

[0009] To overcome this problem, the inventors have devised circuitry that includes a first connection from the output of a first operational amplifier to the inverting input of a second operational amplifier and a second connection from the output of the second operational amplifier to the inverting input of the first operational amplifier to increase the differential impedance to voltage gain of the circuit. A further explanation of how these connections provide such an advantage is provided below in relation to Figures 3, 4A, 4B, 5A and 5B.

[0010] The increase in the differential impedance to voltage gain is provided by increasing the differential mode of the input currents and decreasing the common mode of the input currents. This is advantageous over the dual transimpedance amplifier configuration where gain of the differential mode is equal to the gain of the common mode because it enables the conversion of the difference between the input impedances into larger voltages so that they can be accurately processed and digitized in integrated circuits. Thus, even small differences between two input currents can be measured. This makes it easier to measure small differences in impedance. In fact, the circuit of the present invention can be used to measure differential impedances generating sub-picoamp differential currents in integrated circuits.

[0011] The inclusion of the two connections, also referred to as bootstrapping, increases the achievable differential impedance to voltage gain beyond that achievable by the typical architectures and components. Additionally, for the same differential impedance to voltage gain achieved by typical architectures and components, the bootstrapping technique results in lower added noise.

[0012] According to an aspect of the invention, there is provided a differential impedance to voltage converter circuit. The circuit comprises a first operational amplifier comprising a first input, a second input and a first output and a second operational amplifier comprising a third input, a fourth input and a second output. The circuit further comprises a first terminal configured to receive a first input current to be converted, a second terminal electrically connected to the second input and the third input, the second terminal configured to be held at a reference voltage and a third terminal configured to receive a second input current to be converted. The circuit further comprises a first feedback loop from the first output to a first junction between the first terminal and the first input, the first feedback loop comprising a first impedance and a second feedback loop from the second output to a second junction between the third terminal and the fourth input, the second feedback loop comprising a second impedance. The circuit further comprises a first connection from the second output to a third junction between the first terminal and the first input, the first connection comprising a third impedance, and a second connection from the first output to a fourth junction between the third terminal and the fourth input, the second connection comprising a fourth impedance.

[0013] The circuit may further comprise a first device under test (DUT) electrically connected to the first terminal, wherein a first voltage may be applied across the first DUT such that the first input current from the first DUT is received at the first terminal, and a second DUT electrically connected to the third terminal, wherein the first voltage may be applied across the second DUT such that the second input current from the first DUT is received at the third terminal.

[0014] The first voltage may be selected based on the desired bias of the first and second DUTs.

[0015] The first, second, third, and/or fourth impedance may be a resistance.

[0016] The first input and the fourth input may be inverting inputs and the second input and third input may be non-inverting inputs.

[0017] The first input and the fourth input may be non-inverting inputs and the second input and third input may be inverting inputs.

[0018] The first and second input currents may be nanoampere scale currents.

[0019] The difference in current between the first input current and second input current may be a sub-picoamp current.

[0020] The first impedance may be substantially equal to the second impedance and the third impedance may be substantially equal to the fourth impedance, and the third impedance may be larger than the first impedance.

[0021] The gain of the first operational amplifier may be substantially the same as the gain of the second operational amplifier.

[0022] The differential mode of the voltage at the first and second outputs may be

and the common mode of the voltage at the first and second outputs may be

where Z_± is the first impedance, Z₃ is the third impedance, I_DIF is the differential mode of the input currents and I_CM is the common mode of the input currents.

[0023] The differential impedance to voltage converter circuit may be operable in an offset storage mode and an impedance to voltage conversion mode and may further comprise a first capacitor between the first terminal and the first input and a second capacitor between the third terminal and the fourth input. The circuit may further comprise a third feedback loop connectable between the first output and a fifth junction between the first capacitor and the first input, and a fourth feedback loop connectable between the second output and a sixth junction between the second capacitor and the fourth input, wherein the first junction and the third junction may be between the first terminal and the first capacitor and the second junction and the fourth junction may be between the third terminal and the second capacitor. In the offset storage mode, the first and second feedback loops and first and second connections may be disconnected and a seventh junction between the first capacitor and the first terminal and an eighth junction between the second capacitor and the third terminal may be configured to be held at a first voltage. Also in the offset storage mode, the third feedback loop may be connected such that the voltage offset of the first operational amplifier is stored across the first capacitor, and the fourth feedback loop may be connected such that the voltage offset of the second operational amplifier is stored across the second capacitor. In the impedance to voltage conversion mode, the third and fourth feedback loops may be disconnected, the first feedback loop may be connected such that the voltage between the first capacitor and the first terminal is the negative voltage offset which compensates the voltage offset of the first operational amplifier. Also in the impedance to voltage conversion mode, the second feedback loop may be connected such that the voltage between the second capacitor and the third terminal is the negative voltage offset which compensates the voltage offset of the second operational amplifier, and the first and second connections may be connected.

[0024] The connections enable the circuit to output voltages which amplify the differential impedance provided by the inputs. However, if the input offset voltages of the operational amplifiers are large, the connections will also amplify the error due to the differential offset voltage applied to the inputs. By combining capacitors for storing the input offset voltage and the connections for amplifying the differential impedance, the circuit is able to amplify the exact difference between the inputs without amplifying an error. Thus, this circuit provides an accurate output voltage which amplifies the differential impedance such that it can easily be processed to obtain an accurate measurement of the differential impedance of the DllTs.

[0025] Throughout the application, impedance to voltage conversion mode may be referred to as conversion mode and offset storage mode may be referred to as storage mode.

[0026] The first impedance may comprise a third capacitor and the second impedance may comprise a fourth capacitor.

[0027] The third impedance may comprise a fifth capacitor and the fourth impedance may comprise a sixth capacitor.

[0028] The circuit may further comprise a fifth feedback loop from the first output to the first and/or third junction and a sixth feedback loop from the second output to the second and/or fourth junction, the fifth feedback loop comprising a first switching element and the sixth feedback loop comprising a second switching element, wherein, before initiation, the first and second switching elements may be closed to set the initial voltage applied to the first DUT and/or second DUT, and on initiation, the first and second switching elements may be opened and remain open during a full integration period.

[0029] According to another aspect of the invention, a system is provided for converting differential impedance to voltage. The system comprises any differential impedance to voltage converter circuit described above. The system further comprises a controller configured to operate the circuit in the offset storage mode and the current to voltage conversion mode or configured to control the first and second switching elements.

[0030] The system may further comprise a filter to filter the first and second outputs. The filter may reduce the noise of the signals output from the circuit.

[0031] The system may further comprise a switch capacitor integrator to reduce the noise of the first and second outputs, and to reduce the errors of the first and second outputs due to mismatched components of the measurement system.

[0032] Many modifications and other embodiments of the inventions set out herein will come to mind to a person skilled in the art to which these inventions pertain in light of the teachings presented herein. Therefore, it will be understood that the disclosure herein is not to be limited to the specific embodiments disclosed herein. Moreover, although the description provided herein provides example embodiments in the context of certain combinations of elements, steps and/or functions may be provided by alternative embodiments without departing from the scope of the invention.

BRIEF INTRODUCTION OF THE DRAWINGS

[0033] Illustrative embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

Figure 1A illustrates a known transimpedance amplifier circuit;

Figure 1 B illustrates a known differential transimpedance amplifier circuit;

Figures 2A and 2B illustrate example circuits of devices under test;

Figure 3 shows a differential impedance to voltage converter circuit having bootstrapping; Figures 4A and 4B show the differential mode simplified equivalent circuit of the differential impedance to voltage converter circuit of Figure 3;

Figures 5A and 5B show the common mode simplified equivalent circuit of the differential impedance to voltage converter circuit of Figure 3;

Figure 6 shows an integrator configuration of the differential impedance to voltage converter circuit of Figure 3;

Figure 7 shows a system for converting differential impedance to voltage; Figure 8A shows a differential impedance to voltage converter circuit having input offset storage and bootstrapping;

Figure 8B shows a timing diagram of the switches of the differential impedance to voltage converter circuit of Figure 8A;

Figure 9 shows an array comprising a plurality of cells, each cell comprising devices under test.

[0034] Throughout the description and the drawings, like reference numerals refer to like parts.

DETAILED DESCRIPTION

[0035] Examples provide systems and circuits suitable for converting differential impedance to a voltage suitable for further processing or digitization.

[0036] One may seek to compare the output current of two devices under test (DUTs). For example, one may seek to compare the impedance of two DUTs by applying a voltage across each DUT and using the output current to calculate the differential impedance of the DUTs. Figure 2A illustrates a first device under test (DUT ) 302 and a second device under test (DUT_N) 304 according to an example. The first and/or second DUT may be any device, for example, an electronic component. The first and/or second DUT may be a device with a quantum tunnelling barrier, such as a capacitor or transistor. The current output of DUT_P 302 is I_INP 202 and the current output of DUT_N 304 is I_INN 204. As it is desirable to compare the currents I_INP 202 and I_INN 204, DUT_N 304 and DUT_P 302 share a common ground 206. However, they could also share other potentials.

[0037] Figure 2B illustrates an example of DUT_N and DUT_P. Figure 2B shows a cell 250 according to an example, in which both DUT_N 304 and DUT_P 302 are transistors 354 and 352 respectively of the cell 250. The gate terminal 180 of each of the transistors 352, 354 is to be connected to the differential impedance to voltage converter circuit. Source and drain terminals 182, 184 of the transistors 352, 354 are held at the same potential. For example, the source and drain terminals 182, 184 of the transistors 352, 354 may be connected to ground 206 (not shown). The gate terminal of each transistor 352, 354 is separated from the source and drain terminals 182, 184 by an oxide layer having a small thickness such that the oxide layer acts as a quantum tunnelling barrier.

[0038] In use, a potential difference exists between the gate terminal 180 of the transistors 352, 354 and the source terminal 182 (and drain terminal 184) of the transistors 352, 354. The potential difference across the insulating layer of each of the transistors enables quantum tunnelling through the quantum tunnelling barrier. Due to inherent differences in the transistors introduced during manufacture, the first quantum tunnelling barrier uniquely characterises the first transistor 352 and the second quantum tunnelling barrier uniquely characterises the second transistor 354. The potential difference may be below a threshold voltage for which current would classically be able to pass through either the first quantum tunnelling barrier or the second quantum tunnelling barrier. Therefore, whilst quantum tunnelling current may flow through the quantum tunnelling barriers of the first and second transistor 352, 354, classical current may not flow.

[0039] Due to the inherent differences between the oxide layers of the first transistor 352 and the second transistor 354, when the same potential difference is applied across the barriers of both transistors, a first quantum tunnelling current I_INP through the first transistor 352 and at terminal 316 is inherently different to a second quantum tunnelling current I_INN through the second transistor 354 and at terminal 318. The quantum tunnelling current flowing through each of the quantum tunnelling barriers is a unique identifier of each transistor 352, 354 (and therefore can be used to uniquely identify a device comprising the transistors). Tunnelling currents I_INP and I_INN measured from terminals 316 and 318 respectively are therefore characteristic of the transistors 352 and 354 and so are characteristic of the particular cell 250. [0040] These tunnelling currents are very small. When connected, the differential impedance to voltage converter circuit receives I_INP and I_INN and amplifies the difference whilst converting them into voltage V_OUTN and V_OUTP. The voltage can then be used to measure the quantum tunnelling current of each transistor 352, 354. Thus, the differential impedance to voltage converter circuit enables effective measurement of the quantum tunnelling current through the oxide layer of the transistors 352, 354 to establish the characteristic of the cell 250 and consequently the unique identity of the device containing the two transistors 352, 354.

[0041] Figure 3 shows a differential impedance to voltage converter circuit 600 according to an example. The skilled person would appreciate that the circuit architecture shown in Figure 3 is for illustrative purposes only and that other architectures may be readily implemented. This circuit 600 may be referred to as a bootstrapped differential impedance to voltage converter circuit. The circuit is to convert the DUT differential impedance, i.e. the difference in impedance between the two DllTs, to a large voltage suitable for further processing or digitization. The circuit 600 comprises first operational amplifier 310 and second operational amplifier 320. The first and second operational amplifiers 310 and 320 are modelled as ideal operational amplifiers but, when implemented, may have non-ideal characteristics. The first and second operational amplifiers 310 and 320 are voltage amplifiers and have a large input impedance and low output impedance. The first and second operational amplifiers 310 and 320 each have an inverting input, a non-inverting input and an output. An input terminal 316 is electrically connected to the inverting input of the first operational amplifier 310. The input terminal 316 may be connected to DUT_P and the input terminal 318 may be connected to DUT_N as mentioned above in relation to Figures 2A and 2B. The input terminal 316 receives input current I_INP to be converted and the input terminal 318 receives input current I_INN to be converted. In some examples, circuit 600 includes DUT_P 302 and DUT_N 304 and the input to the circuit is an applied biasing voltage across DUT_P 302 and DUT_N 304 which generate current I_INP 202 and I_INN 204 respectively. However in some examples the circuit 600 may not include the DllTs, for example, these may be detachable from the circuit. The non-inverting inputs of the first and second operational amplifiers 310 and 320 are connected to a terminal 626 that is held at reference voltage V₂. There is a feedback loop from the output of the first operational amplifier 310 to the junction 630 between the input terminal 316 and the inverting input of the first operational amplifier 310. This feedback loop has impedance Z_± 602. This feedback loop connects the inverting input and output of the first operational amplifier 310. There is also a feedback loop from the output of the second operational amplifier 320 to the junction 634 between the input terminal 318 and the inverting input of the operational amplifier 320. This feedback loop has impedance Z₂ 604. This feedback loop connects the inverting input and output of the operational amplifier 320.

[0042] In addition to the feedback loops connecting the inverting input and output of each of the first and second operational amplifiers 310, 320, the circuit 600 of Figure 3 also comprises a connection from the output of the second operational amplifier 320 to a junction 628 between the input terminal 316 and the inverting input of the first operational amplifier 310. That is, the connection, which may be referred to as a feedback loop, connects the output of the second operational amplifier 320 to the inverting input of the other operational amplifier, which is the first operational amplifier 310. This connection has impedance Z₃ 606. The circuit 600 of Figure 3 also comprises a connection from the output of the first operational amplifier 310 to a junction 632 between the input terminal 318 and the inverting input of the second operational amplifier 320. That is, the connection, which may be referred to as a feedback loop, connects the output of the first operational amplifier 310 to the inverting input of the other operational amplifier, which is the second operational amplifier 320. This connection has impedance Z₄ 608. The impedances Z_± to Z₄ are used to generate the current to voltage gain of the circuit. In particular, the connections, having impedance Z₃ and Z₄, further increase the differential current to voltage gain.

[0043] The skilled person would appreciate that the junctions 628, 630, 632, and 634 have been shown as separate junctions in the circuit 600 but that other configurations may be used. For example, first junction 630 and third junction 628 may meet at a single junction, and similarly the second junction 634 and fourth junction 632 may meet at a single junction. For example, the feedback loop and connection that form the first junction 630 and third junction 628 may be electrically connected and form their own junction before meeting at a single junction at the inverting input to the operational amplifier 310. The feedback loop and connection that form the second junction 634 and fourth junction 632 may be electrically connected and form their own junction before meeting at a single junction at the inverting input to the operational amplifier 320.

[0044] The circuit has the following conditions

Zi « Z₂ Z₃ « Z₄ Z₃ > Z-L X-L « 4₂ i » 1

[0045] The output of the circuit may be expressed as a function of a common mode and a differential mode. The common mode is representative of the amount of current common to both inputs, i.e. the minimum of I_INP and I_INN. The differential mode is representative of the difference in current between the two inputs. To aid in explaining the analysis of the circuit 600 of Figure 3, the Figures 4A and 4B show only the differential mode circuits of the circuit 600, and Figures 5A and 5B show only the common mode circuits of the circuit 600. The circuits 750 and 850 of Figures 4B and 5B are equivalent circuits of the circuits 700 and 800 of Figures 4A and 5A respectively. The relationship between the common mode input current and differential mode input current and the input currents I_INP and I_INN is shown below.

[0046] Firstly, input currents I_INP and I_INN are defined. lNP ⁼ lNN ⁼ ^2

[0047] Secondly, the differential mode input current I_DIF and common mode input current I_CM are defined.

I DIF ⁼ (J INP ~ NN

[0048] Finally, using the above equations, input currents I_INP and I_INN can be defined in terms of common mode and differential mode currents.

[0049] In the common mode equivalent circuits of Figures 5A and 5B and the differential mode equivalent circuits of Figures 4A and 4B, the input currents have been replaced with the common mode and differential mode currents respectively based on the above equations such that only the common mode and differential mode currents appear in these figures.

[0050] Figure 4A shows the extracted differential mode circuit 700 of circuit 600 of Figure 3. In this figure, the I_INP branch appears as ^^D1F 12 ^ar|d the I_INN branch appears as ~^Idi f The difference between these currents is therefore I_DIF. The circuit 700 of Figure 4A can be simplified to the circuit 750 of Figure 4B by symmetry such that the circuit 750 of Figure 4B is equivalent to the circuit 700 of Figure 4A. The difference between V_OUTP and V_OUTN is V_0UTDIF. The triangle 716 represents an ideal amplifier with a gain of -1 and multiplies the input with a gain of -1 and outputs the result to Z₃. This triangle 716 represents the connections between the output of each operational amplifier to the inverting input of the other operational amplifier. As mentioned above, Z_± « Z₂ and Z₃ « Z₄ so the impedances can be simplified to just Z_± and Z₃, as illustrated in Figure 4B.

[0051] The following equations apply to the differential mode equivalent circuit 750 of Figure 4B.

[0052] The amplifier gain is much larger than 1 so— > >

^Z « 0 so / 1 _Zi 1 = ^l/°^[ Z^T ,^D,F and I_z 3 = ^V° Z^U 3^TDIF

[0053] Applying Kirchhoffs law:

[0054] If there was no connection between the output of the second operational amplifier and the input of the first operational amplifier, Z₃ would not exist and so the differential gain (GM_DIFF) would be -Z_±. As mentioned above, Z₃ > Z_± so the differential gain (GM_DIFF) is larger due to the connection between the different operational amplifiers of impedance Z₃. Thus, circuit 600 of Figure 3 provides an increased differential impedance to voltage gain (GM_DIFF) with respect to typical implementations.

[0055] Figure 5A shows the extracted common mode circuit 800 of circuit 600 of Figure 3. The common mode current of the current I_INP and the current I_INN is I_CM 812. The circuit 800 of Figure 5A can be simplified to the circuit 850 of Figure 5B by symmetry such that the circuit 850 of Figure 5B is equivalent to the circuit 800 of Figure 5A. The common mode voltage of V_OUTP and V_OUTN is V_0UTCM. As mentioned above, Z_r = Z₂ and Z₃ = Z₄ so the impedances can be simplified to just Z_r and Z₃, as illustrated in Figure 5B.

[0056] The following equations apply to the common mode equivalent circuit 850 of Figure 5B. QUTCM — ^l^CM

[0057] The amplifier gain is m

[0058] Applying Kirchhoffs law:

[0059] As mentioned above, Z₃ > Z so the common mode gain (GM_CM) is smaller due to the connection between the different operational amplifiers of impedance Z₃. Thus, circuit 600 of Figure 3 provides a decreased common mode impedance to voltage gain (GM_CM) with respect to typical implementations.

[0060] Thus, the connections between operational amplifiers are a form of bootstrapping that allows both increased differential impedance to voltage gain and decreased common mode impedance to voltage gain with respect to typical implementations.

[0061] Figure 6 shows a differential impedance to voltage converter circuit 900 according to an example. The differential impedance to voltage converter circuit 900 is an example of differential impedance to voltage converter circuit 600 of Figure 3. By including capacitors as each of the impedances 7. to Z₄ and switches and S₂, the circuit 600 of Figure 3 can be operated in integration mode, as shown in circuit 900 of Figure 6. The circuit 900 is in an integration configuration. The circuit 900 is the same as circuit 600 of Figure 3 except the circuit 900 includes switches

and S₂, impedance Z₃ 606 comprises capacitance C₃ 906, impedance Z₄ 602 comprises capacitance 902, impedance Z₂ 604 comprises capacitance C₂ 904 and impedance Z₄608 comprises capacitance C₄ 908. The switches and S₂, when closed, provide direct feedback between the output and inverting input of first and second operational amplifiers 310 and 320 respectively and are used to set the initial voltage applied to the DllTs. The switches and S₂ are closed at the beginning of the operation to set the initial voltage applied to DllTs. Then the switches are opened and remain in this state during the full integration period. In some examples the circuit 900 may not include the DllTs, for example, these may be detachable from the circuit.

[0062] Figure 7 shows a system 1000 according to an example. The system 1000 comprises a differential impedance to voltage converter circuit 1004 and a controller 1002. The differential impedance to voltage converter circuit 1004 may be any of the differential impedance to voltage converter circuits mentioned above. For example, differential impedance to voltage converter circuit 1004 may be differential impedance to voltage converter circuit 600 of Figure 3, differential impedance to voltage converter circuit 900 of Figure 6 or differential impedance to voltage converter circuit 1100 of Figure 8A. The controller 1002 is configured to control the switches of the circuit 1004. For example, where circuit 1004 is differential impedance to voltage converter circuit 1100 of Figure 8A, controller may control whether the switches S_o to S₉ are open or closed, depending on the mode the circuit is operating in. When circuit 1004 is differential impedance to voltage converter circuit 900 of Figure 6, the controller may control whether the switches

and S₂ are open or closed, based on whether they are setting the initial voltage or during the full integration period. The controller may also be configured to determine the value of and/or provide voltages V_± and V₂ to terminals 324 and 326 respectively when the controller is controlling circuit 1100 of Figure 8A, or to determine the value of and/or provide voltage V₂ to terminal 626 when the controller is controlling circuit 600 of Figure 3 or circuit 900 of Figure 6.

[0063] The system 1000 may further comprise a filter 1102 and an integrator 1104. For example, the filter 1102 may filter the outputs V_OUTP and V_OUTN of the differential impedance to voltage converter circuit 1004 to remove high frequency components. The filter 1102 may provide enhanced noise reduction capabilities. The integrator 1104 may be a switch capacitor integrator to reduce the noise of the outputs V_OUTP and V_OUTN. The integrator 1104 may reduce the noise at the outputs and reduce measurement errors due to mismatch effects of components of the measurement system. [0064] Figure 8A shows a differential impedance to voltage converter circuit 1100 according to an example. The differential impedance to voltage converter circuit 1100 may comprise the features of differential impedance to voltage converter circuit 600 of Figure 3. The circuit 1100 may be a differential impedance to voltage converter circuit having both input offset storage and bootstrapping.

[0065] The differential impedance to voltage converter circuit 1100 comprises a first operational amplifier 310 and a second operational amplifier 320, each with an inverting input, a noninverting input and an output. The first and second operational amplifiers 310 and 320 may be first and second operational amplifiers 310, 320 of Figures 3 and/or 6. The output of the first operational amplifier 310 is connected to an output terminal 312 which has a voltage V_OUTP. The output of the second operational amplifier 320 is connected to an output terminal 314 which has a voltage V_OUTN. The non-inverting input of both first and second operational amplifiers 310, 320 is connected to a terminal 326 which is held at a reference voltage V₂.

[0066] The circuit 1100 has two terminals 316, 318 to receive input current, the first terminal 316 configured to receive current I_INP 202 from DUT_P 302 and the second terminal 318 configured to receive current I_INN 204 from DUT_N 304. In some examples, circuit 1100 includes DUT_P 302 and DUT_N 304. In some examples the circuit 1100 may not include the DllTs, for example, these may be detachable from the circuit. The terminal 316 is connected to the inverting input of the first operational amplifier 310 via a capacitor C_± 306. The terminal 318 is connected to the inverting input of the second operational amplifier 320 via a capacitor C₂ 308. These capacitors provide the circuit 1100 with input offset storage for both operational amplifiers, as explained below.

[0067] The circuit 1100 comprises a junction 340 between the input terminal 316 and the capacitor C_± 306 which is connected to a terminal 324 having a voltage V_±. The circuit 1100 comprises a switch Si 402 between the junction 340 and the terminal 316. In some examples, the circuit 1100 may comprise a switch S_o 366 between the input terminal 316 and the junction 340. The circuit 1100 also comprises a feedback loop between the output of the first operational amplifier 310 and a junction 328 between the capacitor C_± 306 and the inverting input of the first operational amplifier 310, the feedback loop comprising a switch S₂ 406.

[0068] The circuit 1100 also comprises a junction 342 between the input terminal 318 and the capacitor C₂ 308 which is also connected to terminal 324 having voltage V_±. The circuit 1100 comprises a switch S₆ 404 between the junction 342 and the terminal 318. In some examples, the circuit 1100 may comprise a switch S₅ 368 between the input terminal 318 and the junction 342. The circuit 1100 also comprises a feedback loop between the output of the second operational amplifier 320 and a junction 330 between the capacitor C₂ 308 and the inverting input of the second operational amplifier 320, the feedback loop comprising a switch S₇ 412. [0069] The circuit 1100 also comprises a feedback loop between the output of the first operational amplifier 310 and a junction 356 between the input terminal 316 and the capacitor 306. This feedback loop has impedance 312 and a switch S₃ 408. There is also a feedback loop between the output of the second operational amplifier 320 and a junction 358 between the input terminal 318 and the capacitor 308. This feedback loop has impedance Z₂ 314 and a switch S₈ 414.

[0070] The circuit 1100 also comprises a connection from the output of the second operational amplifier 320 to a junction 628 between the terminal 316 and the inverting input of the first operational amplifier 310, the connection having impedance Z₃ 606 and a switch S₄ 1108. The circuit 1100 of Figure 8A also comprises a connection from the output of the first operational amplifier 310 to a junction 632 between the terminal 318 and the inverting input of the second operational amplifier 320, the connection having impedance Z₄608 and a switch S₉ 1114. These connections, a form of bootstrapping, increase the differential mode impedance to voltage gain and reduce the common mode impedance to voltage gain of the outputs V_OUTP and V_OUTN, as explained in relation to Figures 3, 4A, 4B, 5A and 5B above.

[0071] The circuit 1100 is operable in a storage mode and a conversion mode. When switches Si, S₆, S₂ and S₇ are closed and switches S_o, S₅, S₃, S₄, S₈ and S₉ are open, the circuit 1100 is operating in storage mode. When switches S_x, S₆, S₂ and S₇ are open and switches S_o, S₅, S₃, S₄, S₈ and S₉ are closed, the circuit 1100 is operating in conversion mode. In an example, the impedance to voltage converter circuit 1100 is first configured to operate in storage mode and is subsequently configured to operate in conversion mode. The circuit may be operated in a transition mode between storage mode and conversion mode.

[0072] In some examples, DUT_P 302 and DUT_N 304 are only connected as illustrated in Figure 8A when the circuit 1100 is operating in impedance to voltage conversion mode. In other examples, DUT_P 302 and DUT_N 304 are connected in all modes and circuit 1100 further comprises switch S_o 366 and switch S₅ 368, which are open in offset storage mode and transition mode and are closed in impedance to voltage conversion mode. These switches may be used to control the provision of the input currents I_INP 202 and I_INN 204 that have been provided by DUT_P 302 and DUT_N 304 respectively so that these currents are only provided in impedance to voltage conversion mode i.e. when they needs to be measured and not in storage mode.

[0073] Regarding the operation of circuit 1100, voltage V_± 324 is applied across DUT_P and DUT_N which generates input current I_INP and DUT_N which generates input current I_INN. The input current I_INP to the operational amplifier 310 is generated by DUT_P based on the impedance of the DUT. The output voltage V_OUTP is based on the input current I_INP and consequently based on the impedance of the DUT. The input current I_INN to the operational amplifier 320 is generated by DUT_N based on the impedance of the DUT. The output voltage V_OUTN is based on the input current I_INN and consequently based on the impedance of the DUT. Thus, the circuit 1100 enables accurate conversion and amplification from DUT impedance to voltage. Moreover, the potential difference V_OUTP and V_OUTN enables the difference between the impedance of each DUT to be calculated. The voltage V_± is selected depending on the desired bias of the DUTs. The voltage V_± may therefore be referred to as the DUT bias voltage. The voltage V₂ may be the same, or substantially the same, as the voltage V_±. The voltage V₂ may be different to the voltage V_± due to the presence of the presence of the capacitors C_± and C₂. [0074] Ideal operational amplifiers are known to have infinite open loop gain, infinite input impedance such that no current flows into either input terminal, zero output impedance, infinite bandwidth and zero input offset voltage. However operational amplifiers 310 and 320 are not ideal. One of the non-ideal characteristics of operational amplifiers is input offset voltage which is combined with voltage V_± 324 to provide a voltage across each DUT. The voltage applied across each DUT is therefore not the known voltage V_± 324 but is dependent on and changed by the input offset voltage of the corresponding operational amplifier, causing a voltage biasing error. This causes an error in the current that is output from each DUT because it is no longer uniquely proportional to the DUT impedances but also depends on the input offset voltage of the amplifiers. This causes errors in the output voltage of the operational amplifiers and consequently in the calculation of the impedance of each DUT because the applied bias voltage is unknown. As explained below, the capacitors C_± 306 stores the input offset voltage of operational amplifier 310 to prevent such errors occurring. The same explanation applies to operational amplifier 320 and capacitor C₂ 308.

[0075] In the offset storage mode, switches S₁, S₆, S₂ and S₇ are closed and switches S_o, S₅, S₃, S₄, S₈ and S₉ are open. The feedback loop having impedance Z_± and the feedback loop having impedance Z₂ and first and second connections having impedance Z₃ and Z₄ respectively are disconnected. A junction 340 between the first capacitor and the first terminal and a junction 342 between the second capacitor and the third terminal are configured to be held at a first voltage V_±. The feedback loop having switch S₂ is connected which permits current to flow between the output and the capacitor C_± 306. This feedback loop enables the input offset voltage of the operational amplifier to be stored across the capacitor C_± 306. The feedback loop having switch S₇ is connected which permits current to flow between the output and the capacitor C₂ 308. This feedback loop enables the input offset voltage of the operational amplifier to be stored across the capacitor C₂ 308. In the storage mode, the input offset voltage of the first operational amplifier 310, V_OFFSETA1, will be stored across the capacitor C_± 306. This is because V_C1 = V_ - V₁ = V₂ - V_0FFSETA1 - V_± = -V_OFFSETA1 when V₂ = V_±. For the same reasons, the input offset voltage of the second operational amplifier 320 will be stored across the capacitor C₂ 308. In storage mode, the DllTs may not be electrically connected to the circuit 1100, either due to being detachable or due to switches S_o 366 and S₅ 368 being open.

[0076] In the impedance to voltage conversion mode, switches S_x, S₆, S₂ and S₇ are open and switches S_o, S₅, S₃, S₄, S₈ and S₉ are closed. The feedback loops having switches S₂ and S₇ respectively are disconnected. The feedback loop having impedance Z_± is connected such that the voltage between the first capacitor C_± and the first terminal is the negative voltage offset which compensates the voltage offset of the first operational amplifier. The feedback loop having impedance Z₂ is connected such that the voltage between the second capacitor C₂ and the third terminal is the negative voltage offset which compensates the voltage offset of the second operational amplifier. The first and second connections having impedance Z₃ and Z₄ respectively are connected.

[0077] In the conversion mode, the voltage at terminal 316 is the negative of the offset voltage of the first operational amplifier 310, - V_OFFSETA1, because the capacitor C_± 306 is inverted and, due to previously being configured in the storage mode, the capacitor is storing the offset voltage V_OFFSETA1. This voltage - V_0FFSETA1 compensates the offset of the first operational amplifier 310 V_OFFSETA1.

[0078] In some examples, the outputs V_OUTP and V_OUTN of the circuit 1100 may be input into a filter 1102 and/or an integrator 1104. However, in some examples the circuit 1100 may not include a filter 1102 and/or an integrator 1104. These have been described above in relation to Figure 7.

[0079] Figure 8B shows an example timing diagram 1150 of the switches of the circuit 1100 of Figure 8A. Each signal line represents a switch being open or closed over time and may represent a control line to control the switch. For each switch, a high signal line represents the switch being closed and a low signal line represents the switch being open. At t1 1152, switches Si, S₆, S₂ and S₇ are closed, represented by their signal lines being high, and switches S_o, S₅, S₃, S₄, S₈ and S₉ are open, represented by their signal lines being low, and so the circuit 1100 is operating in storage mode. At t4 1158, switches Si, S₆, S₂ and S₇ are open and switches S_o, S₅, S₃, S₄, S₈ and S₉ are closed, and so the circuit 1100 is operating in conversion mode. Due to the delay in transitioning between storage mode and conversion mode, at t2 1154, which is between t1 1152 and t4 1158, all switches except Si and S₆ may be open. Moreover, at t3 1156, which is between t1 1152 and t4 1158, all switches except S₃, S₈, S₄ and S₉ may be open. An example time for t1 1152 is 1 ps. An example time for t2 1154 and t3 1156 either combined or separately is 0.1 ps. An example time for t4 1158 is 1ms. In this example, Z! 312 and Z₂ 314 may be capacitors having a capacitance value of 400fF, Z₃ 606 and Z₄ 608 may be capacitors having a capacitance value of 360fF and C_± 306 and C₂ 308 may have a capacitance value of 200fF. [0080] Figure 9 shows an example of a use of the differential impedance to voltage converter circuit of Figures 3, 6 or 8A. Figure 9 shows an example of a block diagram of an array 1200 for use in identifying a device. As can be seen in Figure 9, the array I arrangement 1200 comprises a plurality of cells 1206. Each cell 1206 may be cell 250 of Figure 2B. Each cell of the plurality of cells can be individually addressed using row decoder 1202 and column decoder 1204. The array 1200 may comprise any number of cells 1206. A cell may be considered as a unit of the array 1200 that can be selectively probed.

[0081] In the example shown in Figure 9, each cell 1206 comprises a single elementary circuit having a quantum tunnelling barrier, although the skilled person would appreciate that a cell may comprise, for example, an entire row or column of the array, or some other addressable unit of the array. Particular cell 1206’ comprises a first electronic component in the form of a first transistor 352, and a second electronic component in the form of a second transistor 354, which may be equated to the transistors 352 and 354 of Figure 2B. Thus, the first transistor may be DUTp 302 input into any of the circuits of Figures 3, 6 and 8A and the second transistor may be DUT_N 304 input into any of the circuits of Figures 3, 6 and 8A.

[0082] The gate terminal 180 of transistor 352 is labelled as “L” in Figure 9 and the gate terminal 180 of transistor 354 is labelled as “R” in Figure 9. The terminal “L” may be connected to input terminal 316 of the circuits of Figures 3, 6 or 8A and the terminal “R” may be connected to input terminal 318 of the circuits of Figures 3, 6 or 8A. The cell 1206’ may be selected using the row decoder 1202 and column decoder 1204 to apply a voltage to terminal “V” in order to apply a potential difference across the quantum tunnelling barriers of the first and second transistors 352, 354. The voltage applied across the quantum tunnelling barrier may be reference voltage V_lt as discussed above in relation to Figure 8A.

[0083] A method for determining an identifier value of a device and the required processing circuitry to operate the above array is described further in United Kingdom patent application no. 1905446.9, entitled “Device Identification With Quantum Tunnelling Currents” and filed on 17 April 2019, which is incorporated by reference herein in its entirety for all purposes.

[0084] A quantum tunnelling current from a cell 1206 of an array 1200 is usually very small (on the scale of nano-amperes or smaller). Each cell 1206 may comprise further electronic circuitry to be able to handle such small currents, for example a switching circuit in order to be able to effectively turn the cell “off”. Such circuitry has been described in United Kingdom patent application no. 1807214.0, entitled “Near-zero leakage switching circuit” and filed on 2 May 2018, which is incorporated by reference herein in its entirety for all purposes.

[0085] Variations of the described embodiments are envisaged, for example, the features of all of the disclosed embodiments may be combined in any way and/or combination, unless such features are incompatible. [0086] A quantum tunnelling barrier as described herein may be of any suitable thickness such that quantum tunnelling through the barrier can occur. For example, the quantum tunnelling barrier may be less than 5nm, or less than 4nm, or less than 3nm, or less than 2nm or less than 1nm. The quantum tunnelling barrier may be formed of any suitable insulating material such as a dielectric oxide. Although silicon has been mentioned throughout this specification other materials may be used, such as lll-V materials. In order to form the quantum tunnelling barriers, dielectrics of any suitable kind may be used. In an example, high-k dielectrics may be used.

[0087] Throughout the specification, transistor devices have been described. The skilled person will appreciate that the transistor devices may be p- or/and n- doped transistor devices and that the dopant density of the devices can also be varied.

[0088] A circuit or system described above may be implemented on a chip, a computer, a tablet, a mobile phone or any other such device.

[0089] It will be appreciated that embodiments of the present invention can be realised in the form of hardware, software or a combination of hardware and software. Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like a ROM, whether erasable or rewritable or not, or in the form of memory such as, for example, RAM, memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a CD, DVD, magnetic disk or magnetic tape. It will be appreciated that the storage devices and storage media are embodiments of machine-readable storage that are suitable for storing a program or programs that, when executed, implement embodiments of the present invention. Accordingly, embodiments provide a program comprising code for implementing a system or method as claimed in any preceding claim and a machine-readable storage storing such a program. Still further, embodiments of the present invention may be conveyed electronically via any medium such as a communication signal carried over a wired or wireless connection and embodiments suitably encompass the same.

[0090] All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

[0091] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. [0092] The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. The claims should not be construed to cover merely the foregoing embodiments, but also any embodiments which fall within the scope of the claims.

Claims

1 . A differential impedance to voltage converter circuit comprising: a first operational amplifier comprising a first input, a second input and a first output and a second operational amplifier comprising a third input, a fourth input and a second output, a first terminal configured to receive a first input current to be converted, a second terminal electrically connected to the second input and the third input, the second terminal configured to be held at a reference voltage, a third terminal configured to receive a second input current to be converted, a first feedback loop from the first output to a first junction between the first terminal and the first input, the first feedback loop comprising a first impedance, a second feedback loop from the second output to a second junction between the third terminal and the fourth input, the second feedback loop comprising a second impedance, a first connection from the second output to a third junction between the first terminal and the first input, the first connection comprising a third impedance, and a second connection from the first output to a fourth junction between the third terminal and the fourth input, the second connection comprising a fourth impedance.

2. A differential impedance to voltage converter circuit as claimed in claim 1 , the circuit further comprising: a first device under test (DUT) electrically connected to the first terminal, wherein a first voltage is applied across the first DUT such that the first input current from the first DUT is received at the first terminal, and a second DUT electrically connected to the third terminal, wherein the first voltage is applied across the second DUT such that the second input current from the first DUT is received at the third terminal.

3. A differential impedance to voltage converter circuit as claimed in claim 2, wherein the first voltage is selected based on the desired bias of the first and second DUTs.

4. A differential impedance to voltage converter circuit as claimed in claim 1 , wherein the first input and the fourth input are inverting inputs and the second input and third input are non-inverting inputs. A differential impedance to voltage converter circuit as claimed in claim 1 or claim 2, wherein the first and second input currents are nanoampere scale currents. A differential impedance to voltage converter circuit as claimed in any preceding claim, wherein the difference in current between the first input current and second input current is a sub-picoamp current. A differential impedance to voltage converter circuit as claimed in any preceding claim, wherein the first impedance is substantially equal to the second impedance and the third impedance is substantially equal to the fourth impedance, and wherein the third impedance is larger than the first impedance. A differential impedance to voltage converter circuit as claimed in any preceding claim, wherein the gain of the first operational amplifier is substantially the same as the gain of the second operational amplifier. A differential impedance to voltage converter circuit as claimed in any preceding claim, wherein, the differential mode of the voltage at the first and second outputs is

and the common mode of the voltage at the first and second outputs is

is the first impedance, Z₃ is the third impedance, II_DIF is the differential mode of the input currents and II_CM is the common mode of the input currents. A differential impedance to voltage converter circuit as claimed in any preceding claim, the differential impedance to voltage converter circuit being operable in an offset storage mode and an impedance to voltage conversion mode and further comprising: a first capacitor between the first terminal and the first input and a second capacitor between the third terminal and the fourth input; a third feedback loop connectable between the first output and a fifth junction between the first capacitor and the first input; and a fourth feedback loop connectable between the second output and a sixth junction between the second capacitor and the fourth input; wherein the first junction and the third junction are between the first terminal and the first capacitor and the second junction and the fourth junction are between the third terminal and the second capacitor; wherein, in the offset storage mode: the first and second feedback loops and first and second connections are disconnected; a seventh junction between the first capacitor and the first terminal and an eighth junction between the second capacitor and the third terminal are configured to be held at a first voltage; the third feedback loop is connected such that the voltage offset of the first operational amplifier is stored across the first capacitor, and the fourth feedback loop is connected such that the voltage offset of the second operational amplifier is stored across the second capacitor; and wherein, in the impedance to voltage conversion mode: the third and fourth feedback loops are disconnected; the first feedback loop is connected such that the voltage between the first capacitor and the first terminal is the negative voltage offset which compensates the voltage offset of the first operational amplifier; the second feedback loop is connected such that the voltage between the second capacitor and the third terminal is the negative voltage offset which compensates the voltage offset of the second operational amplifier; and the first and second connections are connected. A differential impedance to voltage converter circuit as claimed in any preceding claim, wherein the first impedance comprises a third capacitor and the second impedance comprises a fourth capacitor. A differential impedance to voltage converter circuit as claimed in claim 11 , wherein the third impedance comprises a fifth capacitor and the fourth impedance comprises a sixth capacitor. A differential impedance to voltage converter circuit as claimed in claim 12, when dependent on claim 11 , the circuit further comprising a fifth feedback loop from the first output to the first and/or third junction and a sixth feedback loop from the second output to the second and/or fourth junction, the fifth feedback loop comprising a first switching element and the sixth feedback loop comprising a second switching element, wherein, before initiation, the first and second switching elements are closed to set the initial voltage applied to the first DUT and/or second DUT, and on initiation, the first and second switching elements are opened and remain open during a full integration period. A system for converting impedance to voltage, comprising: an impedance to voltage converter circuit as claimed in claim 10; and a controller configured to operate the circuit in the offset storage mode and the current to voltage conversion mode. A system for converting differential impedance to voltage, comprising: a differential impedance to voltage converter circuit as claimed in claim 13; and a controller to control the first and second switching elements. The system as claimed in claim 14 or claim 15, the system further comprising a filter to filter the noise of the first and second outputs. The system as claimed in any of claims 14 to 16, the system further comprising a switch capacitor integrator to improve the signal to noise ratio of the first and second outputs.