WO2022034828A1 - Semiconductor device - Google Patents

Abstract

This semiconductor device includes: a semiconductor layer having a first main surface and a second main surface; a first-electroconductivity-type drift region formed inside the semiconductor layer; a second-electroconductivity-type base region formed on the surface layer part of the drift region; a plurality of trench structures including a first trench structure, a second trench structure, and a third trench structure, which are formed with gaps therebetween in the first main surface so as to penetrate the base region; a first region partitioned between the first trench structure and the second trench structure in the semiconductor layer; a second region partitioned between the second trench structure and the third trench structure in the semiconductor layer; a channel region controlled by the first trench structure; and a first-electroconductivity-type high-concentration region having a higher concentration than the drift region, the high-concentration region being formed in a second-main-surface-side region with respect to the base region in either of the first region or the second region.

Description

Semiconductor device

This application corresponds to Japanese Patent Application No. 2020-135971 filed with the Japan Patent Office on August 11, 2020, and the entire disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor).

Patent Document 1 discloses a semiconductor device including a trench-type IGBT. This semiconductor device has a semiconductor layer having one surface and the other surface, a p-type semiconductor region formed on the surface layer portion of one main surface of the semiconductor layer, and n formed on the surface layer portion of the other main surface of the semiconductor layer. It includes a type semiconductor region and a high concentration region formed between a p-type semiconductor region and an n-type semiconductor region and having an n-type impurity concentration higher than that of the n-type semiconductor region.

U.S. Patent Application Publication No. 2018/083131

One embodiment of the present invention provides a semiconductor device having a novel structure.

One embodiment of the present invention comprises a semiconductor layer having a first main surface on one side and a second main surface on the other side, a first conductive type drift region formed in the semiconductor layer, and the drift region. A second conductive type base region formed on the surface layer portion, and a first trench structure, a second trench structure, and a third trench structure formed at intervals on the first main surface so as to penetrate the base region. A plurality of trench structures including, a first region partitioned between the first trench structure and the second trench structure in the semiconductor layer, and the second trench structure and the third trench structure in the semiconductor layer. A second region partitioned between the two regions, a channel region controlled by the first trench structure, and a first conductive impurity concentration higher than the drift region, and either the first region or the second region. On one side, the first conductive type high concentration region formed in the region on the second main surface side with respect to the base region and not formed on the other side of the first region and the second region is included. , Provides semiconductor devices.

In one embodiment, a semiconductor layer having a first main surface on one side and a second main surface on the other side, a first conductive type drift region formed in the semiconductor layer, and a surface layer portion of the drift region. A plurality of formed second conductive type base regions, including a first trench structure, a second trench structure, and a third trench structure formed at intervals on the first main surface so as to penetrate the base region. In the semiconductor layer, a first region partitioned between the first trench structure and the second trench structure in the semiconductor layer, and a partition between the second trench structure and the third trench structure in the semiconductor layer. A second region, a channel region controlled by the first trench structure, and a first conductive impurity concentration higher than the drift region, in at least one of the first region and the second region. Provided is a semiconductor device including a first conductive type high concentration region formed on a surface layer portion of the drift region so as to be connected to the base region from one direction along the first main surface.

The above or yet other objectives, features and effects will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

FIG. 1 is a plan view showing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view showing the structure of the first main surface of the semiconductor layer. FIG. 3 is an enlarged view of the region III shown in FIG. FIG. 4 is an enlarged view of the region IV shown in FIG. FIG. 5 is a cross-sectional view taken along the line VV shown in FIG. 4, and is a cross-sectional view showing a first embodiment example of the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing a second embodiment example of the semiconductor device shown in FIG. FIG. 7 is a cross-sectional view showing a third embodiment example of the semiconductor device shown in FIG. FIG. 8 is a cross-sectional view showing a fourth embodiment example of the semiconductor device shown in FIG. FIG. 9 is a cross-sectional view showing the semiconductor device according to the second embodiment of the present invention together with the structure according to the first embodiment. FIG. 10 is a cross-sectional view showing a second embodiment example of the semiconductor device shown in FIG. FIG. 11 is a cross-sectional view showing a third embodiment example of the semiconductor device shown in FIG. FIG. 12 is a cross-sectional view showing a fourth embodiment example of the semiconductor device shown in FIG. FIG. 13 is a plan view showing the internal structure of the semiconductor device according to the third embodiment of the present invention. FIG. 14 is a cross-sectional view taken along the line XIV-XIV shown in FIG. FIG. 15 is a cross-sectional view taken along the line XV-XV shown in FIG. FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. FIG. 17 is a plan view showing the internal structure of the semiconductor device according to the fourth embodiment of the present invention. FIG. 18 is a cross-sectional view taken along the line XVIII-XVIII shown in FIG. FIG. 19 is a cross-sectional view taken along the line XIX-XIX shown in FIG. FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. FIG. 21 is a plan view showing the internal structure of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 1 is a plan view showing a semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a plan view showing the structure of the first main surface 3 of the semiconductor layer 2. The semiconductor device 1 is a semiconductor switching device (electronic component) provided with an IGBT (Insulated Gate Bipolar Transistor). With reference to FIGS. 1 and 2, the semiconductor device 1 includes a rectangular parallelepiped semiconductor layer 2. In this form (this embodiment), the semiconductor layer 2 is made of a Si single crystal. The semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. ing.

With reference to FIGS. 1 and 2, the semiconductor device 1 includes a rectangular parallelepiped semiconductor layer 2. The semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. ing. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter, simply referred to as “plan view”) viewed from their normal direction Z. The side surface 5B and the side surface 5D extend along the first direction Y and face each other in the second direction X intersecting (specifically, orthogonally) the first direction Y. The side surface 5A and the side surface 5C extend along the second direction X and face each other in the first direction Y. The thickness of the semiconductor layer 2 may be 50 μm or more and 200 μm or less.

The semiconductor layer 2 includes an active region 6 and an outer region 7. The active region 6 is a region in which the IGBT is formed. The active region 6 is set in the central portion of the semiconductor layer 2 at intervals from the side surfaces 5A to 5D of the semiconductor layer 2 to the inner region in a plan view. The active region 6 may be set in a square shape having four sides parallel to the side surfaces 5A to 5D of the semiconductor layer 2 in a plan view.

The outer region 7 is an region outside the active region 6. The outer region 7 may extend in a strip shape along the peripheral edge of the active region 6 in a plan view. The outer region 7 may extend in an annular shape (endless shape) surrounding the active region 6 in a plan view. The active region 6 includes at least one IGBT region 8 formed at intervals in the first direction Y. The active region 6 includes a plurality of rows of IGBT regions 8 in this form. The plurality of IGBT regions 8 face each other in the first direction Y. The IGBT region 8 is a region in which the IGBT is formed. As shown in FIGS. 1 and 2, the plurality of IGBT regions 8 may be formed in a rectangular shape in a plan view. Specifically, the plurality of IGBT regions 8 may be formed in a rectangular shape long in the first direction Y.

In the active region 6, an emitter terminal electrode 9 (see the broken line portion in FIG. 1) is formed on the first main surface 3 (above). The emitter terminal electrode 9 may contain at least one of aluminum, copper, aluminum-silicon-copper alloy, aluminum-silicon alloy, or aluminum-copper alloy. The emitter terminal electrode 9 may have a single-layer structure containing any one of these conductive materials. The emitter terminal electrode 9 may have a laminated structure in which at least two of these conductive materials are laminated in any order. The emitter terminal electrode 9 is made of an aluminum-silicon-copper alloy in this form.

The emitter terminal electrode 9 transmits an emitter signal to the active region 6 (IGBT region 8). The emitter potential may be a circuit reference potential that serves as a reference for circuit operation. The circuit reference potential may be a ground potential or a potential exceeding the ground potential. A gate terminal electrode 10 is formed on the first main surface 3 in the outer region 7. The gate terminal electrode 10 is formed in a rectangular shape in a plan view. The gate terminal electrode 10 transmits a gate potential (gate signal) to the active region 6 (IGBT region 8). The arrangement position of the gate terminal electrode 10 is arbitrary.

The gate wiring 11 is electrically connected to the gate terminal electrode 10. The gate terminal electrode 10 may contain at least one of aluminum, copper, aluminum-silicon-copper alloy, aluminum-silicon alloy, or aluminum-copper alloy. The gate terminal electrode 10 may have a single-layer structure containing any one of these conductive materials. The gate terminal electrode 10 may have a laminated structure in which at least two of these conductive materials are laminated in any order. In this embodiment, the gate terminal electrode 10 contains the same conductive material as the emitter terminal electrode 9.

The gate wiring 11 extends from the outer region 7 toward the active region 6. The gate wiring 11 transmits the gate signal applied to the gate terminal electrode 10 to the active region 6 (IGBT region 8). Specifically, the gate wiring 11 includes an outer region 11a located in the outer region 7 and an inner region 11b located in the active region 6 and connected to the outer region 11a. The outer region 11a is electrically connected to the gate terminal electrode 10. In this embodiment, the outer region 11a is selectively routed in the region on the side surface 5D side in the outer region 7.

A plurality of inner regions 11b (four in the examples of FIGS. 1 and 2) are formed in the active region 6. The plurality of inner regions 11b are formed at intervals in the first direction Y. The plurality of inner regions 11b extend in a band shape in the second direction X. The plurality of inner regions 11b extend from the region on the side surface 5D side to the region on the side surface 5B side in the outer region 7, respectively. The plurality of inner regions 11b may cross the active region 6.

The gate signal applied to the gate terminal electrode 10 is transmitted to the inner region 11b via the outer region 11a. As a result, the gate signal is transmitted to the active region 6 (IGBT region 8) via the inner region 11b. FIG. 3 is an enlarged view of the region III shown in FIG. FIG. 4 is an enlarged view of the region IV shown in FIG. FIG. 5 is a cross-sectional view taken along the line VV shown in FIG.

With reference to FIGS. 3 ^to 5, an n− type drift region 12 is formed inside the semiconductor layer 2. Specifically, the drift region 12 is formed in the entire area of the semiconductor layer 2. The concentration of n-type impurities in the drift region 12 may be 1.0 × 10 ¹³ cm ^-3 or more and 1.0 × 10 ¹⁵ cm ^-3 or less. In this form, the semiconductor layer 2 has a single-layer structure including an n ^- type semiconductor substrate 13. The semiconductor substrate 13 may be a silicon FZ substrate formed by the FZ (Floating Zone) method or a silicon MCZ substrate formed by the MCZ (Magnetic Field applied Czochralski) method. The drift region 12 is formed by the semiconductor substrate 13.

A collector terminal electrode 14 is formed on the second main surface 4 of the semiconductor layer 2. The collector terminal electrode 14 is electrically connected to the second main surface 4. Specifically, the collector terminal electrode 14 is electrically connected to the IGBT region 8 (collector region 16 described later). The collector terminal electrode 14 forms ohmic contact with the second main surface 4. The collector terminal electrode 14 transmits a collector signal to the IGBT region 8.

The collector terminal electrode 14 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer and an Al layer. The collector terminal electrode 14 may have a laminated structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer and an Al layer are laminated in any manner. An n-type buffer layer 15 is formed on the surface layer portion of the second main surface 4 of the semiconductor layer 2. The buffer layer 15 may be formed over the entire surface layer portion of the second main surface 4. The concentration of n-type impurities in the buffer layer 15 is higher than the concentration of n-type impurities in the drift region 12. The concentration of n-type impurities in the buffer layer 15 may be 1.0 × 10 ¹⁴ cm ^-3 or more and 1.0 × 10 ¹⁷ cm ^-3 or less.

As shown in FIG. 5, each IGBT region 8 includes a p-type collector region 16 formed on the surface layer portion of the second main surface 4 of the semiconductor layer 2. The collector area 16 is exposed from the second main surface 4. The collector region 16 may be formed over the entire surface layer portion of the second main surface 4. The concentration of p-type impurities in the collector region 16 may be 1.0 × 10 ¹⁵ cm ^-3 or more and 1.0 × 10 ¹⁸ cm ^-3 or less. The collector region 16 forms ohmic contact with the collector terminal electrode 14.

In each IGBT region 8, a p-type base region 41 is formed on the surface layer portion of the first main surface 3. The concentration of p-type impurities in the base region 41 may be 1.0 × 10 ¹⁷ cm ^-3 or more and 1.0 × 10 ¹⁸ cm ^-3 or less. Each IGBT region 8 includes a FET structure 21 formed on the first main surface 3 of the semiconductor layer 2. Each IGBT region 8 includes, in this embodiment, a trench gate type FET structure 21. Specifically, the FET structure 21 includes a trench gate structure (first trench structure) 22 formed on the first main surface 3. A gate signal (gate potential) is applied to the trench gate structure 22. In FIGS. 3 and 4, the trench gate structure 22 is shown by hatching.

A plurality of trench gate structures 22 are formed in the IGBT region 8 at intervals in the second direction X. The distance between the two trench gate structures 22 adjacent to each other in the second direction X may be 1 μm or more and 20 μm or less. Each trench gate structure 22 is formed in a band shape extending in the first direction Y in a plan view. The plurality of trench gate structures 22 are formed in a striped shape as a whole in a plan view. The plurality of trench gate structures 22 have one end in the first direction Y and the other end in the first direction Y.

The FET structure 21 further includes a first outer trench gate structure 23 and a second outer trench gate structure 24. In FIG. 3, the first outer trench gate structure 23 and the second outer trench gate structure 24 are shown by hatching. The first outer trench gate structure 23 extends in the second direction X and is connected to one end of a plurality of trench gate structures 22. The second outer trench gate structure 24 extends in the second direction X and is connected to the other end of the plurality of trench gate structures 22.

The first outer trench gate structure 23 and the second outer trench gate structure 24 have the same structure as the trench gate structure 22 except that the extending directions are different. Hereinafter, the structure of the trench gate structure 22 will be mainly described. Each trench gate structure 22 includes a gate trench 31 (first trench), a gate insulating film (first insulating film) 32, and a gate electrode (first electrode) 33.

The gate trench 31 is formed on the first main surface 3 of the semiconductor layer 2. The gate trench 31 includes a side wall and a bottom wall. The side wall of the gate trench 31 may be formed perpendicular to the first main surface 3. The side wall of the gate trench 31 may be inclined downward from the first main surface 3 toward the bottom wall. The gate trench 31 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the gate trench 31 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 31 may be formed in a convex curved shape toward the second main surface 4.

The gate trench 31 penetrates the base region 41. The bottom wall of the gate trench 31 is located below the bottom of the base region 41 in the normal direction Z. The depth of the gate trench 31 may be 2 μm or more and 8 μm or less. The width of the gate trench 31 may be 0.5 μm or more and 3 μm or less. The gate insulating film 32 is formed in a film shape along the inner wall of the gate trench 31. The gate insulating film 32 partitions the recess space in the gate trench 31. The gate insulating film 32 includes a silicon oxide film in this form. The gate insulating film 32 may include a silicon nitride film in place of or in addition to the silicon oxide film.

The gate electrode 33 is embedded in the gate trench 31 with the gate insulating film 32 interposed therebetween. The gate electrode 33 is controlled by a gate signal (gate potential). The gate electrode 33 may contain conductive polysilicon. The gate electrode 33 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The gate electrode 33 has an upper end portion located on the opening side of the gate trench 31. The upper end of the gate electrode 33 is located on the bottom wall side of the gate trench 31 with respect to the first main surface 3. The gate electrode 33 is electrically connected to the gate wiring 11 in a region (not shown). The gate signal applied to the gate terminal electrode 10 is transmitted to the gate electrode 33 via the gate wiring 11.

Each IGBT region 8 includes a region separation structure 25 that partitions the FET structure 21 from other regions on the first main surface 3 of the semiconductor layer 2. The region separation structure 25 is formed in a region adjacent to the FET structure 21 in the surface layer portion of the first main surface 3. The region separation structure 25 is formed on both sides of the FET structure 21. The region separation structure 25 is formed in a region between two adjacent FET structures 21. As a result, the plurality of FET structures 21 are separated by the region separation structure 25. The region separation structure 25 is formed in a closed region partitioned by two adjacent trench gate structures 22, a first outer trench gate structure 23, and a second outer trench gate structure 24.

The region separation structure 25 includes a plurality of (three in the example of FIG. 3) separation trench structures extending in the first direction Y. In FIGS. 3 and 4, a plurality of separation trench structures 26 are shown by hatching. The plurality of separation trench structures 26 are formed in the IGBT region 8 at intervals in the second direction X. In this form, the plurality of separated trench structures 26 include a first separated trench structure 26A (second trench structure), a second separated trench structure 26B (third trench structure), and a third separated trench structure 26C (fourth trench structure). Structure) is included.

The first separation trench structure 26A is formed at a distance from one trench gate structure 22 on one side of the second direction X (on the right side of the paper in FIGS. 3 and 4). The second separation trench structure 26B is formed at a distance from the first separation trench structure 26A on one side of the second direction X. The third separation trench structure 26C is formed at a distance from the second separation trench structure 26B on one side of the second direction X. The second separation trench structure 26B is sandwiched in the second direction X by the first separation trench structure 26A and the third separation trench structure 26C.

Each separation trench structure 26 is formed in a band shape extending in the first direction Y in a plan view. The plurality of separation trench structures 26 are formed in a striped shape as a whole. The plurality of separation trench structures 26 have one end in the first direction Y and the other end in the first direction Y. The distance in the second direction X between the trench gate structure 22 and the separation trench structure 26 (first separation trench structure 26A) may be 0.5 μm or more and 5 μm or less. The distance in the second direction X between the two adjacent separation trench structures 26 may be 0.5 μm or more and 5 μm or less. The distance in the second direction X between the two adjacent separated trench structures 26 may be approximately equal to the distance in the second direction X between the trench gate structure 22 and the separated trench structure 26 (first separated trench structure 26A). preferable.

The region separation structure 25 further includes a first outer separation trench structure 27 and a second outer separation trench structure 28. In FIG. 3, the first outer separation trench structure 27 and the second outer separation trench structure 28 are shown by hatching. The first outer separation trench structure 27 extends in the second direction X and is connected to one end of the plurality of separation trench structures 26. The second outer separation trench structure 28 extends in the second direction X and is connected to the other end of the plurality of separation trench structures 26.

The first outer separation trench structure 27 and the second outer separation trench structure 28 have the same structure as the separation trench structure 26 except that the extending directions are different. Hereinafter, the structure of the separation trench structure 26 will be mainly described. Each separation trench structure 26 includes a separation trench 36 (second trench, third trench), a separation insulating film 37 (second insulating film, third insulating film), and a separation electrode 38 (second electrode, third electrode). .. The separation trench 36 is formed on the first main surface 3 of the semiconductor layer 2. The separation trench 36 includes a side wall and a bottom wall. The side wall of the separation trench 36 may be formed perpendicular to the first main surface 3.

The side wall of the separation trench 36 may be inclined downward from the first main surface 3 toward the bottom wall. The separation trench 36 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the separation trench 36 may be formed parallel to the first main surface 3. The bottom wall of the separation trench 36 may be formed in a convex curved shape toward the second main surface 4. The depth of the separation trench 36 may be 2 μm or more and 8 μm or less. The width of the separation trench 36 may be 0.5 μm or more and 3 μm or less. The width of the separation trench 36 is the width of the separation trench 36 in the second direction X. The width of the separation trench 36 may be equal to the width of the gate trench 31.

The separation insulating film 37 is formed in a film shape along the inner wall of the separation trench 36. The separation insulating film 37 partitions the recess space in the separation trench 36. The separation insulating film 37 includes a silicon oxide film in this form. The separation insulating film 37 may include a silicon nitride film in place of or in addition to the silicon oxide film. The separation electrode 38 is embedded in the separation trench 36 with the separation insulating film 37 interposed therebetween. The separation electrode 38 is electrically connected to the emitter terminal electrode 9 in a region (not shown). An emitter potential is applied to the separation electrode 38. The separation electrode 38 may contain conductive polysilicon.

The separation electrode 38 is formed in a wall shape extending along the normal direction Z in a cross-sectional view. The separation electrode 38 has an upper end portion located on the opening side of the separation trench 36. The upper end of the separation electrode 38 is located on the bottom wall side of the separation trench 36 with respect to the first main surface 3. The plurality of separated trench structures 26 partition the first region 29 from the trench gate structure 22 in the semiconductor layer 2 of the FET structure 21 in a cross-sectional view along the second direction X. The first region 29 is formed on both sides of the trench gate structure 22. The first region 29 is also a region where the FET structure 21 is formed. That is, each FET structure 21 includes, in this embodiment, two first regions 29 adjacent to each other in the first direction Y.

The first region 29 of one of the two first regions 29 is partitioned between the trench gate structure 22 and the first separation trench structure 26A. The other first region 29 of the two first regions 29 is partitioned between the trench gate structure 22 and the third separation trench structure 26C. The two first regions 29 are formed in a band shape extending along the trench gate structure 22 and the separation trench structure 26, respectively.

The plurality of separation trench structures 26 partition the second region 30 in the semiconductor layer 2 of the region separation structure 25 in a cross-sectional view along the second direction X. In this embodiment, the plurality of separation trench structures 26 partition the plurality of second regions 30 adjacent to each other in the first direction Y into the semiconductor layer 2. Each region separation structure 25 includes, in this embodiment, two second regions 30 adjacent to each other in the first direction Y.

One side region 30A of the two second regions 30 (on the left side of the paper in FIG. 5) is partitioned between the first separation trench structure 26A and the second separation trench structure 26B. The other side region 30B on the other side (right side of the paper in FIG. 5) of the two second regions 30 is partitioned between the second separation trench structure 26B and the third separation trench structure 26C. The two second regions 30 are each formed in a band shape extending along the plurality of separation trench structures 26.

In this embodiment, in the IGBT region 8, a plurality of (two in this embodiment) second regions 30 sandwich a plurality of (two in this embodiment) first regions 29, and the plurality of second regions 30 are plural. The first region 29 and the second direction X are alternately arranged. The plurality of first regions 29 and the plurality of second regions 30 are formed in a striped shape as a whole in a plan view. In the IGBT region 8, an IE (Injection Enhanced) structure including the FET structure 21 and the region separation structure 25 is formed. In the IE structure, the plurality of FET structures 21 are separated in the second direction X by the region separation structure 25.

The region separation structure 25 limits the movement of holes injected into the semiconductor layer 2. That is, the holes bypass the region separation structure 25 and flow into the FET structure 21. As a result, holes are accumulated in the region immediately below the FET structure 21 in the semiconductor layer 2, and the density of holes is increased. As a result, the on-resistance and the on-voltage are reduced (IE effect). In the FET structure 21, an n ⁺ type emitter region 42 is formed on the surface layer portion of the base region 41. The concentration of n-type impurities in the emitter region 42 is higher than the concentration of n-type impurities in the drift region 12. The concentration of n-type impurities in the emitter region 42 may be 1.0 × 10 ¹⁹ cm ^-3 or more and 1.0 × 10 ²¹ cm ^-3 or less.

The emitter region 42 is formed on both sides of the trench gate structure 22. The emitter region 42 is formed in a strip shape extending along the trench gate structure 22 in a plan view. The emitter region 42 is exposed from the first main surface 3 and the side wall of the gate trench 31. The bottom of the emitter region 42 is formed in the region between the top of the gate electrode 33 and the bottom of the base region 41 with respect to the normal direction Z.

In each first region 29, a p ⁺ type contact region 43 is formed on the surface layer portion of the base region 41. The p-type impurity concentration in the contact region 43 is higher than the p-type impurity concentration in the base region 41. The concentration of p-type impurities in the contact region 43 may be 1.0 × 10 ¹⁹ cm ^-3 or more and 1.0 × 10 ²⁰ cm ^-3 or less. In the semiconductor layer 2, an n ⁺ type high concentration region 44 is formed in a region on the second main surface 4 side with respect to the base region 41. The n-type impurity concentration in the high concentration region 44 is higher than the n-type impurity concentration in the drift region 12. The concentration of n-type impurities in the high concentration region 44 may be 1.0 × 10 ¹⁵ cm ^-3 or more and 1.0 × 10 ¹⁷ cm ^-3 or less.

The high concentration region 44 is formed in the region on the second main surface 4 side with respect to the base region 41 in the semiconductor layer 2 of the first region 29, and is not formed in the second region 30. That is, in the IGBT region 8, the high-concentration region 44 is formed in the first region 29 of the FET structure 21, and the high-concentration region 44 is not formed in the one-side region 30A and the other-side region 30B of the region separation structure 25. The high concentration region 44 is formed in the region on the second main surface 4 side with respect to the base region 41 so as to be connected to the base region 41 in the first region 29.

The high concentration region 44 is formed at a depth position between the base region 41 and the bottom wall of the gate trench 31. The high concentration region 44 is formed at a distance from the bottom wall of the gate trench 31 toward the base region 41. The high concentration region 44 exposes a part of the side wall and the bottom wall of the gate trench 31. The high concentration region 44 faces the gate electrode 33 with the gate insulating film 32 interposed therebetween on the side wall of the gate trench 31.

The high concentration region 44 is formed at a depth position between the base region 41 and the bottom wall of the separation trench 36. The high concentration region 44 is formed at a distance from the bottom wall of the separation trench 36 toward the base region 41. The high concentration region 44 exposes a part of the side wall and the bottom wall of the separation trench 36. The high concentration region 44 faces the separation electrode 38 with the separation insulating film 37 interposed therebetween on the side wall of the separation trench 36.

The high concentration region 44 is formed in a band shape extending in the second direction X along the trench structures 22 and 26 in a plan view. Both the top of the high concentration region 44 and the bottom of the high concentration region 44 are located above the center position in the depth direction of the trench structures 22 and 26 with respect to the normal direction Z, as shown in FIG. .. That is, the high concentration region 44 is formed shallower than the central position in the depth direction of the trench structures 22 and 26.

The high concentration region 44 may be formed deeper than the central position in the depth direction of the trench structures 22 and 26. It is preferable that the high concentration region 44 is formed shallower than the central position in the depth direction of the trench structures 22 and 26. The high concentration region 44 is formed in at least one of the two first regions 29. The high concentration region 44 is formed in both of the two first regions 29 in this form.

The high concentration region 44 has an n-type offset compensation region 45 (a compensation region) containing p-type impurities and n-type impurities at the connection portion with the base region 41 in the first region 29. "Offset compensation" is also referred to as "offset," "compensation," "carrier offset," or "carrier compensation." The offset compensation region 45 is a region in which a part of the n-type impurities in the high concentration region 44 is offset compensated by a part of the p-type impurities in the base region 41 to form an n-type semiconductor region as a whole. The n-type impurity concentration in the offset compensation region 45 is reduced from the n-type impurity concentration in the high concentration region 44 by the amount compensated by the p-type impurities in the base region 41.

In other words, the p-type impurity concentration on the bottom side of the base region 41 is reduced by the amount compensated for by the n-type impurity concentration in the high concentration region 44. The base region 41 includes a first portion 51 formed in a relatively shallow region in the first region 29, and a second portion 52 formed deeper than the first portion 51 in the second region 30. The first portion 51 has a first depth D1. The first portion 51 is a region thinned (shallowed) by the high concentration region 44 (offset compensation region 45) in the first region 29. The second region 30 is a region that is not thinned (shallowed) by the high concentration region 44. The second portion 52 has a second depth D2 that exceeds the first depth D1.

The high concentration region 44 functions as a carrier storage region that suppresses the carriers (holes) supplied to the semiconductor layer 2 from being pulled back (discharged) to the base region 41. As a result, holes are accumulated in the region directly below the FET structure 21 in the semiconductor layer 2. As a result, the on-resistance and the on-voltage can be reduced. As described above, in the first region 29, the base region 41 and the emitter region 42 face the gate electrode 33 with the gate insulating film 32 interposed therebetween. In this embodiment, the high concentration region 44 also faces the gate electrode 33 with the gate insulating film 32 interposed therebetween.

The FET structure 21 includes a channel region controlled by the trench gate structure 22 in the surface layer portion of the base region 41. The channel region is formed in the base region 41 between the emitter region 42 and the drift region 12 (high concentration region 44). In the IGBT region 8, the interlayer insulating layer 61 is formed on the first main surface 3. The interlayer insulating layer 61 is formed in a film shape along the first main surface 3. The interlayer insulating layer 61 may have a laminated structure including a plurality of insulating layers. The interlayer insulating layer 61 may contain silicon oxide or silicon nitride. The interlayer insulating layer 61 may contain at least one of NGS (Non-doped Silicate Glass), PSG (Phosphor Silicate Glass) and BPSG (Boron Phosphor Silicate Glass). The thickness of the interlayer insulating layer 61 may be 0.1 μm or more and 2 μm or less.

As shown in FIG. 5, a plurality of first emitter openings 62 are formed in the interlayer insulating layer 61 at positions corresponding to the contact region 43. The plurality of first emitter openings 62 penetrate the interlayer insulating layer 61 up and down to expose the corresponding first regions 29, respectively. As shown in FIG. 5, the first contact electrode 63 is embedded in each of the plurality of first emitter openings 62. The plurality of first contact electrodes 63 are electrically connected to the emitter region 42 and the contact region 43, respectively, in the corresponding first emitter opening 62.

The plurality of first contact electrodes 63 are electrically connected to the first region 29 in the FET structure 21 and are not connected to the one side region 30A and the other side region 30B of the second region 30 in the region separation structure 25. Therefore, the base region 41 (that is, the second portion 52) on the region separation structure 25 side is electrically formed in a floating state. That is, the base region 41 (that is, the second portion 52) on the region separation structure 25 side functions as a p-type floating region.

The first contact electrode 63 may have a laminated structure including a barrier electrode layer and a main electrode layer (not shown). The barrier electrode layer is formed in a film shape along the inner wall of the first emitter opening 62. The barrier electrode layer may have a single layer structure including a titanium layer or a titanium nitride layer. The barrier electrode layer may have a laminated structure including a titanium layer and a titanium nitride layer, and in this case, the titanium nitride layer may be laminated on the titanium layer. The main electrode layer is embedded in the first emitter opening 62 with the barrier electrode layer interposed therebetween. The main electrode layer 93 may contain tungsten.

The above-mentioned emitter terminal electrode 9 and gate terminal electrode 10 are formed on the interlayer insulating layer 61. As shown in FIG. 5, the emitter terminal electrode 9 is electrically connected to the emitter region 42 and the contact region 43 via the first contact electrode 63 on the interlayer insulating layer 61. Further, although not shown, a plurality of contact electrodes for the separation electrode for electrically connecting the emitter terminal electrode 9 and the separation electrode 38 are provided. Although not shown, the interlayer insulating layer 61 is formed with emitter openings for a plurality of separation electrodes at positions corresponding to the separation electrodes 38. The contact electrode for the separation electrode is electrically connected to the corresponding separation electrode 38 via the emitter opening for the separation electrode.

A pad electrode may be formed on the emitter terminal electrode 9. The pad electrode may include at least one of a nickel layer, a palladium layer and a gold layer. The pad electrode may have a laminated electrode including a nickel layer, a palladium layer, and a gold layer laminated in this order from the emitter terminal electrode 9 side.

FIG. 6 is a cross-sectional view showing a second embodiment example of the semiconductor device 1. FIG. 6 is a cross-sectional view corresponding to FIG. In FIG. 6, the parts common to the first embodiment are designated by the same reference numerals as those in FIGS. 1 to 5, and specific description thereof will be omitted.

The difference between the second embodiment and the first embodiment is that the emitter terminal electrode 9 is electrically connected to the base region 41 of the one side region 30A in addition to the base region 41 of the first region 29, and the other side region. It is a point that is not electrically connected to the base region 41 of 30B. The base region 41 of the other side region 30B is electrically formed in a floating state. Specifically, the interlayer insulating layer 61 is formed with a second emitter opening 72 at a position corresponding to the base region 41 of the one-sided region 30A. The second emitter opening 72 penetrates the interlayer insulating layer 61 up and down to expose the base region 41 of the one-sided region 30A.

A second contact electrode 73 is embedded in the second emitter opening 72 of the interlayer insulating layer 61. The second contact electrode 73 is electrically connected to the base region 41 of the one-sided region 30A via the second emitter opening 72. The emitter terminal electrode 9 is electrically connected to the second contact electrode 73 on the interlayer insulating layer 61. Like the first contact electrode 63, the second contact electrode 73 may have a laminated structure including a barrier electrode layer and a main electrode layer. In addition, a specific description of the second contact electrode 73 will be omitted.

FIG. 7 is a cross-sectional view showing a third embodiment example of the semiconductor device 1. FIG. 7 is a cross-sectional view corresponding to FIG. In FIG. 7, the same reference numerals as those in FIGS. 1 to 5 are attached to the portions common to the first embodiment, and specific description thereof will be omitted. The difference between the third embodiment and the first embodiment is that the emitter terminal electrode 9 is electrically connected to the base region 41 of the other region 30B in addition to the base region 41 of the first region 29, and is one-sided region. It is a point that is not electrically connected to the base region 41 of 30A. The base region 41 of the one side region 30A is electrically formed in a floating state.

Specifically, the interlayer insulating layer 61 is formed with a third emitter opening 77 at a position corresponding to the base region 41 of the other side region 30B. The third emitter opening 77 penetrates the interlayer insulating layer 61 up and down to expose the base region 41 of the other side region 30B. A third contact electrode 78 is embedded in the third emitter opening 77 of the interlayer insulating layer 61. The third contact electrode 78 is electrically connected to the base region 41 of the other side region 30B via the third emitter opening 77. The emitter terminal electrode 9 is electrically connected to the third contact electrode 78 on the interlayer insulating layer 61. Like the first contact electrode 63, the third contact electrode 78 may have a laminated structure including a barrier electrode layer and a main electrode layer. In addition, a specific description of the third contact electrode 78 will be omitted.

FIG. 8 is a cross-sectional view showing a fourth embodiment example of the semiconductor device 1. FIG. 8 is a cross-sectional view corresponding to FIG. In FIG. 8, the parts common to the first embodiment are designated by the same reference numerals as those in FIGS. 1 to 7, and specific description thereof will be omitted. The fourth embodiment differs from the first embodiment in that the emitter terminal electrode 9 is a base region 41 of one side region 30A and a base region 41 of the other side region 30B in addition to the base region 41 of the first region 29. It is a point that is electrically connected to both. That is, the semiconductor device 1 according to the fourth embodiment includes a second emitter opening 72 and a second contact electrode 73 (see FIG. 6), and a third emitter opening 77 and a third contact electrode 78 (see FIG. 7). ..

The second contact electrode 73 is electrically connected to the base region 41 of the one-sided region 30A via the second emitter opening 72. The third contact electrode 78 is electrically connected to the base region 41 of the other side region 30B via the third emitter opening 77. The emitter terminal electrode 9 is electrically connected to the second contact electrode 73 and the third contact electrode 78 on the interlayer insulating layer 61.

In the IGBT, when the collector-emitter voltage VCE is increased, the collector current monotonically increases as the collector-emitter voltage VCE increases. The collector-emitter voltage VCE is the voltage between the collector and the emitter of the IGBT. When the collector-emitter voltage VCE exceeds a predetermined value, the collector current saturates. The region where the increase ratio of the collector current Ic is relatively small with respect to the increase ratio of the collector-emitter voltage VCE is defined as the saturation region. The voltage value between the collector and the emitter when a specified voltage (for example, 15V) is applied between the gate and the emitter and a rated collector current is passed is defined as "saturation voltage VCE (sat)".

The values of the saturation voltage VCE (sat) between the collector and the emitter of the first to fourth embodiments are summarized in Table 1 below. Table 1 below shows the values of the saturation voltage VCE (sat) when the rated collector current is 30 A. Table 1 also shows the values of the saturation voltage VCE (sat) of the first to fourth reference examples. The first to fourth reference examples correspond to the first to fourth morphological examples, respectively. Specifically, the first reference example has a structure in which the n ⁺ type high concentration region 44 is removed from the first form example. Similarly, the second to fourth reference examples have a structure in which the n ⁺ type high concentration region 44 is removed from the second to fourth morphological examples.

From Table 1, in the semiconductor device 1 of the first embodiment, the minimum value (1.31 V) of the saturation voltage VCE (sat) is smaller than that of the reference example, and the maximum value (1. It can be seen that 52V) is larger than that of the reference example. Therefore, the voltage difference (0.21V) between the maximum value and the minimum value of the saturation voltage VCE (sat) is larger than that of the reference example. As described above, by changing the aspect of the semiconductor device 1 from the first to fourth reference examples to the first to fourth embodiments (that is, introducing the high concentration region 44), the basic layout is not changed. The value of the saturation voltage VCE (sat) can be adjusted. As described above, according to this embodiment, it is possible to provide the semiconductor device 1 having a structure in which the saturation voltage VCE (sat) is adjusted by a novel structure.

FIG. 9 is a cross-sectional view showing the semiconductor device 201 according to the second embodiment of the present invention together with the structure according to the first embodiment. FIG. 9 is a cross-sectional view corresponding to FIG. In FIG. 9, the parts common to the first embodiment are designated by the same reference numerals as those in FIGS. 1 to 5, and specific description thereof will be omitted. The semiconductor device 201 according to the second embodiment has an IGBT region 208 instead of the IGBT region 8.

The difference between the IGBT region 208 and the IGBT region 8 according to the first embodiment (example of the first embodiment) is that the high concentration region 44 replaces the first region 29 with the second region 30 of the region separation structure 25 (the first embodiment). It is a point formed in at least one of the one-side region 30A and the other-side region 30B). In this embodiment, the high concentration region 44 is formed in both the one-sided region 30A and the other-sided region 30B. In other respects, the IGBT region 208 is common to the IGBT region 8 according to the first embodiment (example of the first embodiment).

The high concentration region 44 is formed in the region on the second main surface 4 side with respect to the base region 41 in the semiconductor layer 2 of the second region 30, and is not formed in the first region 29. That is, in the IGBT region 208, the high concentration region 44 is formed in the one side region 30A and the other side region 30B of the region separation structure 25, and the high concentration region 44 is not formed in the first region 29 of the FET structure 21. The high concentration region 44 is formed in the region on the second main surface 4 side with respect to the base region 41 so as to be connected to the base region 41 in the second region 30.

The high concentration region 44 is formed in a band shape extending in the second direction X along the separation trench structure 26 in a plan view. The high concentration region 44 is formed in the second region 30 at a depth position between the base region 41 and the bottom wall of the separation trench 36. The high concentration region 44 is formed at a depth position between the base region 41 and the bottom wall of the separation trench 36. The high concentration region 44 is formed at a distance from the bottom wall of the separation trench 36 toward the base region 41. The high concentration region 44 exposes a part of the side wall and the bottom wall of the separation trench 36. The high concentration region 44 faces the separation electrode 38 with the separation insulating film 37 interposed therebetween on the side wall of the separation trench 36.

The high concentration region 44 is formed shallower than the central position in the depth direction of the separation trench structure 26. The high concentration region 44 may be formed deeper than the central position in the depth direction of the separation trench structure 26. It is preferable that the high concentration region 44 is formed shallower than the central position in the depth direction of the separation trench structure 26. The high concentration region 44 has an n-type offset compensation region 45 containing p-type impurities and n-type impurities at the connection portion with the base region 41 in the second region 30.

The base region 41 includes a first portion 51 formed in a relatively deep region in the first region 29, and a second portion 52 formed in a region shallower than the first portion 51 in the second region 30. The first portion 51 has a first depth D11. The first portion 51 is a region in the first region 29 that is not thinned (shallowed) by the high concentration region 44. The second portion 52 has a second depth D12 that is less than the first depth D11. The second portion 52 is a region thinned (shallowed) by the high concentration region 44 (offset compensation region 45) in the second region 30.

The plurality of first contact electrodes 63 are electrically connected to the first region 29 via the plurality of first emitter openings 62, and are not electrically connected to the second region 30. The emitter terminal electrode 9 is electrically connected to the base region 41 of the first region 29 via the first contact electrode 63. Therefore, the base region 41 on the second region 30 side is electrically formed in a floating state. That is, in this embodiment, the high concentration region 44 is formed in the region directly below the base region 41 as a floating region in the second region 30.

FIG. 10 is a cross-sectional view showing a second embodiment example of the semiconductor device 201. FIG. 10 is a cross-sectional view corresponding to FIG. In FIG. 10, the same reference numerals as those in FIG. 9 are attached to the parts common to the first embodiment, and specific description thereof will be omitted. The difference between the second embodiment and the first embodiment is that the emitter terminal electrode 9 is electrically connected to the base region 41 of the one side region 30A in addition to the base region 41 of the first region 29, and the other side region. It is a point that is not connected to the base region 41 of 30B. That is, while the base region 41 of the one side region 30A is grounded to the emitter, the base region 41 of the other side region 30B is electrically formed in a floating state.

Specifically, the interlayer insulating layer 61 is formed with a second emitter opening 272 at a position corresponding to the base region 41. The second emitter opening 272 penetrates the interlayer insulating layer 61 up and down to expose only the base region 41 of the one-sided region 30A. A second contact electrode 273 is embedded in the second emitter opening 272 of the interlayer insulating layer 61. The second contact electrode 273 is electrically connected to the base region 41 of the one-sided region 30A within the second emitter opening 272. The emitter terminal electrode 9 is electrically connected to the second contact electrode 273 on the interlayer insulating layer 61. The second contact electrode 273 may have a laminated structure including a barrier electrode layer and a main electrode layer, similarly to the first contact electrode 63. In addition, a specific description of the second contact electrode 273 will be omitted.

FIG. 11 is a cross-sectional view showing a third embodiment example of the semiconductor device 201 according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view corresponding to FIG. In FIG. 11, the parts common to the first embodiment are designated by the same reference numerals as those in FIG. 9, and specific description thereof will be omitted. The difference between the third embodiment and the first embodiment is that the emitter terminal electrode 9 is electrically connected to the base region 41 of the other region 30B in addition to the base region 41 of the first region 29, and is one-sided region. It is a point that is not connected to the base region 41 of 30A. That is, while the base region 41 of the other side region 30B is grounded to the emitter, the base region 41 of the one side region 30A is electrically formed in a floating state.

Specifically, the interlayer insulating layer 61 is formed with a third emitter opening 277 at a position corresponding to the base region 41 of the other side region 30B. The third emitter opening 277 penetrates the interlayer insulating layer 61 up and down to expose the base region 41 of the other side region 30B. A third contact electrode 278 is embedded in the third emitter opening 277 of the interlayer insulating layer 61. The third contact electrode 278 is electrically connected to the base region 41 of the other side region 30B in the third emitter opening 277. The emitter terminal electrode 9 is electrically connected to the third contact electrode 278 on the interlayer insulating layer 61. The third contact electrode 278 may have a laminated structure including a barrier electrode layer and a main electrode layer, similarly to the first contact electrode 63. In addition, a specific description of the third contact electrode 278 will be omitted.

FIG. 12 is a cross-sectional view showing a fourth embodiment example of the semiconductor device 201 according to the second embodiment of the present invention. FIG. 12 is a cross-sectional view corresponding to FIG. In FIG. 12, the parts common to the first embodiment are designated by the same reference numerals as those in FIG. 9, and specific description thereof will be omitted. The fourth embodiment differs from the first embodiment in that the emitter terminal electrode 9 is a base region 41 of one side region 30A and a base region 41 of the other side region 30B in addition to the base region 41 of the first region 29. It is a point that is electrically connected to both. That is, the semiconductor device 201 according to the fourth embodiment includes a second emitter opening 272 and a second contact electrode 273 (see FIG. 10), and a third emitter opening 277 and a third contact electrode 278 (see FIG. 11). ..

The second contact electrode 273 is electrically connected to the base region 41 of the one-sided region 30A via the second emitter opening 272. The third contact electrode 278 is electrically connected to the base region 41 of the other side region 30B via the third emitter opening 277. The emitter terminal electrode 9 is electrically connected to the second contact electrode 273 and the third contact electrode 278 on the interlayer insulating layer 61.

The values of the saturation voltage VCE (sat) in the first to fourth embodiments of the second embodiment are shown in Table 2 below. Table 2 below shows the values of the saturation voltage VCE (sat) when the rated collector current is 30 A.

From Table 2, it can be seen that in the second embodiment, the saturation voltage VCE (sat) value is larger than that of the reference example as a whole. Therefore, by changing the aspect of the semiconductor device 201 from the first reference example to the first to fourth embodiments (that is, introducing the high concentration region 44), the saturation voltage VCE (that is, the saturation voltage VCE (that is, the high concentration region 44 is introduced) without changing the basic layout is changed. The value of sat) can be adjusted. As described above, according to this embodiment, it is possible to provide the semiconductor device 201 having a structure in which the saturation voltage VCE (sat) is adjusted by a novel structure.

FIG. 13 is a plan view showing the internal structure of the semiconductor device 301 according to the third embodiment of the present invention. FIG. 14 is a cross-sectional view taken along the line XIV-XIV shown in FIG. FIG. 15 is a cross-sectional view taken along the line XV-XV shown in FIG. FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. In FIGS. 13 to 16, the parts common to the first embodiment are designated by the same reference numerals as those in FIGS. 1 to 5, and specific description thereof will be omitted.

With reference to FIGS. 13 to 16, the semiconductor device 301 according to the third embodiment has an IGBT region 308 instead of the IGBT region 8. The difference between the IGBT region 308 and the IGBT region 8 according to the first embodiment is that a plurality of base regions 41 are formed in the first region 29 at intervals in the first direction Y, and a high concentration region. The point is that the 344 is not connected to the base region 41 from the normal direction Z, but is connected to the base region 41 from the first direction Y along the first main surface 3. In such a structure, the emitter region 42 and the contact region 43 are formed on the surface layer portion of the base region 41, respectively, and are not formed on the surface layer portion of the plurality of high concentration regions 344. In other respects, the IGBT region 308 is common to the IGBT region 8 according to the first embodiment (example of the first embodiment).

The high concentration region 344 corresponds to the above-mentioned high concentration region 44. That is, the high concentration region 344 has an n-type impurity concentration higher than that of the drift region 12. The high concentration region 344 is formed on one side of the first region 29 and the second region 30, and is not formed on the other side. In this embodiment, the high concentration region 344 is formed in the first region 29 and not in the second region 30.

That is, in the IGBT region 308, the high concentration region 344 is formed only in the first region 29 of the FET structure 21, and the high concentration region 344 is formed in the one side region 30A and the other side region 30B of the region separation structure 25. do not have. In this form, a high concentration region 344 is formed in both of the two first regions 29. Of course, a form in which the high-concentration region 344 is formed in only one of the two first regions 29 and the high-concentration region 344 is not formed in the other first region 29 may be adopted.

The high concentration region 344 is formed alternately in the base region 41 and the first direction Y in the first region 29. In this embodiment, a plurality of high-concentration regions 344 are alternately arranged in the plurality of base regions 41 and the first direction Y in a manner in which one base region 41 is sandwiched from the first direction Y in the first region 29. .. The high concentration region 344 is connected to the base region 41 in the first region 29.

The high concentration region 344 is formed at a depth position between the first main surface 3 and the bottom wall of the gate trench 31. The high concentration region 344 is formed at intervals from the bottom wall of the gate trench 31 to the first main surface 3 side. The high concentration region 344 exposes a part of the side wall and the bottom wall of the gate trench 31. The high concentration region 344 faces the gate electrode 33 with the gate insulating film 32 interposed therebetween on the side wall of the gate trench 31.

The high concentration region 344 is formed at a depth position between the first main surface 3 and the bottom wall of the separation trench 36. The high concentration region 344 is formed at intervals from the bottom wall of the separation trench 36 to the first main surface 3 side. The high concentration region 344 exposes a part of the side wall and the bottom wall of the separation trench 36. The high concentration region 344 faces the separation electrode 38 with the separation insulating film 37 interposed therebetween on the side wall of the separation trench 36.

The high concentration region 344 is formed deeper than the base region 41. The bottom of the high concentration region 344 may project toward the bottom of the base region 41 and cover the bottom of the base region 41. The depth of the high concentration region 344 may be about the same as that of the base region 41, or may be shallower than the depth of the base region 341. As described above, according to this embodiment, it is possible to provide the semiconductor device 301 having a structure in which the saturation voltage VCE (sat) is adjusted by a novel structure.

FIG. 17 is a plan view showing the internal structure of the semiconductor device 401 according to the fourth embodiment of the present invention. FIG. 18 is a cross-sectional view taken along the line XVIII-XVIII shown in FIG. FIG. 19 is a cross-sectional view taken along the line XIX-XIX shown in FIG. FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. In FIGS. 17 to 20, the parts common to the third embodiment are designated by the same reference numerals as those in FIGS. 17 to 20, and specific description thereof will be omitted.

The semiconductor device 401 according to the fourth embodiment has an IGBT region 408 instead of the IGBT region 308. The difference between the IGBT region 408 and the IGBT region 8 according to the first embodiment is that the high concentration region 344 is formed in the second region 30 (one side region 30A and the other side region 30B) of the region separation structure 25. Is. Further, a high concentration region is not formed in the first region 29 of the FET structure 21.

The high concentration region 344 is connected to the base region 41 in the second region 30. The high concentration region 344 is formed at a depth position between the first main surface 3 and the bottom wall of the gate trench 31. The high concentration region 344 is formed at intervals from the bottom wall of the separation trench 36 to the first main surface 3 side. The high concentration region 344 exposes a part of the side wall and the bottom wall of the separation trench 36. The high concentration region 344 faces the separation electrode 38 with the separation insulating film 37 interposed therebetween on the side wall of the separation trench 36.

The bottom of the high concentration region 344 is formed in the region between the first main surface 3 and the bottom wall of the separation trench 36 with respect to the normal direction Z. As shown in FIG. 20, the bottom portion of the high concentration region 344 is formed in a region between the bottom portion of the base region 41 and the second main surface 4 with respect to the normal direction Z. That is, the high concentration region 344 is formed deeper than the base region 41. As shown in FIG. 20, the bottom of the high concentration region 344 is located above the central position in the depth direction of the separation trench structure 26 with respect to the normal direction Z. That is, the high concentration region 344 is formed shallower than the central position in the depth direction of the separation trench structure 26.

Further, at the bottom of the high concentration region 344, as shown in FIG. 20, a part of the high concentration region 344 may project in the second direction X and reach the region below the base region 41. Further, the depth of the high-concentration region 344 may be about the same as that of the base region 41, or the high-concentration region 344 may be formed shallower than the base region 41. As described above, according to this embodiment, it is possible to provide the semiconductor device 401 having a structure in which the saturation voltage VCE (sat) is adjusted by a novel structure.

FIG. 21 is a plan view showing the internal structure of the semiconductor device 501 according to the fifth embodiment of the present invention. In FIG. 21, the parts common to the third embodiment and the fourth embodiment are designated by the same reference numerals as those in FIGS. 13 to 20, and specific description thereof will be omitted. The semiconductor device 501 according to the fifth embodiment has a structure in which the structure according to the third embodiment and the structure according to the fourth embodiment are combined. That is, in the semiconductor device 501, the high concentration region 344 is formed in both the first region 29 and the second region 30.

On the first region 29 side, a plurality of base regions 41 are formed at intervals in the first direction Y. On the first region 29 side, a plurality of high-concentration regions 344 are formed at intervals in the first direction Y. On the first region 29 side, the plurality of high-concentration regions 344 are alternately arranged with the plurality of base regions 41. On the second region 30 side, a plurality of base regions 41 are formed at intervals in the first direction Y. On the second region 30 side, a plurality of high-concentration regions 344 are formed at intervals in the first direction Y. On the second region 30 side, the plurality of high-concentration regions 344 are alternately arranged with the plurality of base regions 41.

The plurality of base regions 41 on the second region 30 side are formed so as to be offset in the first direction Y with respect to the plurality of base regions 41 on the first region 29 side. The plurality of base regions 41 on the second region 30 side may be displaced in the first direction Y so as not to face the second direction X with respect to the plurality of base regions 41 on the first region 29 side. The plurality of base regions 41 on the second region 30 side face the plurality of high concentration regions 344 on the first region 29 side in the second direction X. The plurality of high-concentration regions 344 on the second region 30 side face the plurality of base regions 41 on the first region 29 side in the second direction X.

From a different point of view, the plurality of high-concentration regions 344 of the first region 29 face the plurality of base regions 41 of the second region 30 in the second direction X. Further, the plurality of base regions 41 of the first region 29 face the plurality of high concentration regions 344 of the second region 30 in the second direction X. As shown in FIG. 21, the high concentration region 344 may be formed in both of the two first regions 29 adjacent to each other. In the high concentration region 344, the high concentration region 344 may be formed only in one of the two first regions 29.

Further, in this embodiment, the high concentration region 344 of the first region 29 may face the base region 41 of the first region 29 in the second direction X. Then, the high concentration region 344 of the second region 30 may face the base region 41 of the second region 30 in the second direction X. As described above, according to this embodiment, it is possible to provide a semiconductor device 501 having a structure in which the saturation voltage VCE (sat) is adjusted by a novel structure.

The present invention can also be implemented in still other embodiments. In each of the above-described embodiments, the semiconductor layer 2 has a laminated structure including a p-type semiconductor substrate and an n ^- type epitaxial layer formed on the semiconductor substrate instead of the n ^- type semiconductor substrate 13. You may be doing it. In this case, the p-type semiconductor substrate corresponds to the collector region 16. Further, the n ^- type epitaxial layer corresponds to the drift region 12. In this case, the p-type semiconductor substrate may be made of silicon. The n ^- type epitaxial layer may be made of silicon. The n ^- type epitaxial layer is formed by epitaxially growing silicon from the main surface of a p-type semiconductor substrate.

In the above-described embodiment, the example in which the first conductive type is n type and the second conductive type is p type has been described, but the first conductive type may be p type and the second conductive type may be n type. The specific configuration in this case is obtained by replacing the n-type region with the p-type region and replacing the p-type region with the n-type region in the above description and the accompanying drawings.

Hereinafter, feature examples extracted from this specification and drawings are shown. In the following, a semiconductor device having a novel structure is provided.

[A1] A semiconductor layer having a first main surface on one side and a second main surface on the other side, a first conductive type drift region formed in the semiconductor layer, and a surface layer portion of the drift region. A plurality of trenches including a second conductive type base region and a first trench structure, a second trench structure, and a third trench structure formed at intervals on the first main surface so as to penetrate the base region. The structure, a first region partitioned between the first trench structure and the second trench structure in the semiconductor layer, and a partition between the second trench structure and the third trench structure in the semiconductor layer. The second region, the channel region controlled by the first trench structure, and the first conductive type impurity concentration higher than the drift region, and the said on either side of the first region or the second region. A semiconductor device including a first conductive type high-concentration region formed in a region on the second main surface side with respect to a base region and not formed on the other side of the first region and the second region.

[A2] Described in A1, the base region on the one side of the first region and the second region is formed shallower than the base region on the other side of the first region and the second region. Semiconductor device.

[A3] In the surface layer portion of the base region of the first region, a first conductive type emitter region formed in a region along the first trench structure and defining the channel region with the drift region is further provided. Included, the semiconductor device according to A1 or A2.

[A4] Any of A1 to A3, wherein the gate potential is applied to the first trench structure, the emitter potential is applied to the second trench structure, and the emitter potential is applied to the third trench structure. The semiconductor device described in one.

[A5] The semiconductor device according to any one of A1 to A4, further including an electrode electrically connected to the first region on the first main surface.

[A6] The semiconductor device according to any one of A1 to A5, wherein the high concentration region is formed shallower than the central position in the depth direction of the plurality of trench structures.

[A7] The semiconductor device according to any one of A1 to A5, wherein the high concentration region is formed deeper than the central position in the depth direction of the plurality of trench structures.

[A8] The one according to any one of A1 to A7, wherein the plurality of trench structures extend in a band shape in one direction in a plan view, and the high concentration region extends in the one direction in a plan view. Semiconductor device.

[A9] The semiconductor device according to any one of A1 to A8, wherein the high concentration region is formed in the first region and is not formed in the second region.

[A10] The semiconductor device according to any one of A1 to A8, wherein the high concentration region is formed in the second region and is not formed in the first region.

[A11] A semiconductor layer having a first main surface on one side and a second main surface on the other side, a first conductive type drift region formed in the semiconductor layer, and a surface layer portion of the drift region. A plurality of trenches including a second conductive type base region and a first trench structure, a second trench structure, and a third trench structure formed at intervals on the first main surface so as to penetrate the base region. The structure, a first region partitioned between the first trench structure and the second trench structure in the semiconductor layer, and a partition between the second trench structure and the third trench structure in the semiconductor layer. The second region, the channel region controlled by the first trench structure, and the first conductive type impurity concentration higher than the drift region, and the first region and the second region on at least one side thereof. 1. A semiconductor device including a first conductive type high-concentration region formed on a surface layer portion of the drift region so as to be connected to the base region from one direction along a main surface.

[A12] The base region is formed at a first depth in the thickness direction of the semiconductor layer from the first main surface, and the high concentration region is formed in the thickness direction of the semiconductor layer from the first main surface. The semiconductor device according to A11, which is formed at a second depth exceeding the first depth.

[A13] The semiconductor device according to A11 or A12, further including a first conductive type emitter region formed on the surface layer portion of the base region of the first region and defining the channel region with the drift region.

[A14] Any of A11 to A13, wherein the gate potential is applied to the first trench structure, the emitter potential is applied to the second trench structure, and the emitter potential is applied to the third trench structure. The semiconductor device described in one.

[A15] The semiconductor device according to any one of A11 to A14, further including an electrode electrically connected to the first region on the first main surface.

[A16] The semiconductor device according to any one of A11 to A15, wherein the high concentration region is alternately arranged in the base region and the one direction.

[A17] The semiconductor device according to any one of A11 to A16, wherein the high concentration region is formed in the first region and is not formed in the second region.

[A18] The plurality of trench structures are formed in a band shape extending in one direction, and the plurality of first regions are partitioned at intervals in the crossing direction intersecting the one direction, and the plurality of second regions are partitioned. The semiconductor device according to A17, wherein the high-concentration region is formed at least one of the plurality of the first regions, which are partitioned at intervals in the crossing direction.

[A19] The semiconductor device according to any one of A11 to A16, wherein the high concentration region is formed in the second region and is not formed in the first region.

[A20] The plurality of trench structures are formed in a band shape extending in one direction, and the plurality of first regions are partitioned at intervals in the crossing direction intersecting the one direction, and the plurality of second regions are partitioned. The semiconductor device according to A19, wherein the high concentration region is formed at least one of the plurality of the second regions, which are partitioned at intervals in the crossing direction.

[A21] The semiconductor device according to any one of A11 to A16, wherein the high concentration region is formed in both the first region and the second region.

[A22] The plurality of trench structures are formed in a band shape extending in one direction, and the plurality of first regions are partitioned at intervals in the crossing direction intersecting the one direction, and the plurality of second regions are partitioned. 21 is partitioned in the crossing direction at intervals, and the high concentration region is formed in at least one of the plurality of the first regions and at least one of the plurality of the second regions. The semiconductor device described in.

[A23] The high concentration region of the first region faces the base region of the second region in the crossing direction, and the high concentration region of the second region meets the base region of the first region. The semiconductor device according to A22, which faces the crossing direction.

Although the embodiments have been described in detail, these are merely specific examples used to clarify the technical contents, and the present invention should not be construed as being limited to these specific examples. The scope of is limited by the scope of the attached claims.

1 Semiconductor device 2 Semiconductor layer 3 First main surface 4 Second main surface 12 Drift region 22 Trench gate structure (first trench structure)
26 Separate trench structure (second trench structure, third trench structure)
26A 1st separation trench structure (2nd trench structure)
26B 2nd separation trench structure (3rd trench structure)
29 1st region 30 2nd region 41 Base region 44 High concentration region 201 Semiconductor device 301 Semiconductor device 344 High concentration region 401 Semiconductor device 501 Semiconductor device

Claims (20)

1. A semiconductor layer having a first main surface on one side and a second main surface on the other side,
   The first conductive type drift region formed in the semiconductor layer and
   The second conductive type base region formed on the surface layer of the drift region and
   A plurality of trench structures including a first trench structure, a second trench structure, and a third trench structure formed at intervals on the first main surface so as to penetrate the base region.
   A first region partitioned between the first trench structure and the second trench structure in the semiconductor layer,
   A second region partitioned between the second trench structure and the third trench structure in the semiconductor layer,
   The channel region controlled by the first trench structure and
   It has a higher concentration of first conductive impurities than the drift region, and is formed in the region on the second main surface side with respect to the base region on either one of the first region and the second region. A semiconductor device comprising a first region and a first conductive type high concentration region that is not formed on the other side of the second region.
2. The first aspect of the present invention, wherein the base region on one side of the first region and the second region is formed shallower than the base region on the other side of the first region and the second region. Semiconductor device.
3. Claimed to further include a first conductive type emitter region formed in a region along the first trench structure and defining the channel region with the drift region in the surface layer portion of the base region of the first region. Item 2. The semiconductor device according to Item 1 or 2.
4. A gate potential is applied to the first trench structure,
   An emitter potential is applied to the second trench structure,
   The semiconductor device according to any one of claims 1 to 3, wherein the emitter potential is applied to the third trench structure.
5. The semiconductor device according to any one of claims 1 to 4, wherein the high concentration region is formed shallower than the central position in the depth direction of the plurality of trench structures.
6. The semiconductor device according to any one of claims 1 to 4, wherein the high concentration region is formed deeper than the central position in the depth direction of the plurality of trench structures.
7. The semiconductor device according to any one of claims 1 to 6, wherein the high concentration region is formed in the first region and is not formed in the second region.
8. The semiconductor device according to any one of claims 1 to 6, wherein the high concentration region is formed in the second region and is not formed in the first region.
9. The semiconductor device according to any one of claims 1 to 8, further comprising an electrode electrically connected to the first region on the first main surface.
10. A semiconductor layer having a first main surface on one side and a second main surface on the other side,
    The first conductive type drift region formed in the semiconductor layer and
    The second conductive type base region formed on the surface layer of the drift region and
    A plurality of trench structures including a first trench structure, a second trench structure, and a third trench structure formed at intervals on the first main surface so as to penetrate the base region.
    A first region partitioned between the first trench structure and the second trench structure in the semiconductor layer,
    A second region partitioned between the second trench structure and the third trench structure in the semiconductor layer,
    The channel region controlled by the first trench structure and
    The said, having a higher concentration of first conductive impurities than the drift region, and being connected to the base region from one direction along the first main surface on at least one side of the first region and the second region. A semiconductor device including a first conductive type high-concentration region formed on a surface layer portion of a drift region.
11. The base region is formed at a first depth in the thickness direction of the semiconductor layer from the first main surface.
    The semiconductor device according to claim 10, wherein the high concentration region is formed at a second depth exceeding the first depth in the thickness direction of the semiconductor layer from the first main surface.
12. The semiconductor device according to claim 10 or 11, further comprising a first conductive type emitter region formed on the surface layer portion of the base region of the first region and defining the channel region with the drift region.
13. A gate potential is applied to the first trench structure,
    An emitter potential is applied to the second trench structure,
    The semiconductor device according to any one of claims 10 to 12, wherein the emitter potential is applied to the third trench structure.
14. The semiconductor device according to any one of claims 10 to 13, wherein the high concentration region is alternately arranged in the base region and the one direction.
15. The semiconductor device according to any one of claims 10 to 14, wherein the high concentration region is formed in the first region and is not formed in the second region.
16. The plurality of trench structures are formed in a band shape extending in one direction.
    A plurality of the first regions are partitioned at intervals in the intersecting directions intersecting the one direction.
    A plurality of the second regions are partitioned in the crossing direction at intervals.
    The semiconductor device according to claim 15, wherein the high concentration region is formed in at least one of the plurality of the first regions.
17. The semiconductor device according to any one of claims 10 to 14, wherein the high concentration region is formed in the second region and is not formed in the first region.
18. The plurality of trench structures are formed in a band shape extending in one direction.
    A plurality of the first regions are partitioned at intervals in the intersecting directions intersecting the one direction.
    A plurality of the second regions are partitioned in the crossing direction at intervals.
    The semiconductor device according to claim 17, wherein the high concentration region is formed in at least one of the plurality of the second regions.
19. The semiconductor device according to any one of claims 10 to 14, wherein the high concentration region is formed in both the first region and the second region.
20. The plurality of trench structures are formed in a band shape extending in one direction.
    A plurality of the first regions are partitioned at intervals in the intersecting directions intersecting the one direction.
    A plurality of the second regions are partitioned in the crossing direction at intervals.
    19. The semiconductor device according to claim 19, wherein the high concentration region is formed in at least one of the plurality of the first regions and at least one of the plurality of the second regions.

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