WO2022032423A9

WO2022032423A9 - Display substrate and display device

Info

Publication number: WO2022032423A9
Application number: PCT/CN2020/108102
Authority: WO
Inventors: 韩林宏; 秦世开; 张毅; 周洋; 张猛
Original assignee: 京东方科技集团股份有限公司; 成都京东方光电科技有限公司
Priority date: 2020-08-10
Filing date: 2020-08-10
Publication date: 2022-04-07
Also published as: CN114342083A; US20220310770A1; WO2022032423A1

Abstract

A display substrate and a display device, which belong to the technical field of displaying. In the display substrate, a base substrate (01) has a display area (A1), a bending area (A2) and a pad area (A3), and the length of the display area (A1) in a first direction (X1) is greater than the length of the display area (A1) in a second direction (Y1). As the pad area (A3), the bending area (A2) and the display area (A1) are arranged in the second direction (Y1), the pad area (A3) is located on the side of the longer boundary line of the display area (A1), so that the length of each signal line introduced from the pad area (A3) to the display area (A1) is shorter in the display area (A1). Correspondingly, a voltage difference between both ends of each signal line introduced from the pad area (A3) to the display area (A1) is small, and a display device using the display substrate has a good display effect.

Description

Display substrate and display device

technical field

The present application relates to the field of display technology, and in particular, to a display substrate and a display device.

Background technique

A display substrate is an indispensable part of a display device.

In the related art, a base substrate in a display substrate has a display area and a pad (PAD) area, and a plurality of pixels arranged in an array may be arranged in the display area. Signal lines for driving the pixels to emit light are generally introduced into the display area through the PAD area, so as to be connected to the plurality of pixels. And the PAD area is generally located on the side where the short side of the display area is located.

However, since the PAD area is located on the side of the short side of the display area in the related art, each signal line introduced from the PAD area to the display area has a longer length in the display area. As a result, the voltage difference between the two ends of each signal line is large, and the display effect of the display device is poor.

SUMMARY OF THE INVENTION

The present application provides a display substrate and a display device, and the technical solutions are as follows:

In one aspect, a display substrate is provided, the display substrate comprising:

A base substrate, the base substrate has a display area, a bending area and a pad area, the length of the display area in the first direction is greater than the length of the display area in the second direction, the first direction perpendicular to the second direction, and the pad area, the bending area and the display area are arranged along the second direction;

a plurality of pixels arranged in an array, located in the display area;

a plurality of first power line groups and a plurality of first signal lines, each of the first power line groups including at least two first power lines for providing a first DC power signal, each of the first power lines Lines and each of the first signal lines extend from the pad area to the display area, and are connected to at least one of the pixels, and each of the first power lines and each of the first signal lines The extension directions of the partial line segments connected to the pixels are all parallel to the second direction.

Optionally, in the bending area, the distance between every two adjacent first power lines in each first power line group is less than or equal to a first distance threshold, and every adjacent two The spacing between the first power line groups is greater than or equal to a second spacing threshold, and the first spacing threshold is smaller than the second spacing threshold.

The display substrate further includes: a first bridging part and a second bridging part, the first bridging part is located in the pad area, and the second bridging part is located in the display area; Each of the first power lines includes a first sub-line segment, a second sub-line segment and a third sub-line segment;

The first sub-line segment is located in the pad area, one end of the first sub-line segment is connected to the power supply terminal, and the other end of the first sub-line segment is connected to the first jumper;

One end of the second sub-line segment is connected to the first jumper, and the other end of the second sub-line segment is connected to the second jumper;

One end of the third sub-line segment is connected to the second jumper, and the other end of the third sub-line segment is connected to at least one of the pixels;

Wherein, the first sub-line segment, the second sub-line segment, the third sub-line segment, the first jumper and the second jumper are all connected to the source-drain metal layer in the display substrate Same layer settings.

Optionally, each of the first power cord groups includes the same number of the first power cords.

Optionally, the line width of each of the first power lines is less than or equal to a first line width threshold.

Optionally, the plurality of first signal lines include: data signal lines for providing data signals, and/or second power lines for providing second DC power signals.

Optionally, the plurality of first signal lines include: a plurality of the data signal lines;

Each of the data signal lines includes: interconnected data line leads and data lines;

Wherein, the data line leads are located in the pad area and the bending area, the data line is located in the display area, and the data line is connected to at least one of the pixels.

Optionally, the data signal line and the first gate metal layer in the display substrate are arranged in the same layer; or, the data signal line and the second gate metal layer in the display substrate are arranged in the same layer.

Optionally, the line width of each of the second power lines is less than or equal to the second line width threshold.

Optionally, the base substrate further has a first lead area and a second lead area, and the first lead area, the display area and the second lead area are arranged along the first direction; The display substrate further includes: a plurality of second signal lines;

Among the plurality of second signal lines, a part of the second signal lines extends from the pad area to the first lead area, and is connected to at least one of the pixels; another part of the second signal lines A line extends from the pad area to the second lead area and is connected to at least one of the pixels.

Optionally, the line width of each of the second signal lines is less than or equal to a third line width threshold.

Optionally, the second signal line is used to provide a gate driving signal; each of the second signal lines includes: a gate line lead and a gate line connected to each other;

Wherein, the gate line leads are located in the pad area and the first lead area, or, the gate line leads are located in the pad area and the second lead area;

The gate line is located in the display area, and the gate line is connected with at least one of the pixels.

Optionally, each of the second signal lines includes: a first metal layer and a second metal layer; the first metal layer and the first gate metal layer in the display substrate are provided in the same layer, and the first metal layer The two metal layers are arranged in the same layer as the second gate metal layer in the display substrate;

Alternatively, each of the second signal lines includes: a first metal layer, a second metal layer, and a third metal layer; the first metal layer and the first gate metal layer in the display substrate are provided in the same layer, The second metal layer is disposed on the same layer as the second gate metal layer in the display substrate, and the third metal layer is disposed on the same layer as the source-drain metal layer in the display substrate.

Optionally, each type of signal line includes at least one target signal line, and the target signal line is close to the edge of the pad area relative to other signal lines except the target signal line;

The part of the target signal line located in the pad area includes a first target sub-line segment and a second target sub-line segment connected in sequence, and the first target sub-line segment is close to the display area relative to the second target sub-line segment , and the included angle between the first target sub-line segment and the boundary line of the display area extending along the first direction is less than or equal to 90 degrees.

Optionally, the display substrate further includes: a plurality of second signal lines; the first signal lines include: a data signal line and a second power supply line;

The pad area includes a symmetrical first subregion and a second subregion;

In each type of signal lines, a part of the signal lines are located in the first partition, and the other part of the signal lines are located in the second partition.

Optionally, in each type of signal lines, the number of signal lines located in the first partition is the same as the number of signal lines located in the second partition.

Optionally, in each of the sub-regions, the target line group, the second power line and the second signal line are sequentially arranged in a direction away from the other sub-region, wherein the target line group includes all the the data signal line and the first power line.

Optionally, the base substrate further has a component setting area, and the component setting area and the pad area are located on the same side of the display area;

The display substrate further includes a camera assembly located in the assembly setting area;

A side of the pad area close to the component setting area has a first part and a second part connected to each other, and the extension direction of the first part intersects with the extension direction of the second part.

In another aspect, a display device is provided, the display device comprising: a driving circuit located in the pad area, and the display substrate according to the above aspect;

Wherein, the driving circuit is connected to various types of signal lines included in the display substrate, and the driving circuit is used to provide signals for the connected signal lines.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 11 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 12 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 13 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 14 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 15 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 16 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 17 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application;

FIG. 18 is a schematic structural diagram of a display device provided by an embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present application. As shown in FIG. 1, the display substrate may include:

The base substrate 01 may have a display area A1, a bending area A2 and a pad area A3. The length of the display area A1 in the first direction X1 may be greater than the length of the display area A1 in the second direction Y1, and the first direction X1 may be perpendicular to the second direction Y1. That is, the length of the boundary line of the base substrate 01 extending along the first direction X1 is greater than the length of the boundary line extending along the second direction Y1 of the base substrate 01 .

For example, referring to FIG. 1 , assuming that the shape of the base substrate 01 is a rectangle with rounded corners, the boundary line extending along the first direction X1 of the display area A1 of the base substrate 01 may be called a long side. The boundary line of the display area A1 of 01 extending along the second direction Y1 may be referred to as a short side. That is, the display area A1 of the base substrate 01 may be surrounded by two long sides and two short sides. Of course, the shape of the base substrate 01 can also be other (eg, oval or polygonal), no matter which shape it is, the length of the base substrate 01 in the first direction X1 is greater than that of the display area A1 in the second direction Length on Y1.

In this embodiment of the present application, the pad area A3, the bending area A2 and the display area A1 may be arranged along the second direction Y1. That is, referring to FIG. 1 , the bending area A2 and the pad area A3 may be located on the side where the long side of the display area A1 is located. Since the signal lines introduced from the pad area A3 to the display area A1 through the bending area A2, the extension direction in the display area A1 is generally parallel to the arrangement direction of the display area A1, the bending area A2 and the pad area A3, so By arranging the bending area A2 and the pad area A3 on the side of the long side of the display area A1, the length of the signal line introduced from the pad area A3 to the display area A1 through the bending area A2 can be made longer in the display area A1 Short, generally equivalent to the length of the short side of the display area A1. Under the influence of loading, the voltage difference between the first and the end of the signal line is positively related to the length of the signal line, that is, the longer the length of the signal line, the greater the pressure difference between the first and the end of the signal line; the length of the signal line The shorter it is, the smaller the voltage difference between the head and the end of the signal line is, therefore, the voltage difference between the head and the end of each signal line introduced from the pad area A3 to the display area A1 can also be made smaller.

FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present application. It can be seen in conjunction with FIG. 1 and FIG. 2 that the display substrate may further include: a plurality of pixels 02 arranged in an array and located in the display area A1. A plurality of first power line groups 03 and a plurality of first signal lines 04 . Wherein, each first power supply line group 03 may include at least two first power supply lines VDD for providing a first DC power supply signal. Each of the first power lines VDD and each of the first signal lines 04 may extend from the pad area A3 to the display area A1 through the bending area A2, and be connected to at least one pixel 02, and each of the first power lines VDD and The extension direction of the part of the line segment connecting each of the first signal lines 04 to the pixel may be parallel to the second direction Y1 .

1 again, by arranging the pad area A3 on the side of the long side of the display area A1, the pad area A3 is arranged on the side of the short side of the display area A1 relative to the related art, so that the pad area A3 is introduced into the display area A1. The length of each signal line in the display area A1 is reduced, thereby reducing the voltage difference between the head and the end of each signal line. Since the smaller the voltage difference between the first and last ends of each signal line, the better the display effect uniformity of the pixels connected to the two ends of each signal line is, therefore, the display effect uniformity of the display substrate is also improved.

It should be noted that, the base substrate 01 provided in the embodiment of the present application may be a base substrate 01 having a special size. The special size may refer to: the length of the display area A1 of the base substrate 01 in the first direction X1 is much larger than the length of the display area A1 in the second direction Y1. For example, the ratio of the length of the display area A1 of the base substrate 01 in the first direction X1 to the length of the display area A1 in the second direction Y1 satisfies the ratio threshold. Optionally, the ratio threshold is approximately 3%. For example, taking the display substrate shown in FIG. 1 as an example, in the display substrate, the ratio of the long side to the short side of the display area A1 of the base substrate 01 may satisfy: 27.5:9.

To sum up, the embodiments of the present application provide a display substrate. In the display substrate, the base substrate has a display area, a bending area and a pad area, and the length of the display area in the first direction is greater than the length of the display area in the second direction. Since the pad area, the bending area and the display area are arranged along the second direction, the pad area is located on the side of the longer boundary line of the display area, so that each signal line introduced from the pad area to the display area is The length in the display area is shorter. Correspondingly, the voltage difference between the two ends of each signal line introduced from the pad area to the display area is small, and the display device using the display substrate has a better display effect.

Optionally, it can be seen with reference to FIG. 2 that, in the display substrate provided by the embodiment of the present application, in the bending area A2, between every two adjacent first power lines VDD in each first power line group 03 The spacing may be equal to the first spacing threshold, the spacing between every two adjacent first power line groups 03 may be greater than or equal to the second spacing threshold, and the first spacing threshold may be smaller than the second spacing threshold. For example, the first spacing threshold is generally about 0.001 micrometer (μm), and the second spacing threshold is generally about 5000 μm. That is, the plurality of first power supply lines VDD can be wired in groups (that is, in blocks) within the bending region A2.

By dividing the wiring, on the one hand, since the cross-sectional area of one first power supply line group 03 becomes larger than that of one first power supply line VDD, each first power supply line VDD in each first power supply line group 03 becomes larger. resistance becomes smaller. On the other hand, it can be facilitated to arrange the signal lines in the bending area A2 where the space (eg, height and width) is limited, ie, even for wiring.

Optionally, FIG. 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present application. As shown in FIG. 3 , the display substrate may further include: a first bridging part B1 and a second bridging part B2. The first bridge portion B1 may be located in the pad area A3, and the second bridge portion B2 may be located in the display area A1.

Each first power supply line VDD may include a first sub-line segment L1 (FIG. 3 only schematically shows a plurality of first power supply lines located in the pad area A3 with a large piece of metal block, and the first sub-line segment L1 belongs to a sub-line segment of the metal block), a second sub-line segment L2 and a third sub-line segment L3. The first sub-line segment L1 may be located in the pad area A3, one end of the first sub-line segment L1 may be connected to the power supply terminal, and the other end of the first sub-line segment L1 may be connected to the first jumper B1. One end of the second sub-line segment L2 may be connected to the first bridge part B1, and the other end of the second sub-line segment L2 may be connected to the second bridge part B2. One end of the third sub-line segment L3 may be connected to the second bridge portion B2, and the other end of the third sub-line segment L3 may be located in the display area A1 and connected to at least one pixel 02 (not shown in the figure).

Referring to FIG. 2 , the first power line VDD is led out from the pad area A3 to the display area A1 through the bending area A2 as follows: the plurality of first power lines VDD included in the plurality of first power line groups 03 are drawn from the pad area A3 It is led out to the display area A1 and connected together at the first bridge part B1. That is, the first jumping portion B1 is a layer of metal blocks formed by connecting the first power lines VDD. Then, the plurality of first power supply lines VDD connected together are separated and continue to be led out to the display area A1, and the plurality of first power supply lines VDD after being separated are connected together again at the second jumping part B2. That is, the second jumping portion B2 is another layer of metal blocks formed by connecting each of the first power lines VDD. In addition, the plurality of first power supply line groups 03 between the first jumping part B1 and the second jumping stage part B2 satisfies: the difference between every two adjacent first power supply lines VDD in each first power supply line group 03 is satisfied. The spacing is less than or equal to the first spacing threshold, and the spacing between every two adjacent first power line groups 03 is greater than or equal to the second spacing threshold. Finally, the plurality of first power supply lines VDD that are connected together again are separated, and each first power supply line VDD is set to be connected to at least one pixel 02 respectively. For example, each of the first power lines VDD can be set to be connected to a column of pixels. Correspondingly, the number of first power lines VDD included in the display substrate may be the same as the number of columns of pixels included.

It should be noted that, in this wiring method, with reference to FIG. 3 , a plurality of first power line groups 03 are located in the pad area A3 close to the bending area A2 and in the display area A1 close to the bending area A2 All satisfy: the distance between every two adjacent first power supply lines VDD in each first power supply line group 03 is less than or equal to the first distance threshold, and the distance between every two adjacent first power supply line groups 03 Greater than or equal to the second spacing threshold. In addition, a driving circuit is also provided in the pad area A3, and the power supply terminal connected to one end of the first sub-line segment L1 can be provided by the driving circuit. That is, one end of the first sub-line segment L1 may be connected to the driving circuit.

Optionally, the first sub-line segment L1, the second sub-line segment L2, the third sub-line segment L3, the first jumping part B1 and the second jumping part B2 may all be related to source and drain metal (source & drain, SD) in the display substrate. The layers are set on the same layer, and the SD layer is an essential part of the formation of pixels. In this way, the manufacturing process can be simplified and the manufacturing cost can be saved.

Optionally, the number of first power lines VDD included in each of the first power line groups 03 may be the same. That is, the first power supply lines VDD may be arranged in uniform blocks. In this way, not only can the wiring be further facilitated, but also the resistances on each of the first power supply lines VDD can be made more consistent. Correspondingly, the differences in the potentials of the first power supply signals provided by the plurality of first power supply lines VDD to the plurality of pixels are small, which further ensures the display uniformity of the display device.

For example, referring to FIG. 4 , assuming that a total of 4000 first power lines VDD need to be set, the 4000 first power lines VDD can be divided into ten first power line groups 03 , and each first power line group 03 is set Both include 400 first power lines VDD. FIG. 4 does not show the specific number, and FIG. 4 only shows each first power line group 03 extending from the bending area A2 to the display area A1.

FIG. 5 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application. As shown in FIG. 5 , the plurality of first signal lines 04 may include: a data signal line D1 for providing a data signal, and/or a second power line VSS for providing a second DC power signal. That is, the plurality of first signal lines 04 may include: a plurality of data signal lines D1, or a plurality of second power supply lines VSS, or a plurality of data signal lines D1 and a plurality of second power supply lines VSS.

5 , each data signal line D1 may include: a data line lead D11 and a data line D12 that are connected to each other. The data line lead D11 may be located in the bending area A2 and the pad area A3, the data line D12 may be located in the display area A1, and the data line D12 may be connected with at least one pixel 02 located in the display area A1 (not shown in the figure). That is, the part of the line segment of the data signal line D1 in the bending area A2 and the pad area A3 may be called the data line lead D11, and the part of the line segment of the data signal line D1 in the display area A1 may be called the data line D12.

Optionally, FIG. 6 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application. FIG. 7 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application. It can be seen in conjunction with FIG. 6 and FIG. 7 that the data signal line D1 may be disposed in the same layer as the first gate metal layer G1 in the display substrate. Alternatively, the data signal line D1 may be disposed in the same layer as the second gate metal layer G2 in the display substrate. For example, referring to FIG. 6 and FIG. 7, it can be seen that in every two adjacent data signal lines D1, one data signal line D1 and the first gate metal layer G1 are arranged in the same layer, and the other data signal line D1 and the first gate metal layer G1 are arranged in the same layer. The two gate metal layers G2 are disposed in the same layer. Since the gate metal layer is also an essential component for forming the pixel 02, the manufacturing process can be further simplified and the manufacturing cost can be saved.

Since an insulating layer is generally arranged between the gate metal layer (eg, G1 and G2) and the SD layer, and since the first power supply line VDD is arranged in the same layer as the SD layer, in order to prevent the bending regions A2 and A2 having a limited size All the required data signal lines D1 and the first power supply line VDD are arranged in the pad area A3, and the data signal line D1 can be arranged below the first power supply line VDD. That is, the orthographic portion of the first power supply line VDD on the base substrate 01 is set to cover the orthographic projection of the data signal line D1 on the base substrate 01 .

FIG. 8 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application. As shown in FIG. 8 , the base substrate 01 may further have a first lead area A4 and a second lead area A5 , and the first lead area A4 , the display area A1 and the second lead area A5 may be arranged along the first direction X1 .

In the embodiment of the present application, the display substrate further includes: a plurality of second signal lines 05 . Among the plurality of second signal lines 05, a part of the second signal lines 05 may extend from the pad area A3 to the first lead area A4, and be connected to at least one pixel. Another part of the second signal line 05 may extend from the pad area A3 to the second lead area A5 and be connected to at least one pixel 02 .

Optionally, the second signal line 05 may be used to provide a gate driving signal. Correspondingly, as shown in FIG. 8 , each second signal line 05 may include a gate line lead 051 and a gate line 052 connected to each other.

The gate line lead 051 may be located in the pad area A3 and the first lead area A4, or the gate line lead 051 may be located in the pad area A3 and the second lead area A5. The gate line 052 may be located in the display area A1 and connected to at least one pixel (not shown in the figure). Optionally, the gate line lead 051 may first provide the gate driving signal to the gate line 052 , and then the gate line 052 may provide the received gate driving signal to the connected pixel 02 . Therefore, the gate line lead 051 may also be referred to as a (gate drive on array, GOA) signal line, and GOA means that the gate drive circuit is integrated on the substrate using the array substrate row driving technology.

Optionally, limited by the size of the bending area A2 and the pad area A3, in order to ensure that each signal line that needs to be set can be set, the line width of each first power line VDD is less than or equal to the first line width threshold. . The line width of each second power supply line VSS may be less than or equal to the second line width threshold. The line width of each second signal line 05 may be less than or equal to the third line width threshold. For example, the first line width threshold may be about 600 μm, the second line width threshold may be about 500 μm, and the third line width threshold may be about 88 μm.

Optionally, each second signal line 05 may include: a first metal layer and a second metal layer. The first metal layer may be provided in the same layer as the first gate metal layer in the display substrate, and the second metal layer may be provided in the same layer as the second gate metal layer in the display substrate. That is, the second signal line 05 may be composed of the first gate metal layer G1 and the second gate metal layer G2 in parallel. Alternatively, as shown in FIGS. 9 and 10 , each of the second signal lines 05 may include: a first metal layer M1 , a second metal layer M2 and a third metal layer M3 . The first metal layer M1 may be provided on the same layer as the first gate metal layer G1 in the display substrate, the second metal layer M2 may be provided on the same layer as the second gate metal layer G2 in the display substrate, and the third metal layer M3 may be provided on the same layer. It is arranged in the same layer as the source-drain metal layer SD layer in the display substrate. That is, the second signal line 05 may be composed of the first gate metal layer G1 , the second gate metal layer G2 and the source-drain metal layer SD in parallel. In addition, referring to FIG. 10 , it can be seen that an insulating layer F1 is provided between every two adjacent metal layers. Furthermore, in order to ensure the reliable connection of the first metal layer M1, the second metal layer M2 and the third metal layer M3, each insulating layer F1 may be provided with a via hole k penetrating the insulating layer, the first metal layer M1 and the third metal layer M1 The three metal layers M3 may be electrically connected through via holes k, and the second metal layer M2 and the third metal layer M3 may be electrically connected through via holes k. By using different layers of metal layers to form the second signal lines 05 in parallel, each second signal line 05 can be composed of multi-section metal lines with shorter lengths. Since the length of the signal line is shorter, the resistance on the signal line is smaller, so the resistance on each second signal line 05 is reduced to ensure a better display effect.

It should be noted that, regardless of whether it is the data line lead D11 or the gate line lead 051, since it is located in the non-display area, it can be called a fanout line. 1, 5 and 8, since the pad area A3 is located on the side of the long side of the display area A1, in order to facilitate the connection of the data line D12 and the gate line 052 with the pixels in the display area A1, compared with the related art, it is also The position of the pixel 02 can be rotated accordingly, so that after the rotation, the extension direction of the gate line 052 connected to the pixel 02 is parallel to the first direction X1, and the extension direction of the data line D12 connected to the pixel 02 is parallel to the second direction Y1. That is, a plurality of pixels arranged along the first direction X1 is called a row of pixels, and a plurality of pixels arranged along the second direction Y1 is called a column of pixels.

Optionally, if the display substrate is an organic light-emitting diode (OLED) substrate, then each pixel O2 may include a pixel circuit and a light-emitting element, and the pixel circuit may be connected to a first power line VDD, a gate line respectively. 052. A data line D12 is connected to one end (eg, anode) of the light-emitting element, and the other end (eg, cathode) of the light-emitting element may also be connected to the second power line VSS. The pixel circuit may output a driving signal to the light emitting element in response to the gate driving signal provided by the gate line 052, the data signal provided by the data line D12, and the first power supply signal provided by the first power supply line VDD. The light-emitting element can emit light under the action of the voltage difference between the received driving signal and the second power supply signal provided by the second power supply line VSS. That is, the potential of the first power supply signal may be an effective potential relative to the potential of the second power supply signal.

Optionally, FIG. 11 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application. 1 and 11, the pad area A3 is located on the side where the long side of the display area A1 is located. Therefore, in order to ensure reliable driving of the pixels on the left and right sides of the display area A1 along the first direction X1. The pad area A3 may include a symmetrical first area A31 and a second area A32. The layout and wiring of the bending area A2 and the pad area A3 are the same.

The first power supply line VDD, the first signal line 04 (including the data signal line D1 and the second power supply line VSS) are introduced to the display area A1 from the pad area A3 through the bending area A2, and the lead wires are introduced from the pad area A3 For the second signal lines 05 in the area, among each type of signal lines, a part of the signal lines may be located in the first area A31, and another part of the signal lines may be located in the second area A32. 11 and FIG. 12 , in the display substrate shown, the number of first power line groups included in the display area A1 from each sub-region of the pad area A3 and introduced into the display area A1 through the bending area A2 is 5, which are respectively marked as 03a, 03b, 03c, 03d and 03e. FIG. 11 also shows the driving circuit 10 disposed in the pad area A3 , and all kinds of signal lines are connected to the driving circuit 10 and receive the signals provided by the driving circuit 10 . That is, the signals provided to the pixels by various signal lines can be derived from the driving circuit 10 .

Taking the second partition A32 as an example, FIG. 12 shows a schematic diagram of the overall structure of the second partition A32. FIG. 13 shows a schematic diagram of other structures except the driving circuit 10 in the second partition A32. It can be further seen in conjunction with FIG. 12 and FIG. 13 that the data signal line D1 may be located below the first power supply line VDD. And before connecting to the pixel 02, the plurality of first power lines VDD drawn from the pad area A3 can be connected to the first jumper B1, and then split into the bending area A2, and just after entering the display area. A1 is all connected to the second jumper B2, and finally split and continues to enter the display area and connected to the pixel 02. FIG. 14 shows a schematic diagram of the internal structure of the driving circuit 10 . It should be noted that, with reference to FIG. 14 , the line widths of the multiple signal lines (eg, fan-out traces) drawn from the driving circuit 10 in the free area (ie, the area without any structure) in the pad area A3 may be greater than The line width threshold, that is, the signal lines located in the free area can be thickened, so as to achieve the effect of reducing the resistance of the signal lines. 15 shows a schematic diagram of the first power supply line VDD, the data line D12 included in the data signal line D1, and the gate line 052 included in the second signal line 05 in the display area A1. Referring to FIG. 15 , it can be further seen that after the plurality of first power lines VDD enter the display area A1 , they are first connected together, that is, connected into one piece, and then split and connected to the pixels.

Optionally, in order to facilitate wiring and ensure the uniformity of the display effect of the pixels 02 at various positions in the display area A1, in each type of signal lines, the number of signal lines located in the first area A31 is the same as the number of signal lines located in the second area A31. The number of signal lines of the partition A32 may be the same.

That is, with reference to FIG. 11 , the display substrate shown includes a total of 10 first power supply line groups 03 , and each first power supply first group 03 may include 400 first power supply lines VDD. The display substrate further includes: two second power lines VSS, a plurality of data signal lines D1, and a plurality of second signal lines 05. Among them, among the ten first power cord groups 03, five first power cord groups 03 can be introduced into the display area A1 from the first partition A31, and five first power cord sets 03 can be introduced into the display area from the second partition A32 A1. Among the two second power supply lines VSS, one second power supply line VSS may be introduced into the display area A1 from the first partition A31, and the other second power supply line VSS may be introduced into the display area A1 through the second partition A32. Among the plurality of data signal lines D1, half of the data signal lines D1 can be led to the display area A1 from the first partition A31, and the other half of the data signal lines D1 can be led to the display area A1 from the second partition A32. Among the plurality of second signal lines 05, half of the second signal lines 05 can be led to the display area A1 from the first partition A31, and the other half of the second signal lines 05 can be led to the display area A1 from the second partition A32.

It can be seen in combination with FIG. 11 that in each partition, the target line group, the second power supply line VSS and the second signal line 05 can be arranged in turn in a direction away from another partition, wherein the target line group can include data signal lines. D1 and the first power supply line VDD. That is, the second signal line 05 , the second power supply line VSS and the target line group may be arranged in sequence from the outermost position of the pad area A3 to the most central position of the pad area A3 .

Optionally, it can be seen in combination with FIG. 11 and FIG. 16 that, limited by the size of the pad area A3, in order to ensure that all types of signal lines required can be arranged in the pad area A3, in each partition, each Each type of signal line includes at least one target signal line, and the target signal line is close to the edge of the pad area A3 relative to other signal lines except the target signal line. FIG. 16 does not show the portion of the bending area A2.

The portion of the target signal line located in the pad area A3 includes a first target sub-line segment L11 and a second target sub-line segment L22 connected in sequence, the first target sub-line segment L11 is close to the display area A1 relative to the second target sub-line segment L12, and the first target sub-line segment L11 is close to the display area A1. The included angle α between the target sub-line segment L11 and the boundary line J1 extending along the first direction X1 of the display area A1 may be less than or equal to 90 degrees. Generally, the angle between the first target sub-line segment L11 and the boundary line J1 extending along the first direction X1 of the display area A1 may be set to about ten degrees. That is, among all types of signal lines, the signal lines near the edge of the pad area A3 extend obliquely from the pad area A3 to the display area A1.

FIG. 17 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application. As shown in FIG. 17 , the base substrate may further include a component setting area A6. And the component setting area A6 and the pad area A3 may be located on the same side of the display area A1. The display substrate also includes a camera component C1 located in the component setting area A6.

Correspondingly, in order to avoid the setting of the camera assembly C1, referring to FIG. 17, the side of the pad area A3 close to the component setting area A6 has a first part l1 and a second part l2 connected to each other, and the extension direction of the first part l1 is the same as that of the first part l1. The extending directions of the second portions l2 intersect, that is, are not parallel. In this way, some space can be saved for the component setting area A6, which facilitates the setting of hardware structures such as the photographing component C1. For example, referring to FIG. 17 , an angle β may be formed between the first part l1 and the second part l2 on the side of the pad area A3 close to the component setting area A6, which may also be called a pad The chamfered corner of the boundary line of area A3.

FIG. 18 is a schematic structural diagram of a display device provided by an embodiment of the present application. As shown in FIG. 18 , the display device may include: the driving circuit 10 located in the pad area A3 , and the display substrate 20 as shown in any one of FIGS. 1 to 17 . Wherein, the driving circuit 10 can be connected with various types of signal lines included in the display substrate 20 and used to provide signals for the connected signal lines.

For example, the driving circuit 10 can provide a data signal for the data signal line D1, can provide a gate driving signal for the second signal line 05, can provide a first power supply signal for the first power supply line VDD, and can provide a second power supply line VSS. the second power signal.

Optionally, the display device may be: OLED display device, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, navigator, and any other product or component with display function.

It should be understood that references herein to "a plurality" means two or more. "And/or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, A and B exist at the same time, and B exists alone.

It should also be understood that "C is about m" referred to herein means that the difference between C and m is within the allowable error range of the process parameters. For example, assuming that the allowable error range of the process parameters is n, C being about m may mean that C is greater than or equal to m-n and less than or equal to m+n.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the display substrate and the display device described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

The above descriptions are only optional embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection of the present application. within the range.

Claims

A display substrate comprising:

A base substrate, the base substrate has a display area, a bending area and a pad area, the length of the display area in the first direction is greater than the length of the display area in the second direction, the first direction perpendicular to the second direction, and the pad area, the bending area and the display area are arranged along the second direction;

a plurality of pixels arranged in an array, located in the display area;

a plurality of first power line groups and a plurality of first signal lines, each of the first power line groups including at least two first power lines for providing a first DC power signal, each of the first power lines Lines and each of the first signal lines extend from the pad area to the display area, and are connected to at least one of the pixels, and each of the first power lines and each of the first signal lines The extension directions of the partial line segments connected to the pixels are all parallel to the second direction.
The display substrate according to claim 1, wherein in the bending region, a distance between every two adjacent first power lines in each of the first power line groups is less than or equal to a first distance threshold , the distance between every two adjacent first power supply line groups is greater than or equal to a second distance threshold, and the first distance threshold is smaller than the second distance threshold.
The display substrate according to claim 1, further comprising: a first bridging part and a second bridging part, the first bridging part is located in the pad area, and the second bridging part is located in the display area; each of the first power lines includes a first sub-line segment, a second sub-line segment and a third sub-line segment;

The first sub-line segment is located in the pad area, one end of the first sub-line segment is connected to the power supply terminal, and the other end of the first sub-line segment is connected to the first jumper;

One end of the second sub-line segment is connected to the first jumper, and the other end of the second sub-line segment is connected to the second jumper;

One end of the third sub-line segment is connected to the second jumper, and the other end of the third sub-line segment is connected to at least one of the pixels;

Wherein, the first sub-line segment, the second sub-line segment, the third sub-line segment, the first jumper and the second jumper are all connected to the source-drain metal layer in the display substrate Same layer settings.
The display substrate according to claim 1, wherein the number of the first power lines included in each of the first power line groups is the same.
The display substrate according to claim 1, wherein a line width of each of the first power lines is less than or equal to a first line width threshold.
The display substrate according to any one of claims 1 to 5, wherein the plurality of first signal lines include: data signal lines for providing data signals, and/or a second power supply for providing second DC power signals Wire.
The display substrate according to claim 6, wherein the plurality of first signal lines comprise: a plurality of the data signal lines;

Each of the data signal lines includes: interconnected data line leads and data lines;

Wherein, the data line leads are located in the pad area and the bending area, the data line is located in the display area, and the data line is connected to at least one of the pixels.
The display substrate according to claim 6, wherein the data signal line and the first gate metal layer in the display substrate are disposed in the same layer; or, the data signal line and the second gate in the display substrate The metal layer is set on the same layer.
The display substrate according to claim 6, wherein a line width of each of the second power lines is less than or equal to a second line width threshold.
The display substrate according to any one of claims 1 to 9, wherein the base substrate further has a first lead area and a second lead area, and the first lead area, the display area and the second lead area arranged along the first direction; the display substrate further includes: a plurality of second signal lines;

Among the plurality of second signal lines, a part of the second signal lines extends from the pad area to the first lead area, and is connected to at least one of the pixels; another part of the second signal lines A line extends from the pad area to the second lead area and is connected to at least one of the pixels.
The display substrate of claim 10, wherein a line width of each of the second signal lines is less than or equal to a third line width threshold.
The display substrate according to claim 10, wherein the second signal lines are used for providing gate driving signals; each of the second signal lines comprises: a gate line lead and a gate line connected to each other;

Wherein, the gate line leads are located in the pad area and the first lead area, or, the gate line leads are located in the pad area and the second lead area;

The gate line is located in the display area, and the gate line is connected with at least one of the pixels.
The display substrate according to claim 12, wherein each of the second signal lines comprises: a first metal layer and a second metal layer; the first metal layer is the same as the first gate metal layer in the display substrate layer arrangement, the second metal layer and the second gate metal layer in the display substrate are arranged in the same layer;

Alternatively, each of the second signal lines includes: a first metal layer, a second metal layer, and a third metal layer; the first metal layer and the first gate metal layer in the display substrate are provided in the same layer, The second metal layer is disposed on the same layer as the second gate metal layer in the display substrate, and the third metal layer is disposed on the same layer as the source-drain metal layer in the display substrate.
The display substrate according to any one of claims 1 to 13, wherein each type of signal line includes at least one target signal line, and the target signal line is close to the target signal line relative to other signal lines except the target signal line. at the edge of the pad area;

The part of the target signal line located in the pad area includes a first target sub-line segment and a second target sub-line segment connected in sequence, and the first target sub-line segment is close to the display area relative to the second target sub-line segment , and the included angle between the first target sub-line segment and the boundary line of the display area extending along the first direction is less than or equal to 90 degrees.
The display substrate according to any one of claims 1 to 14, further comprising: a plurality of second signal lines; the first signal lines comprising: data signal lines and second power supply lines;

The pad area includes a symmetrical first subregion and a second subregion;

In each type of signal lines, a part of the signal lines are located in the first partition, and the other part of the signal lines are located in the second partition.
The display substrate according to claim 15 , wherein in each type of signal lines, the number of signal lines located in the first partition is the same as the number of signal lines located in the second partition.
The display substrate according to claim 15, wherein in each of the partitions, the target line group, the second power supply lines and the second signal lines are sequentially arranged in a direction away from another of the partitions, wherein the The target line group includes the data signal line and the first power line.
The display substrate according to any one of claims 1 to 17, wherein the base substrate further has a component setting area, and the component setting area and the pad area are located on the same side of the display area;

The display substrate further includes a camera assembly located in the assembly setting area;

A side of the pad area close to the component setting area has a first part and a second part connected to each other, and the extension direction of the first part intersects with the extension direction of the second part.
The display substrate according to claim 13, wherein the plurality of first signal lines comprise: data signal lines for providing data signals, and/or second power lines for providing second DC power signals; each The data signal lines include: data line leads and data lines connected to each other; wherein, the data line leads are located in the pad area and the bending area, the data lines are located in the display area, and the A data line is connected to at least one of the pixels; the data signal line and the first gate metal layer in the display substrate are arranged in the same layer; or, the data signal line and the second gate in the display substrate The metal layer is set on the same layer;

The line width of each of the second power lines is less than or equal to the second line width threshold; the line width of each of the second signal lines is less than or equal to the third line width threshold;

Each type of signal line includes at least one target signal line, and the target signal line is close to the edge of the pad area relative to other signal lines except the target signal line; the target signal line is located at the edge of the pad area. A portion of the pad area includes a first target sub-line segment and a second target sub-line segment connected in sequence, the first target sub-line segment is close to the display area relative to the second target sub-line segment, and the first target sub-line segment is adjacent to the display area. The included angle between the target sub-line segment and the boundary line extending along the first direction of the display area is less than or equal to 90 degrees;

The pad area includes a symmetrical first partition and a second partition; in each type of signal lines, a part of the signal lines is located in the first partition, and another part of the signal lines is located in the second partition, and In each type of signal line, the number of signal lines located in the first partition is the same as the number of signal lines located in the second partition; in each of the partitions, the target line group, the second power supply line and the second signal lines are sequentially arranged in a direction away from the other partition, wherein the target line group includes the data signal line and the first power line;

The base substrate further has a component setting area, and the component setting area and the pad area are located on the same side of the display area; the display substrate further includes a camera component located in the component setting area; A side of the panel area close to the component setting area has a first part and a second part connected to each other, and the extending direction of the first part intersects the extending direction of the second part.
A display device, the display device comprising: a drive circuit located in the pad area, and the display substrate according to any one of claims 1 to 19;

Wherein, the driving circuit is connected to various types of signal lines included in the display substrate, and the driving circuit is used to provide signals for the connected signal lines.