WO2022027951A1 - 驱动电路 - Google Patents

驱动电路 Download PDF

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Publication number
WO2022027951A1
WO2022027951A1 PCT/CN2021/076150 CN2021076150W WO2022027951A1 WO 2022027951 A1 WO2022027951 A1 WO 2022027951A1 CN 2021076150 W CN2021076150 W CN 2021076150W WO 2022027951 A1 WO2022027951 A1 WO 2022027951A1
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WIPO (PCT)
Prior art keywords
signal
pull
transistor
clock
driving
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PCT/CN2021/076150
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English (en)
French (fr)
Inventor
谷银川
Original Assignee
长鑫存储技术有限公司
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Filing date
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21820445.1A priority Critical patent/EP4195509A1/en
Priority to US17/374,999 priority patent/US11290104B2/en
Publication of WO2022027951A1 publication Critical patent/WO2022027951A1/zh
Priority to US17/653,131 priority patent/US11777493B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices

Definitions

  • the embodiments of the present application relate to the technical field of semiconductor devices, and in particular, to a driving circuit.
  • the memory it is necessary to realize the driving of the data signal through the driving circuit, so as to improve its transmission speed.
  • the driving capability of the existing driving circuit can no longer meet the rapidly developing use requirements.
  • the present application provides a driving circuit.
  • One aspect of the present application provides a driving circuit, comprising:
  • a main driving module configured to receive a first signal and generate a second signal according to the first signal, the driving capability of the second signal is greater than the driving capability of the first signal
  • an auxiliary drive module connected to the output end of the main drive module, for receiving the first signal, and generating an auxiliary drive signal according to the first signal, the auxiliary drive signal being used to shorten the duration of the second signal Rise Time.
  • a driving circuit comprising:
  • a second pull-up transistor for generating an auxiliary driving signal and outputting the auxiliary driving signal to the main driving module, where the auxiliary driving signal is used to shorten the rise time of the output signal of the main driving module;
  • an edge enhancement unit connected to the periodic clock generation component and the control terminal of the second pull-up transistor, respectively, the edge enhancement unit is used for receiving the clock signal and the first signal input from the outside, and according to the clock The signal and the first signal generate an edge enhancement signal, and the edge enhancement signal is used to control the on-off of the second pull-up transistor.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment
  • FIG. 2 is a schematic structural diagram of a driving circuit according to another embodiment
  • FIG. 4 is a comparison diagram of the eye diagram test results of the second signal
  • FIG. 6 is a voltage-time relationship diagram of a second signal according to an embodiment
  • FIG. 7 is a schematic structural diagram of a driving circuit according to still another embodiment.
  • FIG. 8 is a schematic structural diagram of a duty cycle modulation circuit according to an embodiment.
  • FIG. 1 is a schematic structural diagram of a driving circuit according to an embodiment.
  • the driving circuit includes a main driving module 100 and an auxiliary driving module 200 .
  • the main driving module 100 is configured to receive the first signal DQ, and generate a second signal VOH according to the first signal DQ.
  • the driving capability of the second signal VOH is greater than the driving capability of the first signal DQ.
  • the main driving module 100 is used for acquiring data signals from the logic circuit, processing the acquired data signals, and transmitting the processed signals to the controller through a signal channel, thereby realizing the transmission of the data signals.
  • the first signal DQ is the data signal obtained by the main driving module 100 from the logic circuit
  • the second signal VOH is the signal processed by the main driving module 100 and sent to the signal channel.
  • the memory can be a dynamic random access memory (Dynamic Random Access Memory, DRAM) and a static random access memory (Static Random-Access Memory, SRAM), specifically, for example, can be low power DDR4 (LPDDR4) or LPDDR4X Memory DRAM, SRAM, Thyristor RAM (TRAM), Zero Capacitor RAM (Z-RAM), Two Transistor RAM (TTRAM) MRAM, etc.
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • LPDDR4 low power DDR4
  • LPDDR4X Memory DRAM SRAM
  • TRAM Thyristor RAM
  • Z-RAM Zero Capacitor RAM
  • TTRAM Two Transistor RAM
  • the auxiliary driving module 200 is connected to the output terminal of the main driving module 100 for receiving the first signal DQ and generating the auxiliary driving signal according to the first signal DQ, and the auxiliary driving signal is used to shorten the rise time of the second signal VOH.
  • the reading and writing of the data signal is performed in response to the clock signal. Therefore, if the data signal to be written does not reach the target level when the rising edge and/or the falling edge of the clock signal arrives, it will result in data reading and writing. Mistake. For example, if the data to be written corresponding to the edge moment of the current clock signal is 1, and the data to be written at the edge moment of the previous clock signal is 0, then it needs to be between two adjacent edge moments of the clock signal, The accurate transmission of the second signal VOH can only be achieved by pulling the second signal VOH from the low level range to the high level range, for example, from 0.1V to 1.1V. If the signal VOH does not reach the high-level range, the signal transmitted to the signal channel is a low-level signal, that is, the actual second signal VOH cannot be accurately transmitted to the signal channel, resulting in a transmission error of the second signal VOH .
  • the memory also needs to achieve faster read and write speed and data transfer rate.
  • the data transfer rate of LPDDR is 400Mbps (Million bits per second)
  • the data transfer rate of LPDDR2 is 1600Mbps
  • the data transfer rate of LPDDR3 is 2133Mbps
  • the data transfer rate of LPDDR4 is 3200Mbps
  • the data transfer rate of LPDDR4X is 4.266Gbps.
  • the period of the clock signal in the memory needs to be shortened accordingly, that is, the time interval between two adjacent edges of the clock signal will be further shortened.
  • the rise time of the second signal VOH If it is too long, the timing margin of the data signal will be reduced, thus limiting the transfer speed and read/write speed of the memory. Therefore, it is necessary to further increase the switching speed between the high and low levels of the second signal VOH to ensure the correct transmission of the second signal VOH.
  • the driving circuit includes: a main driving module 100, configured to receive a first signal DQ, and generate a second signal VOH according to the first signal DQ, and the driving capability of the second signal VOH is greater than that of the first signal DQ.
  • the driving capability of a signal DQ the auxiliary driving module 200, connected to the output end of the main driving module 100, is used for receiving the first signal DQ, and generating an auxiliary driving signal according to the first signal DQ, the auxiliary driving The driving signal is used to shorten the rise time of the second signal VOH.
  • the main driving module 100 realizes the improvement of the driving capability of the first signal DQ, and through the cooperation of the auxiliary driving module 200, the rise time of the second signal VOH is shortened, and the timing margin of the data signal is improved, so that more Fast signal transmission speed.
  • FIG. 2 is a schematic structural diagram of a driving circuit according to another embodiment.
  • the main driving module 100 includes a first pull-up transistor MN1 , a first pull-down transistor MNDN and a pre-driving unit 110 .
  • the first pull-up transistor MN1 and the first pull-down transistor MNDN are jointly used to generate the second signal VOH, and the output end of the first pull-up transistor MN1 and the output end of the first pull-down transistor MNDN are connected to jointly output the second signal VOH.
  • the pre-driving unit 110 is connected to the first pull-up transistor MN1 and the first pull-down transistor MNDN respectively.
  • the pre-driving unit 110 is used to receive the first signal DQ and control the first pull-up transistor MN1 according to the first signal DQ. on and off of the second pull-up transistor MN2.
  • the first pull-up transistor MN1 is used to pull up the voltage of the second signal VOH to a first preset level.
  • the first preset level belongs to a high-level range.
  • the high-level range is, for example, greater than 1V.
  • the pull-down transistor MNDN is used to pull down the voltage of the second signal VOH to a second preset level, and the second preset level belongs to a low-level range, and the low-level range is, for example, less than 0.2V.
  • the first pull-up transistor MN1 and the first pull-down transistor MNDN have different pull-up capabilities, wherein the transistor with stronger pull-up capability can pull the voltage of the second signal VOH to the corresponding first pre-drive level.
  • Set the level or the second preset level For example, if the pull-up capability of the first pull-up transistor MN1 is strong, the voltage of the second signal VOH will be pulled up to the first preset level.
  • the pre-driving unit 110 respectively generates a first control signal and a second control signal according to the first signal DQ, and transmits the first control signal to the first pull-up transistor MN1 and transmits the second control signal to the first pull-down transistor MNDN.
  • the first pull-up transistor MN1 and the first pull-down transistor MNDN may be of the same type, where the types of transistors include N-type and P-type.
  • the first pull-up transistor MN1 and the first pull-down transistor MNDN are of the same type, the first pull-up transistor MN1 and the first pull-down transistor MNDN are both turned on at a high level, or both are turned on at a low level. Therefore, the level states of the first control signal and the second control signal can be reversed, for example, the first control signal is at a high level and the second control signal is at a low level, so that the first pull-up transistor can be controlled.
  • an inverter may be provided in the pre-driving unit 110, and the input end of the inverter is connected to the first control signal to invert the first control signal, thereby generating the second control signal.
  • the types of the first pull-up transistor MN1 and the first pull-down transistor MNDN may also be different.
  • the first pull-up transistor MN1 One of the transistor MN1 and the first pull-down transistor MNDN is turned on at a high level, and the other is turned on at a low level.
  • the level state of the first control signal and the second control signal can be the same, for example, the first control signal and the second control signal are both at a high level, and the first pull-up transistor MN1 and the first pull-up transistor MN1 and the first The control of the pull-down transistor MNDN so that the two transistors have different pull-up capabilities and can simplify the control signal generation circuit.
  • the first pull-up transistor MN1 and the first pull-down transistor MNDN are both N-type transistors.
  • power consumption is an important reference factor in the process of driving circuit design, and can be estimated by referring to the following formula:
  • C Load is the load capacitance
  • V DD is the power supply voltage VDDQL
  • V swing is the output voltage swing
  • P out is the output power. It can be known from the formula that when any one of the parameters of load capacitance, power supply voltage VDDQL and output voltage swing decreases, the output power can be reduced.
  • an N-type transistor is used as the first pull-up transistor MN1. Due to the structural characteristics of the N-type transistor itself, the N-type transistor has better load capacitance characteristics than the P-type transistor. Therefore, the use of the N-type transistor can effectively ground to reduce the output power consumption of the drive circuit.
  • the N-type first pull-up transistor MN1 may transmit a signal lower than the power supply voltage VDDQL. Therefore, compared with the driving circuit in which the first pull-up transistor MN1 is a P-type transistor, the driving circuit of this embodiment can transmit a signal with a smaller output voltage swing than the driving circuit in which the first pull-up transistor MN1 is a P-type transistor.
  • the output voltage swing of LPDDR4X is 0.366V
  • the output voltage swing of LPDDR4 is 0.3V. Therefore, LPDDR4X using N-type first pull-up transistor MN1 can reduce power consumption by about 20% compared to LPDDR4.
  • using the N-type transistor as the first pull-up transistor MN1 can effectively reduce the size of the main driving module 100 .
  • the same N-type transistor can be used for the first pull-up transistor MN1 and the first pull-down transistor MNDN, so as to improve the symmetry characteristics of the first pull-up transistor MN1 and the first pull-down transistor MNDN, so as to further improve the driving circuit. performance.
  • the drain of the first pull-up transistor MN1 is connected to the power supply voltage VDDQL
  • the source of the first pull-up transistor MN1 is connected to the drain of the first pull-down transistor MNDN
  • the The source is connected to the ground voltage GND; wherein, the source of the first pull-up transistor MN1 and the drain of the first pull-down transistor MNDN are jointly used to output the second signal VOH.
  • the first preset level is the power supply voltage VDDQL
  • the second preset level is the ground voltage GND.
  • the first control signal is high and the second control signal is low
  • the first pull-up transistor MN1 is turned on
  • the first pull-down transistor MNDN is turned off
  • the second signal VOH is pulled up to the power supply voltage VDDQL
  • the first control signal is at a low level and the second control signal is at a low level
  • the first pull-up transistor MN1 is turned off, the first pull-down transistor MNDN is turned on
  • the second signal VOH is pulled down to the ground voltage GND .
  • the present embodiment can shorten the rise time when the second signal VOH is switched from a low level to a high level, thereby expanding the timing margin of the signal to provide a higher reliability. , Faster output signal.
  • the auxiliary driving module 200 includes a second pull-up transistor MN2 and an edge enhancement unit 210 .
  • the second pull-up transistor MN2 is used to generate the auxiliary driving signal.
  • the auxiliary driving signal may be, for example, a charging current, that is, the auxiliary driving module 200 is used to generate a charging current according to the first signal DQ, and the charging current is used to speed up the charging speed of the second signal VOH, so as to shorten the charging current of the second signal VOH. Rise Time.
  • the auxiliary driving module 200 needs to be turned on, that is, the edge enhancement unit 210 controls the second pull-up transistor MN2 to be turned on, so that the second pull-up transistor MN2 outputs the charging current
  • the charging current to the main driving module 100 can speed up the charging speed of the output terminal of the main driving module 100, thereby shortening the rise time of the second signal VOH.
  • the second pull-up transistor MN2 is an N-type transistor, the control terminal of the second pull-up transistor MN2 is connected to the edge enhancement unit 210, the drain of the second pull-up transistor MN2 is connected to the power supply voltage VDDQL, and the second pull-up transistor MN2 is connected to the power supply voltage VDDQL.
  • the source of MN2 is used to output the auxiliary drive signal. That is, the second pull-up transistor MN2 and the first pull-up transistor MN1 are both connected to the power supply voltage VDDQL. Therefore, when the second pull-up transistor MN2 is turned on, the voltage of the output terminal of the main driving module 100 is rapidly raised to a high level. Thus, the rise time of the second signal VOH is shortened.
  • the N-type second pull-up transistor MN2 can transmit a signal lower than the power supply voltage VDDQL, and the driving circuit of this embodiment can transmit a drive that is a P-type transistor than the second pull-up transistor MN2.
  • the output voltage swing of the circuit is smaller.
  • the output voltage swing of LPDDR4X is 0.366V
  • the output voltage swing of LPDDR4 is 0.3V. Therefore, LPDDR4X can reduce power consumption by about 20% compared to LPDDR4.
  • using the N-type transistor as the second pull-up transistor MN2 can effectively reduce the size of the auxiliary driving module 200 .
  • the edge enhancement unit 210 is connected to the control terminal of the second pull-up transistor MN2 for receiving the first signal DQ, and generates an edge enhancement signal according to the first signal DQ, and the edge enhancement signal is used to control the on-off of the second pull-up transistor MN2 .
  • the edge enhancement signal is used as an enable signal to control the second pull-up transistor MN2, and the edge enhancement signal includes a high level and a low level.
  • the second pull-up transistor MN2 when the signal is at a high level, the second pull-up transistor MN2 is controlled to be turned on to output an auxiliary driving signal, thereby accelerating the switching of the second signal VOH from a low level to a high level; when the signal is at a low level, The second pull-up transistor MN2 is controlled to be turned off and the auxiliary driving signal is not output.
  • the edge enhancement unit 210 includes a pulse generation component 211 , a periodic clock generation component 212 and an operation component 213 .
  • the pulse generating component 211 is configured to receive the first signal DQ, and generate a pulse signal according to the first signal DQ.
  • Periodic clock generation component 212 is used to generate a clock signal.
  • the operation component 213 is respectively connected with the pulse generation component 211 and the periodic clock generation component 212, and the operation component 213 is configured to generate an edge enhancement signal according to the pulse signal and the clock signal.
  • the clock signal may also come from outside the edge enhancement unit 210, and the periodic clock generation component 212 may not function or only function as a delay.
  • FIG. 3 is a signal timing diagram of an embodiment. Referring to FIG. 3 , the period of the clock signal matches the period of data update of the first signal DQ, thereby ensuring the timing accuracy of signal reading and writing.
  • the pulse generating component 211 responds to the rising edge of the first signal DQ, and generates a pulse signal; wherein, the clock signal is configured with a preset clock period, and the width of the high level of the pulse signal is less than or equal to half of the clock period, for example As shown in FIG. 3 , the width of the high level of the pulse signal is equal to the width of the high level of the clock signal. It can be understood that the impact of maintaining the high level of the pulse signal on the power consumption of the driving circuit is higher than that of maintaining the low level state on the power consumption of the driving circuit.
  • the width of the high level of the pulse signal can achieve better power consumption performance. Specifically, an appropriate high level width can be selected according to the timing margin of the signal and power consumption requirements.
  • the high level width of the pulse signal can be 1/3, 1/4, etc. of the clock period. Further, when the high level width of the pulse signal generated by the pulse generation component 211 is greater than half of the clock period, it is impossible to accurately drive the second signal VOH based on the pulse signal. It can be understood that the period clock generation component 212 Therefore, when the high-level width of the pulse signal does not meet the requirements, the operation component 213 can choose to output the clock signal to ensure the accurate driving of the signal.
  • FIG. 4 is a comparison diagram of the eye diagram test results of the second signal VOH.
  • the two test diagrams on the left are the test results of the second signal VOH using the driving circuit of the prior art. Because the arrows in the upper left test diagram The rising speed of the second signal VOH pointing to the position is insufficient, resulting in an excessively long rise time of the second signal VOH, which in turn leads to severe noise, that is, the lower left eye diagram test result is insufficiently opened, and the signal timing margin is low.
  • the two test charts on the right are the test results of the second signal VOH using the driving circuit of this embodiment. Since the boosting speed of the second signal VOH at the position where the arrow points in the upper right test chart is significantly improved, the eye chart test on the lower right is significantly improved. The resulting noise is reduced and the timing margin of the signal is increased.
  • the width of the high level of the edge enhancement signal is less than or equal to the width of the high level of the pulse signal.
  • the width T2 of the high level of the edge enhancement signal is smaller than the width of the high level T1 of the pulse signal.
  • the rising edge of the edge enhancement signal is delayed by T3 compared to the rising edge of the pulse signal, and the falling edge of the edge enhancement signal is basically aligned with the falling edge of the pulse signal (there may be a delay of several logic gates in the actual circuit).
  • FIG. 5 is a signal timing diagram of another embodiment. In the embodiment shown in FIG.
  • the width T2 of the high level of the edge enhancement signal is wider than the width T2 of the high level of the edge enhancement signal in FIG. 3 .
  • the delay time T3 is adjustable.
  • the arithmetic component 213 may include a multiplexer, and the multiplexer is connected to the pulse generation component 211 and the periodic clock generation component 212 respectively, and the multiplexer selects the output pulse signal, so that the high level of the edge enhancement signal can be made.
  • the width of the level is equal to the width of the high level of the pulse signal or less than the width of the high level of the pulse signal, and the rising edge of the edge enhancement signal can be controlled to be delayed for a certain time compared to the rising edge of the pulse signal, such as Figure 3 and Figure 5 At the same time, the falling edge of the edge enhancement signal can also be controlled to be substantially aligned with the falling edge of the pulse signal.
  • the edge enhancement signal is only generated when the second signal VOH is close to the high voltage threshold. Limited by the NMOS transistor driving structure used in FIG.
  • the pull-up effect of the MN1 transistor on the second signal VOH becomes weak, resulting in the second signal VOH being at the high voltage threshold.
  • the rising speed is slow in the stage.
  • the edge enhancement signal turns on the MN2 tube, and the MN1 tube and the MN2 tube jointly pull up the second signal VOH, which can speed up the rising speed of the second signal VOH.
  • the pull-up effect of the MN1 tube on the second signal VOH becomes weaker and weaker as the second signal VOH rises. If the edge enhancement signal makes the MN2 tube turn on earlier, the second signal VOH can be faster.
  • the rise of VOH exceeds the high voltage threshold, but it also consumes more power consumption. Therefore, the moment when the rising edge of the pulse of the edge enhancement signal generated by the edge enhancement unit arrives should compromise the rising speed of the second signal VOH and the consumption power consumption.
  • the edge enhancement signal includes a plurality of enhancement pulses, the pulse signal includes a plurality of initial pulses, the enhancement pulses correspond to the initial pulses one-to-one, and the falling edges of the enhancement pulses are aligned with the corresponding falling edges of the initial pulses.
  • the edge enhancement signal includes 3 enhancement pulses, the pulse signal includes 3 initial pulses, and the first enhancement pulse corresponds to the first initial pulse, and the second enhancement pulse corresponds to the first enhancement pulse.
  • the third enhancement pulse corresponds to the third initial pulse.
  • the rising edge of the enhancement pulse is delayed by a preset time length from the corresponding rising edge of the initial pulse, and the preset time length is the time T3 shown in the embodiment of FIG. 3 .
  • the generation time of the auxiliary driving signal can be controlled, so that the timing of the auxiliary driving signal matches the timing of the second signal VOH to achieve better driving effect.
  • FIG. 6 is a voltage-time relationship diagram of the second signal VOH according to an embodiment.
  • FIG. 6 shows the voltage change during the transition of the second signal VOH from a low level to a high level.
  • the solid line in FIG. 6 shows The curve of the second signal VOH output by the driving circuit in the prior art is shown, and the dotted line in FIG. 6 shows the curve of the second signal VOH output by the driving circuit in this embodiment.
  • the voltage increasing speed is fast, and as the voltage of the second signal VOH continues to increase, the voltage increasing speed gradually slows down.
  • the auxiliary driving signal can be increased.
  • the output terminal of the second signal VOH is reached at the right moment, so as to achieve a better effect of improving the rise time of the second signal VOH with lower energy consumption.
  • the generation time of the charging current is equal to or later than the first time, where the first time may be, for example, the time when the voltage of the second signal VOH rises to the low level threshold.
  • the first time is the time t1 in FIG. 6
  • the power consumption of the driving circuit can be reduced by making the generation time of the charging current equal to or later than the first time.
  • the generation time of the charging current can be, for example, time t2 or time t3. etc.
  • an appropriate generation time can be selected according to the driving capability of the first pull-up transistor MN1 and the first pull-down transistor MNDN.
  • FIG. 6 illustrates the auxiliary charging current generation from time t3.
  • FIG. 7 is a schematic structural diagram of a driving circuit according to another embodiment.
  • the driving circuit includes a second pull-up transistor MN2 , a periodic clock generating component 212 and an edge enhancement unit 210 .
  • the second pull-up transistor MN2 is used for generating an auxiliary driving signal and outputting the auxiliary driving signal to the main driving module 100 , and the auxiliary driving signal is used for shortening the rise time of the output signal of the main driving module 100 .
  • the periodic clock generation component 212 is used to generate a clock signal with a duty cycle of 50%.
  • the edge enhancement unit 210 is respectively connected with the periodic clock generation component 212 and the control terminal of the second pull-up transistor MN2, and the edge enhancement unit 210 is used for receiving the clock signal and the first signal DQ input from the outside, and according to the clock signal and the first signal DQ An edge enhancement signal is generated, and the edge enhancement signal is used to control the on-off of the second pull-up transistor MN2.
  • the periodic clock generation component 212 includes a clock signal generation circuit 2121 and a duty cycle modulation circuit 2122 .
  • the clock signal generation circuit 2121 is used to generate a clock signal configured with a preset clock period;
  • the duty cycle modulation circuit 2122 is connected to the clock signal generation circuit 2121 for modulating the clock signal so that the duty cycle of the clock signal is 50% .
  • FIG. 8 is a schematic structural diagram of a duty cycle modulation circuit 2122 according to an embodiment.
  • the duty cycle modulation circuit 2122 includes a phase converter 2123 and a cross-coupling latch 2124 .
  • the phase converter 2123 is connected to the clock signal generating circuit 2121, and is used for receiving the clock signal, and performing phase conversion on the clock signal to generate a converted signal, and the phase difference between the converted signal and the clock signal is 180°.
  • the cross-coupling latch 2124 is connected to the phase converter 2123 for receiving the clock signal and the conversion signal, and performing duty cycle modulation according to the clock signal and the conversion signal, so that the duty cycle of the clock signal is 50%.
  • the cross-coupled latch 2124 includes two antiparallel inverters.
  • the modulation of the duty cycle of the clock signal can be achieved with a relatively simple circuit structure, so as to improve the jitter phenomenon of the clock signal, thereby obtaining wider timing margin.

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Abstract

本申请实施例涉及一种驱动电路包括：主驱动模块，用于接收第一信号，并根据所述第一信号生成第二信号，所述第二信号的驱动能力大于所述第一信号的驱动能力；辅助驱动模块，与所述主驱动模块的输出端连接，用于接收所述第一信号，并根据所述第一信号生成辅助驱动信号，所述辅助驱动信号用于缩短所述第二信号的上升时间。

Description

驱动电路
本申请要求于2020年8月7日提交的申请号为202010787892.X、名称为“驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体器件技术领域，特别是涉及一种驱动电路。
背景技术
随着移动设备的不断发展，手机、平板电脑、可穿戴设备等带有电池供电的移动设备被越来越多地应用于生活中，存储器作为移动设备中必不可少的元件，人们对存储器的高速、低功耗的存储功能提出了巨大的需求。
在存储器中，需要通过驱动电路实现对数据信号的驱动，从而提高其传输速度。但是，受到存储器的功耗的限制，现有的驱动电路的驱动能力已无法满足飞速发展的使用需求。
发明内容
基于此，本申请提供一种驱动电路。
本申请的一个方面提供一种驱动电路，包括：
主驱动模块，用于接收第一信号，并根据所述第一信号生成第二信号，所述第二信号的驱动能力大于所述第一信号的驱动能力；
辅助驱动模块，与所述主驱动模块的输出端连接，用于接收所述第一信号，并根据所述第一信号生成辅助驱动信号，所述辅助驱动信号用于缩短所述第二 信号的上升时间。
本申请的另一个方面提供一种驱动电路，包括：
第二上拉晶体管，用于生成辅助驱动信号，并输出所述辅助驱动信号至主驱动模块，所述辅助驱动信号用于缩短所述主驱动模块的输出信号的上升时间；
周期时钟生成组件，用于生成一占空比为50％的时钟信号；
边缘增强单元，分别与所述周期时钟生成组件和所述第二上拉晶体管的控制端连接，所述边缘增强单元用于接收所述时钟信号和外部输入的第一信号，并根据所述时钟信号和所述第一信号生成边缘增强信号，所述边缘增强信号用于控制所述第二上拉晶体管的通断。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明本申请的实施例，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为一实施例的驱动电路的结构示意图；
图2为另一实施例的驱动电路的结构示意图；
图3为一实施例的信号时序图；
图4为第二信号的眼图测试结果的对比图；
图5为另一实施例的信号时序图；
图6为一实施例的第二信号的电压-时间关系图；
图7为再一实施例的驱动电路的结构示意图；
图8为一实施例的占空比调制电路的结构示意图。
具体实施方式
为了便于理解本申请实施例，下面将参照相关附图对本申请实施例进行更全面的描述。附图中给出了本申请实施例的首选实施例。但是，本申请实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请实施例的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请实施例的技术领域的技术人员通常理解的含义相同。本文中在本申请实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请实施例。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1为一实施例的驱动电路的结构示意图，参考图1，在本实施例中，驱动电路包括主驱动模块100和辅助驱动模块200。
主驱动模块100用于接收第一信号DQ，并根据第一信号DQ生成第二信号VOH，第二信号VOH的驱动能力大于第一信号DQ的驱动能力。其中，主驱动模块100用于从逻辑电路获取数据信号，对获取到的数据信号进行处理，并将处理后的信号通过信号通道(channel)传输至控制器，从而实现数据信号的传输。在本实施例中，第一信号DQ即为主驱动模块100从逻辑电路获取的数据信号，第二信号VOH即为主驱动模块100处理后发送至信号通道的信号。通过主驱动模块100对第一信号DQ进行处理，本实施例的驱动电路可以获得具有更大驱动能力的第二信号VOH，从而有效提高了信号的传输速度。
示例性地，存储器可以为动态随机存取存储器(Dynamic Random Access Memory，DRAM)和静态随机存取存储器(Static Random-Access Memory，SRAM)，具体地，例如可以为低功率DDR4(LPDDR4)或LPDDR4X存储器的DRAM、SRAM、 晶闸管RAM(TRAM)、零电容器RAM(Z-RAM)、双晶体管RAM(TTRAM)MRAM等。
辅助驱动模块200与主驱动模块100的输出端连接，用于接收第一信号DQ，并根据第一信号DQ生成辅助驱动信号，辅助驱动信号用于缩短第二信号VOH的上升时间。
具体地，数据信号的读写是响应于时钟信号执行的，因此，若时钟信号的上升沿和/或下降沿到达时，待写入的数据信号未达到目标电平，则会导致数据读写错误。例如，若在当前时钟信号的边沿时刻对应的待写入数据为1，而在上一时钟信号的边沿时刻的写入数据为0，则需要在时钟信号相邻的两个边沿时刻之间，将第二信号VOH由低电平范围拉高至高电平范围，例如由0.1V拉高至1.1V，才能实现第二信号VOH的准确传输，若在当前时钟信号的边沿时刻到达时，第二信号VOH未达到高电平范围，则传输至信号通道的信号为低电平信号，即，未能将实际的第二信号VOH准确地传输至信号通道，从而导致了第二信号VOH的传输错误。
进一步地，存储器还需要实现更快地读写速度和数据传输速率，例如，LPDDR的数据传输速率为400Mbps(Million bits per second)，LPDDR2的数据传输速率为1600Mbps，LPDDR3的数据传输速率为2133Mbps，LPDDR4的数据传输速率为3200Mbps，而LPDDR4X的数据传输速率为4.266Gbps，明显地，随着存储器的不断进步，数据传输速率也在不断提升。为了实现数据的快速传输和读写，需要相应地缩短存储器中的时钟信号的周期，即，时钟信号相邻的两个边沿之间的时间间隔也会进一步缩短，若第二信号VOH的上升时间过长，会导致数据信号的时序裕度降低，从而限制了存储器的传输速度和读写速度。因此，需要使第二信号VOH的高低电平之间的切换速度进一步提升，以确保第二信号VOH的正确传输。
在本实施例中，驱动电路包括：主驱动模块100，用于接收第一信号DQ，并根据所述第一信号DQ生成第二信号VOH，所述第二信号VOH的驱动能力大于所述第一信号DQ的驱动能力；辅助驱动模块200，与所述主驱动模块100的输出端连接，用于接收所述第一信号DQ，并根据所述第一信号DQ生成辅助驱动信号，所述辅助驱动信号用于缩短所述第二信号VOH的上升时间。通过主驱动模块100实现了对第一信号DQ的驱动能力的提升，并通过辅助驱动模块200的配合，缩短了第二信号VOH的上升时间，提升了数据信号的时序裕度，从而可以实现更快的信号传输速度。
图2为另一实施例的驱动电路的结构示意图，参考图2，在本实施例中，主驱动模块100包括第一上拉晶体管MN1、第一下拉晶体管MNDN和预驱动单元110。
其中，第一上拉晶体管MN1和第一下拉晶体管MNDN共同用于生成第二信号VOH，第一上拉晶体管MN1的输出端和第一下拉晶体管MNDN的输出端相连接，以共同输出第二信号VOH，预驱动单元110分别与第一上拉晶体管MN1和第一下拉晶体管MNDN连接，预驱动单元110用于接收第一信号DQ，并根据第一信号DQ控制第一上拉晶体管MN1的通断和第二上拉晶体管MN2的通断。
具体地，第一上拉晶体管MN1用于将第二信号VOH的电压上拉至第一预设电平，第一预设电平属于高电平范围，高电平范围例如为大于1V，第一下拉晶体管MNDN用于将第二信号VOH的电压下拉至第二预设电平，第二预设电平属于低电平范围，低电平范围例如为小于0.2V。在预驱动单元110的控制下，第一上拉晶体管MN1和第一下拉晶体管MNDN具有不同的拉动能力，其中拉动能力较强的晶体管可以将第二信号VOH的电压拉动至相应的第一预设电平或第二预设电平，例如若第一上拉晶体管MN1的拉动能力较强，则第二信号VOH的电压会被上拉至第一预设电平。
预驱动单元110根据第一信号DQ分别生成第一控制信号和第二控制信号，并将第一控制信号传输至第一上拉晶体管MN1，将第二控制信号传输至第一下拉晶体管MNDN。
在一些示例中，第一上拉晶体管MN1和第一下拉晶体管MNDN的类型可以相同，其中，晶体管的类型包括N型和P型。当第一上拉晶体管MN1和第一下拉晶体管MNDN的类型相同时，第一上拉晶体管MN1和第一下拉晶体管MNDN同为高电平导通，或同为低电平导通。因此，可以采用使第一控制信号和第二控制信号的电平状态相反，例如使第一控制信号为高电平，且第二控制信号为低电平，即可实现对第一上拉晶体管MN1和第一下拉晶体管MNDN的控制，以使两个晶体管具有不同的拉动能力。进一步地，可以在预驱动单元110中设置一反相器，反相器的输入端与第一控制信号连接，以对第一控制信号进行反相，从而生成第二控制信号。
在另一些示例中，第一上拉晶体管MN1和第一下拉晶体管MNDN的类型也可以不相同，当第一上拉晶体管MN1和第一下拉晶体管MNDN的类型不相同时，第一上拉晶体管MN1和第一下拉晶体管MNDN中的一个高电平导通，且另一个低电平导通。因此，可以采用使第一控制信号和第二控制信号的电平状态相同，例如使第一控制信号和第二控制信号均为高电平，即可实现对第一上拉晶体管MN1和第一下拉晶体管MNDN的控制，以使两个晶体管具有不同的拉动能力，并可以简化控制信号的生成电路。
在其中一个实施例中，继续参考图2，第一上拉晶体管MN1和第一下拉晶体管MNDN均为N型晶体管。具体地，功耗是驱动电路设计过程中的重要参考因素，并可以参考以下公式进行估算：
Figure PCTCN2021076150-appb-000001
其中，C Load为负载电容，V DD为电源电压VDDQL，V swing为输出电压摆幅，P out为输出功率。由公式可知，当负载电容、电源电压VDDQL和输出电压摆幅中的任一个参数减小时，即可减小输出功率。在本实施例中，采用N型晶体管作为第一上拉晶体管MN1，由于N型晶体管自身的结构特性，N型晶体管具有比P型晶体管更好的负载电容特性，因此，采用N型晶体管可以有效地降低驱动电路的输出功耗。
与P型的第一上拉晶体管MN1相比，N型的第一上拉晶体管MN1可以传输低于电源电压VDDQL的信号。因此，与第一上拉晶体管MN1为P型晶体管的驱动电路相比，本实施例的驱动电路可以传输比第一上拉晶体管MN1为P型晶体管的驱动电路的输出电压摆幅更小的信号，例如，LPDDR4X的输出电压摆幅为0.366V，LPDDR4的输出电压摆幅为0.3V，因此，采用N型的第一上拉晶体管MN1的LPDDR4X可以比LPDDR4降低约20％的功耗。此外，与P型晶体管相比，使用N型晶体管作为第一上拉晶体管MN1可以有效地减小主驱动模块100的尺寸。再进一步地，可以使第一上拉晶体管MN1和第一下拉晶体管MNDN采用相同的N型晶体管，从而提高第一上拉晶体管MN1和第一下拉晶体管MNDN的对称特性，以进一步提升驱动电路的性能。
在其中一个实施例中，第一上拉晶体管MN1的漏极与电源电压VDDQL连接，第一上拉晶体管MN1的源极与第一下拉晶体管MNDN的漏极连接，第一下拉晶体管MNDN的源极与地电压GND连接；其中，第一上拉晶体管MN1的源极和第一下拉晶体管MNDN的漏极共同用于输出第二信号VOH。
具体地，在本实施例中，第一预设电平即电源电压VDDQL，第二预设电平即地电压GND。当第一控制信号为高电平，且第二控制信号为低电平时，第一上拉晶体管MN1导通，且第一下拉晶体管MNDN断开，第二信号VOH被拉高 至电源电压VDDQL。当第一控制信号为低电平，且第二控制信号为低电平时，第一上拉晶体管MN1断开，且第一下拉晶体管MNDN导通，第二信号VOH被拉低至地电压GND。进一步地，通过辅助驱动模块200的配合，本实施例可以缩短第二信号VOH由低电平向高电平切换时的上升时间，从而扩大信号的时序裕度，以提供一种可靠性更高、速率更快的输出信号。
在其中一个实施例中，继续参考图2，辅助驱动模块200包括第二上拉晶体管MN2和边缘增强单元210。
第二上拉晶体管MN2用于生成辅助驱动信号。其中，辅助驱动信号例如可以为一充电电流，即，辅助驱动模块200用于根据第一信号DQ生成一充电电流，充电电流用于加快第二信号VOH的充电速度，以缩短第二信号VOH的上升时间。其中，当第二信号VOH需要由低电平切换至高电平时，需要开启辅助驱动模块200，即由边缘增强单元210控制第二上拉晶体管MN2开启，以使第二上拉晶体管MN2输出充电电流至主驱动模块100充电电流可以加快主驱动模块100的输出端的充电速度，从而缩短第二信号VOH的上升时间。
具体地，第二上拉晶体管MN2为N型晶体管，第二上拉晶体管MN2的控制端与边缘增强单元210连接，第二上拉晶体管MN2的漏极与电源电压VDDQL连接，第二上拉晶体管MN2的源极用于输出辅助驱动信号。即，第二上拉晶体管MN2与第一上拉晶体管MN1均连接至电源电压VDDQL，因此，当第二上拉晶体管MN2开启时，会使主驱动模块100的输出端的电压迅速抬升至高电平，从而缩短了第二信号VOH的上升时间。与第一上拉晶体管MN1相似地，N型的第二上拉晶体管MN2可以传输低于电源电压VDDQL的信号，本实施例的驱动电路可以传输比第二上拉晶体管MN2为P型晶体管的驱动电路的输出电压摆幅更小的信号，例如，LPDDR4X的输出电压摆幅为0.366V，LPDDR4的输出电压摆幅为0.3V， 因此，LPDDR4X可以比LPDDR4降低约20％的功耗。此外，与P型晶体管相比，使用N型晶体管作为第二上拉晶体管MN2可以有效地减小辅助驱动模块200的尺寸。
边缘增强单元210与第二上拉晶体管MN2的控制端连接，用于接收第一信号DQ，并根据第一信号DQ生成边缘增强信号，边缘增强信号用于控制第二上拉晶体管MN2的通断。边缘增强信号作为使能信号控制第二上拉晶体管MN2，边缘增强信号包括高电平和低电平。即，当信号处于高电平阶段时，控制第二上拉晶体管MN2开启，以输出辅助驱动信号，从而加快第二信号VOH由低电平切换至高电平；当信号处于低电平阶段时，控制第二上拉晶体管MN2关闭，不输出辅助驱动信号。
在其中一个实施例中，边缘增强单元210包括脉冲生成组件211、周期时钟生成组件212和运算组件213。
具体地，脉冲生成组件211用于接收第一信号DQ，并根据第一信号DQ生成脉冲信号。周期时钟生成组件212用于生成时钟信号。运算组件213分别与脉冲生成组件211和周期时钟生成组件212连接，运算组件213用于根据脉冲信号和时钟信号生成边缘增强信号。时钟信号也可以来源于边缘增强单元210外部，周期时钟生成组件212可以不起作用或仅仅起到延时等作用。图3为一实施例的信号时序图，参考图3，时钟信号的周期是与第一信号DQ的数据更新的周期相匹配的，从而确保信号读写的时序准确性。
进一步地，脉冲生成组件211响应于第一信号DQ的上升沿，并生成脉冲信号；其中，时钟信号配置有预设时钟周期，脉冲信号的高电平的宽度小于或等于时钟周期的一半，例如如图3所示，脉冲信号的高电平的宽度等于时钟信号的高电平的宽度。可以理解的是，脉冲信号维持高电平状态对驱动电路的功耗影响 高于维持低电平状态对驱动电路的功耗影响，因此，在可以确保信号的准确传输的前提下，通过缩窄脉冲信号的高电平的宽度，可以实现更好的功耗性能。具体地，可以根据信号的时序裕度和功耗需求选择恰当的高电平的宽度，例如，脉冲信号的高电平的宽度可以为时钟周期的1/3、1/4等。进一步地，当脉冲生成组件211生成的脉冲信号的高电平宽度大于时钟周期的一半时，是无法基于脉冲信号实现对第二信号VOH的准确驱动的，可以理解的是，周期时钟生成组件212的稳定性优于脉冲生成组件211，因此，当脉冲信号的高电平宽度不满足要求时，运算组件213可以选择输出时钟信号，以确保信号的准确驱动。
图4为第二信号VOH的眼图测试结果的对比图，参考图4，左侧的两个测试图为采用现有技术的驱动电路的第二信号VOH的测试结果，由于左上测试图中箭头指向位置的第二信号VOH的提升速度不足，导致第二信号VOH的上升时间过长，进而导致噪声严重，即，左下的眼图测试结果的张开不足，信号的时序裕度较低。右侧的两个测试图为采用本实施例的驱动电路的第二信号VOH的测试结果，由于右上测试图中箭头指向位置的第二信号VOH的提升速度明显提高，使右下的眼图测试结果中的噪声降低，信号的时序裕度增大。
在其中一个实施例中，边缘增强信号的高电平的宽度小于或等于脉冲信号的高电平的宽度。继续参考图3，在图3所示的实施例中，边缘增强信号的高电平的宽度T2小于脉冲信号的高电平T1的宽度。边缘增强信号的上升沿比脉冲信号的上升沿延迟时间为T3，边缘增强信号的下降沿基本与脉冲信号的下降沿对齐(实际电路中可能会有几个逻辑门的延迟)。图5为另一实施例的信号时序图，在图5所示的实施例中，边缘增强信号的高电平的宽度T2相比图3中的边缘增强信号的高电平的宽度T2更宽，也即延迟时间T3是可调的。其中，运算组件213可以包括一多路选择器，多路选择器分别与脉冲生成组件211和周期 时钟生成组件212连接，并使多路选择器选择输出脉冲信号，即可使边缘增强信号的高电平的宽度等于脉冲信号的高电平的宽度或小于脉冲信号的高电平的宽度，同时可以控制边缘增强信号上升沿相较于脉冲信号的上升沿延迟一定时间，例如图3和图5中的延迟时间T3，同时还可以控制边缘增强信号的下降沿与脉冲信号的下降沿基本对齐。同时参考图2、图3、图4，边缘增强信号只在第二信号VOH快接近于高电压阈值的阶段才产生。受限于图2中使用的NMOS管驱动结构，在第二信号VOH上升到接近高电压阈值阶段时，MN1管对第二信号VOH的上拉作用变弱，导致第二信号VOH在高电压阈值阶段上升速度缓慢，此时边缘增强信号将MN2管打开，MN1管和MN2管共同对第二信号VOH进行上拉，可以加快第二信号VOH的上升速度。实际上，MN1管对第二信号VOH的上拉作用随着第二信号VOH的上升而变的越来越弱，如果边缘增强信号使得MN2管打开的更早一些，第二信号VOH可以更快的上升超过高电压阈值，但这同时也消耗了更多的功耗，因此，边缘增强单元产生的边缘增强信号的脉冲上升沿到来的时刻应该折衷考虑第二信号VOH的上升速度和所消耗的功耗。
在其中一个实施例中，边缘增强信号包括多个增强脉冲，脉冲信号包括多个初始脉冲，增强脉冲与初始脉冲一一对应，增强脉冲的下降沿与对应的初始脉冲的下降沿对齐。具体地，在图3所示的实施例中，边缘增强信号包括3个增强脉冲，脉冲信号包括3个初始脉冲，且第一个增强脉冲与第一个初始脉冲相对应，第二个增强脉冲与第二个初始脉冲相对应，第三个增强脉冲与第三个初始脉冲相对应，通过使增强脉冲的下降沿与对应的初始脉冲的下降沿对齐，可以提高边缘增强信号的时序准确性。
在其中一个实施例中，增强脉冲的上升沿比对应的初始脉冲的上升沿延迟预设时长，该预设时长即图3实施例中所示的时间T3。在本实施例中，通过对 边缘增强信号进行延迟，可以控制辅助驱动信号的生成时间，从而使辅助驱动信号的时序与第二信号VOH的时序相匹配，以实现更好的驱动效果。
图6为一实施例的第二信号VOH的电压-时间关系图，图6中示出了第二信号VOH由低电平向高电平转换过程中的电压变化情况，图6中实线示出了现有技术的驱动电路输出的第二信号VOH的曲线，图6中虚线示出了采用本实施例的驱动电路输出的第二信号VOH的曲线。参考图6，在第二信号VOH由低电平向高电平转换的初期，电压的提升速度较快，并随着第二信号VOH的电压的不断升高，电压的提升速度逐渐减缓。可以理解的是，若辅助驱动信号在第二信号VOH的电压提升速度较快的时间段输出，对第二信号VOH的电压提升速度的改善作用较小，因此，本实施例可以使辅助驱动信号在恰当的时刻到达第二信号VOH的输出端，从而以较低的能耗实现较好的改善第二信号VOH的上升时间的效果。
进一步地，以辅助驱动信号为充电电流为例，充电电流的生成时刻等于或晚于第一时刻，其中，第一时刻例如可以为第二信号VOH的电压上升至低电平阈值的时刻。第一时刻即图6中的t1时刻，通过使充电电流的生成时刻等于或晚于第一时刻可以降低驱动电路的功耗，再进一步地，充电电流的生成时刻例如可以为t2时刻、t3时刻等，具体可以根据第一上拉晶体管MN1和第一下拉晶体管MNDN的驱动能力选择恰当的生成时刻，图6中示意了从t3时刻辅助性的充电电流产生。
图7为再一实施例的驱动电路的结构示意图，参考图7，在本实施例中，驱动电路包括第二上拉晶体管MN2、周期时钟生成组件212和边缘增强单元210。
第二上拉晶体管MN2用于生成辅助驱动信号，并输出辅助驱动信号至主驱动模块100，辅助驱动信号用于缩短主驱动模块100的输出信号的上升时间。周期时钟生成组件212用于生成一占空比为50％的时钟信号。边缘增强单元210分 别与周期时钟生成组件212和第二上拉晶体管MN2的控制端连接，边缘增强单元210用于接收时钟信号和外部输入的第一信号DQ，并根据时钟信号和第一信号DQ生成边缘增强信号，边缘增强信号用于控制第二上拉晶体管MN2的通断。可以理解的是，在双倍速率存储器中，时钟信号的上升沿和下降沿都需要用于数据的读写和传输，而制备工艺、温度等参数的变化会导致时钟信号的占空比降低，从而导致信号抖动，因此，使时钟信号的占空比为50％可以避免相应的信号抖动，从而提高时钟信号的可靠性。
在其中一个实施例中，周期时钟生成组件212包括时钟信号生成电路2121和占空比调制电路2122。时钟信号生成电路2121用于生成配置有预设时钟周期的时钟信号；占空比调制电路2122与时钟信号生成电路2121连接，用于对时钟信号进行调制以使时钟信号的占空比为50％。
进一步地，图8为一实施例的占空比调制电路2122的结构示意图，参考图8，在本实施例中，占空比调制电路2122包括相位转换器2123和交叉耦合锁存器2124。相位转换器2123与时钟信号生成电路2121连接，用于接收时钟信号，并对时钟信号进行相位转换以生成转换信号，转换信号与时钟信号之间的相位差为180°。交叉耦合锁存器2124与相位转换器2123连接，用于接收时钟信号和转换信号，并根据时钟信号和转换信号进行占空比调制，以使时钟信号的占空比为50％。示例性地，交叉耦合锁存器2124包括两个反向并联的反相器。在本实施例中，通过相配合的相位转换器2123和交叉耦合锁存器2124，可以以较简单的电路结构实现对时钟信号的占空比的调制，从而改善时钟信号的抖动现象，进而获得了更宽的时序裕度。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特 征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请实施例构思的前提下，还可以做出若干变形和改进，这些都属于本申请实施例的保护范围。因此，本申请实施例专利的保护范围应以所附权利要求为准。

Claims (17)

  1. 一种驱动电路，包括：
    主驱动模块，用于接收第一信号，并根据所述第一信号生成第二信号，所述第二信号的驱动能力大于所述第一信号的驱动能力；
    辅助驱动模块，与所述主驱动模块的输出端连接，用于接收所述第一信号，并根据所述第一信号生成辅助驱动信号，所述辅助驱动信号用于缩短所述第二信号的上升时间。
  2. 根据权利要求1所述的驱动电路，其中，所述主驱动模块包括：
    第一上拉晶体管；
    第一下拉晶体管；
    预驱动单元，分别与所述第一上拉晶体管和所述第一下拉晶体管连接，所述预驱动单元用于接收所述第一信号，并根据所述第一信号控制所述第一上拉晶体管的通断和所述第二上拉晶体管的通断；
    其中，第一上拉晶体管和第一下拉晶体管共同用于生成所述第二信号，所述第一上拉晶体管的输出端和所述第一下拉晶体管的输出端相连接，以共同输出所述第二信号。
  3. 根据权利要求2所述的驱动电路，其中，所述第一上拉晶体管和所述第一下拉晶体管均为N型晶体管。
  4. 根据权利要求3所述的驱动电路，其中，所述第一上拉晶体管的漏极与电源电压连接，所述第一上拉晶体管的源极与所述第一下拉晶体管的漏极连接，所述第一下拉晶体管的源极与地电压连接；
    其中，所述第一上拉晶体管的源极和所述第一下拉晶体管的漏极共同用于 输出所述第二信号。
  5. 根据权利要求1所述的驱动电路，其中，所述辅助驱动模块包括：
    第二上拉晶体管，用于生成所述辅助驱动信号；
    边缘增强单元，与所述第二上拉晶体管的控制端连接，用于接收所述第一信号，并根据所述第一信号生成边缘增强信号，所述边缘增强信号用于控制所述第二上拉晶体管的通断。
  6. 根据权利要求5所述的驱动电路，其中，所述第二上拉晶体管为N型晶体管。
  7. 根据权利要求6所述的驱动电路，其中，所述第二上拉晶体管的控制端与所述边缘增强单元连接，所述第二上拉晶体管的漏极与电源电压连接，所述第二上拉晶体管的源极用于输出所述辅助驱动信号。
  8. 根据权利要求5所述的驱动电路，其中，所述边缘增强单元包括：
    脉冲生成组件，用于接收所述第一信号，并根据所述第一信号生成脉冲信号；
    周期时钟生成组件，用于生成时钟信号；
    运算组件，分别与所述脉冲生成组件和所述周期时钟生成组件连接，所述运算组件用于根据所述脉冲信号和所述时钟信号生成所述边缘增强信号。
  9. 根据权利要求8所述的驱动电路，其中，所述脉冲生成组件响应于所述第一信号的上升沿，并生成所述脉冲信号；
    其中，所述时钟信号配置有预设时钟周期，所述脉冲信号的高电平的宽度小于或等于所述时钟周期的一半。
  10. 根据权利要求8所述的驱动电路，其中，所述边缘增强信号的高电平的宽度小于或等于所述脉冲信号的高电平的宽度。
  11. 根据权利要求8所述的驱动电路，其中，所述边缘增强信号包括多个增 强脉冲，所述脉冲信号包括多个初始脉冲，所述增强脉冲与所述初始脉冲一一对应，所述增强脉冲的上升沿比对应的所述初始脉冲的上升沿延迟预设时长。
  12. 根据权利要求8所述的驱动电路，其中，所述边缘增强信号包括多个增强脉冲，所述脉冲信号包括多个初始脉冲，所述增强脉冲与所述初始脉冲一一对应，所述增强脉冲的下降沿与对应的所述初始脉冲的下降沿对齐。
  13. 根据权利要求1所述的驱动电路，其中，所述辅助驱动模块用于根据所述第一信号生成一充电电流，所述充电电流用于加快所述第二信号的充电速度，以缩短所述第二信号的上升时间。
  14. 根据权利要求13所述的驱动电路，其中，所述充电电流的生成时刻等于或晚于第一时刻；
    其中，所述第一时刻为所述第二信号的电压上升至低电平阈值的时刻。
  15. 一种驱动电路，包括：
    第二上拉晶体管，用于生成辅助驱动信号，并输出所述辅助驱动信号至主驱动模块，所述辅助驱动信号用于缩短所述主驱动模块的输出信号的上升时间；
    周期时钟生成组件，用于生成一占空比为50％的时钟信号；
    边缘增强单元，分别与所述周期时钟生成组件和所述第二上拉晶体管的控制端连接，所述边缘增强单元用于接收所述时钟信号和外部输入的第一信号，并根据所述时钟信号和所述第一信号生成边缘增强信号，所述边缘增强信号用于控制所述第二上拉晶体管的通断。
  16. 根据权利要求15所述的驱动电路，其中，所述周期时钟生成组件包括：
    时钟信号生成电路，用于生成配置有预设时钟周期的时钟信号；
    占空比调制电路，与所述时钟信号生成电路连接，用于对所述时钟信号进行调制以使所述时钟信号的占空比为50％。
  17. 根据权利要求15所述的驱动电路，其中，所述占空比调制电路包括：
    相位转换器，与所述时钟信号生成电路连接，用于接收所述时钟信号，并对所述时钟信号进行相位转换以生成转换信号，所述转换信号与所述时钟信号之间的相位差为180°；
    交叉耦合锁存器，与所述相位转换器连接，用于接收所述时钟信号和所述转换信号，并根据所述时钟信号和所述转换信号进行占空比调制，以使所述时钟信号的占空比为50％。
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CN106160853A (zh) * 2015-04-01 2016-11-23 索尔思光电（成都）有限公司 一种多功能ld驱动电路、模块及方法

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