WO2022022595A1 - 一种显示模组、电子设备 - Google Patents

一种显示模组、电子设备 Download PDF

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Publication number
WO2022022595A1
WO2022022595A1 PCT/CN2021/109048 CN2021109048W WO2022022595A1 WO 2022022595 A1 WO2022022595 A1 WO 2022022595A1 CN 2021109048 W CN2021109048 W CN 2021109048W WO 2022022595 A1 WO2022022595 A1 WO 2022022595A1
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WO
WIPO (PCT)
Prior art keywords
chip
light
pixel
circuit
circuit board
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Application number
PCT/CN2021/109048
Other languages
English (en)
French (fr)
Inventor
龙浩晖
曹轩
叶润清
方建平
陈晓晨
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21849920.0A priority Critical patent/EP4181199A4/en
Priority to US18/007,259 priority patent/US11955080B2/en
Publication of WO2022022595A1 publication Critical patent/WO2022022595A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/129—Chiplets

Definitions

  • the present application relates to the field of display technology, and in particular, to a display module and an electronic device.
  • display modules that can realize self-illumination, such as display modules using active matrix organic light emitting diode (AMOLED) technology, are provided with organic light emitting diodes (organic light emitting diodes) in their sub pixels.
  • organic light emitting diodes organic light emitting diodes
  • OLED organic light emitting diode
  • the AMOLED display module is provided with a thin film transistor (TFT) backplane 10 and a printed circuit board (PCB) for carrying a control chip 11 .
  • the TFT backplane 10 is provided with a driving circuit mainly composed of TFTs, and the driving circuit is used to drive the OLED device located above the TFT backplane to emit light.
  • TFT backplane 10 and PCB due to the existence of the above-mentioned TFT backplane 10 and PCB, it is difficult to further reduce the thickness and weight of the self-luminous display module, which is not conducive to the thin and light design of the display module.
  • the present application provides a display module and an electronic device, which are used to improve the problems of large thickness and weight of the self-luminous display module.
  • a display module in one aspect of the present application, includes a circuit board, an integrated chip and a pixel chip set.
  • the integrated chip is electrically connected to the circuit board.
  • the integrated chip includes a first chip body and a plurality of display pixel driving circuits integrated in the first chip body.
  • the pixel chip set includes a plurality of light-emitting chips.
  • at least one pixel chip set is disposed on one side surface of the integrated chip away from the circuit board.
  • a light-emitting chip arranged on the integrated chip is electrically connected to a display pixel driving circuit in the integrated chip, and the display pixel driving circuit is used for driving the light-emitting chip to emit light.
  • the display pixel driving circuit for driving the light-emitting chip to emit light can be integrated in the first chip body in the above-mentioned integrated chip, the display module provided by the embodiment of the present application is relatively different from the current AMOLED display module. , no need to make a TFT backplane, which can effectively reduce the weight of the display module and reduce the thickness of the display module.
  • the display module further includes a circuit substrate.
  • the circuit substrate is electrically connected with the circuit board, and the circuit substrate is integrated with a plurality of display pixel driving circuits.
  • the vertical projection area of the circuit substrate on the circuit board is smaller than the vertical projection area of the integrated chip on the circuit board.
  • the display module further includes two or more of the above-mentioned pixel chip sets.
  • a pixel chip set is arranged on a side surface of a circuit substrate away from the circuit board.
  • a light-emitting chip disposed on the circuit substrate is electrically connected to a display pixel circuit in the circuit substrate.
  • integrating the display pixel driving circuit for driving the light-emitting chip to emit light into the circuit substrate can effectively reduce the weight of the display module and reduce the thickness of the display module.
  • the circuit board includes a main viewing area and a peripheral area located around the main viewing area.
  • the integrated chip is arranged in the main viewing area, and the circuit substrate is arranged in the peripheral area.
  • the peripheral area is located at the edge of the circuit board.
  • the size of the integrated chip is larger and the contact area with the circuit board is larger, while the size of the circuit substrate is smaller and the contact area with the circuit board is smaller.
  • the above-mentioned peripheral area is likely to be slightly deformed under the action of external force, for example, in the process of being collided.
  • the circuit substrate with smaller size can be arranged in the peripheral area, and the integrated chip with larger size can be arranged in the main viewing area that is not easily deformed, so that when the display module is under the action of external force, the peripheral area collides with , it is not easy to break the circuit substrate, which is beneficial to improve the reliability of the product.
  • the display module further includes a rotating shaft, and the rotating shaft is disposed on a side of the circuit board away from the integrated chip.
  • the circuit board is a flexible circuit board.
  • the circuit board includes a first main viewing area, a second main viewing area, a first peripheral area, a second peripheral area and a bending area. Wherein, the bending area is located between the first main viewing area and the second main viewing area, and the vertical projection of the rotating shaft on the circuit board is located in the bending area.
  • the first peripheral area is arranged around the first main viewing area, and the second peripheral area is arranged around the second main viewing area.
  • the integrated chip is arranged in the first main viewing area and the second main viewing area; a plurality of circuit substrates are arranged in the bending area, the first peripheral area and the second peripheral area. It can be seen from the above that the size of the integrated chip is larger, and the contact area with the circuit board is larger, while the size of the circuit substrate is smaller, and the contact area with the circuit board is smaller.
  • the first peripheral area and the second peripheral area of the circuit board are located at the edge of the circuit board. In this case, during transportation or use of the display module, the first peripheral area and the second peripheral area are easily deformed slightly under the action of an external force, such as during a collision.
  • the circuit substrate with smaller size can be arranged in the first peripheral area and the second peripheral area, and the integrated chip with larger size can be arranged in the main viewing area that is not easily deformed, so that when the display module is under the action of external force , so that when the first peripheral area and the second peripheral area collide, the circuit substrate is not easily broken, which is beneficial to improve the reliability of the product.
  • the circuit board includes a plurality of metal wires, and the plurality of metal wires are arranged in the bending area.
  • the metal wiring is bent, and two ends of the metal wiring are respectively connected with the two circuit substrates.
  • the metal traces have certain tensile properties, they can be deformed with the bending of the bending area, reducing the stress generated at the position of the circuit substrate due to the deformation of the bending area, and further reducing the The purpose of breaking the circuit substrate.
  • the plurality of circuit substrates in the bending region are arranged in a matrix form.
  • the plurality of metal wires include a plurality of first metal wires and a plurality of second metal wires.
  • the first metal traces are connected to two adjacent circuit substrates along a first direction
  • the second metal traces are connected to two adjacent circuit substrates along a second direction.
  • the first direction is perpendicular to the second direction.
  • the plurality of light-emitting chips in the same pixel chip group include a first light-emitting chip, a second light-emitting chip, and a third light-emitting chip.
  • the first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are respectively used for emitting light of three primary colors.
  • the first light-emitting chip, the second light-emitting chip, and the third light-emitting chip in the same pixel chip group can constitute one pixel.
  • the purpose of controlling the pixel gray scale of the image when the display module performs color display can be achieved.
  • the integrated chip further includes a plurality of fingerprint pixel acquisition circuits integrated in the first chip body.
  • the pixel chipset also includes a fingerprint capture chip.
  • a fingerprint collection chip arranged on the integrated chip is electrically connected with a fingerprint pixel collection circuit in the integrated chip, and the fingerprint pixel collection circuit is used for driving the fingerprint collection chip to perform fingerprint collection.
  • a plurality of fingerprint acquisition chips in different pixel chipsets constitute a fingerprint acquisition device. In this way, it is not necessary to separately set the fingerprint collector on the circuit board, but the collecting pixels of the fingerprint collector are integrated into each pixel chipset, which is beneficial to improve the integration degree of the display module.
  • the integrated chip further includes a plurality of fingerprint pixel acquisition circuits integrated in the first chip body; the circuit substrate further integrates a fingerprint pixel acquisition circuit.
  • the pixel chipset also includes a fingerprint capture chip.
  • a fingerprint collection chip arranged on the integrated chip is electrically connected with a fingerprint pixel collection circuit in the integrated chip, and the fingerprint collection chip arranged on the circuit substrate is electrically connected with the fingerprint pixel collection circuit in the circuit substrate.
  • the fingerprint pixel acquisition circuit is used to drive the fingerprint acquisition chip to perform fingerprint acquisition.
  • a plurality of fingerprint acquisition chips in different pixel chipsets constitute a fingerprint acquisition device.
  • both the integrated chip and the pixel chipset above the circuit substrate are provided with the acquisition pixels of the fingerprint collector, which is beneficial to improve the precision of fingerprint acquisition.
  • the technical effects of the fingerprint collection chip and the fingerprint pixel collection circuit are the same as described above, and will not be repeated here.
  • the integrated chip further includes a plurality of light-emitting pixel driving circuits and a plurality of light-receiving pixel driving circuits integrated in the first chip body.
  • the pixel chipset further includes a light emitting chip and a light receiving chip.
  • a light emitting chip disposed on the integrated chip is electrically connected with a light emitting pixel driving circuit in the integrated chip, and a light receiving chip is electrically connected with a light receiving pixel driving circuit in the integrated chip.
  • the light emitting pixel driving circuit is used for driving the light emitting chip to emit light.
  • the light-receiving pixel driving circuit is used for driving the light-receiving chip to receive light.
  • a plurality of light emitting chips in different pixel chip groups constitute a light transmitter
  • a plurality of light receiving chips in different pixel chip groups constitute a light receiver. Therefore, it is not necessary to separately arrange the light emitter on the circuit board, but the pixels of the light emitter are integrated into each pixel chipset, thereby helping to improve the integration degree of the display module. Therefore, it is not necessary to separately arrange the light receiver on the circuit board, but the pixels of the light receiver are integrated into each pixel chipset, thereby helping to improve the integration degree of the display module.
  • the integrated chip further includes a plurality of light-emitting pixel driving circuits and a plurality of light-receiving pixel driving circuits integrated in the first chip body.
  • the circuit substrate also integrates a light-emitting pixel driving circuit and a light-receiving pixel driving circuit.
  • the pixel chipset further includes a light emitting chip and a light receiving chip. A light emitting chip disposed on the integrated chip is electrically connected with a light emitting pixel driving circuit in the integrated chip, and a light receiving chip is electrically connected with a light receiving pixel driving circuit in the integrated chip.
  • a light emitting chip disposed on the circuit substrate is electrically connected with a light emitting pixel driving circuit in the circuit substrate, and a light receiving chip is electrically connected with a light receiving pixel driving circuit in the circuit substrate.
  • the light-emitting pixel driving circuit is used for driving the light-emitting chip to emit light;
  • the light-receiving pixel driving circuit is used for driving the light-receiving chip to receive light.
  • a plurality of light emitting chips in different pixel chip groups constitute a light transmitter, and a plurality of light receiving chips in different pixel chip groups constitute a light receiver.
  • both the integrated chip and the pixel chipset above the circuit substrate are provided with the pixels of the light emitter and the light receiver, which is beneficial to improve the accuracy of fingerprint collection.
  • the technical effects of the light emitting chip, the light receiving chip, and the light emitting pixel driving circuit and the light receiving pixel driving circuit are the same as those described above, and will not be repeated here.
  • the first chip body includes a system-on-chip, a power management unit, a central processing unit, an image processor, or a memory chip.
  • the types of the first chip bodies in different integrated chips can be different, so that more chips can be integrated.
  • the integrated chip further includes a second chip body.
  • the second chip body and the first chip body are stacked and disposed, and the second chip body is located on the side of the first chip body close to the circuit board.
  • the second chip body includes a system-on-chip, a power management unit, a central processing unit or an image processor; the first chip body includes a memory chip.
  • the circuit board is a flexible circuit board.
  • the circuit board includes a first portion and a second portion connected to the first portion.
  • the vertical projection of the pixel chip set on the circuit board is located on the first part, and the second part is bent on the side of the first part away from the pixel chip set.
  • the display module further includes additional electronic components, which are arranged on the surface of the second part close to the first part and are electrically connected with the circuit board. In this way, more electronic components can be integrated in the display module, and the integration degree of the display module can be improved.
  • the display module further includes an adapter board.
  • the adapter board is electrically connected with the circuit board, and at least two integrated chips are arranged on the side surface of the adapter board away from the circuit board, and are electrically connected through the adapter board.
  • a circuit for realizing the mutual communication between the at least two integrated chips can be formed in the adapter board. In this way, there is no need to fabricate a circuit structure interconnecting all integrated circuits in the circuit board, which can save space for circuit layout in the circuit board.
  • the circuit substrate further includes a substrate body and a redistribution layer which are separated from the circuit board in sequence, the transistors of the display pixel driving circuit are integrated in the substrate body, and the wires in the display pixel driving circuit are integrated in the redistribution layer.
  • the material of the substrate body includes single crystal silicon.
  • the above-mentioned CMOS process can be used to form the transistors for forming the display pixel circuit in the silicon substrate.
  • the above-mentioned redistribution layer is formed on the side of the substrate body on which the transistors are formed away from the circuit board.
  • the transistors in the substrate body are interconnected according to design requirements through the metal wires in the redistribution layer, so as to form the above display pixel driving circuit.
  • the display module further includes an encapsulation layer, and the encapsulation layer is located on the side of the pixel chip set away from the circuit board and covers the integrated chip and the pixel chip set.
  • the encapsulation layer is used to protect the integrated chip and the pixel chip set to prevent water and oxygen from eroding the integrated chip and the pixel chip.
  • the display module further includes a cover plate, the cover plate covers a side surface of the encapsulation layer away from the circuit board, and is connected with the encapsulation layer to protect the encapsulation layer.
  • the display module further includes a heat dissipation layer, and the heat dissipation layer covers a side surface of the circuit board away from the pixel chipset and is connected to the circuit board.
  • the heat dissipation layer can transfer the heat generated by the display module and the heat generated by the battery to other components, such as the casing of the display module.
  • the heat inside the display module can be transferred to the outside of the display module, thereby playing the role of heat dissipation.
  • Another aspect of the present application provides an electronic device including a battery and any one of the above-mentioned display modules.
  • This battery is located on the side of the board away from the pixel chipset. The battery is used to power the display module.
  • the above-mentioned electronic device has the same technical effect as the display module provided by the above-mentioned embodiment, which will not be repeated here.
  • a display module including a circuit board, a circuit substrate, and a pixel chip set.
  • the circuit substrate is electrically connected with the circuit board, and the circuit substrate is integrated with a plurality of display pixel driving circuits.
  • the pixel chip set includes a plurality of light-emitting chips.
  • a pixel chip set is arranged on a side surface of a circuit substrate away from the circuit board; a light-emitting chip arranged on the circuit substrate is electrically connected to a display pixel circuit in the circuit substrate, and the display pixel driving circuit is used to drive the light-emitting chip glow.
  • the display module has the same technical effect as the display module provided by the foregoing embodiments, and details are not described herein again.
  • the display module further includes a rotating shaft, and the rotating shaft is disposed on a side of the circuit board away from the circuit substrate.
  • the circuit board is a flexible circuit board.
  • the circuit board includes a first area, a second area, and a bending area between the first area and the second area.
  • the vertical projection of the rotating shaft on the flexible circuit board is located in the bending area.
  • the circuit board includes a plurality of metal wirings, and the plurality of metal wirings are arranged in the bending area; the metal wirings are bent, and two ends of the metal wirings are respectively connected with the two circuit substrates.
  • the technical effect of the metal wiring is the same as described above, and will not be repeated here.
  • the plurality of circuit substrates in the bending area are arranged in a matrix form.
  • the plurality of metal wires include a plurality of first metal wires and a plurality of second metal wires.
  • the first metal traces are connected to two adjacent circuit substrates along a first direction
  • the second metal traces are connected to two adjacent circuit substrates along a second direction; wherein the first direction is connected to the second circuit substrates.
  • Orientation is vertical.
  • the plurality of light-emitting chips in the same pixel chip group include a first light-emitting chip, a second light-emitting chip, and a third light-emitting chip.
  • the first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are respectively used for emitting light of three primary colors.
  • the technical effects of the first light-emitting chip, the second light-emitting chip, and the third light-emitting chip are the same as described above, and will not be repeated here.
  • the circuit substrate further integrates a fingerprint pixel acquisition circuit.
  • the pixel chipset also includes a fingerprint capture chip.
  • a fingerprint collection chip arranged on the circuit substrate is electrically connected with a fingerprint pixel collection circuit in the circuit substrate.
  • the fingerprint pixel acquisition circuit is used to drive the fingerprint acquisition chip to perform fingerprint acquisition.
  • a plurality of fingerprint acquisition chips in different pixel chipsets constitute a fingerprint acquisition device. The technical effects of the fingerprint collection chip and the fingerprint pixel collection circuit are the same as described above, and will not be repeated here.
  • the circuit substrate further integrates a light-emitting pixel driving circuit and a light-receiving pixel driving circuit.
  • the pixel chipset further includes a light emitting chip and a light receiving chip.
  • a light emitting chip disposed on the circuit substrate is electrically connected with a light emitting pixel driving circuit in the circuit substrate, and a light receiving chip is electrically connected with a light receiving pixel driving circuit in the circuit substrate.
  • the light-emitting pixel driving circuit is used for driving the light-emitting chip to emit light; the light-receiving pixel driving circuit is used for driving the light-receiving chip to receive light.
  • a plurality of light emitting chips in different pixel chip groups constitute a light transmitter
  • a plurality of light receiving chips in different pixel chip groups constitute a light receiver.
  • the technical effects of the light-emitting pixel driving circuit and the light-receiving pixel driving circuit, as well as the light-emitting chip and the light-receiving chip are the same as those described above, and will not be repeated here.
  • the circuit substrate further includes a substrate body and a redistribution layer which are separated from the circuit board in sequence, the transistors of the display pixel driving circuit are integrated in the substrate body, and the wires in the display pixel driving circuit are integrated in the redistribution layer.
  • the material of the substrate body includes single crystal silicon.
  • the circuit board is a flexible circuit board.
  • the circuit board includes a first part and a second part connected with the first part; a plurality of circuit substrates are arranged on the first part. The second portion is bent at a side of the first portion away from the circuit substrate.
  • the display module further includes additional electronic components, which are arranged on the surface of the second part close to the first part and are electrically connected with the circuit board. The technical effects of the first part, the second part and the additional electronic components of the circuit board are the same as described above, and will not be repeated here.
  • Another aspect of the present application provides an electronic device including a battery and any one of the above-mentioned display modules.
  • This battery is located on the side of the board away from the pixel chipset. The battery is used to power the display module.
  • the above-mentioned electronic device has the same technical effect as the display module provided by the above-mentioned embodiment, which will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an AMOLED electronic device provided by the prior art
  • FIG. 2 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 3A is a schematic structural diagram of the display module in FIG. 2;
  • FIG. 3B is a schematic structural diagram of the integrated chip in FIG. 3A;
  • FIG. 4 is a schematic structural diagram of another display module provided by an embodiment of the present application.
  • 5A is a schematic structural diagram of a DCU provided by an embodiment of the present application.
  • FIG. 5B is another schematic structural diagram of a DCU provided by an embodiment of the present application.
  • FIG. 6A is a schematic structural diagram of a PU provided by an embodiment of the present application.
  • FIG. 6B is a schematic structural diagram of a DCU and a PU provided by an embodiment of the present application.
  • FIG. 6C is another schematic structural diagram of a PU provided by an embodiment of the present application.
  • FIG. 7A is a schematic structural diagram of an integrated chip provided by an embodiment of the present application.
  • FIG. 7B is another schematic structural diagram of a DCU provided by an embodiment of the present application.
  • FIG. 8A is a schematic structural diagram of a circuit substrate provided by an embodiment of the present application.
  • FIG. 8B is another schematic structural diagram of a PU provided by an embodiment of the present application.
  • 9A is a schematic structural diagram of an integrated chip provided by an embodiment of the present application.
  • FIG. 9B is another schematic structural diagram of a DCU provided by an embodiment of the present application.
  • FIG. 10A is a schematic structural diagram of a circuit substrate provided by an embodiment of the present application.
  • FIG. 10B is a schematic structural diagram of a wafer according to an embodiment of the present application.
  • FIG. 10C is a schematic diagram of a partial structure of the wafer shown in FIG. 10B ;
  • FIG. 10D is a schematic structural diagram of another wafer according to an embodiment of the present application.
  • FIG. 10E is another schematic structural diagram of a PU provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of an electronic device according to an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of a foldable display module provided by an embodiment of the application.
  • FIG. 13A is a schematic diagram of a region division of the circuit board in FIG. 12;
  • FIG. 13B is a schematic diagram of the bending structure of the circuit board in FIG. 12;
  • FIG. 14A is a schematic structural diagram of a display module provided by an embodiment of the present application.
  • 14B is a schematic diagram of a binding process of a PU and a circuit board provided by an embodiment of the present application;
  • 14C is a schematic diagram of a binding process of a DCU and a circuit board provided by an embodiment of the present application;
  • 14D is a schematic diagram of another binding process of a DCU and a circuit board provided by an embodiment of the present application.
  • 15A is a schematic structural diagram of another display module provided by an embodiment of the present application.
  • 15B is a schematic structural diagram of another display module provided by an embodiment of the present application.
  • 16A is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • 16B is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • 17 is a schematic structural diagram of another electronic device provided by an embodiment of the application.
  • 18A is a schematic diagram of area division of a circuit board provided by an embodiment of the present application.
  • FIG. 18B is a schematic structural diagram of a display module formed by using the circuit board shown in FIG. 18A;
  • 19 is a schematic structural diagram of another display screen provided by an embodiment of the application.
  • 20 is a schematic structural diagram of another display screen provided by an embodiment of the application.
  • FIG. 21 is a schematic diagram of area division provided by an embodiment of the present application.
  • 22 is a schematic structural diagram of another display module provided by an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.
  • 10-TFT backplane 11-control chip; 02-electronic equipment; 01-display module; 13-battery; 14-circuit board; 20-integrated chip; 201-first chip body; 30-circuit substrate; 40 - Pixel chipset; 202 - Second chip body; 401 - Light-emitting chip; 401a - First light-emitting chip; 401b - Second light-emitting chip; 401c - Third light-emitting chip; 100 - Display pixel drive circuit; 301 - Substrate body ; 101-fingerprint pixel acquisition circuit; 402-fingerprint acquisition chip; 102-light emitting pixel drive circuit; 103-light receiving pixel drive circuit; 403-light emitting chip; 404-light receiving chip; 200-wafer; 60-welding 51-light emitter; 52-light receiver; 15-rotating shaft; 140a-first main viewing area; 140b-second main viewing area; 141a-first peripheral area; 141b-second peripheral area
  • first”, second, etc. are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implying the number of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • directional terms such as “left” and “right” may include, but are not limited to, definitions relative to the schematic placement of components in the accompanying drawings. It should be understood that these directional terms may be relative concepts, They are used for relative description and clarification, which may vary accordingly depending on the orientation in which the components are placed in the drawings.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • An embodiment of the present application provides an electronic device, which may include a mobile phone (mobile phone), a tablet computer (pad), a TV, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (virtual reality, VR) ) terminal equipment, augmented reality (AR) terminal equipment and other electronic products with display functions.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • the above-mentioned electronic device 02 is a mobile phone as shown in FIG. 2 as an example for description.
  • the electronic device 02 may include a display module 01 for displaying images, and a battery 13 located on the back of the display module 01 , and the battery 13 is used to supply power to the display module 01 .
  • the structure of the display module 01 will be described in detail below through different examples.
  • the display module 01 in the electronic device 02 may include a circuit board 14 .
  • the circuit board 14 may have a first surface A1 and a second surface A2 disposed opposite to each other.
  • the above-mentioned display module 01 may further include an integrated chip 20 and a circuit substrate 30 which are disposed on the first surface A1 of the circuit board 14 and are electrically connected to the circuit board 14.
  • the display module 01 is described by taking as an example that the display module 01 includes two or more (hereinafter referred to as multiple) integrated chips 20 and multiple circuit substrates 30 .
  • the integrated chip 20 may include a first chiplet 201 .
  • the cross section of the first chip body 201 (parallel to the first surface A1 ) may be a rectangle, and the dimension L of any side of the rectangle (hereinafter referred to as simply unilateral dimension) can be in the order of millimeters.
  • the above-mentioned first chip body 201 may be a system on a chip (SoC), a power management unit (PMU), a graphics processor (graphics processing unit, GPU), or a central processing unit (central processing unit). processing unit, CPU).
  • SoC system on a chip
  • PMU power management unit
  • GPU graphics processor
  • central processing unit central processing unit
  • processing unit, CPU central processing unit
  • the above-mentioned first chip body 201 may be a memory chip, for example, a universal flash storage (UFS) or a double data rate (DDR) memory.
  • UFS universal flash storage
  • DDR double data rate
  • the first chip bodies 201 in different integrated chips 20 may be different.
  • the above-mentioned first chip body 201 may be a bare chip (die), or may be a chip package structure obtained by packaging the bare chip.
  • the above-mentioned integrated chip 20 may include a first chip 201 and a second chip body 202 .
  • the second chip body 202 is stacked with the first chip body 201 .
  • the second chip body 202 may be located on the side of the first chip body 201 close to the circuit board 14 .
  • the second chip body 202 can be directly electrically connected to the circuit board 14, and the first chip body 201 can use a flip chip bonding process, so that the circuit structure in the first chip body 201 is located where The front side of the second chip body 202 faces the side surface of the second chip body 202 away from the circuit board 14 .
  • the first chip body 201 may be indirectly electrically connected to the circuit board 14 through a through silicon via (TSV) penetrating the second chip body 202 .
  • TSV through silicon via
  • the size of a single side of the second chip body 202 may be in the order of millimeters.
  • the above-mentioned second chip body 202 may include a SoC, a PMU, a CPU or a GPU.
  • the first chip body 201 may include UFS or DDR.
  • the first chip body 201 may include a SoC, a PMU, a CPU, or a GPU.
  • the second chip body 202 may include UFS or DDR.
  • the above-mentioned display module 01 may further include a plurality of pixel chip sets 40 as shown in FIG. 4 .
  • the plurality of pixel chip sets 40 at least one pixel chip set 40 is disposed on a side surface of the integrated chip 20 away from the circuit board 14 .
  • a plurality of pixel chip groups 40 as shown in FIG. 5A may be disposed on a surface of one integrated chip 20 away from the circuit board 14 .
  • each pixel chip group 40 may be the smallest repeating unit of the components of the display module 01 for realizing the display function.
  • each pixel chip group 40 may include a plurality of light emitting chips 401 .
  • the light-emitting chip 401 refers to the use of semiconductor chip manufacturing process to form crystal grains arranged in an array on a wafer, and each crystal grain has a light-emitting layer. The wafer on which the above-mentioned die is formed is then diced so that each die is independent of each other.
  • each independent die is used as the above-mentioned light-emitting chip 401 , and the edge formed after the die is diced is used as the boundary of the light-emitting chip 401 .
  • the light-emitting chip 401 may be a micro light emitting diode (LED) with a grain size of several tens of microns, or a miniature (mini) with a grain size of more than 100 microns. )LED.
  • the above-mentioned light-emitting chip 401 is a current driving device.
  • each light-emitting chip 401 can be used as a sub pixel of the display module 01, and the plurality of light-emitting chips 404 in the same pixel chip set 40 can emit at least three primary colors of light.
  • the above-mentioned pixel chip set 40 It can be used as a pixel of the display module 01, so that the display module 01 can display an image.
  • the single side size of the first chip body 201 or the second chip body 202 in the integrated chip 20 can be in the order of millimeters, for example, about 10 mm.
  • the integrated chip 20 and the integrated chip 20 can be arranged on the integrated chip 20.
  • the plurality of pixel chipsets 40 are referred to as millimeter-scale display chiplet units (display chiplet units, DCUs) 100 .
  • the plurality of light-emitting chips in the same pixel chipset 40 may include a first light-emitting chip 401 a , a second light-emitting chip 401 b , and a third light-emitting chip 401 c .
  • the first light-emitting chip 401a, the second light-emitting chip 401b and the third light-emitting chip 401c can be respectively used for emitting light of three primary colors.
  • the first light emitting chip 401a, the second light emitting chip 401b, and the third light emitting chip 401c may be used to emit red (red, R) light, blue (blue, B) light, and green (Green, G) light, respectively.
  • the first light-emitting chip 401a, the second light-emitting chip 401b, and the third light-emitting chip 401c in the same pixel chip set 40 can constitute one pixel.
  • the integrated chip 20 further includes a plurality of display pixel driving circuits 100 integrated in the first chip body 201 .
  • the display pixel driving circuit can be 100 is integrated in the first chip body 201 .
  • a light-emitting chip 401 provided on the integrated chip 20 can be electrically connected to a display pixel driving circuit 100 in the integrated chip 20 .
  • the above-mentioned display pixel driving circuit 100 is used for driving the light-emitting chip 401 to emit light.
  • the display pixel driving circuit 100 may include a plurality of transistors formed by using a CMOS process.
  • the above-mentioned display pixel driving circuit 100 may include a driving transistor and a plurality of switching transistors. Data voltages related to display data can be written to the driving transistors by controlling the switching transistors to be turned on and off.
  • the driving transistor can generate a driving current matching the data voltage according to the data voltage. Since the above-mentioned light-emitting chip 401 is a current driving device, when the above-mentioned driving current flows through the light-emitting chip 401, the light-emitting chip 401 can be driven to emit light.
  • the light-emitting brightness of the light-emitting chip 401 can be controlled.
  • the present application does not limit the connection manner of the plurality of transistors in the display pixel driving circuit 100, as long as the purpose of driving the light-emitting chip 401 electrically connected thereto to emit light can be achieved.
  • the integrated chip 20 has a chip body, such as the above-mentioned first chip body 201, and when the integrated chip 20 includes a first chip body 201 and a second chip body 202 arranged in layers, the first chip body 201 and The pixel chipset 40 is in direct contact.
  • the above are all based on the display pixel driving circuit 100 integrated in the first A chip body 201 is described as an example.
  • the integrated chip 20 when the integrated chip 20 includes a first chip body 201 and a second chip body 202 that are stacked in layers, the above-mentioned display pixel driving circuit 100 may also be integrated into the second chip body 202 .
  • the light emitting device 401 disposed on the integrated chip 20 can be indirectly electrically connected to the display pixel driving circuit 100 integrated in the second chip body 202 through the first chip body 201 .
  • one pixel chip set 40 is disposed on a side surface of a circuit substrate 30 away from the circuit board 14 . That is, as shown in FIG. 6A , one pixel chip group 40 is provided on one circuit substrate 30 .
  • the structure of the pixel chip set 40 is the same as described above, and may include a first light-emitting chip 401a, a second light-emitting chip 401b and a third light-emitting chip 401c.
  • the area of the vertical projection of the circuit substrate 30 on the circuit board 14 (as shown in FIG. 4 ) is smaller than the area of the vertical projection of the integrated chip 20 on the circuit board 14 .
  • the size of a single side of the circuit substrate 30 may be in the order of micrometers, for example, about 60 ⁇ m. Therefore, for convenience of description below, the circuit substrate 30 and a pixel chipset 40 disposed on the circuit substrate 30 may be referred to as a micron-scale pixel unit (pixel unit, PU).
  • the circuit substrate 30 may include a plurality of display pixel driving circuits 100 .
  • the circuit substrate 30 may further include a substrate body 301 and a re-distribution layer (RDL) which are in turn away from the circuit board 14 .
  • the material of the substrate body 301 may be single crystal silicon, and in this case, the substrate body 301 may be referred to as a silicon base.
  • the transistors for forming the display pixel circuit 100 can be formed in the silicon substrate using the above-mentioned CMOS process.
  • the above-mentioned RDL is fabricated on the side of the substrate body 301 on which the transistors are fabricated away from the circuit board 14 .
  • the transistors in the substrate body 301 are interconnected according to design requirements through the metal traces in the RDL, so as to form the above-mentioned display pixel driving circuit 100 .
  • the transistors of the display pixel driving circuit 100 are integrated in the substrate body 301, and the wirings in the display pixel driving circuit 100 are integrated in the RDL.
  • a light-emitting chip 401 disposed on the circuit substrate 30 can be electrically connected to a display pixel circuit 100 in the circuit substrate 30 , so as to emit light under the driving action of the display pixel driving circuit 100 .
  • the display module 01 provided by the embodiment of the present application includes the circuit board 14 , and a plurality of DCUs and a plurality of PUs disposed on the same side of the circuit board 14 .
  • the DCU includes an integrated chip 20 electrically connected to the circuit board 14 , and a pixel chip set 40 disposed on the side of the integrated chip 20 away from the circuit board 14 .
  • the pixel chip set 40 is provided with a plurality of light-emitting chips 401 . Each light-emitting chip 401 is electrically connected to a display pixel driving circuit 100 integrated in the first chip body 201 of the integrated chip 20 .
  • FIG. 5B the DCU includes an integrated chip 20 electrically connected to the circuit board 14 , and a pixel chip set 40 disposed on the side of the integrated chip 20 away from the circuit board 14 .
  • the pixel chip set 40 is provided with a plurality of light-emitting chips 401 .
  • Each light-emitting chip 401 is electrically connected to a display
  • the PU includes a circuit substrate 30 electrically connected to the circuit board 14 , and a pixel chip set 40 disposed on the side of the circuit substrate 30 away from the circuit board 14 .
  • the pixel chip set 40 is also provided with a plurality of light-emitting chips 401 .
  • One light-emitting chip 401 on the circuit substrate 30 may be electrically connected to one display pixel driving circuit 100 integrated in the circuit substrate 30 .
  • the above-mentioned display pixel driving circuit 100 can drive the light-emitting chip 401 electrically connected thereto to emit light.
  • Each light-emitting chip 401 can be used as a sub-pixel of the display module 01, so that the entire display module 01 can realize image display.
  • the embodiments of the present application provide Compared with the current AMOLED display module, the display module 01 does not need to make a TFT backplane, which can effectively reduce the weight of the display module 01 and reduce the thickness of the display module 01 .
  • some of the light-emitting chips 401 are stacked with the integrated chip 20, and some of the light-emitting chips 401 are stacked with the circuit substrate 30. Both the integrated chip 20 and the circuit substrate 30 are arranged on the same side of the circuit board 14, thus improving the display mode.
  • the power consumption of the micro LED is lower than that of the OLED, which is beneficial to reduce the volume of the battery in the display module 01.
  • micro LEDs are brighter and smaller in size and thus have a smaller aperture ratio. In this way, the component space in the display module 01 can be effectively saved, which is favorable for integrating more electronic components.
  • the above-mentioned pixel driving group 40 may be the smallest repeating unit of the components of the display module 01 used to realize the display function and the fingerprint collection function.
  • the pixel chipset 40 disposed on the first chip body 201 further includes a fingerprint collecting chip 402
  • a fingerprint collecting chip 402 disposed on the first chip body 201 can be combined with the first fingerprint collecting chip 402 .
  • a fingerprint pixel acquisition circuit 101 (as shown in FIG. 7A ) in a chip body 201 is electrically connected.
  • the fingerprint pixel collection circuit 101 is used to drive the fingerprint collection chip 402 to perform fingerprint collection.
  • the circuit substrate 30 in the above-mentioned PU may further include the above-mentioned fingerprint pixel acquisition circuit 101 as shown in FIG. 8A , which is integrated in the circuit substrate 30 .
  • FIG. 8B when the pixel chip set 40 disposed on the substrate body 301 further includes a fingerprint collecting chip 402 , a fingerprint collecting chip 402 disposed on the substrate body 301 can be integrated with the circuit A fingerprint pixel acquisition circuit 101 (as shown in FIG. 8A ) in the bottom 30 is electrically connected.
  • the fingerprint collecting chip 402 in each pixel chip set 40 can be used as a collecting pixel of a fingerprint collecting device.
  • a plurality of fingerprint collecting chips 402 in different pixel chipsets 40 can jointly constitute the above-mentioned fingerprint collecting device, so it is not necessary to set up a fingerprint collecting device on the circuit board 14 separately, but the collecting pixels of the fingerprint collecting device are integrated in each fingerprint collecting device.
  • Each of the pixel chipsets 40 is beneficial to improve the integration degree of the display module.
  • the pixel chip group 40 provided on the integrated chip 20, or at least one pixel chip group 40 in the pixel chip group 40 provided on the circuit substrate 30 may include the first light-emitting chip 401a, the second light-emitting chip 401b, The third light-emitting chip 401c and the above-mentioned fingerprint collection chip 402 .
  • the fingerprint pixel acquisition circuit 101 may include a plurality of transistors formed by CMOS technology, and the present application does not limit the connection mode of the plurality of transistors in the fingerprint pixel acquisition circuit 101, as long as the drive can be electrically connected to it.
  • the purpose of the fingerprint collection chip 402 is to collect fingerprints.
  • the fingerprint collection chip 402 can collect fingerprints by optical means. At this time, the fingerprint collection chip 402 is provided with a photoelectric conversion element, and the type of the fingerprint is collected by the difference of reflected light from the ridge and valley lines in the fingerprint. Transfer the acquisition results to the SoC or CPU. Or, for another example, the fingerprint collection chip 402 can also use different capacitances (or inductances) formed between the semiconductor electrodes and the ridges and valleys in the fingerprint to collect the fingerprint and transmit the collection result to the SoC or CPU. The SoC or CPU can obtain the pattern of the fingerprint according to the collection result of the fingerprint collection chip 402 and the position coordinates of the fingerprint collection chip 402, so as to achieve the purpose of fingerprint collection or identification.
  • the integrated chip 20 in the above-mentioned DCU may also include a light-emitting pixel driving circuit 102 integrated in the first chip body 201 . and the light-receiving pixel drive circuit 103 .
  • the above-mentioned light-emitting pixel driving circuit 102, light-receiving pixel driving circuit 103, and the light-emitting pixel driving circuit 103 as shown in Fig.
  • the display pixel driving circuit 100 and the fingerprint pixel collecting circuit 101 shown in 9A are integrated in the first chip body 201 , thereby forming the above-mentioned integrated chip 20 .
  • the above-mentioned pixel driving group 40 may be the smallest repeating unit of the components of the display module 01 used to realize the display function and the face or gesture recognition function.
  • a die to wafer D2W
  • the light-receiving chip 404 may be disposed on the integrated chip 20 in a D2W bonding manner, and electrically connected to the light-receiving pixel driving circuit 103 (as shown in FIG. 9A ) in the first chip body 201 .
  • the light emitting pixel driving circuit 102 is used for driving the light emitting chip 403 to emit light
  • the light receiving pixel driving circuit 103 is used for driving the light receiving chip 404 to receive light.
  • the mass transfer method can be used to use in the above-mentioned D2W binding method, any one of the first light-emitting chip 401 a , the second light-emitting chip 401 b , and the third light-emitting chip 401 c is disposed on the integrated chip 20 , and is connected with a display pixel in the first chip body 201
  • the drive circuit 100 is electrically connected.
  • the D2W binding method is adopted, and the fingerprint collection chip 402 is disposed on the integrated chip 20 and is electrically connected with the fingerprint pixel collection circuit 101 in the first chip body 201 .
  • the at least one pixel chip set 40 provided on the integrated chip 20 may include a first light emitting chip 401a, a second light emitting chip 401b, a third light emitting chip 401c, a fingerprint collecting chip 402, a light emitting chip 403 and a light receiving chip 404.
  • the circuit substrate 30 in the above-mentioned PU may further include the above-mentioned light-emitting pixel driving circuit 102 and light-receiving pixel driving circuit 103 integrated in the circuit substrate 30 .
  • the light-emitting pixel driving circuit 102 and the light-receiving pixel driving circuit 103, as well as the above-mentioned display pixel driving circuit 100 and fingerprints may be fabricated on a silicon (Si) wafer 200 as shown in FIG. 10B using a CMOS process. Transistors in the pixel acquisition circuit 101 .
  • the above-described RLD is fabricated on the wafer 200 on which the transistors are fabricated.
  • the transistors in the wafer 200 are interconnected according to design requirements through the metal traces in the RLD, thereby forming the above-mentioned light-emitting pixel driving circuit 102, light-receiving pixel driving circuit 103, and the above-mentioned display pixel driving circuit 100 and fingerprint pixel acquisition circuit. 101.
  • a plurality of pads 60 as shown in FIG. 10C can also be formed on the surface of the side of the RLD away from the wafer 200 .
  • a D2W bonding method can be used, and the above-mentioned pad 60 (as shown in FIG. 10C ) can be used for binding.
  • the light emitting chip 403 is disposed on the wafer 200 and is electrically connected with the light emitting pixel driving circuit 102 (shown in FIG. 10B ) in the wafer 200 .
  • the light receiving chip 404 is disposed on the wafer 200 through the above-mentioned pads 60 and is electrically connected to the light receiving pixel driving circuit 103 (shown in FIG. 10B ) in the wafer 200 .
  • the pixel chip set 40 disposed in the PU includes the first light-emitting chip 401a, the second light-emitting chip 401b, the third light-emitting chip 401c, and the fingerprint collection chip 402, the above-mentioned D2W can be transferred by the method of mass transfer.
  • any one of the first light-emitting chip 401a, the second light-emitting chip 401b, and the third light-emitting chip 401c is arranged on the wafer 200 through the above-mentioned pads 60, and is displayed with one of the wafers 200.
  • the pixel driving circuit 100 (shown in FIG. 10B ) is electrically connected.
  • the D2W binding method is adopted, and the fingerprint collection chip 402 is disposed on the wafer 200 through the above-mentioned pads 60 , and is electrically connected to the fingerprint pixel collection circuit 101 (as shown in FIG. 10B ) in the wafer 200 .
  • the pixel chip set 40 disposed in at least one PU on the wafer 200 may include a first light-emitting chip 401a, a second light-emitting chip 401b, a third light-emitting chip 401c, a fingerprint collection chip 402, a light emitting chip 403, and a light emitting chip 403.
  • Receive chip 404 receive chip 404 .
  • the wafer 200 may be cut along a pre-set cutting path (CL) on the wafer 200 to form an independent PU as shown in FIG. 10E .
  • CL pre-set cutting path
  • the light emitting chip 403 in each pixel chip set 40 may serve as the pixel of the light emitter 51 as shown in FIG. 11 .
  • a plurality of light emitting chips 403 in different pixel chip groups 40 can jointly constitute the above-mentioned light emitter 51 . Therefore, it is not necessary to dispose the light emitter 51 on the circuit board 14 separately, but the pixels of the light emitter 51 are integrated into each pixel chipset 40 , which is beneficial to improve the integration degree of the display module.
  • the light receiving chip 404 in each pixel chip set 40 can be used as a pixel of the light receiver 52 as shown in FIG. 11 .
  • a plurality of light receiving chips 404 in different pixel chip groups 40 can jointly constitute the above-mentioned light receiver 52 . Therefore, it is not necessary to dispose the light receiver 52 on the circuit board 14 separately, but the pixels of the light receiver 52 are integrated into each pixel chipset 40, which is beneficial to improve the integration degree of the display module.
  • the light-emitting pixel driving circuit 102 and the light-receiving pixel driving circuit 103 may include a plurality of transistors formed by CMOS technology.
  • the connection mode of the plurality of transistors is not limited, as long as the light-emitting pixel driving circuit 102 can drive the light-emitting chip 403 electrically connected to it to emit light, and the light-receiving pixel driving circuit 103 drives the light-receiving chip 404 electrically connected to it to receive light. That's it.
  • the present application does not limit the manner in which the light transmitter 51 and the light receiver 52 shown in FIG. 11 are used to realize face or gesture recognition.
  • the purpose of recognizing faces or gestures can be achieved by recognizing the deformation of structured light.
  • each light emitting chip 403 serving as a pixel in the light emitter 51 can be controlled to emit light, so that the light emitter 51 emits light S1 with a specific pattern, when the light hits the user's face as shown in FIG. 11 . , the user's face will reflect the incident light to form reflected light S2.
  • each light receiving chip 404 serving as a pixel in the light receiver 52 receives the reflected light S2, performs photoelectric conversion, converts the light signal into an electrical signal, and transmits it to the SoC or CPU.
  • the SoC or the CPU can obtain the pattern of the reflected light S2 on the user's face, and compare the pattern with the light S1 emitted by the light transmitter 51. The original pattern is compared to obtain the deformation degree of the structured light, and finally the purpose of identifying the user's face (or gesture) is achieved.
  • the purpose of recognizing faces or gestures can be achieved by recognizing the time of flight (TOF) of light.
  • TOF time of flight
  • each light emitting chip 403 in the light emitter 51 can be controlled to emit light S1.
  • the light irradiates the user's face as shown in FIG. 11 the user's face will reflect the incident light to form reflected light S2 .
  • each light receiving chip 404 in the light receiver 52 receives the reflected light S2 of the user's face.
  • the SoC or CPU obtains the distance between the user's face and the display module 01 according to the time when the light receiver 52 receives the reflected light S2 and the position coordinates of each light-receiving chip 404 in the light receiver 52, so as to recognize the user's face (or gestures). )the goal of.
  • the above-mentioned DCU and PU can be disposed on the first surface A1 of the above-mentioned circuit board 14 and electrically connected with the circuit board 14 , so that the display screen of the display device 01 can be formed.
  • the display module 01 in the electronic device 02 has a DCU as shown in FIG. 9B and a PU as shown in FIG.
  • the pixel chipset 40 in the DCU and the PU includes a first light-emitting chip 401a, a second light-emitting chip 401b, the third light-emitting chip 401c, the fingerprint collection chip 402, the light emitting chip 403 and the light receiving chip 404 are taken as examples to illustrate the setting method of the DCU and the PU in the display module 01.
  • the circuit board 14 for carrying the above-mentioned DCU and PU is a flexible printed circuit (FPC).
  • the display device 01 may further include a rotating shaft 15 .
  • the rotating shaft 15 may be disposed on the side where the second surface A2 of the circuit board 14 is located. In this way, under the action of the rotating shaft 15 , the circuit board 14 can be bent at the position of the rotating shaft 15 , so that the entire display module 01 can be folded.
  • the circuit board 14 may include a first main viewing area 140a, a second main viewing area 140b, a first peripheral area 141a, a second peripheral area 141b, and a bending area 141c.
  • the bending area 141c is located between the first main viewing area 140a and the second main viewing area 140b.
  • the vertical projection of the rotating shaft 15 on the circuit board 14 is located in the bending area 141 c shown in FIG. 13A .
  • the first peripheral area 141a is disposed at the periphery of the first main viewing area 140a
  • the second peripheral area 141b is disposed at the periphery of the second main viewing area 140b.
  • the area of the vertical projection of the integrated chip 20 in the DCU on the circuit board 14 is larger than the area of the vertical projection of the circuit substrate 30 in the PU on the circuit board 14 .
  • the single-side size of the DCU is millimeter-level
  • the single-side size of the PU is micrometer-level.
  • the bending region 141c may be deformed.
  • a PU with a smaller size can be arranged in the bending region 141c. Since the size of the PU is small, the contact area between the PU and the bending region 141c is relatively small relative to the area where the bending region 141c is deformed. Therefore, during the bending process of the bending region 141c, it is not easy for the PU to occur. Fracture is conducive to improving the reliability of the product.
  • the first peripheral area 141 a and the second peripheral area 141 b of the circuit board 14 are located at the edge of the circuit board 14 .
  • the first peripheral area 141a and the second peripheral area 141b are easily deformed slightly under the action of external force, such as during collision. Therefore, a PU with a smaller size can be arranged in the first peripheral area 141a and the second peripheral area 141b, so that when the display module 01 is under the action of an external force, the first peripheral area 141a and the second peripheral area 141b collide, It is not easy to make the PU break, which is beneficial to improve the reliability of the product.
  • each independent PU is welded to the first side of the circuit board 14 as shown in FIG. 14A .
  • the peripheral area 141a, the second peripheral area 141b and the bending area 141c are electrically connected to the circuit board 14, so that the assembly of the PU can be completed.
  • the contact area with the circuit board 14 is large, so the DCU can be arranged in the area of the circuit board 14 that is not easily deformed, such as the first main viewing area 140a and The second main viewing area 140b.
  • a plurality of PUs are distributed around a plurality of DCUs arranged together in a matrix.
  • a circuit (not shown in the figure) for realizing the mutual communication between the multiple DCUs can be fabricated In the circuit board 14, in this case, a chip to FPC bonding method can be used.
  • each DCU is soldered on the side of the integrated chip 20 close to the circuit board 14.
  • the plate 60 is soldered on the circuit board 14 and electrically connected to the circuit board 14, so as to realize the assembly of the DCU.
  • the display module 01 when the display module 01 has multiple DCUs that need to communicate with each other, but the space for making circuits in the circuit board 14 is limited, as shown in FIG. 14D , the display module 01 also An interposer 80 may be included.
  • the adapter board 80 is electrically connected to the circuit board 14 , and at least two DCUs are disposed on a side surface of the adapter board 80 away from the circuit board 14 .
  • a circuit (not shown in the figure) for realizing the mutual communication between the at least two DCUs is formed in the adapter board 80 .
  • different DCUs can be integrated on the adapter board by flip-chip bonding process through the chip bodies (including the first chip body 201 and the second chip body 202 ) formed by using different process nodes in the integrated chip 20 first. 80 to form an integrated module. Then, the integrated module can be bound to the circuit board 14 through solder balls 81 disposed on the side of the adapter board 80 close to the circuit board 14 and electrically connected to the circuit board 14, thereby realizing the assembly of the DCU.
  • the above-mentioned chip bodies formed with different process nodes refer to different process nodes (eg, minimum line widths of transistors in the chip bodies) used in the manufacturing process of different chip bodies.
  • the process node may be 7nm, 5nm or 3nm.
  • the process node can be but not limited to 90nm.
  • the process node can be but not limited to 14nm.
  • the circuit board 14 further includes a plurality of metal traces 61 disposed in the bending area 141c. .
  • the metal traces 61 can be fabricated together with the process of fabricating the circuit board 14 .
  • the material constituting the metal trace 61 may be a metal material commonly used in the circuit board 14 , for example, metal copper.
  • the above-mentioned metal traces 61 are curved, for example, S-shaped or ⁇ -shaped.
  • both ends of the metal trace 61 are respectively connected to the circuit substrates 30 of the two PUs.
  • the circuit substrates 30 of the two PUs can be connected to the metal traces 61 on the circuit board 14 .
  • the metal trace 61 has a certain tensile property, it can be deformed with the bending of the bending region 141c, thereby reducing the stress generated at the position of the PU due to the deformation of the bending region 141c, so as to further reduce the stress.
  • the purpose of breaking the small PU since the metal trace 61 has a certain tensile property, it can be deformed with the bending of the bending region 141c, thereby reducing the stress generated at the position of the PU due to the deformation of the bending region 141c, so as to further reduce the stress. The purpose of breaking the small PU.
  • the circuit substrates 30 in the plurality of PUs in the bending region 141c are arranged in a matrix form.
  • the above-mentioned plurality of metal wires may include a plurality of first metal wires 61a and a plurality of second metal wires 61b.
  • the first metal trace 61a is connected to the circuit substrates 30 in the two adjacent PUs along the first direction X
  • the second metal trace 61b is connected to the circuits in the two adjacent PUs along the second direction Y
  • the substrates 30 are connected.
  • the first direction is perpendicular to the second direction.
  • the plurality of first metal wires 61a and the plurality of second metal wires 61b can form a mesh structure to connect the plurality of PUs in the bending area 141c, thereby increasing the toughness of the bending area 141c. To further reduce the breakage of PU.
  • the encapsulation layer 71 covers the above-mentioned DCU and PU, and is used for protecting the DCU and PU to prevent water and oxygen from eroding the DCU and PU.
  • the cover plate 72 can cover a surface of the encapsulation layer 71 away from the circuit board 14 , and is connected to the encapsulation layer 71 to protect the encapsulation layer 71 .
  • the material constituting the encapsulation layer 71 may be a transparent resin material, and a layer of resin film may be directly formed on the surface of the DCU and PU away from the circuit board 14 through a film forming process as the encapsulation layer 71 .
  • the display module 01 provided by the embodiment of the present application
  • the structure and fabrication process of the encapsulation layer 71 are simpler.
  • the material constituting the cover plate 72 may be a transparent resin material. It should be noted that the transparent material in the embodiments of the present application refers to that the light transmittance of the material can reach more than 85%.
  • the above-mentioned display module 01 may further include a heat dissipation layer 73 as shown in FIG. 16A .
  • the heat dissipation layer 73 can cover the side surface of the circuit board 14 away from the DCU (including the integrated chip 20 and the pixel chipset 40 ) and the PU including the circuit substrate 30 and the pixel chipset 40 ) and be connected to the circuit board 14 .
  • the material constituting the heat dissipation layer 73 may include graphene.
  • the battery 13 may be located on the side of the heat dissipation layer 73 away from the circuit board 14 .
  • the heat dissipation layer 73 can transfer the heat generated by the light-emitting chips 401 in the DCU and PU and the heat generated by the battery 13 to other components, such as the casing of the display module 01 (the position in the figure). In this way, since the outer casing is in contact with the air, the heat inside the display module 01 can be transferred to the outside of the display module 01 , so as to dissipate heat.
  • the above-mentioned display module 01 may include two batteries 13 , which are located on both sides of the rotating shaft 15 respectively.
  • the first chip bodies 201 in different DCUs may be different.
  • the first chip bodies 201 in different positions shown in FIG. 16A may be SoC, PMU, DDR, and USF, respectively.
  • the DCU may further include the first chip body 201 and the second chip body 202 arranged in layers as shown in FIG. 16B . By stacking the two chip bodies, the component space of the display module 01 can be further reduced, thereby facilitating the integration of more chips with different functions.
  • the circuit board 14 may include the first part 142 and the first part 142 and the first part 142 is connected to the second part 143 .
  • a plurality of DCUs (including the integrated chip 20 and the pixel chipset 40 ) and a plurality of PUs (including the circuit substrate 30 and the pixel chipset 40 ) are disposed in the first part 142 .
  • the vertical projection on the circuit board 14 of the pixel chipset 40 disposed on the side of the DCU and PU away from the circuit board 14 may be located in the first portion 142 of the circuit board 14 .
  • the second portion 143 is bent at the side of the first portion 142 away from the DCU.
  • the above-mentioned display module 01 further includes at least one additional electronic component 203 , the additional electronic component 203 may be disposed on the surface of the second portion 143 close to the first portion 142 and electrically connected to the circuit board 14 .
  • the above-mentioned additional electronic components 203 may be chips, such as SoC, PMU, CPU, GPU, UFS, or DDR.
  • the above-mentioned additional electronic components 203 may also be devices such as sensors.
  • the circuit board 14 is an FPC. In other embodiments of the present application, the circuit board 14 may also be a PCB. In this case, the above-mentioned display module 01, such as a mobile phone, is a candy bar phone that cannot be folded. At this time, as shown in FIG. 18A , the circuit board 14 may include a main viewing area 140 and a peripheral area 141 located around the main viewing area 140 .
  • the peripheral area 141 is located at the periphery of the main viewing area 140, during the transportation or use of the display module 01, the peripheral area 141 is easily deformed slightly under the action of an external force, such as during a collision.
  • the main viewing area 140 located inside the peripheral area 141 is not easily deformed under the action of external force. Therefore, a PU with a smaller size can be arranged in the peripheral area 141, so that when the display module 01 collides with the peripheral area 141 under the action of an external force, the PU is not easily broken, which is beneficial to improve the reliability of the product.
  • a DCU with a larger size is installed in the main viewing area 140 that is not easily deformed.
  • a plurality of PUs including the circuit substrate 30 and the pixel chip set 40
  • a plurality of DCUs including the integrated chip 20 and the pixel chip set 40 arranged together in a matrix form surrounding.
  • the DCU and the PU are disposed on the circuit board 14 and electrically connected to the circuit board 14 in the same manner as described above, and will not be repeated here.
  • the pixel chipset 40 of each DCU and the pixel chipset 40 of each PU include a plurality of light-emitting chips (for example, the first light-emitting chip 401a, the second light-emitting chip 401b and the third light-emitting chip 401b as shown in FIG. 10E ).
  • the fingerprint collection chip 402 the light-emitting chip 403 and the light-receiving chip 404 are further included as an example.
  • the fingerprint collection chip 402 may be provided in the pixel chipset 40 of the DCU and PU in the display module 01 only at the positions where fingerprint collection is required.
  • the display module 01 only the pixel chipset 40 of the DCU and the PU at the position of the light emitter 51 (as shown in FIG. 11 ) needs to be provided with the light emitting chip 403 .
  • the arrangement of the above-mentioned encapsulation layer 71 and cover plate 72, as well as the heat dissipation layer 73 and the battery 13 are the same as described above, and will not be repeated here.
  • the display module 01 in the electronic device 02 includes a circuit board 14 as shown in FIG. 19 .
  • the difference from Example 1 is that the display module 01 only includes the DCU.
  • the DCU as described above includes an integrated chip 20 and a plurality of pixel chip groups 40 located on a surface of the integrated chip 20 on a side away from the circuit board 14 .
  • the pixel chipset 40 includes a plurality of light-emitting chips (eg, a first light-emitting chip 401a, a second light-emitting chip 401b, and a third light-emitting chip 401c), and further includes a fingerprint collection chip 402, a light emitting chip 403, and a light-emitting chip 402. Take the receiving chip 404 as an example.
  • the integrated circuit 20 may include a display pixel driving circuit 100 , a fingerprint pixel collecting circuit 101 , a light emitting pixel driving circuit 102 and a light receiving pixel driving circuit 103 integrated in the first chip body 201 .
  • the light-emitting chip, the fingerprint collecting chip 402, the light emitting chip 403, and the light receiving chip 404 are respectively integrated with the above-mentioned display pixel driving circuit 100, the fingerprint pixel collecting circuit 101, the light emitting pixel driving circuit 102 and the light receiving chip integrated in the first chip body 201.
  • the pixel driving circuit 103 is electrically connected.
  • the manufacturing process of the above-mentioned DCU and the process of electrically connecting the DCU and the circuit board 14 are the same as those described above, and will not be repeated here.
  • a fingerprint collection chip 402 may be provided in the pixel chip set 40 of the DCU in the display module 01 only at a position where fingerprint collection is required.
  • the display module 01 it is only necessary to set the light emitting chip 403 in the pixel chipset 40 of the DCU at the position where the light emitter 51 (as shown in FIG. 11) is set.
  • the display module 01 it is only necessary to set the light emitting chip 403 in the pixel chip set 40 of the DCU at the position where the light receiver 52 (as shown in FIG. 11) is set.
  • the above-mentioned encapsulation layer 71 and cover plate 72 , as well as the heat dissipation layer 73 and the battery 13 are arranged in the same manner as described above, and will not be repeated here.
  • the display module 01 in the electronic device 02 includes a circuit board 14 as shown in FIG. 20 .
  • the difference from Example 1 is that the display module 01 only includes a PU.
  • the PU as described above, includes a circuit substrate 30 and a plurality of pixel chip sets 40 located on a surface of the circuit substrate 30 on a side away from the circuit board 14 .
  • the pixel chip set 40 includes a plurality of light-emitting chips (eg, a first light-emitting chip 401a, a second light-emitting chip 401b, and a third light-emitting chip 401c), and further includes a fingerprint collection chip 402, a light emitting chip 403, and a light emitting chip 403.
  • the circuit substrate 30 may include a display pixel driving circuit 100 , a fingerprint pixel collecting circuit 101 , a light emitting pixel driving circuit 102 and a light receiving pixel driving circuit 103 integrated in the substrate body 301 .
  • the light-emitting chip, the fingerprint collecting chip 402 , the light emitting chip 403 and the light receiving chip 404 are respectively integrated with the above-mentioned display pixel driving circuit 100 , fingerprint pixel collecting circuit 101 , and light emitting pixel driving circuit integrated in the substrate body 301 of the circuit substrate 30 . 102 and the light-receiving pixel driving circuit 103 are electrically connected.
  • the manufacturing process of the PU and the process of electrically connecting the PU to the circuit board 14 are the same as described above, and will not be repeated here.
  • the fingerprint collection chip 402 may be provided in the pixel chipset 40 of the PU in the display module 01 only at the position where fingerprint collection is required.
  • the display module 01 it is only necessary to set the light emitting chip 403 in the pixel chip set 40 of the PU at the position where the light emitter 51 (as shown in FIG. 11) is set.
  • the display module 01 it is only necessary to set the light emitting chip 403 in the pixel chip set 40 of the PU at the position where the light receiver 52 (as shown in FIG. 11) is set.
  • the above-mentioned circuit board 14 may be a PCB.
  • the circuit board 14 can be an FPC, and the display module 01 includes a rotating shaft 15 located on the side of the circuit board 14 away from the PU.
  • the circuit board 14 may have a first area 151 , a second area 152 and a bending area 141 c between the first area 151 and the second area 152 as shown in FIG. 21 .
  • the vertical projection of the rotating shaft 15 on the circuit board 14 is located in the bending area 141c.
  • the circuit board 14 further includes a plurality of metal traces ( For example, a plurality of first metal traces 61a and a plurality of second metal traces 61b).
  • Both ends of any metal trace are respectively connected to the circuit substrates 30 of two adjacent PUs.
  • the shape and manufacturing process of the above-mentioned metal wires, and the arrangement of the first metal wires 61 a and the second metal wires 61 b are the same as those described above, and will not be repeated here.
  • the encapsulation layer 71 and the cover plate 72 , the heat dissipation layer 73 and the battery 13 in the display module 01 provided in this example are arranged in the same manner as described above, and will not be repeated here.
  • the circuit board 14 when the circuit board 14 is an FPC, the circuit board 14 may include a first part 142 and a second part 143 connected to the first part 142 .
  • a plurality of PUs (including the circuit substrate 30 and the pixel chipset 40 ) are disposed on the first portion 142 .
  • the second portion 143 is bent on the side of the first portion 142 away from the PU.
  • Some additional electronic components 203 in the display module 01 can be disposed on the surface of the second part 143 close to the first part 142 and electrically connected to the circuit board 14. connect.

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Abstract

一种显示模组、电子设备，涉及显示技术领域，用于改善自发光的显示模组厚度和重量较大的问题。该显示模组包括电路板、集成芯片以及像素芯片组。集成芯片与电路板电连接。集成芯片包括第一芯片本体以及集成于第一芯片本体中的多个显示像素驱动电路。像素芯片组包括多个发光芯片。此外，至少一个像素芯片组设置于一个集成芯片远离电路板的一侧表面。设置于集成芯片上的一个发光芯片与集成芯片中的一个显示像素驱动电路电连接，显示像素驱动电路用于驱动发光芯片发光。用于驱动发光芯片发光的显示像素驱动电路集成于上述集成芯片中的第一芯片本体中，能够减小显示模组的重量和厚度。

Description

一种显示模组、电子设备
本申请要求于2020年07月30日提交国家知识产权局、申请号为202010753480.4、申请名称为“一种屏幕组件、屏幕模组和电子设备”的中国专利申请，以及于2020年12月18日提交国家知识产权局、申请号为202011507874.8、申请名称为“一种显示模组、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示模组、电子设备。
背景技术
目前，能够实现自发光的显示模组，例如采用有源矩阵有机发光二极管(active matrix organic light emitting diode，AMOLED)技术的显示模组，其子像素(sub pixel)中设置有机发光二极管(organic light emitting diode，OLED)。通过控制不同OLED的发光亮度，即可以实现灰阶显示。因此无需设置用于提供背光源的背光模组(back light unit，BLU)，从而能够减小显示模组的厚度。
如图1所示，AMOLED显示模组中设置有薄膜晶体管(thin film transistor，TFT)背板10，以及用于承载控制芯片11的印刷电路板(printed circuit board，PCB)。TFT背板10中设置有主要由TFT构成的驱动电路，该驱动电路用于驱动位于TFT背板上方的OLED器件发光。然而，由于上述TFT背板10和PCB的存在，会使得自发光的显示模组很难进一步降低厚度和重量，不利于显示模组的轻薄化设计。
发明内容
本申请提供一种显示模组、电子设备，用于改善自发光的显示模组厚度和重量较大的问题。
为达到上述目的，本申请采用如下技术方案：
在本申请的一方面，提供一种显示模组。该显示模组包括电路板、集成芯片以及像素芯片组。集成芯片与电路板电连接。集成芯片包括第一芯片本体以及集成于第一芯片本体中的多个显示像素驱动电路。像素芯片组包括多个发光芯片。此外，至少一个像素芯片组设置于一个集成芯片远离电路板的一侧表面。设置于集成芯片上的一个发光芯片与集成芯片中的一个显示像素驱动电路电连接，显示像素驱动电路用于驱动发光芯片发光。这样一来，由于用于驱动发光芯片发光的显示像素驱动电路可以集成于上述集成芯片中的第一芯片本体中，因此本申请实施例提供的显示模组相对于目前的AMOLED显示模组而言，无需制作TFT背板，能够有效减小显示模组的重量，减薄显示模组的厚度。
可选的，显示模组还包括电路衬底。电路衬底与电路板电连接，电路衬底集成有多个显示像素驱动电路。电路衬底在电路板上的垂直投影的面积，小于集成芯片在电路板上的垂直投影的面积。显示模组还包括两个或者两个以上的上述像素芯片组。一个像素芯片组设置于一个电路衬底远离电路板的一侧表面。设置于电路衬底上的一个 发光芯片与电路衬底中的一个显示像素电路电连接。同理，将用于驱动发光芯片发光的显示像素驱动电路集成于电路衬底中，能够有效减小显示模组的重量，减薄显示模组的厚度。
可选的，电路板包括主视区和位于主视区周边的周边区。集成芯片设置于主视区，电路衬底设置于周边区。周边区位于电路板的边缘位置。集成芯片的尺寸较大，与电路板的接触面积较大，而电路衬底的尺寸较小，与电路板的接触面积较小。在此情况下，显示模组在运输或使用的过程中，上述周边区容易在外力作用下，例如受到碰撞的过程中发生轻微的变形。因此，可以将尺寸较小的电路衬底设置于周边区，将尺寸较大的集成芯片设置于不容易发生变形的主视区，从而当显示模组在外力作用下，使得周边区发生碰撞时，不容易使得电路衬底发生断裂，有利于提高产品的可靠性。
可选的，显示模组还包括转轴，转轴设置于电路板远离集成芯片的一侧。电路板为柔性电路板。电路板包括第一主视区、第二主视区、第一周边区、第二周边区以及弯折区。其中，弯折区位于第一主视区和第二主视区之间，且转轴在电路板的垂直投影位于弯折区内。第一周边区设置于第一主视区的周边，第二周边区设置于第二主视区的周边。集成芯片设置于第一主视区和第二主视区；多个电路衬底设置于弯折区、第一周边区以及第二周边。由上述可知，集成芯片的尺寸较大，与电路板的接触面积较大，而电路衬底的尺寸较小，与电路板的接触面积较小。电路板的第一周边区和第二周边区位于电路板的边缘位置。在此情况下，显示模组在运输或使用的过程中，上述第一周边区和第二周边区容易在外力作用下，例如受到碰撞的过程中发生轻微的变形。因此，可以将尺寸较小的电路衬底设置于第一周边区和第二周边区，将尺寸较大的集成芯片设置于不容易发生变形的主视区，从而当显示模组在外力作用下，使得第一周边区和第二周边区发生碰撞时，不容易使得电路衬底发生断裂，有利于提高产品的可靠性。
可选的，电路板包括多条金属走线，多条金属走线设置于弯折区。金属走线呈弯曲状，且金属走线的两端分别与两个电路衬底相连接。这样一来，由于金属走线具有一定的拉伸性能，能够随着弯折区的弯折而发生变形，减小由于弯折区形变而在电路衬底所在位置产生的应力，达到进一步减小电路衬底发生断裂的目的。
可选的，弯折区的多个电路衬底呈矩阵形式排列。多条金属走线包括多条第一金属走线和多条第二金属走线。第一金属走线沿第一方向与相邻的两个电路衬底相连接，第二金属走线沿第二方向与相邻的两个电路衬底相连接。其中，第一方向与第二方向垂直。这样一来，上述多条第一金属走线和多条第二金属走线可以构成网状结构将弯折区中的多个电路衬底相连接，从而能够增加弯折区的韧性，进一步减小电路衬底发生断裂。
可选的，同一像素芯片组中的多个发光芯片包括第一发光芯片、第二发光芯片以及第三发光芯片。第一发光芯片、第二发光芯片以及第三发光芯片分别用于发出三原色光。这样一来，同一个像素芯片组中的第一发光芯片、第二发光芯片以及第三发光芯片可以构成一个像素。通过调节同一个像素芯片组中的第一发光芯片、第二发光芯片以及第三发光芯片各自的发光亮度，可以达到控制显示模组进行彩色显示时，显示图像的像素灰阶的目的。
可选的，集成芯片还包括集成于第一芯片本体中的多个指纹像素采集电路。像素芯片组还包括指纹采集芯片。设置于集成芯片上的一个指纹采集芯片与集成芯片中的一个指纹像素采集电路电连接，指纹像素采集电路用于驱动指纹采集芯片进行指纹采集。其中，不同像素芯片组中的多个指纹采集芯片构成指纹采集器。这样一来，无需单独在电路板上设置指纹采集器，而是将指纹采集器的采集像素集成于每个像素芯片组中，从而有利于提高显示模组的集成度。
可选的，集成芯片还包括集成于第一芯片本体中的多个指纹像素采集电路；电路衬底还集成有一个指纹像素采集电路。像素芯片组还包括指纹采集芯片。设置于集成芯片上的一个指纹采集芯片与集成芯片中的一个指纹像素采集电路电连接，设置于电路衬底上的指纹采集芯片与电路衬底中的指纹像素采集电路电连接。指纹像素采集电路用于驱动指纹采集芯片进行指纹采集。其中，不同像素芯片组中的多个指纹采集芯片构成指纹采集器。这样一来，集成芯片和电路衬底上方的像素芯片组中均设置有指纹采集器的采集像素，有利于提高指纹采集的精度。此外，指纹采集芯片和指纹像素采集电路的技术效果同上所述，此处不再赘述。
可选的，集成芯片还包括集成于第一芯片本体中的多个光线发射像素驱动电路和多个光线接收像素驱动电路。像素芯片组还包括光线发射芯片以及光线接收芯片。设置于集成芯片上的一个光线发射芯片与集成芯片中的一个光线发射像素驱动电路电连接，一个光线接收芯片与集成芯片中的一个光线接收像素驱动电路电连接。光线发射像素驱动电路用于驱动光线发射芯片发射光线。光线接收像素驱动电路用于驱动光线接收芯片接收光线。其中，不同像素芯片组中的多个光线发射芯片构成光线发射器，不同像素芯片组中的多个光线接收芯片构成光线接收器。因此无需单独在电路板上设置光线发射器，而是将光线发射器的像素集成于每个像素芯片组中，从而有利于提高显示模组的集成度。因此无需单独在电路板上设置光线接收器，而是将光线接收器的像素集成于每个像素芯片组中，从而有利于提高显示模组的集成度。
可选的，集成芯片还包括集成于第一芯片本体中的多个光线发射像素驱动电路和多个光线接收像素驱动电路。电路衬底还集成有一个光线发射像素驱动电路和一个光线接收像素驱动电路。像素芯片组还包括光线发射芯片以及光线接收芯片。设置于集成芯片上的一个光线发射芯片与集成芯片中的一个光线发射像素驱动电路电连接，一个光线接收芯片与集成芯片中的一个光线接收像素驱动电路电连接。设置于电路衬底上的一个光线发射芯片与电路衬底中的一个光线发射像素驱动电路电连接，一个光线接收芯片与电路衬底中的一个光线接收像素驱动电路电连接。光线发射像素驱动电路用于驱动光线发射芯片发射光线；光线接收像素驱动电路用于驱动光线接收芯片接收光线。其中，不同像素芯片组中的多个光线发射芯片构成光线发射器，不同像素芯片组中的多个光线接收芯片构成光线接收器。这样一来，集成芯片和电路衬底上方的像素芯片组中均设置有光线发射器和光线接收器的像素，有利于提高指纹采集的精度。此外，光线发射芯片、光线接收芯片以及光线发射像素驱动电路和光线接收像素驱动电路的技术效果同上所述，此处不再赘述。
可选的，第一芯片本体包括系统级芯片、电源管理单元、中央处理器、图像处理器，或者，存储芯片。不同集成芯片中的第一芯片本体的类型可以不同，从而可以集 成更多的芯片。
可选的，集成芯片还包括第二芯片本体。第二芯片本体与第一芯片本体堆叠设置，且第二芯片本体位于第一芯片本体靠近电路板的一侧。第二芯片本体包括系统级芯片、电源管理单元、中央处理器或者图像处理器；第一芯片本体包括存储芯片。这样一来，通过将第一芯片本体和第二芯片本体堆叠后形成上述集成芯片，可以进一步节省显示模组中的部件空间。
可选的，电路板为柔性电路板。电路板包括第一部分以及与第一部分相连接的第二部分。像素芯片组在电路板上的垂直投影位于第一部分，第二部分弯折于第一部分远离像素芯片组的一侧。显示模组还包括附加电子元件，附加电子元件设置于第二部分靠近第一部分的表面上，且与电路板电连接。这样一来，可以使得显示模组中集成更多的电子元器件，提高显示模组的集成度。
可选的，显示模组还包括转接板。转接板与电路板电连接，至少两个集成芯片设置于转接板远离电路板的一侧表面，且通过转接板电连接。该转接板内可以形成有用于实现上述至少两个集成芯片相互通信的电路。这样一来，无需将所有集成电路之间互联的电路结构制作与电路板中，能够节约电路板中布局电路的空间。
可选的，电路衬底还包括依次远离电路板的衬底本体和重布线层，显示像素驱动电路的晶体管集成于衬底本体中，显示像素驱动电路中的走线集成于重布线层中。其中，衬底本体的材料包括单晶硅。这样一来，可以采用上述CMOS工艺在硅基底内形成用于构成显示像素电路的晶体管。然后，在制作有晶体管的衬底本体远离电路板的一侧制作上述重布线层。通过该重布线层中的金属走线将衬底本体中的晶体管按照设计要求进行互联，从而形成上述显示像素驱动电路。
可选的，显示模组还包括封装层，封装层位于像素芯片组远离电路板的一侧，且覆盖集成芯片以及像素芯片组。封装层用于对集成芯片以及像素芯片组进行保护，避免水氧侵蚀集成芯片以及像素芯片。
可选的，显示模组还包括盖板，盖板覆盖封装层远离电路板的一侧表面，且与封装层相连接，对封装层进行保护。
可选的，显示模组还包括散热层，散热层覆盖电路板远离像素芯片组的一侧表面，且与电路板相连接。这样一来，散热层能够对显示模组产生的热量，以及电池产生的热量传递至其余部件，例如显示模组的外壳。这样一来，由于外壳与空气相接触，从而能够使得显示模组内部的热量传递至显示模组外部，起到散热的作用。
本申请的另一方面，提供一种电子设备，包括电池以及如上所述的任意一种显示模组。该电池位于电路板远离像素芯片组的一侧。电池用于向显示模组供电。上述电子设备具有与前述是实施例提供的显示模组相同的技术效果，此处不再赘述。
本申请的另一方面，提供一种显示模组，包括电路板、电路衬底以及像素芯片组。电路衬底与电路板电连接，电路衬底集成有多个显示像素驱动电路。像素芯片组包括多个发光芯片。一个像素芯片组设置于一个电路衬底远离电路板的一侧表面；设置于电路衬底上的一个发光芯片与电路衬底中的一个显示像素电路电连接，显示像素驱动电路用于驱动发光芯片发光。该显示模组具有与前述实施例提供的显示模组相同的技术效果，此处不再赘述。
可选的，显示模组还包括转轴，转轴设置于电路板远离电路衬底的一侧。电路板为柔性电路板。电路板包括第一区、第二区以及位于第一区和第二区之间的弯折区。转轴在柔性电路板的垂直投影位于弯折区内。电路板包括多条金属走线，多条金属走线设置于弯折区；金属走线呈弯曲状，且金属走线的两端分别与两个电路衬底相连接。金属走线的技术效果同上所述，此处不再赘述。
可选的，弯折区的多个电路衬底呈矩阵形式排列呈矩阵形式排列。多条金属走线包括多条第一金属走线和多条第二金属走线。第一金属走线沿第一方向与相邻的两个电路衬底相连接，第二金属走线沿第二方向与相邻的两个电路衬底相连接；其中，第一方向与第二方向垂直。第一金属走线和多条第二金属走线的技术效果同上所述，此处不再赘述。
可选的，同一像素芯片组中的多个发光芯片包括第一发光芯片、第二发光芯片以及第三发光芯片。第一发光芯片、第二发光芯片以及第三发光芯片分别用于发出三原色光。第一发光芯片、第二发光芯片以及第三发光芯片的技术效果同上所述，此处不再赘述。
可选的，电路衬底还集成有指纹像素采集电路。像素芯片组还包括指纹采集芯片。设置于电路衬底上的一个指纹采集芯片与电路衬底中的一个指纹像素采集电路电连接。指纹像素采集电路用于驱动指纹采集芯片进行指纹采集。其中，不同像素芯片组中的多个指纹采集芯片构成指纹采集器。指纹采集芯片和指纹像素采集电路的技术效果同上所述，此处不再赘述。
可选的，电路衬底还集成有光线发射像素驱动电路和光线接收像素驱动电路。像素芯片组还包括光线发射芯片以及光线接收芯片。设置于电路衬底上的一个光线发射芯片与电路衬底中的一个光线发射像素驱动电路电连接，一个光线接收芯片与电路衬底中的一个光线接收像素驱动电路电连接。光线发射像素驱动电路用于驱动光线发射芯片发射光线；光线接收像素驱动电路用于驱动光线接收芯片接收光线。其中，不同像素芯片组中的多个光线发射芯片构成光线发射器，不同像素芯片组中的多个光线接收芯片构成光线接收器。光线发射像素驱动电路和光线接收像素驱动电路，以及光线发射芯片以及光线接收芯片的技术效果同上所述，此处不再赘述。
可选的，电路衬底还包括依次远离电路板的衬底本体和重布线层，显示像素驱动电路的晶体管集成于衬底本体中，显示像素驱动电路中的走线集成于重布线层中。其中，衬底本体的材料包括单晶硅。衬底本体和重布线层的技术效果同上所述，此处不再赘述。
可选的，电路板为柔性电路板。电路板包括第一部分以及与第一部分相连接的第二部分；多个电路衬底设置于第一部分。第二部分弯折于第一部分远离电路衬底的一侧。显示模组还包括附加电子元件，附加电子元件设置于第二部分靠近第一部分的表面上，且与电路板电连接。电路板的第一部分、第二部分，以及附加电子元件的技术效果同上所述，此处不再赘述。
本申请的另一方面，提供一种电子设备，包括电池以及如上所述的任意一种显示模组。该电池位于电路板远离像素芯片组的一侧。电池用于向显示模组供电。上述电子设备具有与前述是实施例提供的显示模组相同的技术效果，此处不再赘述。
附图说明
图1为现有技术提供的一种AMOLED电子设备的结构示意图；
图2为本申请实施例提供的一种电子设备的结构示意图；
图3A为图2中显示模组的一种结构示意图；
图3B为图3A中集成芯片的一种结构示意图；
图4为本申请实施例提供的另一种显示模组的结构示意图；
图5A为本申请实施例提供的DCU的一种结构示意图；
图5B为本申请实施例提供的DCU的另一种结构示意图；
图6A为本申请实施例提供的PU的一种结构示意图；
图6B为本申请实施例提供的DCU和PU的一种结构示意图；
图6C为本申请实施例提供的PU的另一种结构示意图；
图7A为本申请实施例提供的一种集成芯片的结构示意图；
图7B为本申请实施例提供的DCU的另一种结构示意图；
图8A为本申请实施例提供的一种电路衬底的结构示意图；
图8B为本申请实施例提供的PU的另一种结构示意图；
图9A为本申请实施例提供的一种集成芯片的结构示意图；
图9B为本申请实施例提供的DCU的另一种结构示意图；
图10A为本申请实施例提供的一种电路衬底的结构示意图；
图10B为本申请实施例提供的一种晶圆的结构示意图；
图10C为图10B所示的晶圆的部分结构示意图；
图10D为本申请实施例提供的另一种晶圆的结构示意图；
图10E为本申请实施例提供的PU的另一种结构示意图；
图11为本申请实施例提供的一种电子设备的结构示意图；
图12为本申请实施例提供的一种可折叠的显示模组的结构示意图；
图13A为图12中电路板的一种区域划分示意图；
图13B为图12中电路板的弯折结构示意图；
图14A为本申请实施例提供的一种显示模组的结构示意图；
图14B为本申请实施例提供的一种PU与电路板的绑定过程示意图；
图14C为本申请实施例提供的一种DCU与电路板的绑定过程示意图；
图14D为本申请实施例提供的另一种DCU与电路板的绑定过程示意图；
图15A为本申请实施例提供的另一种显示模组的结构示意图；
图15B为本申请实施例提供的另一种显示模组的结构示意图；
图16A为本申请实施例提供的另一种电子设备的结构示意图；
图16B为本申请实施例提供的另一种电子设备的结构示意图；
图17为本申请实施例提供的另一种电子设备的结构示意图；
图18A为本申请实施例提供的一种电路板的区域划分示意图；
图18B为采用图18A所示的电路板构成的显示模组的一种结构示意图；
图19为本申请实施例提供的另一种显示屏的结构示意图；
图20为本申请实施例提供的另一种显示屏的结构示意图；
图21为本申请实施例提供的一种区域划分示意图；
图22为本申请实施例提供的另一种显示模组的结构示意图；
图23为本申请实施例提供的另一种电子设备的结构示意图。
附图标记：
10-TFT背板；11-控制芯片；02-电子设备；01-显示模组；13-电池；14-电路板；20-集成芯片；201-第一芯片本体；30-电路衬底；40-像素芯片组；202-第二芯片本体；401-发光芯片；401a-第一发光芯片；401b-第二发光芯片；401c-第三发光芯片；100-显示像素驱动电路；301-衬底本体；101-指纹像素采集电路；402-指纹采集芯片；102-光线发射像素驱动电路；103-光线接收像素驱动电路；403-光线发射芯片；404-光线接收芯片；200-晶圆；60-焊盘；51-光线发射器；52-光线接收器；15-转轴；140a-第一主视区；140b-第二主视区；141a-第一周边区；141b-第二周边区；141c-弯折区；80-转接板；81-焊球；61-金属走线；61a-第一金属轴线；61b-第二金属走线；71-封装层；72-盖板；73-散热层；142-第一部分；143-第二部分；203-附加电子元件；151-第一区；152-第二区。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。
此外，本申请中，“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以是通过中间媒介间接的电性连接。
本申请实施例提供一种电子设备，该电子设备可以包括手机(mobile phone)、平板电脑(pad)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality AR)终端设备等具有显示功能的电子产品。本申请实施例对上述电子设备的具体形式不做特殊限制。以下为了方便说明，以上述电子设备02为如图2所示的手机为例进行说明。该电子设备02可以包括用于显示图像的显示模组01，以及位于该显示模组01背面的电池13，电池13用于向显示模组01供电。以下通过不同的示例对该显示模组01的结构进行详细的说明。
示例一
本示例中，电子设备02中的显示模组01，如图3A所示，可以包括电路板14。该电路板14可以具有相对设置的第一表面A1和第二表面A2。在此基础上，上述显示模组01还可以包括设置于电路板14的第一表面A1上，且与该电路板14电连接的 集成芯片20和电路衬底30。本申请是以显示模组01包括两个或者两个(以下简称多个)以上的集成芯片20，以及多个电路衬底30为例进行的说明。
在本申请的一些实施例中，如图3A所示，集成芯片20可以包括第一芯片本体(chiplet)201。如图3B(沿图3A中的箭头B1得到的俯视图)所示，第一芯片本体201的横截面(与第一表面A1平行)可以为矩形，该矩形的任意一条边的尺寸L(以下简称单边尺寸)可以为毫米级。
示例的，上述第一芯片本体201可以为系统级芯片(system on a chip，SoC)、电源管理单元(Power management unit，PMU)、图像处理器(graphics processing unit，GPU)或者中央处理器(central processing unit，CPU)。或者，上述第一芯片本体201可以为存储芯片，例如，通用闪存存储器(universal flash storage，UFS)，或者双倍数据速率(double data rate，DDR)存储器。不同的集成芯片20中的第一芯片本体201可以不相同。上述第一芯片本体201可以为裸芯片(die)，也可以为对裸芯片进行封装后得到的芯片封装结构。
或者，在本申请的另一些实施例中，如图4所示，上述集成芯片20可以包括第一芯片201和第二芯片本体202。该第二芯片本体202与第一芯片本体201堆叠设置。例如，第二芯片本体202可以位于第一芯片本体201靠近电路板14的一侧。在此情况下，第二芯片本体202可以与电路板14直接电连接，而第一芯片本体201可以采用倒装芯片绑定(flip chip bonding)工艺，使得第一芯片本体201中的电路结构所在的正面朝向第二芯片本体202远离电路板14的一侧表面。并且，第一芯片本体201可以通过贯穿第二芯片本体202的穿透硅通孔(through silicon via，TSV)与电路板14间接电连接。同理，第二芯片本体202的单边尺寸可以为毫米级。
示例的，上述第二芯片本体202可以包括SoC、PMU、CPU或者GPU。该第一芯片本体201可以包括UFS或者DDR。或者，又示例的，第一芯片本体201可以包括SoC、PMU、CPU或者GPU。第二芯片本体202可以包括UFS或者DDR。
在此基础上，上述显示模组01还可以包括如图4所示的多个像素芯片组40。该多个像素芯片组40中，至少一个像素芯片组40设置于一个集成芯片20远离电路板14的一侧表面。示例的，一个集成芯片20远离电路板14的一侧表面上可以设置有如图5A(沿图4中的B2箭头得到的俯视图)所示的多个上述像素芯片组40。
示例的，上述像素驱动组40可以为显示模组01用于实现显示功能的部件的最小重复单元。在此情况下，每个像素芯片组40可以包括多个发光芯片401。其中，该发光芯片401是指采用半导体芯片制备工艺，在晶圆(wafer)上形成阵列排布的晶粒，每个晶粒具有发光层。然后对形成有上述晶粒的晶圆进行切割，使得各个晶粒彼此独立。切割后每个独立的晶粒作为上述发光芯片401，该晶粒被切割后形成的边缘作为该发光芯片401的边界。在本申请的一些实施例中，该发光芯片401可以为晶粒尺寸在几十微米的微型(micro)发光二极管(light emitting diode，LED)，或者，晶粒尺寸在100微米以上的小型(mini)LED。上述发光芯片401为电流驱动器件。在此情况下，每个发光芯片401可以作为显示模组01的一个子像素(sub pixel)，同一像素芯片组40中的多个发光芯片404可以至少发出三原色光，此时上述像素芯片组40可以作为显示模组01的一个像素(pixel)，使得显示模组01能够显示图像。
由上述可知，集成芯片20中第一芯片本体201或第二芯片本体202的单边尺寸可以为毫米级，例如10mm左右，以下为了方便说明，可以将集成芯片20以及设置于该集成芯片20上的多个像素芯片组40称为毫米级显示芯片集成单元(display chiplet unit，DCU)100。
在本申请的一些实施例中，如图5A所示，同一像素芯片组40中的多个发光芯片可以包括第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c。其中，第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c可以分别用于发出三原色光。例如，第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c可以分别用于发出红(red，R)光、蓝(blue，B)光以及绿(Green，G)光。这样一来，同一个像素芯片组40中的第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c可以构成一个像素(pixel)。通过调节同一个像素芯片组40中的第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c各自的发光亮度，可以达到控制显示模组01进行彩色显示时，显示图像的像素灰阶的目的。
基于此，为了能够驱动设置于该集成芯片20上的发光芯片401发光，如图5B所示，上述集成芯片20还包括集成于第一芯片本体201中的多个显示像素驱动电路100。例如，在采用互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)工艺制作上述第一芯片本体201(例如SoC、PMU、CPU、GPU、UFS或者DDR)的过程中，可以将该显示像素驱动电路100集成于第一芯片本体201中。在此情况下，上述设置于集成芯片20上的一个发光芯片401可以与该集成芯片20中的一个显示像素驱动电路100电连接。上述显示像素驱动电路100用于驱动发光芯片401发光。
需要说明的是，该显示像素驱动电路100可以包括多个采用CMOS工艺形成的晶体管。上述显示像素驱动电路100可以包括驱动晶体管和多个开关晶体管。通过控制开关晶体管的到导通和关闭可以将与显示数据有关的数据电压写入至驱动晶体管。该驱动晶体管可以根据上述数据电压产生与该数据电压相匹配的驱动电流。由于上述发光芯片401为电流驱动器件，因此当上述驱动电流流过发光芯片401时，可以驱动发光芯片401发光。通过控制驱动电流的大小，可以对发光芯片401的发光亮度进行控制。本申请对显示像素驱动电路100中的多个晶体管的连接方式不做限定，只要能够达到驱动与其电连接的发光芯片401发光的目的即可。
此外，当集成芯片20中具有一个芯片本体，例如上述第一芯片本体201时，以及集成芯片20包括层叠设置的第一芯片本体201和第二芯片本体202时，该第一芯片本体201均与像素芯片组40直接接触。在此情况下，为了使得显示像素驱动电路100与设置于集成芯片20上的发光器件401之间的信号传输距离最短，提高信号传输的效率，上述均是以该显示像素驱动电路100集成于第一芯片本体201为例进行的说明。
或者，在本申请的另一些实施例中，当集成芯片20包括层叠设置的第一芯片本体201和第二芯片本体202时，还可以将上述显示像素驱动电路100集成于第二芯片本体202中。在此情况下，设置于集成芯片20上的发光器件401可以通过第一芯片本体201，与集成于第二芯片本体202中的该显示像素驱动电路100间接电连接。
在此基础上，如图4所示，该显示模组01中的上述多个像素芯片组40中，一个像素芯片组40设置于一个电路衬底30远离电路板14的一侧表面。即，如图6A所示， 一个电路衬底30上设置有一个像素芯片组40。该像素芯片组40的结构同上所述，可以包括第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c。
如图6B所示，电路衬底30在电路板14(如图4所示)上的垂直投影的面积，小于集成芯片20在电路板14上的垂直投影的面积。示例的，该电路衬底30的单边尺寸可以为微米级，例如60μm左右。因此，以下为了方便说明，可以将电路衬底30以及设置于该电路衬底30上的一个像素芯片组40称为微米级像素集成单元(pixel unit，PU)。
基于此，为了能够驱动设置于该电路衬底30上的发光芯片发光，如图6C所示，该电路衬底30可以包括多个显示像素驱动电路100。在本申请的一些实施例中，电路衬底30还可以包括依次远离电路板14的衬底本体301和重布线层(re-distribution layer，RDL)。衬底本体301的材料可以为单晶硅，此时，该衬底本体301可以称为硅基底。
这样一来，可以采用上述CMOS工艺在硅基底内形成用于构成显示像素电路100的晶体管。然后，在制作有晶体管的衬底本体301远离电路板14的一侧制作上述RDL。通过该RDL中的金属走线将衬底本体301中的晶体管按照设计要求进行互联，从而形成上述显示像素驱动电路100。此时，显示像素驱动电路100的晶体管集成于衬底本体301中，显示像素驱动电路100中的走线集成于RDL中。在此情况下，设置于电路衬底30上的一个发光芯片401可以与电路衬底30中的一个显示像素电路100电连接，从而可以在显示像素驱动电路100的驱动作用下发光。
综上所述，本申请实施例提供的显示模组01包括电路板14，以及设置于电路板14同一侧的多个DCU和多个PU。其中，如图5B所示，DCU包括与电路板14电连接的集成芯片20，以及设置于该集成芯片20远离电路板14一侧的像素芯片组40。该像素芯片组40中设置有多个发光芯片401。每个发光芯片401就与集成于集成芯片20的第一芯片本体201中的一个显示像素驱动电路100电连接。此外，如图6B所示，PU包括与电路板14电连接的电路衬底30，以及设置于该电路衬底30远离电路板14一侧的像素芯片组40。该像素芯片组40中同样设置有多个发光芯片401。电路衬底30上的一个发光芯片401可以与集成于电路衬底30中的一个显示像素驱动电路100电连接。上述显示像素驱动电路100可以驱动与其电连接的发光芯片401发光。每个发光芯片401可以作为显示模组01的一个子像素，使得整个显示模组01能够实现图像显示。
这样一来，一方面，由于用于驱动发光芯片401发光的显示像素驱动电路100可以集成于上述DCU中的第一芯片本体201以及PU中的电路衬底30中，因此本申请实施例提供的显示模组01相对于目前的AMOLED显示模组而言，无需制作TFT背板，能够有效减小显示模组01的重量，减薄显示模组01的厚度。另一方面，部分发光芯片401与集成芯片20层叠设置，部分发光芯片401与电路衬底30层叠设置，集成芯片20和电路衬底30均设置于电路板14的同一侧，因此提高了显示模组01的集成度。又一方面，以发光芯片401为micro LED为例，micro LED相对于OLED而言，功耗更低，有利于减小显示模组01中电池的体积。此外，micro LED相对于OLED而言，亮度更高，尺寸更小从而具有更小的开口率。这样一来，能够有效节约显示模组01中的部件空间，有利于集成更多的电子元器件。
在此基础上，为了使得显示模组01能够具有指纹识别功能，如图7A所示，上述DCU中的集成芯片20还可以包括集成于第一芯片本体201中的多个指纹像素采集电路101。此时，上述像素驱动组40可以为显示模组01用于实现显示功能以及指纹采集功能的部件的最小重复单元。在此情况下，如图7B所示，当设置于第一芯片本体201上的像素芯片组40还包括指纹采集芯片402时，设置于第一芯片本体201上的一个指纹采集芯片402可以与第一芯片本体201中的一个指纹像素采集电路101(如图7A所示)电连接。该指纹像素采集电路101用于驱动指纹采集芯片402进行指纹采集。
此外，上述PU中的电路衬底30还可以包括集成于电路衬底30中的，如图8A所示的上述指纹像素采集电路101。在此情况下，如图8B所示，当设置于衬底本体301上的像素芯片组40还包括指纹采集芯片402时，设置于衬底本体301上的一个指纹采集芯片402可以与该电路衬底30中的一个指纹像素采集电路101(如图8A所示)电连接。
在此情况下，每个像素芯片组40中的指纹采集芯片402可以作为一个指纹采集器的采集像素。这样一来，不同像素芯片组40中的多个指纹采集芯片402可以共同构成上述指纹采集器，因此无需单独在电路板14上设置指纹采集器，而是将指纹采集器的采集像素集成于每个像素芯片组40中，从而有利于提高显示模组的集成度。此时，设置集成芯片20上的像素芯片组40，或者，设置于电路衬底30上的像素芯片组40中的至少一个像素芯片组40可以包括第一发光芯片401a、第二发光芯片401b、第三发光芯片401c以及上述指纹采集芯片402。
需要说明的是，该指纹像素采集电路101可以包括多个采用CMOS工艺形成的晶体管，本申请对指纹像素采集电路101中的多个晶体管的连接方式不做限定，只要能够达到驱动与其电连接的指纹采集芯片402进行指纹采集的目的即可。
本申请对指纹采集芯片402进行指纹采集的方式不做限定。例如，该指纹采集芯片402可以采用光学方式对指纹进行采集，此时指纹采集芯片402内设置有光电转换元件，通过指纹中脊线和谷线反射光线的不同，对指纹的类别进行采集，并将采集结果传输至SoC或者CPU。或者，又例如，上述指纹采集芯片402还可以采用半导体电极与指纹中的脊线和谷线之间形成的电容(或电感)不同，对指纹进行采集，并将采集结果传输至SoC或者CPU。SoC或者CPU根据指纹采集芯片402的采集结果以及指纹采集芯片402的位置坐标可以获得指纹的图案，达到指纹采集或识别的目的。
在此基础上，为了使得显示模组01能够具有面部或者手势识别功能，上述DCU中的集成芯片20如图9A所示，还可以包括集成于第一芯片本体201中的光线发射像素驱动电路102和光线接收像素驱动电路103。示例的，可以通过CMOS工艺在制作第一芯片本体201(例如SoC、PMU、CPU、GPU、UFS或者DDR)的同时，将上述光线发射像素驱动电路102、光线接收像素驱动电路103，以及如图9A所示的显示像素驱动电路100、指纹像素采集电路101集成于该第一芯片本体201中，从而形成上述集成芯片20。
基于此，上述像素驱动组40可以为显示模组01用于实现显示功能以及面部或者手势识别功能的部件的最小重复单元。在此情况下，如图9B所示，当设置于第一芯片本体201上的像素芯片组40还包括光线发射芯片403以及光线接收芯片404时，可 以采用芯片到晶圆(die to wafer，D2W)，也可以称为(chip to wafer，C2W)的绑定(bonding)方式将光线发射芯片403设置于集成芯片20上，并与第一芯片本体201中的光线发射像素驱动电路102(如图9A所述)电连接。此外，可以采用D2W的绑定方式将光线接收芯片404设置于集成芯片20上，并与第一芯片本体201中的光线接收像素驱动电路103(如图9A所示)电连接。该光线发射像素驱动电路102用于驱动光线发射芯片403发射光线，光线接收像素驱动电路103用于驱动光线接收芯片404接收光线。
同理，当设置于集成芯片20上的像素芯片组40包括上述第一发光芯片401a、第二发光芯片401b、第三发光芯片401c、指纹采集芯片402时，可以通过巨量转移的方法，利用上述D2W的绑定方式，将第一发光芯片401a、第二发光芯片401b、第三发光芯片401c中的任意一个发光芯片设置于集成芯片20上，并与第一芯片本体201中的一个显示像素驱动电路100电连接。同理采用D2W的绑定方式，将指纹采集芯片402设置于集成芯片20上，与第一芯片本体201中的指纹像素采集电路101电连接。此时，设置集成芯片20上的至少一个像素芯片组40可以包括第一发光芯片401a、第二发光芯片401b、第三发光芯片401c、指纹采集芯片402、光线发射芯片403以及光线接收芯片404。
此外，上述PU中的电路衬底30如图10A所示，还可以包括集成于电路衬底30中的上述光线发射像素驱动电路102和光线接收像素驱动电路103。示例的，可以在如图10B所示的硅(Si)晶圆(wafer)200上，采用CMOS工艺制作光线发射像素驱动电路102和光线接收像素驱动电路103，以及上述显示像素驱动电路100、指纹像素采集电路101中的晶体管。然后，由上述可知，在制作有晶体管的晶圆200上制作上述RLD。通过该RLD中的金属走线将晶圆200中的晶体管按照设计要求进行互联，从而形成上述光线发射像素驱动电路102、光线接收像素驱动电路103，以及上述显示像素驱动电路100、指纹像素采集电路101。
在此基础上，还可以在RLD远离晶圆200的一侧表面上，制作如图10C所示的多个焊盘60。接下来，如图10D所示，当设置于PU中的像素芯片组40还包括光线发射芯片403以及光线接收芯片404时，可以采用D2W的绑定方式，通过上述焊盘60(如图10C所示)将光线发射芯片403设置于晶圆200上，并与晶圆200中的光线发射像素驱动电路102(如图10B所示)电连接。此外，采用D2W的绑定方式，通过上述焊盘60将光线接收芯片404设置于晶圆200上，并与晶圆200中的光线接收像素驱动电路103(如图10B所示)电连接。
同理，当设置于PU中的像素芯片组40包括上述第一发光芯片401a、第二发光芯片401b、第三发光芯片401c、指纹采集芯片402时，可以通过巨量转移的方法，采用上述D2W的绑定方式，通过上述焊盘60将第一发光芯片401a、第二发光芯片401b、第三发光芯片401c中的任意一个发光芯片设置于晶圆200上，并与晶圆200中的一个显示像素驱动电路100(如图10B所示)电连接。同理采用D2W的绑定方式，通过上述焊盘60将指纹采集芯片402设置于晶圆200上，并与晶圆200中的指纹像素采集电路101(如图10B所示)电连接。此时，设置于晶圆200上的至少一个PU中的像素芯片组40可以包括第一发光芯片401a、第二发光芯片401b、第三发光芯片401c、指 纹采集芯片402、光线发射芯片403以及光线接收芯片404。
接下来，如图10D所示，可以沿在晶圆200上预先设置的切割路径(CL)对晶圆200进行切割，形成如图10E所示的独立的PU。
在此情况下，每个像素芯片组40中的光线发射芯片403可以作为如图11所示的光线发射器51的像素。这样一来，不同像素芯片组40中的多个光线发射芯片403可以共同构成上述光线发射器51。因此无需单独在电路板14上设置光线发射器51，而是将光线发射器51的像素集成于每个像素芯片组40中，从而有利于提高显示模组的集成度。同理，每个像素芯片组40中的光线接收芯片404可以作为如图11所示的光线接收器52的像素。这样一来，不同像素芯片组40中的多个光线接收芯片404可以共同构成上述光线接收器52。因此无需单独在电路板14上设置光线接收器52，而是将光线接收器52的像素集成于每个像素芯片组40中，从而有利于提高显示模组的集成度。
需要说明的是，由上述可知，该光线发射像素驱动电路102和光线接收像素驱动电路103可以包括多个采用CMOS工艺形成的晶体管，本申请对光线发射像素驱动电路102和光线接收像素驱动电路103中的多个晶体管的连接方式不做限定，只要能够使得光线发射像素驱动电路102驱动与其电连接的光线发射芯片403发射光线，光线接收像素驱动电路103驱动与其电连接的光线接收芯片404接收光线即可。
示例的，本申请对采用图11所示的光线发射器51和光线接收器52，实现面部或者手势识别的方式不做限定。例如，可以通过识别结构光的变形，达到识别面部或者手势的目的。在此情况下，可以控制光线发射器51中作为像素的各个光线发射芯片403进行发光，使得光线发射器51发出具有特定图案的光线S1，当该光线照射到如图11所示的用户面部时，用户面部会对入射的光线进行反射，形成反射光S2。接下来，光线接收器52中作为像素的各个光线接收芯片404接收上述反射光S2，并进行光电转换，将光信号转换成电信号后传输至SoC或者CPU。SoC或者CPU根据光线接收器52输出的信号以及光线接收器52中各个光线接收芯片404的位置坐标，可以获得用户面部反射光S2的图案，并将该图案与光线发射器51发出的光线S1的原始图案进行比对，获得结构光的变形程度，最终达到识别用户面部(或手势)的目的。
或者，又例如，可以通过识别光线的飞行时间(time of flight，TOF)，达到识别面部或者手势的目的。在此情况下，可以控制光线发射器51中各个光线发射芯片403发出光线S1。当该光线照射到如图11所示的用户面部时，用户面部会对入射的光线进行反射，形成反射光S2。接下来，光线接收器52中各个光线接收芯片404接收用户面部的反射光S2。SoC或者CPU根据光线接收器52接收到反射光S2的时间以及光线接收器52中各个光线接收芯片404的位置坐标，获得用户面部与显示模组01之间的距离，达到识别用户面部(或手势)的目的。
在此基础上，可以将上述DCU和PU设置于上述电路板14的第一表面A1上，并与电路板14电连接，从而可以形成该显示装置01的显示屏。以电子设备02中的显示模组01具有如图9B所示的DCU，以及如图10B所示的PU，并且，DCU和PU中的像素芯片组40包括第一发光芯片401a、第二发光芯片401b、第三发光芯片401c、指纹采集芯片402、光线发射芯片403以及光线接收芯片404为例，对该显示模组01中 DCU和PU的设置方式进行举例说明。
在本申请的一些实施例中，如图12所示，用于承载上述DCU和PU的电路板14为柔性电路板(flexible printed circuit，FPC)。在此基础上，该显示装置01还可以包括转轴15。该转轴15可以设置于电路板14的第二表面A2所在的一侧。这样一来，在转轴15的作用下，可以使得电路板14在转轴15位置处进行弯折，从而使得整个显示模组01能够折叠。
在此情况下，如图13A所示，电路板14可以包括第一主视区140a、第二主视区140b、第一周边区141a、第二周边区141b以及弯折区141c。其中，弯折区141c位于第一主视区140a和第二主视区140b之间。并且，如图13B所示，转轴15在电路板14的垂直投影位于图13A所示的弯折区141c内。在此情况下，当电路板14在转轴15的作用下发生弯折时，电路板14中弯折区141c所在的部分会发生弯曲变形。此外，第一周边区141a设置于第一主视区140a的周边，第二周边区141b设置于第二主视区140b的周边。
由上述可知，DCU中的集成芯片20在电路板14上的垂直投影的面积，大于PU中电路衬底30在电路板14上的垂直投影的面积。示例的，DCU的单边尺寸为毫米级，而PU的单边尺寸为微米级。此外，电路板14在弯折的过程中，弯折区141c会发生变形。在此情况下，可以如图14A所示，将尺寸较小的PU设置于弯折区141c。由于PU的尺寸较小，因此PU与弯折区141c的接触面积相对于弯折区141c发生形变的面积而言较小，所以在弯折区141c发生弯折的过程中，不容易使得PU发生断裂，有利于提高产品的可靠性。
此外，上述电路板14的第一周边区141a和第二周边区141b位于电路板14的边缘位置。在此情况下，显示模组01在运输或使用的过程中，上述第一周边区141a和第二周边区141b容易在外力作用下，例如受到碰撞的过程中发生轻微的变形。因此，可以将尺寸较小的PU设置于第一周边区141a和第二周边区141b，从而当显示模组01在外力作用下，使得第一周边区141a和第二周边区141b发生碰撞时，不容易使得PU发生断裂，有利于提高产品的可靠性。
示例的，当沿如图10C所示的切割路径(CL)对晶圆200进行切割，以形成如图10D所示的独立的PU后，可以采用芯片到柔性电路板(chip to FPC)的工艺，通过设置于PU中衬底本体301远离像素集成组件40一侧表面上的焊盘60(如图14B所示)，将各个独立的PU焊接于如图14A所示的电路板14的第一周边区141a、第二周边区141b以及弯折区141c，以与电路板14电连接，从而可以完成PU的组装。
此外，由于DCU的尺寸较大，因此与电路板14的接触面积较大，所以可以将DCU设置于电路板14中不容易发生变形的区域，例如图13B所示的第一主视区140a和第二主视区140b。在此情况下，如图14A所示，多个PU分布于以矩阵形式排列在一起的多个DCU的周边。
在本申请的一些实施例中，当显示模组01具有多个DCU，且多个DCU之间需要相互通信时，可以将用于实现多个DCU相互通信的电路(图中未示出)制作于电路板14中，在此情况下，可以采用芯片到柔性电路板(chip to FPC)的绑定方式，如图14C所示，将每个DCU通过集成芯片20靠近电路板14一侧的焊盘60，焊接于电路板14 上与电路板14电连接，从而实现DCU的组装。
或者，在本申请的另一些实施例中，在显示模组01具有多个需要相互通信的DCU，但是电路板14中制作电路的空间有限时，如图14D所示，该显示模组01还可以包括转接板(interposer)80。转接板80与电路板14电连接，至少两个DCU设置于转接板80远离电路板14的一侧表面。该转接板80内形成有用于实现上述至少两个DCU相互通信的电路(图中未示出)。这样一来，可以先将不同DCU，通过集成芯片20内采用不同工艺节点构成的芯片本体(包括第一芯片本体201和第二芯片本体202)，采用倒装绑定工艺集成于该转接板80上形成一个集成模块。然后再将该集成模块通过设置于转接板80靠近电路板14一侧的可以通过焊球(solder ball)81绑定到电路板14上与该电路板14电连接，从而实现DCU的组装。
需要说明的是，上述采用不同工艺节点构成的芯片本体是指，不同的芯片本体在制作的过程中采用的工艺节点(例如，芯片本体中晶体管的最小线宽)不同。例如，当芯片本体为SoC时，工艺节点可以为7nm、5nm或者3nm。当芯片本体为PMU时，工艺节点可以但不限于90nm。当芯片本体为UFS时，工艺节点可以但不限于14nm。
由上述可知，当用户折叠显示模组01时，电路板14的弯折区141c会发生弯折，且该弯折区141c的形变量大于收到碰撞而发生形变的第一周边区141a和第二周边区141b的形变量。因此，为了进一步避免位于弯折区的PU发生断裂，提高显示模组01的弯折可靠性，如图15A所示，上述电路板14还包括多条设置于弯折区141c的金属走线61。
该金属走线61可以在制作电路板14的过程中一并制作而成。构成该金属走线61的材料可以为电路板14中常用的金属材料例如，金属铜。上述金属走线61呈弯曲状，例如，为S型或者为Ω型。并且，该金属走线61的两端分别与两个PU的电路衬底30相连接。当采用上述芯片到柔性电路板的绑定工艺，通过设置于电路衬底30上的焊盘60(如图14B所示)，将各个独立的PU焊接于电路板14的弯折区141c时，可以将两个PU的电路衬底30与该电路板14上的金属走线61相连接。这样一来，由于金属走线61具有一定的拉伸性能，能够随着弯折区141c的弯折而发生变形，减小由于弯折区141c形变而在PU所在位置产生的应力，达到进一步减小PU发生断裂的目的。
在本申请的一些实施例中，如图15B所示，弯折区141c中的多个PU中的电路衬底30呈矩阵形式排列。在此情况下，上述多条金属走线可以包括多条第一金属走线61a和多条第二金属走线61b。其中，第一金属走线61a沿第一方向X与相邻的两个PU中的电路衬底30相连接，第二金属走线61b沿第二方向Y与相邻的两个PU中的电路衬底30相连接。其中，第一方向与第二方向垂直。这样一来，上述多条第一金属走线61a和多条第二金属走线61b可以构成网状结构将弯折区141c中的多个PU相连接，从而能够增加弯折区141c的韧性，进一步减小PU发生断裂。
在此基础上，当上述DCU和PU均设置于电路板14上之后，如图16A所示，还可以在DCU和PU远离电路板14的一侧依次制作封装层71和盖板72。其中，封装层71覆盖上述DCU和PU，用于对DCU和PU进行保护，避免水氧侵蚀DCU和PU。盖板72可以覆盖封装层71远离电路板14的一侧表面，且与封装层71相连接，对封装层71进行保护。示例的，构成上述封装层71的材料可以为透明的树脂材料，可以 通过成膜工艺直接在DCU和PU远离电路板14的一侧表面形成一层树脂薄膜作为上述封装层71即可。
因此，相对于AMOLED显示模组采用的薄膜封装(thin film encapsulation)工艺，形成由多层交替设置的有机薄膜层和无机薄膜层构成的封装结构而言，本申请实施例提供的显示模组01的封装层71的结构和制作工艺更加简单。当显示模组01为柔性显示模组时，构成上述盖板72的材料可以为透明的树脂材料。需要说明的是，本申请实施例中的透明材料是指，该材料的透光率可以达到85％以上。
此外，上述显示模组01还可以包括如图16A所示的散热层73。其中，散热层73可以覆盖电路板14远离DCU(包括集成芯片20和像素芯片组40)和PU包括电路衬底30和像素芯片组40)的一侧表面，且与电路板14相连接。构成该散热层73的材料可以包括石墨烯。电池13可以位于散热层73远离电路板14的一侧。散热层73能够对DCU和PU中发光芯片401产生的热量，以及电池13产生的热量传递至其余部件，例如显示模组01的外壳(图中位置处)。这样一来，由于外壳与空气相接触，从而能够使得显示模组01内部的热量传递至显示模组01外部，起到散热的作用。
需要说明的是，本申请对电池13的数量不做限定，例如，如图16A所示，上述显示模组01可以包括两个电池13，分别位于转轴15的两侧。
由图16A可知，不同DCU中的第一芯片本体201可以不相同，例如图16A中所示的不同位置的第一芯片本体201可以分别为SoC、PMU、DDR以及USF。这样一来，可以使得显示模组01中集成更多不同功能的芯片。此外，由上述可知，DCU中还可以包括如图16B所示的层叠设置的第一芯片本体201和第二芯片本体202。通过将两个芯片本体层叠设置，可以进一步减小显示模组01的部件空间，从而有利于集成更多不同功能的芯片。
在此基础上，在电路板14为FPC的情况下，为了使得显示模组01中能够集成更多的附加电子元件，如图17所示，该电路板14可以包括第一部分142以及与第一部分142相连接的第二部分143。多个DCU(包括集成芯片20和像素芯片组40)和多个PU(包括电路衬底30和像素芯片组40)设置于第一部分142。在此情况下，设置于DCU和PU远离电路板14一侧的像素芯片组40在电路板14上的垂直投影可以位于该电路板14的第一部分142中。此外，第二部分143弯折于第一部分142远离DCU的一侧。
在此情况下，上述显示模组01还包括至少一个附加电子元件203，该附加电子元件203可以设置于第二部分143靠近第一部分142的表面上，且与电路板14电连接。在本申请的一些实施例中，上述附加电子元件203可以为芯片，例如SoC、PMU、CPU、GPU、UFS或者DDR等。或者，在本申请的另一些实施例中，上述附加电子元件203还可以为传感器等器件。
上述是以电路板14为FPC为例进行的说明，在本申请的另一些实施例中，该电路板14还可以为PCB。在此情况下，上述显示模组01，例如手机为不能够折叠的直板手机。此时，如图18A所示，电路板14可以包括主视区140和位于主视区140周边的周边区141。
由上述可知，由于周边区141位于主视区140的周边，显示模组01在运输或使用 的过程中，上述周边区141容易在外力作用下，例如受到碰撞的过程中发生轻微的变形。然而，位于周边区141内部的主视区140不容易在外力作用下发生变形。因此，可以将尺寸较小的PU设置于周边区141，从而当显示模组01在外力作用下，使得周边区141发生碰撞时，不容易使得PU发生断裂，有利于提高产品的可靠性。并且，将尺寸较大的DCU设置于不容易发生变形的主视区140。在此情况下，如图18B所示，多个PU(包括电路衬底30和像素芯片组40)分布于以矩阵形式排列在一起的多个DCU(包括集成芯片20和像素芯片组40)的周边。
需要说明的是，DCU和PU设置于电路板14上，且与该电路板14电连接的方式同上所述，此处不再赘述。上述均是每个DCU的像素芯片组40，以及每个PU的像素芯片组40在包括多个发光芯片(例如，如图10E所示的第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c)的基础上，还包括指纹采集芯片402、光线发射芯片403以及光线接收芯片404为例进行的说明。
在本申请的另一些实施例中，可以在显示模组01中仅需要进行指纹采集的位置的DCU和PU的像素芯片组40中设置指纹采集芯片402。同理，可以在显示模组01中，仅需要设置光线发射器51(如图11所示)的位置处的DCU和PU的像素芯片组40中，设置光线发射芯片403。在显示模组01中，仅需要设置光线接收器52(如图11所示)的位置处的DCU和PU的像素芯片组40中，设置光线发射芯片403。
此外，对于直板显示模组而言，上述封装层71和盖板72，以及散热层73和电池13的设置方式同上所述，此处不再赘述。
示例二
本示例与示例一相同，电子设备02中的显示模组01如图19所示包括电路板14。此外，与示例一的不同之处在于，该显示模组01仅包括DCU。该DCU同上所述包括集成芯片20和位于集成芯片20远离电路板14一侧表面的多个像素芯片组40。
图19以像素芯片组40包括多个发光芯片(例如，第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c)的基础上，还包括指纹采集芯片402、光线发射芯片403以及光线接收芯片404为例。在此情况下，该集成电路20可以包括集成于第一芯片本体201中的显示像素驱动电路100、指纹像素采集电路101、光线发射像素驱动电路102和光线接收像素驱动电路103。发光芯片、指纹采集芯片402、光线发射芯片403以及光线接收芯片404分别与集成于第一芯片本体201中的上述显示像素驱动电路100、指纹像素采集电路101、光线发射像素驱动电路102和光线接收像素驱动电路103电连接。上述DCU的制作过程以及DCU与电路板14电连接的过程同上所述，此处不再赘述。
同理，在本申请的一些实施例中，可以在显示模组01中仅需要进行指纹采集的位置的DCU的像素芯片组40中设置指纹采集芯片402。在显示模组01中，仅需要设置光线发射器51(如图11所示)的位置处的DCU的像素芯片组40中，设置光线发射芯片403。在显示模组01中，仅需要设置光线接收器52(如图11所示)的位置处的DCU的像素芯片组40中，设置光线发射芯片403。
此外，本示例提供的显示模组01中，上述封装层71和盖板72，以及散热层73和电池13的设置方式同上所述，此处不再赘述。
示例三
本示例与示例一相同，电子设备02中的显示模组01如图20所示包括电路板14。此外，与示例一的不同之处在于，该显示模组01仅包括PU。该PU同上所述包括电路衬底30和位于电路衬底30远离电路板14一侧表面的多个像素芯片组40。
图20以像素芯片组40包括多个发光芯片(例如，第一发光芯片401a、第二发光芯片401b以及第三发光芯片401c)的基础上，还包括指纹采集芯片402、光线发射芯片403以及光线接收芯片404为例。在此情况下，该电路衬底30可以包括集成于衬底本体301中的显示像素驱动电路100、指纹像素采集电路101、光线发射像素驱动电路102和光线接收像素驱动电路103。发光芯片、指纹采集芯片402、光线发射芯片403以及光线接收芯片404分别与集成于电路衬底30的衬底本体301中的上述显示像素驱动电路100、指纹像素采集电路101、光线发射像素驱动电路102和光线接收像素驱动电路103电连接。上述PU的制作过程以及PU与电路板14电连接的过程同上所述，此处不再赘述。
同理，在本申请的一些实施例中，可以在显示模组01中仅需要进行指纹采集的位置的PU的像素芯片组40中设置指纹采集芯片402。在显示模组01中，仅需要设置光线发射器51(如图11所示)的位置处的PU的像素芯片组40中，设置光线发射芯片403。在显示模组01中，仅需要设置光线接收器52(如图11所示)的位置处的PU的像素芯片组40中，设置光线发射芯片403。
此外，在本示例中，上述电路板14可以为PCB。或者，电路板14可以为FPC，且显示模组01包括位于电路板14远离上述PU一侧的转轴15。在此情况下，该电路板14可以具有如图21所示的第一区151、第二区152以及位于第一区151和第二区152之间的弯折区141c。同上所述，转轴15在电路板14的垂直投影位于弯折区141c。
同理，当用户折叠显示模组01时，电路板14的弯折区141c会发生弯折，且该弯折区141c的形变量大于收到碰撞而发生形变的第一周边区141a和第二周边区141b的形变量。因此，为了进一步避免位于弯折区的PU发生断裂，提高显示模组01的弯折可靠性，如图22所示，上述电路板14还包括多条设置于弯折区141c的金属走线(例如，多条第一金属走线61a和多条第二金属走线61b)。任意一条金属走线的两端分别与相邻两个PU的电路衬底30相连接。上述金属走线的形状、制作过程以及第一金属走线61a和第二金属走线61b的设置方式同上所述，此处不再赘述。
此外，如图23所示，本示例提供的显示模组01中的封装层71和盖板72，以及散热层73和电池13的设置方式同上所述，此处不再赘述。并且，当电路板14为FPC时，该电路板14可以包括第一部分142以及与第一部分142相连接的第二部分143。多个PU(包括电路衬底30和像素芯片组40)设置于第一部分142。此外，第二部分143弯折于第一部分142远离PU的一侧。显示模组01中的一些附加电子元件203，例如SoC、PMU、CPU、GPU、UFS、DDR，或者传感器等，可以设置于第二部分143靠近第一部分142的表面上，且与电路板14电连接。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为 准。

Claims (29)

  1. 一种显示模组，其特征在于，包括：
    电路板；
    集成芯片，与所述电路板电连接，所述集成芯片包括第一芯片本体以及集成于所述第一芯片本体中的多个显示像素驱动电路；
    像素芯片组，包括多个发光芯片；至少一个所述像素芯片组设置于一个所述集成芯片远离所述电路板的一侧表面；设置于所述集成芯片上的一个所述发光芯片与所述集成芯片中的一个显示像素驱动电路电连接，所述显示像素驱动电路用于驱动所述发光芯片发光。
  2. 根据权利要求1所述的显示模组，其特征在于，所述显示模组还包括：
    电路衬底，与所述电路板电连接，所述电路衬底集成有多个显示像素驱动电路；所述电路衬底在所述电路板上的垂直投影的面积，小于所述集成芯片在所述电路板上的垂直投影的面积；
    所述显示模组包括两个或者两个以上的所述像素芯片组，一个所述像素芯片组设置于一个所述电路衬底远离所述电路板的一侧表面；设置于所述电路衬底上的一个所述发光芯片与所述电路衬底中的一个所述显示像素电路电连接。
  3. 根据权利要求2所述的显示模组，其特征在于，所述电路板包括主视区和位于所述主视区周边的周边区；
    所述集成芯片设置于所述主视区；所述电路衬底设置于所述周边区。
  4. 根据权利要求2所述的显示模组，其特征在于，所述显示模组还包括转轴，所述转轴设置于所述电路板远离所述集成芯片的一侧；所述电路板为柔性电路板；所述电路板包括第一主视区、第二主视区、第一周边区、第二周边区以及弯折区；
    其中，所述弯折区位于所述第一主视区和所述第二主视区之间，且所述转轴在所述电路板的垂直投影位于所述弯折区内；所述第一周边区设置于所述第一主视区的周边，所述第二周边区设置于所述第二主视区的周边；
    所述集成芯片设置于所述第一主视区和所述第二主视区；所述电路衬底设置于所述弯折区、所述第一周边区以及所述第二周边。
  5. 根据权利要求4所述的显示模组，其特征在于，所述电路板包括多条金属走线，所述多条金属走线设置于所述弯折区；所述金属走线呈弯曲状，且所述金属走线的两端分别与两个所述电路衬底相连接。
  6. 根据权利要求5所述的显示模组，其特征在于，所述弯折区的多个所述电路衬底呈矩阵形式排列；
    所述多条金属走线包括多条第一金属走线和多条第二金属走线；所述第一金属走线沿第一方向与相邻的两个所述电路衬底相连接，所述第二金属走线沿第二方向与相邻的两个所述电路衬底相连接；其中，所述第一方向与所述第二方向垂直。
  7. 根据权利要求1-6任一项所述的显示模组，其特征在于，同一所述像素芯片组中的所述多个发光芯片包括第一发光芯片、第二发光芯片以及第三发光芯片；所述第一发光芯片、所述第二发光芯片以及所述第三发光芯片分别用于发出三原色光。
  8. 根据权利要求1-7任一项所述的显示模组，其特征在于，
    所述集成芯片还包括集成于所述第一芯片本体中的多个指纹像素采集电路；
    所述像素芯片组还包括指纹采集芯片；设置于所述集成芯片上的一个所述指纹采集芯片与所述集成芯片中的一个指纹像素采集电路电连接，所述指纹像素采集电路用于驱动所述指纹采集芯片进行指纹采集；其中，不同所述像素芯片组中的多个所述指纹采集芯片构成指纹采集器。
  9. 根据权利要求2-7任一项所述的显示模组，其特征在于，
    所述集成芯片还包括集成于所述第一芯片本体中的多个指纹像素采集电路；所述电路衬底还集成有一个所述指纹像素采集电路；
    所述像素芯片组还包括指纹采集芯片；设置于所述集成芯片上的一个所述指纹采集芯片与所述集成芯片中的一个指纹像素采集电路电连接，设置于所述电路衬底上的所述指纹采集芯片与所述电路衬底中的指纹像素采集电路电连接；所述指纹像素采集电路用于驱动所述指纹采集芯片进行指纹采集；其中，不同所述像素芯片组中的多个所述指纹采集芯片构成指纹采集器。
  10. 根据权利要求1-9任一项所述的显示模组，其特征在于，所述集成芯片还包括集成于所述第一芯片本体中的多个光线发射像素驱动电路和多个光线接收像素驱动电路；
    所述像素芯片组还包括光线发射芯片以及光线接收芯片；设置于所述集成芯片上的一个所述光线发射芯片与所述集成芯片中的一个所述光线发射像素驱动电路电连接，一个所述光线接收芯片与所述集成芯片中的一个所述光线接收像素驱动电路电连接；所述光线发射像素驱动电路用于驱动所述光线发射芯片发射光线；所述光线接收像素驱动电路用于驱动所述光线接收芯片接收光线；
    其中，不同所述像素芯片组中的多个所述光线发射芯片构成光线发射器，不同所述像素芯片组中的多个所述光线接收芯片构成光线接收器。
  11. 根据权利要求2-9任一项所述的显示模组，其特征在于，所述集成芯片还包括集成于所述第一芯片本体中的多个光线发射像素驱动电路和多个光线接收像素驱动电路；所述电路衬底还集成有一个所述光线发射像素驱动电路和一个所述光线接收像素驱动电路；
    所述像素芯片组还包括光线发射芯片以及光线接收芯片；设置于所述集成芯片上的一个所述光线发射芯片与所述集成芯片中的一个所述光线发射像素驱动电路电连接，一个所述光线接收芯片与所述集成芯片中的一个所述光线接收像素驱动电路电连接；设置于所述电路衬底上的一个所述光线发射芯片与所述电路衬底中的一个所述光线发射像素驱动电路电连接，一个所述光线接收芯片与所述电路衬底中的一个所述光线接收像素驱动电路电连接；
    所述光线发射像素驱动电路用于驱动所述光线发射芯片发射光线；所述光线接收像素驱动电路用于驱动所述光线接收芯片接收光线；
    其中，不同所述像素芯片组中的多个所述光线发射芯片构成光线发射器，不同所述像素芯片组中的多个所述光线接收芯片构成光线接收器。
  12. 根据权利要求1-11任一项所述的显示模组，其特征在于，所述第一芯片本体包括系统级芯片、电源管理单元、中央处理器、图像处理器，或者，存储芯片。
  13. 根据权利要求1-11任一项所述的显示模组，其特征在于，所述集成芯片还包括第二芯片本体；
    所述第二芯片本体与所述第一芯片本体堆叠设置，且所述第二芯片本体位于所述第一芯片本体靠近所述电路板的一侧；
    所述第二芯片本体包括系统级芯片、电源管理单元、中央处理器或者图像处理器；所述第一芯片本体包括存储芯片。
  14. 根据权利要求1所述的显示模组，其特征在于，所述电路板为柔性电路板；
    所述电路板包括第一部分以及与所述第一部分相连接的第二部分；所述像素芯片组在所述电路板上的垂直投影位于所述第一部分，所述第二部分弯折于所述第一部分远离所述像素芯片组的一侧；
    所述显示模组还包括附加电子元件，所述附加电子元件设置于所述第二部分靠近所述第一部分的表面上，且与所述电路板电连接。
  15. 根据权利要求1所述的显示模组，其特征在于，所述显示模组还包括转接板；
    所述转接板与所述电路板电连接，至少两个所述集成芯片设置于所述转接板远离所述电路板的一侧表面，且通过所述转接板电连接。
  16. 根据权利要求2所述的显示模组，其特征在于，所述电路衬底还包括依次远离所述电路板的衬底本体和重布线层，所述显示像素驱动电路的晶体管集成于所述衬底本体中，所述显示像素驱动电路中的走线集成于所述重布线层中；
    其中，所述衬底本体的材料包括单晶硅。
  17. 根据权利要求1-16任一项所述的显示模组，其特征在于，所述显示模组还包括封装层，所述封装层位于所述像素芯片组远离所述电路板的一侧，且覆盖所述集成芯片以及所述像素芯片组。
  18. 根据权利要求17所述的显示模组，其特征在于，所述显示模组还包括盖板，所述盖板覆盖所述封装层远离所述电路板的一侧表面，且与所述封装层相连接。
  19. 根据权利要求1-18任一项所述的显示模组，其特征在于，所述显示模组还包括散热层，所述散热层覆盖所述电路板远离所述像素芯片组的一侧表面，且与所述电路板相连接。
  20. 一种电子设备，其特征在于，包括电池以及如权利要求1-19任一项所述的显示模组，所述电池位于所述电路板远离所述像素芯片组的一侧。
  21. 一种显示模组，其特征在于，包括：
    电路板；
    电路衬底，与所述电路板电连接，所述电路衬底集成有多个显示像素驱动电路；
    像素芯片组，包括多个发光芯片；一个所述像素芯片组设置于一个所述电路衬底远离所述电路板的一侧表面；设置于所述电路衬底上的一个所述发光芯片与所述电路衬底中的一个所述显示像素电路电连接，所述显示像素驱动电路用于驱动所述发光芯片发光。
  22. 根据权利要求21所述的显示模组，其特征在于，所述显示模组还包括转轴，所述转轴设置于所述电路板远离所述电路衬底的一侧；所述电路板为柔性电路板；
    所述电路板包括第一区、第二区以及位于所述第一区和第二区之间的弯折区；所 述转轴在所述柔性电路板的垂直投影位于所述弯折区内；
    所述电路板包括多条金属走线，所述多条金属走线设置于所述弯折区；所述金属走线呈弯曲状，且所述金属走线的两端分别与两个所述电路衬底相连接。
  23. 根据权利要求22所述的显示模组，其特征在于，所述弯折区的多个所述电路衬底呈矩阵形式排列呈矩阵形式排列；
    所述多条金属走线包括多条第一金属走线和多条第二金属走线；所述第一金属走线沿第一方向与相邻的两个所述电路衬底相连接，所述第二金属走线沿第二方向与相邻的两个所述电路衬底相连接；其中，所述第一方向与所述第二方向垂直。
  24. 根据权利要求21-23任一项所述的显示模组，其特征在于，同一所述像素芯片组中的所述多个发光芯片包括第一发光芯片、第二发光芯片以及第三发光芯片；所述第一发光芯片、所述第二发光芯片以及所述第三发光芯片分别用于发出三原色光。
  25. 根据权利要求21-24任一项所述的显示模组，其特征在于，
    所述电路衬底还集成有指纹像素采集电路；
    所述像素芯片组还包括指纹采集芯片；设置于所述电路衬底上的一个所述指纹采集芯片与所述电路衬底中的一个所述指纹像素采集电路电连接；所述指纹像素采集电路用于驱动所述指纹采集芯片进行指纹采集；其中，不同所述像素芯片组中的多个所述指纹采集芯片构成指纹采集器。
  26. 根据权利要求21-25任一项所述的显示模组，其特征在于，所述电路衬底还集成有光线发射像素驱动电路和光线接收像素驱动电路；
    所述像素芯片组还包括光线发射芯片以及光线接收芯片；设置于所述电路衬底上的一个所述光线发射芯片与所述电路衬底中的一个所述光线发射像素驱动电路电连接，一个所述光线接收芯片与所述电路衬底中的一个所述光线接收像素驱动电路电连接；
    所述光线发射像素驱动电路用于驱动所述光线发射芯片发射光线；所述光线接收像素驱动电路用于驱动所述光线接收芯片接收光线；
    其中，不同所述像素芯片组中的多个所述光线发射芯片构成光线发射器，不同所述像素芯片组中的多个所述光线接收芯片构成光线接收器。
  27. 根据权利要求21所述的显示模组，其特征在于，所述电路衬底还包括依次远离所述电路板的衬底本体和重布线层，所述显示像素驱动电路的晶体管集成于所述衬底本体中，所述显示像素驱动电路中的走线集成于所述重布线层中；
    其中，所述衬底本体的材料包括单晶硅。
  28. 根据权利要求21所述的显示模组，其特征在于，所述电路板为柔性电路板；
    所述电路板包括第一部分以及与所述第一部分相连接的第二部分；所述电路衬底设置于所述第一部分；所述第二部分弯折于所述第一部分远离所述电路衬底的一侧；
    所述显示模组还包括附加电子元件，所述附加电子元件设置于所述第二部分靠近所述第一部分的表面上，且与所述电路板电连接。
  29. 一种电子设备，其特征在于，包括电池以及如权利要求21-28任一项所述的显示模组，所述电池位于所述电路板远离所述像素芯片组的一侧。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114883315A (zh) * 2022-07-08 2022-08-09 珠海华萃科技有限公司 一种侧边发光的led驱动芯片集成结构及制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230138918A1 (en) * 2021-10-29 2023-05-04 Avago Technologies International Sales Pte. Limited Integrated circuit package with serpentine conductor and method of making

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201910207U (zh) * 2010-11-22 2011-07-27 金建电子有限公司 一种高密度全彩led显示板
CN106409145A (zh) * 2015-07-31 2017-02-15 乐金显示有限公司 柔性显示装置及其制造方法
CN107466158A (zh) * 2017-07-28 2017-12-12 武汉华星光电技术有限公司 Cof柔性电路板及触摸显示面板
US20190013307A1 (en) * 2016-09-26 2019-01-10 Prilit Optronics, Inc. Microled display panel
CN110600463A (zh) * 2019-10-09 2019-12-20 深圳韦侨顺光电有限公司 基于芯片堆叠的集成封装led显示面板
CN111341813A (zh) * 2020-03-11 2020-06-26 上海天马微电子有限公司 显示面板及显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009053064A1 (de) * 2009-11-13 2011-05-19 Osram Opto Semiconductors Gmbh Dünnfilm-Halbleiterbauelement mit Schutzdiodenstruktur und Verfahren zur Herstellung eines Dünnfilm-Halbleiterbauelements
CN101887889B (zh) * 2010-05-20 2012-07-04 广东威创视讯科技股份有限公司 一种led集成电路模块和led显示模块
US9177500B2 (en) * 2011-01-31 2015-11-03 Global Oled Technology Llc Display with secure decryption of image signals
US9367094B2 (en) 2013-12-17 2016-06-14 Apple Inc. Display module and system applications
US9818725B2 (en) 2015-06-01 2017-11-14 X-Celeprint Limited Inorganic-light-emitter display with integrated black matrix
KR101727512B1 (ko) * 2014-11-04 2017-04-17 엘지전자 주식회사 이동 단말기
US10488887B2 (en) 2016-10-04 2019-11-26 Semiconductor Energy Laboratory Co., Ltd. Electronic device
US20180284844A1 (en) 2017-04-04 2018-10-04 Microsoft Technology Licensing, Llc Foldable display device with interactable user interface surface on the external shell
TWI708382B (zh) 2018-07-25 2020-10-21 錼創顯示科技股份有限公司 微型發光二極體顯示面板
CN208888832U (zh) * 2018-08-31 2019-05-21 Oppo广东移动通信有限公司 显示装置及电子设备
DE102019100802A1 (de) * 2019-01-14 2020-07-16 Tdk Electronics Ag LED Modul und Verwendung des LED Moduls
CN109802018B (zh) * 2019-03-27 2020-07-31 京东方科技集团股份有限公司 微发光二极管阵列基板的制作方法
CN110472547B (zh) * 2019-08-07 2021-08-27 上海天马有机发光显示技术有限公司 一种显示模组和显示装置
CN110675755B (zh) 2019-10-12 2021-08-24 武汉天马微电子有限公司 可折叠显示装置
CN211088267U (zh) 2019-12-17 2020-07-24 重庆慧库科技有限公司 Cob灯条贴装设备
CN111210729B (zh) 2020-02-28 2022-08-26 上海天马微电子有限公司 一种可折叠显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201910207U (zh) * 2010-11-22 2011-07-27 金建电子有限公司 一种高密度全彩led显示板
CN106409145A (zh) * 2015-07-31 2017-02-15 乐金显示有限公司 柔性显示装置及其制造方法
US20190013307A1 (en) * 2016-09-26 2019-01-10 Prilit Optronics, Inc. Microled display panel
CN107466158A (zh) * 2017-07-28 2017-12-12 武汉华星光电技术有限公司 Cof柔性电路板及触摸显示面板
CN110600463A (zh) * 2019-10-09 2019-12-20 深圳韦侨顺光电有限公司 基于芯片堆叠的集成封装led显示面板
CN111341813A (zh) * 2020-03-11 2020-06-26 上海天马微电子有限公司 显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4181199A4

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114883315A (zh) * 2022-07-08 2022-08-09 珠海华萃科技有限公司 一种侧边发光的led驱动芯片集成结构及制作方法
CN114883315B (zh) * 2022-07-08 2022-11-11 珠海华萃科技有限公司 一种侧边发光的led驱动芯片集成结构及制作方法

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