Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2851—Testing of integrated circuits [IC]
  • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections

Definitions

• Embodiments of the present disclosure relate to testing of substrates, particularly of large area substrates for display manufacturing.
• Embodiments relate to defect identification.
• Embodiments of the present disclosure generally relate to testing systems for large area substrates having electronic devices formed thereon and, more particularly, to line defects for the electronic devices.
• embodiments relate to a method for identifying a defect on a substrate having a plurality of pixels of a display located on the substrate, a computer readable medium containing a program for a corresponding method, and an apparatus for identifying a line defect on a substrate.
• Displays are often manufactured on large area substrates with continuously growing substrate sizes. Further, displays such as TFT-displays are subject to continuous improvement. For example, display bezels are getting narrower, OLED displays are more and more used also for laptops, desktop PC monitors and TVs besides mobile devices, and first m-LED displays are commercially available.
• Active matrix liquid crystal displays (LCDs) and OLED displays are commonly used for applications such as computer and television monitors, cell phone displays, personal digital assistants (PDAs), and an increasing number of other devices.
• an active matrix LCD or and OLED display comprises two flat plates or panels having a layer of liquid crystal materials or OLED material, respectively, sandwiched between the flat plates.
• the flat plates are typically made of glass, a polymer, or other material suitable for having electronic devices formed thereon.
• the display typically includes an array of thin film transistors (TLTs), each coupled to a pixel. Each pixel is activated by providing signals to driver circuits, such as data and gate lines and transistors, and activation of the pixel may be provided by simultaneously addressing an appropriate data line and gate line. TFTs may be switched on or off to generate an electrical field between a respective TFT and a portion of the color filter. TFTs may be switched on or off to drive a current through an OLED or m-LED. Because of the high pixel densities, the close proximity of the gate lines and data lines, and the complexity of forming the TFTs, there is a high probability of defects during the manufacturing process.
• a TFT array may be utilized for LCD displays. Yet, also OLED and m- LED displays and other displays may be based on a TFT array backplane, wherein the pixel electrode is charged to activate the pixel of the display.
• tests with a special test pattern can be executed. For example, specific tests can be provided for specific defects such as line open defects and line short defects.
• specific defects such as line open defects and line short defects.
• additional lines may be provided. The possibility of line defects increases. Accordingly, additional tests may be beneficial, which may however increase the tact time and, thus, reduce the throughput.
• a method for identifying a line defect on a substrate having a display located on the substrate includes determining a line defect with a first test, the line defect having a first orientation; setting line test parameters for a line-retest; and testing one or more first stripes oriented along the first orientation, the one or more first stripes being parallel to the line defect, the one or more first stripes have a first dimension and second dimension, the first dimension extending at least along a field of view of a charged particle beam device and the second dimension extending along only a portion of the field of view.
• an apparatus for identifying a line defect on a substrate having a plurality of pixels located thereon includes a detector configured for voltage contrast image generation on the substrate; and a computer-readable medium containing a program for identifying a line defect on a substrate having a plurality of pixels located thereon, which, when executed by a processor, performs a method according to any of the embodiments of the present disclosure.
• FIG. 1 illustrates an electron beam test apparatus that may be used for electron beam testing, in accordance with an embodiment of the present disclosure
• FIG. 2 illustrates an exemplary large area flat panel substrate having an array of thin film transistors (TFTs), each coupled to a pixel and having gate drivers and gate lines and data lines that may be tested according to embodiments described herein;
• TFTs thin film transistors
• FIGS. 3 A and 3B show tables illustrating test sequences according to embodiments of the present disclosure
• FIG. 4 shows a glass substrate having a plurality of displays manufactured on the substrate, and testing regions associated with a beam test apparatus to illustrate embodiments of the present disclosure
• FIG. 5 shows a portion of the glass substrate and a display on the substrate, respectively, to illustrate methods of identifying a defect on a substrate, particularly a line defect on the substrate, according to embodiments of the present disclosure
• FIG. 6 shows a portion of the glass substrate and a display on the substrate, respectively, to illustrate methods of identifying a defect on a substrate, particularly a line defect on the substrate, according to embodiments of the present disclosure
• FIG. 7 shows a portion of the glass substrate and a display on the substrate, respectively, to illustrate methods of identifying a defect on a substrate, particularly a line defect on the substrate, according to embodiments of the present disclosure
• FIG. 8 shows a portion of the glass substrate and a display on the substrate, respectively, to illustrate methods of identifying a defect on a substrate, particularly a line defect on the substrate, according to embodiments of the present disclosure
• FIG. 9 shows a portion of the glass substrate and a display on the substrate, respectively, to illustrate methods of identifying a defect on a substrate, particularly a line defect on the substrate, according to embodiments of the present disclosure
• FIG. 10 shows a charged particle beam device according to embodiments of the present disclosure
• FIG. 11 is a flow chart of example operations for identifying whether a line defect exists in accordance with an embodiment of the present disclosure.
• Embodiments of the present disclosure provide techniques and an apparatus for determining whether a line defect is provided within a display, and particularly to characterize the line defect.
• Embodiments of the present disclosure particularly provide an increased throughput for detection of line defects. For specific examples, a gate line open in a large, high resolution display that may commonly be detected within around 20 seconds may be detected within a time period of below two seconds. Accordingly, a significant reduction in test time can be provided.
• a line defect can be detected with a first test stripe, i.e. a reduced number of pixels that are tested, or a standard test.
• One or more subsequent second test stripes along or parallel to the detected line defects can be provided to localize and/or identify a line opening or a line short position.
• an analog scanning technique and a digital scanning technique may be distinguished.
• An analog scanning technique may include an analog sawtooth signal provided to the scanning deflector assembly with a predetermined frequency. The sawtooth signal can be combined with a continuous or quasi-continuous substrate movement to a scan area of the substrate.
• a digital scanning technique provides discrete values for x-positioning and y-positioning of the charged particle beam on the substrate and the individual pixels of a scanned image are addressed pixel-per-pixel by coordinate values, i.e. digitally.
• An analog scanning technique (“flying stage”) that may be considered preferable for semiconductor wafer SEM inspection due to the scanning speed and the reduced complexity, may allow for predetermined areas, wherein the entire area is measured.
• the areas to be scanned may be scanned digitally, i.e. by providing a list of the desired beam position coordinates. That is, specific stripes on a display or substrate may be scanned with a digital scanning technique, i.e. a digital scanner. Addressing the coordinates individually allows for variable definition of scanning areas, such as test stripes, which may increase throughput of testing a substrate.
• FIG. 1 illustrates an external view of an exemplary electron beam test system 100 (e-beam test system) that may be used for electron beam testing in connection with one or more embodiments of the disclosure.
• the electron beam test system 100 is an integrated system requiring minimum space and is capable of testing large glass panel substrates, up to and exceeding 1.25 meters by 1.5 meters, for example, up to and exceeding 2.94 meters by 3.37 meters.
• the electron beam test system 100 may include a load lock chamber 104 and a test chamber 150. Further, optionally a prober storage assembly and/or a prober transfer assembly can be provided.
• large area substrates may have a size of at least 1.375 m 2
• the size may be from about 1.375 m 2 (1100 mm x 1250 mm- GEN 5) to about 9 m 2 , more specifically from about 2 m 2 to about 9 m 2 or even up to 12 m 2 .
• the substrates or substrate receiving areas, for which the structures, apparatuses, and methods according to embodiments described herein are provided, can be large area substrates as described herein.
• a large area substrate or carrier can be GEN 5, which corresponds to about 1.375 m 2 substrates (1.1 m x 1.25 m), GEN 7.5, which corresponds to about 4.39 m 2 substrates (1.95 m x 2.25 m), GEN 8.5, which corresponds to about 5.7m 2 substrates (2.2 m x 2.5 m), or even GEN 10.5, which corresponds to about 10.5 m 2 substrates (2.94 m x 3.37 m). Even larger generations such as GEN 11 and GEN 12 and corresponding substrate areas can similarly be implemented.
• a prober storage assembly can be provided and may, for example, house one or more probers or may include prober bars near to the test chamber 150 for easy use and retrieval.
• the test chamber 150 includes a prober bar, which may adapt to various configurations or designs of displays on a large area substrate. Accordingly, specific probers for display layout on a substrate may be avoided and a prober storage assembly may also be avoided.
• the electron beam test system 100 may further include four or more electron beam test (EBT) columns 125, such as 10 or more EBT columns.
• EBT electron beam test
• the EBT columns may be disposed on an upper surface of the test chamber 150.
• certain voltages may be applied to the TFTs by using one or more probers, and the electron beam from an EBT column is directed to the individual pixels under investigation and/or to contact pads for the driver circuit.
• secondary electrons or signal electrons may provide a voltage contrast image.
• An energy fdter may be used for detection of the signal electrons to generate a voltage contrast image.
• testing of a large area substrate may include operation of two or more electron beam test columns.
• operation of neighboring test columns may be synchronized to reduce crosstalk between neighboring columns.
• Each of the electron beam test columns i.e. charged particle beam devices
• FOV field of view
• the charged particle beam device or the EBT column has a field of view with the dimension of 200 mm or above.
• a scanning electron microscope for high resolution imaging for example, for the semiconductor industry may not be a suitable apparatus for testing large area substrates with high speed, in light of the limited size of the field of view of such a device.
• a large area substrate having one or more displays disposed thereon can be transported from the load lock chamber to the test chamber.
• a first portion of a display can be provided below EBT columns, such that the first portion of the display can be tested within the fields of view of the EBT column.
• a plurality of tests can be conducted for the first portion of the display. After the tests of the first portion of the display are completed, the substrate can be moved such that a second portion of the display is provided below the test columns.
• Each of the EBT test columns can test a sub-portion of the displays with the FOV of the EBT column or the charged particle beam device.
• the area of the FOV of a charged particle beam device may also be referred to as a sub display for testing purposes.
• Each sub-display can be tested with a sequence of different tests.
• the different test may include a re-test of a main test, wherein the same test pattern as compared to the main test is generated on the sub-display.
• a re-test may confirm the result of the main test under the same conditions.
• a re-test may be conducted with a different pattern, different voltages, or different timing of the signals as compared to the main test. Accordingly, defect characterization or identifying of further defects may be provided for a re-test.
• a sequence of tests may further include different main test, wherein a re- test may optionally be provided for one or more of the main tests.
• FIG. 2 illustrates a section of a flat panel substrate 200 having a plurality of pixels 12.
• the flat panel substrate 200 is typically a flat, rectangular piece of glass, a polymer material, or other suitable material capable of having electronic devices formed thereon and typically has a large surface area.
• One or more thin film transistors 18 (TFT) and, e.g. one or more capacitors, may be associated with each pixel 12.
• the flat panel substrate 200 further includes data lines 14 and gate lines 16. Further, common lines and also other lines may be provided if necessary.
• the pixels 12, thin film transistors 18, data lines 14, and gate lines 16 may be formed on the flat panel substrate 200 by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), photolithographic methods, or other suitable fabrication processes.
• CVD chemical vapor deposition
• PECVD plasma enhanced chemical vapor deposition
• PVD physical vapor deposition
• photolithographic methods or other suitable fabrication processes.
• the driver circuits 20, for example, gate driver circuits, are connected to a respective line, for example, a gate line 16. During testing of the flat panel substrate 200, the driver circuits 20 may be operated to drive the pixels 12.
• the driver circuits 20 being gate driver circuits may be operated in combination with the operation of the data lines, i.e. signal lines.
• the data lines may be operated by an external driver circuit, by biasing one or more shorting bars, or by another operation method.
• the pixels 12 can be tested by, for example, a voltage contrast measurement determining the charge provided on a pixel.
• the transistor of a pixel 12 can be opened by applying +15 V to the gate of the transistor, a voltage of 5 V can be provided to the pixel electrode via the signal line, the transistor can be closed with a gate voltage of -15 V and with a closed transistor, a voltage of -10 V can be provided to the signal line. Without a defect such as short or open, the charge of 5 V should remain for the closed transistor on the pixel electrode.
• identification of a defect and even type may be possible.
• defects on flat panel substrates may include pixel defects, line defects and/or defects in a driver circuit.
• Pixel defects may include short to pixel gate line and short to pixel data line.
• Line defects may include line-to-line shorts (e.g., data line to data line or gate line to gate line), cross shorts (e.g., data line to gate line), and open line defects.
• Other flat circuit panels, such as printed circuit boards and multi-chip modules, may also be tested according to the various embodiments described herein.
• FIGS. 3A and 3B show tables illustrating examples of test sequences that may be provided on a substrate. Embodiments of line tests and line retests are described in more detail below. Generally, there is a sequence of tests. Optionally, for one of more tests of the sequence of tests, a retest can be provided. In the example shown in FIG. 3 A, the first test, i.e. “Test 1”, is a standard main test. Thereafter, a further main test, i.e. “Specific Test 1” or “Test 2”, is provided.
• the further main test can be provided with a different pattern on the display or sub-display, different voltages, and/or different timing, for example, delay between driving the pixels and testing the pixels.
• the above described test properties and further test properties may be referred to as test parameters.
• one or more retests can be provided.
• “Retest 1” and/or “Retest 2” can be provided, particularly under the condition based on the result of the further main test.
• the retests may be provided with the same test parameters or different test parameters.
• a yet further main test “Test 3” can be provided.
• the main test or a retest can be a line test, wherein line defects are identified by testing a stripe according to embodiments of the present disclosure.
• “Test 4” can be a specific main test for line defects.
• a retest for line defects can be provided as a retest for “Test 4”.
• identifying a line defect includes at least one retest to further characterize a line defect of the main test and/or to identify the line defect.
• the main test can be a standard main test or a specific main test in general. Further, the main test can be a line test.
• the retest for identifying a line defect is a retest of the standard main test, for example, “Test 1”. Further tests can be provided as illustrated in FIGS. 3 A and 3B and as described above.
• FIG. 4 shows a substrate, such as a flat panel substrate 200.
• six displays 402 are manufactured on the substrate.
• a plurality of fields of view or sub-displays are provided.
• Each field of view or sub-display, respectively, corresponds to a field of view of a charged particle beam device as shown in FIG. 10.
• a plurality of charged particle beam devices can be provided to simultaneously test a corresponding field of view.
• the displays can be driven, for example, by a driver circuit.
• each display can be driven from the left-hand side of the respective display and/or the right-hand side of the respective display.
• the plurality of tests of a test sequence as exemplarily shown in FIGS.
• 3 A and 3B are conducted in the fields of view or sub-displays indicated by reference numerals 420 -431. After completion of the testing of the sub-displays, the substrate can be moved as indicated by arrow 432. Further sub-displays are provided at the fields of view of the charged particle beam devices.
• the plurality of tests of a test sequence are provided for each field of view or each sub-display, respectively.
• the test results of one charged particle beam device corresponding to one FOV defines the further tests of the same charged particle beam device and the corresponding same FOV.
• the test results of different charged particle beam devices can be analyzed independent from each other.
• a method for identifying a line defect on a substrate having a plurality of pixels of a display located on the substrate includes determining a line defect with a first test, the line defect having a first orientation. After the first test, a line test pattern for a line- retest is set. At least a first stripe oriented along the first orientation is tested. For example, one or more first stripes can be tested. The one or more first stripes are parallel to the line defect. The one or more first stripes have a first dimension and second dimension, the first dimension extending at least along a field of view of a charged particle beam device and the second dimension extending along only a portion of the field of view.
• an aspect ratio between the first dimension and the second dimension may be at least 10:1, particularly at least 40: 1 , more particularly at least 100: 1.
• the stripe may have a length of at least an entire field of view or a sub-display in one dimension and may have a width of only a few 10 pixels.
• the number of pixels of a stripe tested on the sub-display, i.e. display pixels can be 200 or below, for example, 100 or below, such as about 50. Accordingly, the area to be tested is much smaller as compared to the size of the sub-display. Due to the option of digitally scanning the individual pixels, the time for an individual test or retest can be significantly reduced. Throughput of testing, for example, of testing a substrate having one or more displays, can be increased.
• a second test i.e. a retest can be executed as stripe tests parallel to the detected line defects, e.g. data line defects, of the first test.
• the software executing the test can look for line defects perpendicular to the scan direction and report the crossing point as the short position.
• FIG. 5 shows a display 402 and illustrates a test procedure according to embodiments of the present disclosure.
• FIG. 5 illustrates all test operations of a method 1100 for identifying a line defect on the substrate, which is shown in FIG. 11. Further, FIG. 5 shows the result of the method of identifying a line defect, namely a defective gate line 510 and a corresponding gate open position within the box 504. The defective gate line and the corresponding gate open position, even though shown in FIG. 5, is the result of the method for identifying the line defect, after the other test operations illustrated in FIG. 5 as described below.
• a line defect is determined with the first test.
• the first test can be a stripe test of stripe 502 shown in FIG. 1.
• the horizontal lines, for example, gate lines of the display 402 can be driven from the left-hand side in FIG. 5.
• a vertical stripe 502 is tested on the right-hand side of the display 402.
• a vertical stripe 502 is tested on the right-hand side of each sub-display 420-1 to 421-2.
• lines can be driven from a first side of the display and a stripe test can be provided on a second side of the display or sub-display, respectively, wherein the second side is opposite the first side.
• larger displays may be driven from two opposite sides because of the resistance and/or capacitance of the lines that may exceed beneficial values for large displays.
• lines such as gate lines
• lines may be driven from both sides.
• line opens such as gate line opens, cannot be detected.
• An additional test with one side only driving, e.g. one gate only testing, can be executed for line open detection.
• Such a test can be executed by a stripe test. For example, subsequent strip tests on opposite sides of a sub-display can be provided.
• a display may be small, i.e. a display may be equal to or smaller than a field of view of a charged particle beam device.
• the testing of sub displays as described herein may be performed for the testing of display, i.e. the entire area of the opto-electronic device, since the display size is entirely within the field of view.
• the first test may include testing of the first stripe, e.g. stripe 502, on the second side while the displays are driven from the opposite, first side and may include a second stripe test (not shown in FIG. 5) on the first side, while the displays are driven from the opposite, second side.
• the first test may be the main test in the form of a stripe test. The first test reveals a defective line, for example, gate line, within the box 504, i.e. the corresponding crossing position.
• line test parameters are provided for a line-retest.
• line test parameters can include a different pattern on the display or sub-, different voltages, and/or different timing, for example, a delay between driving the pixels and testing the pixels.
• the entire display is driven with one set of line test parameters during testing of one or more sub-displays.
• the defective line within the boxes 504 has a first orientation, e.g. horizontal orientation in the example of FIG. 5.
• a stripe 512 along the first orientation is tested in operation 194.
• Testing the stripe 512 can be considered a retest of the first test testing the stripe 502.
• the line test parameters set for the retest can be the same test parameters as the first test or can be different parameters.
• the stripe 512 is positioned to include the line defect determined in the box 504.
• the stripe tested may include the line defect.
• the gate open position shown in the box 514 in FIG. 5, i.e. the corresponding crossing position is revealed. Accordingly, the line defect on the substrate can be identified.
• a method for identifying a line defect on a substrate may refer to a sub-display or a field of view of a charged particle beam device, respectively.
• FIG. 5 shows four sub-displays 420-1 , 421 -1 , 420-2, and 421-2. At a first substrate position, the upper sub-displays 420-1 and 421 - 2 are tested. The first test, i.e. the first main stripe test does not reveal a defect.
• the substrate can be moved to position the display 402 below the charged particle beam devices corresponding to the two fields of view such that the lower sub-displays 420-2 and 421-2 can be tested.
• the stripe 502 is tested by subsequently testing a first portion of the stripe, i.e. an upper portion of the stripe, and a second portion of the stripe, i.e. a lower portion of the stripe.
• the line defect is determined in the box 504. That is, the corresponding crossing position is revealed.
• a subsequent retest with the stripe 512 is conducted for the lower sub-displays 420-2 and 421-2.
• the gate open position within the box 514 is identified.
• determining the line defect with the first tests may include conducting a main stripe test with one or more second stripes, for example, the stripe 502 shown in FIG. 5, oriented along a second orientation different from the first orientation, the one or more second stripes having a first dimension and second dimension.
• the second stripe i.e. a stripe 502 is perpendicular to the line defect.
• the second dimension extends at least along the field of view of the charged particle beam device and the first dimension extending along only a portion of the field of view.
• an aspect ratio between the first dimension and the second dimension may be at least 10:1, particularly at least 40:1, more particularly at least 100:1.
• the stripe may have a length of at least an entire field of view or sub-display in one dimension and may have a width of only a few 10 pixels.
• the first main stripe test may include driving a display from a first side of the display and testing the second stripe at a second side of the display opposing the first side.
• the first main stripe test may further include driving the display from the second side of the display and testing a third stripe at the first side of the display.
• identifying the line defect may include locating a crossing position between a first line and a second line. At least the first stripe and or the second stripe can be scanned with a digital scanner. Flexibility of defining various stripes for the sub-displays or the fields of view, respectively, can be provided by the digital scanner to provide flexible improvement of the throughput for testing.
• FIG. 6 shows another example of a method for identifying a line defect on a substrate having one or more displays on the substrate.
• FIG. 6 shows a display 402 as a portion of the substrate.
• sub-displays indicated by reference numerals 420 to 424 are shown.
• the upper row of sub displays shows the situation for testing below a plurality of fields of view.
• the middle row of sub displays shows a situation for subsequent testing below the plurality of fields of view.
• the lower row of sub-displays shows a situation for even further subsequent testing below the fields of view.
• a testing sequence is described with respect to the testing of one display of one or more displays on a substrate. It is to be understood that the test sequence can, according to embodiments of the present disclosure, be provided for a sub-display.
• a standard main test reveals the gate line defect of the gate line 510.
• the standard main test includes testing of an entire field of view for the respective sub-displays.
• determining the line defect with the first test includes setting main test parameters different from the line test parameters.
• the first test may include testing the field of view with an extension along the field of view in the first dimension and the second dimension.
• a retest of the standard main test see for example FIG. 3B, can be provided to test the stripe 512. The retest, i.e. testing at least a first stripe along the first orientation of the gate line 510, reveals the data line 610 and the crossing position within the box 514.
• FIG. 7 shows a further example of a method for identifying a line defect on the substrate with a stripe test.
• the first test is a standard main test revealing a vertical line, for example, a data line 712 as being defective.
• Test line parameters are set for a line-retest.
• the data line 712 indicated by the standard main test is a vertical line in the example shown in FIG. 7.
• Three stripes 713 are tested in a retest.
• the stripe 713 are parallel to the data line 712.
• the at least first stripe tested based upon the main test is parallel to the line defect of the first test and/or excludes the line defect tested by the first tests.
• the at least first drive can be a plurality of stripes within the field of view.
• FIG. 7 shows the stripes 713 extending within an upper field of view.
• the stripes may extend along the display. According to some embodiments, which can be combined with other embodiments described herein, a stripe extends along the sub-display. Particularly, since each sub-display is tested individually, a stripe according to embodiments of the present disclosure extends along the sub display.
• the defective gate line 710 is revealed in the retest by the stripe 713 as indicated by the boxes 714.
• the test shown in FIG. 7 can identify a data-com short defect.
• FIG. 8 refers to testing of a display 402. Similar to the embodiments described above, sub displays indicated by reference numerals 420 - 424 are tested individually. Reference is made to testing of the display 402. The sub-displays can be tested separately. When testing the various sub displays, particularly simultaneously, the upper sub-displays, indicated by reference numerals 420 - 424, and after movement of the substrate that centers the sub-displays and the lower sub-displays within a corresponding field of view of a charged particle beam device, the main test with horizontal stripes, such as stripes 512, revealed a data line 712 as a line defect. The data line 712 provides a crossing position within the boxes 813.
• testing of a stripe 713 particularly of a stripe 713 including the boxes 813, reveals a crossing position with a gate line 510 within the box 814.
• the test shown in FIG. 8 can identify a Com-Shield short defect.
• FIG. 9 shows an example for a main test being a stripe test.
• the order of directions or orientations being tested is swapped.
• the first sub-displays 420-1 to 424-1 are tested with respective fields of view with stripe 713.
• the second sub-displays 420-2 to 424-2 are tested with respective fields of view with the stripe 713.
• the third sub-displays 420-3 to 424-3 are tested with respective fields of view with the stripe 713.
• a line defect for the gate line 510 is detected. This is indicated by the boxes 514.
• the boxes 514 are disposed within the sub-displays 421-3 to 424-3.
• the gate line 510 is a horizontal gate line shown in FIG. 9.
• a stripe retest is provided within the sub-displays 421-3 to 424-3 determining the line defect of the first test with the stripe 713.
• the stripe retest can be provided by stripes 512.
• the stripe retest reveals the data line 712 with a crossing position within the box 914.
• a line defect of the gate line 512 has not occurred in the sub-display 420-3 and the sub-displays having the reference numeral suffix “-1” and “-2”. Accordingly, the stripe 512 is not provided in these sub-displays.
• the test shown in FIG. 9 can identify a Com-Shield short defect, wherein a vertical stripe is provided as the main test.
• the samples described herein refer to gate lines being oriented horizontally and data lines being oriented vertically. Further, orientations of lines of the display can be provided and may particularly be perpendicular to each other. Embodiments of the disclosure are not limited to horizontal gate lines and vertical data lines. Gate lines may be oriented vertically and data lines may be oriented horizontally. Further, further lines may be oriented horizontally and/or vertically. Further, lines on a display are generally described to be either vertical or horizontal. According to embodiments of the present disclosure, the lines to be tested for a line defect can be provided in any other arbitrary coordinate system.
• FIG. 10 illustrates an electron beam (e-beam) test apparatus, e.g. a charged particle beam device 900 for localizing defects, e.g. of a pixel and/or a line, associated with malfunctioning pixels of a large area substrate, such as a TFT array.
• the charged particle beam device can be an EBT column.
• power to a charged particle beam gun e.g. an e-beam gun, may be supplied from a power supply.
• the controller may also control operation (e.g., through executable software) of deflection elements (e.g., deflection coils or plates) in an effort to scan the electron beam to individual pixels of the pixel array fabricated on the TFT array or to scan for a generation of a voltage contrast image, e.g. an SEM image.
• deflection elements e.g., deflection coils or plates
• a detector may be provided to sense the voltage from signal particles, e.g. backscattered or secondary electrons.
• FIG. 10 shows a charged particle beam device or a charged particle beam device 900.
• the charged particle beam device or the charged particle beam microscope has a field of view with the dimension of 200 mm or above.
• a person skilled in the art will appreciate that a scanning electron microscope for high resolution imaging for example, for the semiconductor industry may not be a suitable apparatus for testing large area substrates with high speed in light of the limited size of the field of view of such a device.
• An electron beam (dotted line) may be generated by the electron beam source 912.
• further beam shaping elements like a suppressor, an extractor, and/or an anode may be provided.
• the electron beam source can include a TFE emitter.
• the gun chamber may be evacuated to a pressure of 10 8 mbar to 10 9 mbar. Even though reference in examples is made to a scanning electron beam device, a charged particle beam device in general may be utilized.
• a condenser lens can be provided in a further vacuum chamber 920 of the column of the charged particle beam device 900, e.g. an EBT column.
• Further electron optical elements can be provided in the further vacuum chamber.
• the further electron optical elements can be selected from the group consisting of: a stigmator, correction elements for chromatic and/or spherical aberrations.
• the primary electron beam or primary charged particle beam can be focused on the substrate 200 by the objective lens 924.
• the substrate 200 is positioned on a substrate position on the substrate support 935.
• signal electrons for example, secondary and/or backscattered electrons, and/or x-rays, are released from the substrate 200, which can be detected by a detector 940.
• a voltage contrast filter such as a grid 941 can be provided.
• the grid 941 can be biased to a potential, allowing electrons above a certain voltage to pass through the grid while repelling electrons with an energy below the corresponding voltage.
• a voltage can be provided to the substrate (the provided voltages can be shifted) to generate a field on secondary electrons for energy filtering, i.e. to generate a voltage contrast image.
• a condenser lens 923 is provided.
• the objective lens 924 can have a magnetic lens component having pole pieces, and having a coil.
• the objective lens focuses the primary electron beam on the substrate 200.
• the objective lens can be an electrostatic-magnetic compound lens having e.g. an axial gap or a radial gap, or the objective lens can be an electrostatic retarding field lens.
• a scanning deflector assembly can be provided.
• the scanning deflector assembly can, for example, be a magnetic and/or an electrostatic scanning deflector assembly, which is configured for high pixel rates.
• the scanning deflector assembly may be a single stage assembly. Alternatively, also a two-stage or even a three-stage deflector assembly can be provided for scanning. Each stage may be provided at a different position along the optical axis.
• a magnetic scanning deflector 971 and an electrostatic scanning deflector 972 can be combined.
• the combination of a magnetic scanning deflector and an electrostatic scanning deflector allows for a large field of view, for example, provided by the magnetic scanning deflector. Further, within the larger field of view, a sub-region of the field of view can be scanned at a faster speed with the electrostatic scanning deflector. Accordingly, fast image acquisition can be provided by the combination of a magnetic scanning deflector and an electrostatic scanning deflector.
• the magnetic scanning deflector can steer the beam to the sub- region.
• the electrostatic scanning deflector can scan the beam within the sub-region, for example with the resolution of 20 pm or below, such as 5 pm. After the sub-region has been scanned, the magnetic scanning deflector can steer the beam to a further region, which is in turn scanned by the electrostatic scanning deflector. Accordingly, precision of the magnetic scanning deflector can be combined with the lack of magnetic hysteresis (and a corresponding reduced scanning speed) of the electrostatic deflector.
• the charged particle beam device 900 shown in FIG. 9 includes a detector 940.
• the detector 940 includes a scintillator arrangement and, for example, a photo multiplier.
• the charged particle beam device and/or a testing system including the charged particle beam device includes a controller 930, the controller being connected to the charged particle beam device with signal line 932 to provide a control of the charged particle beam device or EBT column for identifying line defects with a stripe test according to embodiments of the present disclosure.
• the controller of the charged particle beam device and/or the testing system may include a central processing unit (CPU), a memory and, for example, support circuits.
• the CPU may be one of any form of general-purpose computer processor that can be used in an industrial setting for controlling various components and sub processors.
• the memory is coupled to the CPU.
• the memory, or a computer readable medium may be one or more readily available memory devices such as a random access memory, a read only memory, a floppy disk, a hard disk, or any other form of digital storage either local or remote.
• the support circuits may be coupled to the CPU for supporting the processor in a conventional manner.
• Test process instructions and/or instructions for identification of line defects may be stored in the memory as a software routine typically known as a recipe.
• the software routine may also be stored and/or executed by a second CPU that is remotely located from the hardware being controlled by the CPU.
• the software routine when executed by the CPU, transforms the general-purpose computer into a specific purpose computer (controller) that controls the charged particle beam device, and can provide for identification of line defects, according to any of the embodiments of the present disclosure.
• controller specific purpose computer
• the embodiments may be implemented in software as executed upon a computer system, and hardware as an application specific integrated circuit or other type of hardware implementation, or a combination of software and hardware.
• the controller may execute or perform a method for identifying a defect on a substrate having a plurality of pixels of a display located on the substrate, for example, for display manufacturing, according to embodiments of the present disclosure.
• the methods of the present disclosure can be conducted using computer programs, software, computer software products and the interrelated controllers, which can have a CPU, a memory, a user interface, and input and output devices being in communication with the corresponding components of the apparatus.
• Methods for testing a display substrate particularly during manufacturing of the display, i.e. before the manufacturing process is completed, and corresponding apparatuses typically include testing of lines and/or of the substrate pixels. Determining a malfunctioning pixel in a large area substrate, such as a liquid crystal display (LCD) panel or an OLED panel, may be based on the pixel, the driver circuit for that pixel, the line (gate line, signal line or other lines), or a combination of the above. Further, localizing line defects is beneficial, particularly with a reduced testing time period.
• LCD liquid crystal display
• an apparatus for identifying a line defect on a substrate having a plurality of pixels located thereon includes a detector configured for voltage contrast image generation on the substrate and a computer-readable medium containing a program for identifying a line defect on a substrate having a plurality of pixels located thereon, which, when executed by a processor, performs a method according to any the embodiments of the present disclosure.
• Testing of a line defect on a substrate may include voltage contrast imaging.
• a scanning electron microscope image including voltage contrast executed by an EBT column may be provided.
• a stripe test can additionally be provided as a high-resolution scan, i.e. an imaging scan as compared to a pixel scan.
• the high-resolution scan can be provided along one or more lines, such as data lines, gate lines, or other lines, in order to assist in localizing short positions.
• Shorts along parallel lines may be difficult to localize, because typically only one coordinate (either gate or data) can be clearly identified.
• a high-resolution (e.g. 5 pm pixel pitch) stripe image along the detected data or gate line can be provided.
• the defect position may be found by comparing the image of the line next to each pixel to that of the neighboring pixel. At the short position, the image may deviate from the non-defect neighborhood. Accordingly, identifying of line defects can be further improved by high -resolution images.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Theoretical Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• General Engineering & Computer Science (AREA)
• Analysing Materials By The Use Of Radiation (AREA)
• Computer Vision & Pattern Recognition (AREA)
• Signal Processing (AREA)
• Health & Medical Sciences (AREA)
• Life Sciences & Earth Sciences (AREA)
• Chemical & Material Sciences (AREA)
• Analytical Chemistry (AREA)
• Biochemistry (AREA)
• General Health & Medical Sciences (AREA)
• Immunology (AREA)
• Pathology (AREA)

Priority Applications (3)

Applications Claiming Priority (1)

Publications (1)

Family

ID=71833323

Family Applications (1)

Country Status (3)

Citations (3)

• 2020
  • 2020-07-23 KR KR1020237006180A patent/KR20230041789A/ko not_active Application Discontinuation
  • 2020-07-23 CN CN202080104842.5A patent/CN116134328A/zh active Pending
  • 2020-07-23 WO PCT/EP2020/070841 patent/WO2022017608A1/en active Application Filing

Patent Citations (3)

Also Published As

Similar Documents

Legal Events