WO2022016525A1 - 编码方法和编码装置 - Google Patents

编码方法和编码装置 Download PDF

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Publication number
WO2022016525A1
WO2022016525A1 PCT/CN2020/104496 CN2020104496W WO2022016525A1 WO 2022016525 A1 WO2022016525 A1 WO 2022016525A1 CN 2020104496 W CN2020104496 W CN 2020104496W WO 2022016525 A1 WO2022016525 A1 WO 2022016525A1
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Prior art keywords
code stream
image
coefficient
encoded
coefficients
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PCT/CN2020/104496
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English (en)
French (fr)
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缪泽翔
郑萧桢
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深圳市大疆创新科技有限公司
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Priority to CN202080005730.4A priority Critical patent/CN112913242B/zh
Priority to PCT/CN2020/104496 priority patent/WO2022016525A1/zh
Publication of WO2022016525A1 publication Critical patent/WO2022016525A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

Definitions

  • the present application relates to the field of encoding and decoding, and more particularly, to an encoding method and an encoding device.
  • JPEG XR Joint Photographic Experts Group Extended Range
  • the JPEG XR code stream structure can be composed of tag image file format (Tagged Image File Format, TIFF) encapsulation information, image header (Image_header) information, index table (Index_table) and the code stream of each tile.
  • tag image file format Tagged Image File Format, TIFF
  • Image_header image header
  • Index_table index table
  • the code stream of each macroblock in the tile can be divided into DC coefficient (Direct Current Coefficient, DC Coefficient), Low Pass Coefficient (LP Coefficient), High Pass Coefficient (High Pass Coefficient, HP Coefficient) and Variable cutoff coefficients (FLEX coefficients) are stored independently.
  • DC coefficient Direct Current Coefficient, DC Coefficient
  • LP Coefficient Low Pass Coefficient
  • High Pass Coefficient High Pass Coefficient
  • HP Coefficient High Pass Coefficient
  • FLEX coefficients Variable cutoff coefficients
  • JPEG XR is encoded in macroblock units.
  • the encoder outputs the corresponding DC coefficients, LP coefficients, HP coefficients, and FLEX coefficients for each macroblock after encoding. code stream.
  • To arrange the output sequence of the encoded code stream into the code stream storage sequence many times of code stream handling are required, and many times of data read and write operations are a huge burden on both software and hardware.
  • Embodiments of the present application provide an encoding method and an encoding device, which can reduce the number of code stream transfers, and further, can improve encoding efficiency.
  • the present application provides an encoding method, including: acquiring multiple code stream components of an image to be encoded, each of the multiple code stream components including a transform coefficient of the image to be encoded.
  • code stream storing the plurality of code stream components in order of the types of the transform coefficients.
  • the present application provides an encoding apparatus, including: a processor, where the processor is configured to: acquire multiple code stream components of an image to be encoded, where each code stream component of the multiple code stream components includes the A code stream of transform coefficients of the image to be encoded; the multiple code stream components are stored in the order of the types of the transform coefficients.
  • an encoding apparatus including a processor and a memory.
  • the memory is used for storing a computer program
  • the processor is used for calling and running the computer program stored in the memory to execute the method in the above-mentioned first aspect or each implementation manner thereof.
  • a chip is provided for implementing the method in the above-mentioned first aspect or each of its implementation manners.
  • the chip includes: a processor for invoking and running a computer program from a memory, so that a device installed with the chip executes the method in the first aspect or each of its implementations.
  • a computer-readable storage medium for storing a computer program, the computer program comprising instructions for performing the method in the first aspect or any possible implementation of the first aspect.
  • a computer program product comprising computer program instructions, the computer program instructions causing a computer to execute the method in the first aspect or each implementation manner of the first aspect.
  • the multiple code stream components of the image to be encoded are stored in the order of the types of transform coefficients, in the encoding process, the number of code stream transfers can be reduced, and further, the encoding efficiency can be improved.
  • FIG. 1 is an architectural diagram of applying the technical solution of the embodiment of the present application.
  • FIG. 2 is a schematic diagram of a video coding framework 2 according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of processing an image according to five levels from large to small when processing an image by JPEG XR provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a JPEG XR encoder provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of forming a transform coefficient based on a macroblock according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a code stream structure provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an example of an index table of an image code stream including two tiles according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of another code stream structure provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an encoding method provided by an embodiment of the present application.
  • FIG. 10a is a schematic diagram of dividing an image to be encoded according to an embodiment of the present application.
  • FIG. 10b is a schematic diagram of dividing an image to be encoded according to another embodiment of the present application.
  • FIG. 10c is a schematic diagram of dividing an image to be encoded according to another embodiment of the present application.
  • FIG. 10d is a schematic diagram of a to-be-coded image division provided by yet another embodiment of the present application.
  • FIG. 11 is a schematic diagram of a code stream generation provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a code stream storage form provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of an encoding method provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of an example of calculating a new index table for an image code stream including two tiles according to another embodiment of the present application.
  • FIG. 15 is a schematic diagram of a code stream storage form provided by another embodiment of the present application.
  • FIG. 16 is a schematic diagram of an example of calculating a new index table for an image code stream including two tiles according to another embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of an encoding apparatus provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • FIG. 1 is an architectural diagram of applying the technical solution of the embodiment of the present application.
  • the system 100 may receive data 102 to be processed, process the data 102 to be processed, and generate processed data 108 .
  • system 100 may receive data to be encoded and encode the data to be encoded to generate encoded data, or system 100 may receive data to be decoded and decode the data to be decoded to generate decoded data.
  • components in system 100 may be implemented by one or more processors, which may be processors in computing devices or processors in mobile devices (eg, drones).
  • the processor may be any type of processor, which is not limited in this embodiment of the present invention.
  • the processor may include an encoder, a decoder, or a codec, among others.
  • One or more memories may also be included in system 100 .
  • the memory may be used to store instructions and data, for example, computer-executable instructions, data to be processed 102 , processed data 108 , etc. that implement the technical solutions of the embodiments of the present invention.
  • the memory may be any type of memory, which is also not limited in this embodiment of the present invention.
  • the data to be encoded may include text, images, graphic objects, animation sequences, audio, video, or any other data that needs to be encoded.
  • the data to be encoded may include sensory data from sensors, which may be visual sensors (eg, cameras, infrared sensors), microphones, near-field sensors (eg, ultrasonic sensors, radar), position sensors, temperature sensor, touch sensor, etc.
  • the data to be encoded may include information from the user, eg, biometric information, which may include facial features, fingerprint scans, retinal scans, voice recordings, DNA sampling, and the like.
  • FIG. 2 is a schematic diagram of a video coding framework 2 according to an embodiment of the present application.
  • each frame of the video to be encoded is encoded in sequence.
  • the current coded frame mainly undergoes: prediction (Prediction), transformation (Transform), quantization (Quantization) and entropy coding (Entropy Coding), etc., and finally outputs the code stream of the current coded frame.
  • the decoding process usually decodes the received code stream according to the inverse process of the above process, so as to recover the video frame information before decoding.
  • the video coding framework 2 includes a coding control module 201 for performing decision control actions and parameter selection in the coding process.
  • the encoding control module 201 controls parameters used in transformation, quantization, inverse quantization, and inverse transformation, controls selection of intra-frame mode or inter-frame mode, and parameter control of motion estimation and filtering, And the control parameters of the encoding control module 201 will also be input into the entropy encoding module to be encoded to form a part of the encoded code stream.
  • the coded frame is divided 202, and specifically, the coded frame is divided into slices first, and then divided into blocks.
  • the coded frame is divided into a plurality of non-overlapping largest CTUs, and each CTU can also be iteratively divided into a series of smaller codes in a quad-tree, binary-tree, or ternary-tree manner.
  • a unit (Coding Unit, CU), in some examples, a CU may also include a prediction unit (Prediction Unit, PU) and a transform unit (Transform Unit, TU) associated with it, where PU is the basic unit of prediction, and TU is the transform and basic units of quantification.
  • Prediction Unit PU
  • Transform Unit Transform Unit
  • PUs and TUs are obtained by dividing into one or more blocks on the basis of CUs, wherein one PU includes multiple prediction blocks (Prediction Blocks, PBs) and related syntax elements.
  • the PU and the TU may be the same, or may be obtained by the CU through different partitioning methods.
  • at least two of the CUs, PUs, and TUs are the same, eg, CUs, PUs, and TUs are not distinguished, and all are predicted, quantized, and transformed in units of CUs.
  • the CTU, CU or other formed data units are hereinafter referred to as coding blocks.
  • a data unit targeted for video coding may be a frame, a slice, a coding tree unit, a coding unit, a coding block, or a group of any of the above.
  • the size of the data unit may vary.
  • a prediction process is performed to remove redundant information in the spatial and temporal domains of the current coded frame.
  • the commonly used predictive coding methods include intra-frame prediction and inter-frame prediction. Intra-frame prediction only uses the reconstructed information in this frame to predict the current coding block, while inter-frame prediction uses the information in other frames (also called reference frames) that have been reconstructed before to predict the current coding block. Make predictions.
  • the encoding control module 201 is configured to decide whether to select intra-frame prediction or inter-frame prediction.
  • the process of intra-frame prediction 203 includes obtaining the reconstructed block of the coded adjacent blocks around the current coding block as a reference block, and using the prediction mode method to calculate the prediction value based on the pixel value of the reference block to generate the prediction block. , the corresponding pixel values of the current coding block and the prediction block are subtracted to obtain the residual of the current coding block.
  • the residual of the current coding block is transformed 204 , quantized 205 and entropy encoded 210 to form the code stream of the current coding block. Further, after all the coded blocks of the current coded frame are subjected to the above coding process, a part of the coded code stream of the coded frame is formed.
  • the control and reference data generated in the intra prediction 203 are also encoded by entropy encoding 210 to form part of the encoded code stream.
  • the transform 204 is used to de-correlate the residuals of image blocks in order to improve coding efficiency.
  • two-dimensional discrete cosine transform Discrete Cosine Transform, DCT
  • two-dimensional discrete sine transform Discrete Sine Transform, DST
  • quantization 205 is used to further improve the compression efficiency.
  • the transform coefficients can be quantized to obtain quantized coefficients, and then the quantized coefficients are entropy encoded 210 to obtain the residual code stream of the current encoding block.
  • the entropy encoding method includes: But not limited to content adaptive binary arithmetic coding (Context Adaptive Binary Arithmetic Coding, CABAC) entropy coding.
  • CABAC Context Adaptive Binary Arithmetic Coding
  • the bit stream obtained by entropy encoding and the encoded encoding mode information are stored or sent to the decoding end.
  • inverse quantization 206 is also performed on the quantized result, and inverse transformation 207 is performed on the inverse quantization result.
  • the reconstructed pixels are obtained using the inverse transformation result and the motion compensation result. Afterwards, the reconstructed pixels are filtered (ie loop filtered) 211. After 211, the filtered reconstructed image (belonging to the reconstructed video frame) is output. Subsequently, the reconstructed image can be used as a reference frame image for other frame images for inter-frame prediction. In this embodiment of the present application, the reconstructed image may also be referred to as a reconstructed image or a reconstructed image.
  • the coded adjacent blocks in the process of intra-frame prediction 203 are: adjacent blocks that have been coded before the current coded block is coded, and the residuals generated in the coding process of the adjacent blocks are transformed 204, quantized 205, After inverse quantization 206 and inverse transform 207, the reconstructed block is obtained by adding the prediction block of the adjacent block.
  • inverse quantization 206 and inverse transform 207 are inverse processes of quantization 206 and transform 204, and are used to restore residual data before quantization and transform.
  • the inter prediction process when the inter prediction mode is selected, the inter prediction process includes motion estimation (Motion Estimation, ME) 208 and motion compensation (Motion Compensation, MC) 209 .
  • the encoder can perform motion estimation 208 according to the reference frame image in the reconstructed video frame, and search for the image block most similar to the current encoding block in one or more reference frame images as the prediction block according to certain matching criteria,
  • the relative displacement between the prediction block and the current coding block is the motion vector (Motion Vector, MV) of the current coding block.
  • the original value of the pixel of the coding block is subtracted from the pixel value of the corresponding prediction block to obtain the residual of the coding block.
  • the residual of the current coded block is transformed 204, quantized 205 and entropy coded 210 to form a part of the coded code stream of the coded frame.
  • motion compensation 209 may be performed based on the motion vector and prediction block determined above to obtain the current coding block.
  • the reconstructed video frame is a video frame obtained after filtering 211 .
  • the reconstructed video frame includes one or more reconstructed images.
  • Filtering 211 is used to reduce compression distortions such as blocking and ringing effects during the encoding process.
  • the reconstructed video frame is used to provide reference frames for inter-frame prediction during the encoding process.
  • the reconstructed video frame is post-processed and output. for the final decoded video.
  • the inter prediction mode may include an advanced motion vector prediction (Advanced Motion Vector Prediction, AMVP) mode, a merge (Merge) mode, or a skip (skip) mode.
  • AMVP Advanced Motion Vector Prediction
  • merge Merge
  • skip skip
  • the motion vector prediction can be determined first. After the MVP is obtained, the starting point of the motion estimation can be determined according to the MVP, and a motion search can be performed near the starting point. After the search is completed, the optimal MV, the position of the reference block in the reference image is determined by the MV, the reference block is subtracted from the current block to obtain the residual block, the MV is subtracted from the MVP to obtain the Motion Vector Difference (MVD), and the difference between the MVD and the MVP is obtained.
  • the index is transmitted to the decoder through the code stream.
  • the MVP can be determined first, and the MVP can be directly determined as the MV of the current block.
  • a MVP candidate list (merge candidate list) can be constructed first.
  • the MVP candidate list at least one candidate MVP can be included, and each candidate MVP can have an index corresponding to the MVP candidate list.
  • the MVP index can be written into the code stream, and the decoder can find the MVP corresponding to the index from the MVP candidate list according to the index, so as to decode the image block.
  • Skip mode is a special case of Merge mode. After the MV is obtained according to the Merge mode, if the encoder determines that the current block is basically the same as the reference block, it does not need to transmit the residual data, only the index of the MVP needs to be passed, and further a flag can be passed, which can indicate that the current block can be directly Obtained from the reference block.
  • the image block to be encoded can be divided into a plurality of sub-image blocks in the shape of a polygon, and a motion vector can be determined for each sub-image block from the motion information candidate list, and based on the The motion vector determines the prediction sub-block corresponding to each sub-image block, and constructs the prediction block of the current image block based on the prediction sub-block corresponding to each sub-image block, so as to realize the encoding of the current image block.
  • the decoding end perform operations corresponding to the encoding end.
  • the residual information is obtained by entropy decoding, inverse quantization and inverse transformation, and according to the decoded code stream, it is determined whether the current image block uses intra-frame prediction or inter-frame prediction. If it is intra-frame prediction, use the reconstructed image blocks in the current frame to construct prediction information according to the intra-frame prediction method; if it is inter-frame prediction, you need to parse out the motion information, and use the parsed motion information in the reconstructed image. Then, the prediction information and the residual information are superimposed, and the reconstruction information can be obtained through the filtering operation.
  • encoding video based on the video encoding framework 2 shown in FIG. 2 can save space or traffic occupied by video image storage and transmission.
  • the uncompressed raw image data collected by the camera occupies a large storage space, with a resolution of 3840 ⁇ 2160 and a storage format of YUV4:2:2 (where Y represents brightness and UV represents chromaticity)
  • YUV4:2:2 where Y represents brightness and UV represents chromaticity
  • JPEG XR is a continuous tone still image compression algorithm and file format, also known as HD Photo or Network Media Photo (Windows Media Photo), developed by Microsoft and part of the Windows Media family. It supports lossy data compression as well as lossless data compression, and is the preferred image format for Microsoft's XML paper specification (XPS) document, where XML is Extensible Markup Language (Extensible Markup Language).
  • XPS XML paper specification
  • XML Extensible Markup Language
  • Currently supported software includes .NET framework (version 3.0 or later), operating system (windows vista/windows 7), Internet Explorer (IE) 9, flashplayer 11, etc.
  • JPEG XR is an image codec that can implement high dynamic range image encoding and only requires integer operations during compression and decompression. It can support monochrome, Red Green Blue (RGB), Cyan Magenta Yellow Black (CMYK), 16-bit unsigned integer or 32-bit fixed-point or floating-point multi-channel color format images, and it also supports RGBE Radiance image format . It can optionally embed an International Color Consortium (ICC) color profile for color consistency across devices.
  • ICC International Color Consortium
  • the alpha channel can represent the degree of transparency, and supports Exchangeable Image File (EXIF) and Extensible Metadata Platform (XMP) metadata formats. This format also supports multiple images in one file. Only partial decoding of the image is supported. For some specific operations such as cropping, downsampling, horizontal and vertical flipping, or rotation, the entire image does not need to be decoded.
  • Figure 3 shows a schematic diagram of processing an image according to five levels from large to small when JPEG XR provides an embodiment of the present application to process an image.
  • the figure includes an image (image), a tile (tile), a macro block (Macro Block, MB), a block (block), and a pixel (pixel).
  • One of the images can consist of one or more tiles. If a tile is on the right or bottom edge of the image, it can be padded to an integer number of macroblocks (16x16).
  • Each macroblock may contain 16 4x4 blocks, and each block may contain 4x4 pixels.
  • JPEG XR performs a two-stage transform on the reconstructed low-pass blocks in each 4x4 block and 16x16 macroblock.
  • FIG. 4 is a schematic structural diagram of a JPEG XR encoder provided in an embodiment of the present application.
  • the JPEG XR encoder may include five modules: a filtering module 410, a transform module 420, a quantization module 430, a prediction module 440, and an entropy encoding module 450.
  • the functions of these five modules are similar to the functions of the modules involved in the above-mentioned FIG. 2 . similar.
  • the filtering module 410 can reduce the block effect of the decoded and reconstructed image by smoothing between adjacent pixels; the transform module 420 can convert the image information from the spatial domain to the frequency domain, and remove some redundant information in the spatial domain; the quantization module 430 can convert the frequency domain
  • the coefficients are reduced to reduce the magnitude of the coefficients to be encoded, and the degree of reduction of the coefficient magnitudes depends on the size of the specified quantization parameter (Quantization Parameter, QP);
  • the prediction module 440 can remove adjacent blocks by predicting between some coefficients of adjacent blocks The correlation between the partial coefficients; the entropy encoding module 450 can encode the finally obtained coefficients into a binary code stream.
  • JPEG XR The transformation of JPEG XR is an integer-based transformation, and each macroblock can participate in two stages of transformation. Transforms can all be done based on 4x4 blocks. As shown in FIG. 5 , it is a schematic diagram of forming a transform coefficient based on a macroblock according to an embodiment of the present application.
  • the macroblock may include 16 blocks, and the first stage transform may be applied to the 16 blocks within the macroblock, resulting in 16 LP coefficients and 240 HP coefficients, ie each of the 16 blocks Each yields one LP coefficient and 15 HP coefficients.
  • the second-stage transformation is applied to the reconstructed block of 16 LP coefficients obtained in the first stage, and the 16 LP coefficients are transformed again to finally generate 1 DC coefficient and 15 LP coefficients.
  • JPEG XR supports two ways: spatial mode code stream arrangement and frequency (frequency) mode code stream arrangement. Since this application relates to frequency mode, only the code stream storage form related to frequency mode is described here.
  • FIG. 6 it is a schematic diagram of a code stream structure provided by an embodiment of the present application.
  • the JPEG XR code stream structure can be composed of TIFF encapsulation information, image header information, index table and the code stream of each tile, where n can represent that the image is divided into n tiles, m represents Tile 1 contains m macroblocks.
  • the code stream of each macroblock in a tile can be stored independently according to DC coefficient, LP coefficient, and HP coefficient.
  • the HP coefficient can be split into two parts for encoding, so two parts of the code stream in the final code stream are derived from the HP coefficient, that is, the HP and FLEX parts can be derived from the HP coefficient.
  • the image header information can store some information of the image, such as width, height, and image format.
  • index table What is stored in the index table is the starting address of each frequency band code stream of each tile (calculated by the number of bytes relative to DC1). It should be noted that the meaning of each data in the index table is immutable according to the standard and can be arranged in the following order: DC1 starting address, LP1 starting address, HP1 starting address, FLEX1 starting address, DC2 starting address, LP2 starting address, HP2 starting address, FLEX2 starting address...DCn starting address, LPn starting address, HPn starting address, FLEXn starting address.
  • index table value it can be calculated according to the formulas (1) to (4), where n represents the number of tiles in the image, i represents the ith tile, and length_X_y represents the yth tile in the X frequency band.
  • the bitstream length in bytes of the tile.
  • index_table_LP_i index_table_DC_i+length_DC_i (2)
  • index_table_HP_i index_table_LP_i+length_LP_i (3)
  • index_table_FLEX_i index_table_HP_i+length_HP_i (4)
  • FIG. 7 it is a schematic diagram of an example of an index table of an image code stream including two tiles.
  • the index table is arranged in the order of the DC start address, LP start address, HP start address and FLEX start address of each tile.
  • tile 1 and tile 2 in the above FIG. 7 may include multiple macroblocks. Taking tile 1 as an example, if tile 1 includes m macroblocks, the starting address of DC1 may be The starting address of macroblock 1 in tile 1.
  • the code stream of the frequency mode of JPEG XR is stored in the format shown in Figure 6, the encoding of JPEG XR is performed in units of macroblocks.
  • the corresponding DC coefficients, LP coefficients, HP coefficients, and FLEX coefficient code streams are output, and the code streams generated by each macroblock in a tile in a natural order can be arranged as shown in the schematic diagram in FIG. 8 .
  • the present application proposes an encoding method, which can reduce the number of code stream transfers, and further, can improve the encoding efficiency.
  • the encoding method 900 may include steps 910-920.
  • each code stream component of the multiple code stream components includes a code stream of a transform coefficient of the image to be encoded.
  • the multiple code stream components in this embodiment of the present application may include DC coefficient code stream components, LP coefficient code stream components, HP coefficient code stream components, and FLEX coefficient code stream components.
  • the multiple code stream components in this embodiment of the present application may include the code stream of DC coefficients, the code stream of LP coefficients, the code stream of HP coefficients, and the code stream of FLEX coefficients mentioned above.
  • storing the multiple code stream components in the order of the types of the transform coefficients may refer to storing the multiple code stream components according to the DC coefficient code stream components, LP coefficient code stream components, Either the HP coefficient code stream components and the FLEX coefficient code stream components are stored in order.
  • the DC coefficient code stream components, the LP coefficient code stream components, the HP coefficient code stream components, and the FLEX coefficient code stream components may be stored in this order, or the HP coefficient code stream components, the DC coefficient code stream components, and the LP coefficient code stream components may be stored in the order
  • the digital stream components and the FLEX coefficient code stream components are stored in this order, and can also be stored in the order of LP coefficient code stream components, HP coefficient code stream components, DC coefficient code stream components, LP coefficient code stream components, and FLEX coefficient code stream components. Storage, etc., is not restricted.
  • the multiple code stream components of the image to be encoded are stored in the order of the types of transform coefficients, in the encoding process, the number of code stream transfers can be reduced, and further, the encoding efficiency can be improved.
  • the image to be encoded includes n tiles, the i-th tile in the n tiles includes several macroblocks, and the same transformation of the several macroblocks
  • the code streams of the coefficients are arranged in sequence to form the code stream of the same kind of transform coefficients of the i-th tile, and the code streams of the same kind of transform coefficients of the n tiles are sequentially arranged to form the code stream of the image to be encoded.
  • n tiles in the embodiments of the present application may be images of the same size, that is, when the to-be-coded image is divided, the to-be-coded image may be divided into equal parts; the n tiles may also be images of different sizes, that is When dividing the to-be-coded image, the to-be-coded image may not be divided into equal parts.
  • FIG. 10a it is a schematic diagram of dividing an image to be encoded according to an embodiment of the present application.
  • two tiles can be obtained by vertically dividing the image to be encoded from the center of the image to be encoded, namely tile 1 (ie 10a-1) and tile 2 (ie 10a-2).
  • tile 1 ie 10a-1
  • tile 2 ie 10a-2
  • the sizes of the two divided tiles are the same, that is, it can be understood that the number of pixels included in the two divided tiles is the same.
  • FIG. 10b it is a schematic diagram of dividing an image to be encoded according to another embodiment of the present application.
  • Two tiles may be obtained by horizontally dividing the to-be-coded image from the center of the to-be-coded image, namely, tile 1 (ie, 10b-1) and tile 2 (ie, 10b-2). It can be seen that the sizes of the two divided tiles are the same.
  • FIG. 10c it is a schematic diagram of dividing an image to be encoded according to another embodiment of the present application. Still taking n as 2 as an example, two tiles can be obtained by vertically dividing the to-be-coded image from the center of the to-be-coded image, namely tile 1 (ie 10c-1) and tile 2 (ie 10c-2) . It can be seen that the sizes of the two divided tiles are different, that is, it can be understood that the numbers of pixels included in the two divided tiles are different.
  • FIG. 10d it is a schematic diagram of dividing an image to be encoded according to another embodiment of the present application. Still taking n as 2 as an example, two tiles can be obtained by horizontally dividing the to-be-coded image from the center of the to-be-coded image, namely tile 1 (ie 10d-1) and tile 2 (ie 10d-2) . It can be seen that the sizes of the two divided tiles are different.
  • tile 1 ie 10a-1
  • tile 2 ie 10a-2
  • the code stream of the DC coefficients of the block can be sequentially arranged to form the code stream of the DC coefficients of tile 1
  • the code stream of the LP coefficients of the 16*16 macroblocks can be formed by sequentially arranging the code stream of the LP coefficients of the tile 1.
  • the code stream of HP coefficients of these 16*16 macroblocks can be sequentially arranged to form the codestream of HP coefficients of tile 1, and the codestream of FLEX coefficients of these 16*16 macroblocks can be formed by sequentially arranging the code stream Codestream of FLEX coefficients for slice 1.
  • the code stream of DC coefficients of these 16*16 macroblocks can be sequentially arranged to form the codestream of DC coefficients of tile 2.
  • the code stream of coefficients can be sequentially arranged to form the code stream of LP coefficients of tile 2
  • the code stream of HP coefficients of these 16*16 macroblocks can be formed by sequentially arranging the code stream of HP coefficients of tile 2.
  • the code stream of FLEX coefficients of 16*16 macroblocks can be sequentially arranged to form a code stream of FLEX coefficients of tile 2.
  • sequentially arranging the code streams of the same transform coefficients of the two tiles can form the code streams of the same transform coefficients of the image to be encoded, that is, for the two tiles.
  • the code stream of the DC coefficients of the tiles can be sequentially arranged to form the code stream of the DC coefficients of the image to be encoded
  • the code streams of the LP coefficients of the two tiles can be sequentially arranged to form the code stream of the LP coefficients of the image to be encoded.
  • Sequentially arranging the code streams of HP coefficients of the two tiles can form the code stream of the HP coefficients of the image to be coded, and arranging the code streams of the FLEX coefficients of the two tiles in sequence can form the code stream of the FLEX coefficients of the image to be coded. code stream.
  • the code streams of the same transform coefficients of several macroblocks included in each of the n tiles are arranged in order A code stream of the same transform coefficient of the corresponding tile is formed, and the code stream of the same transform coefficient of the n tiles is sequentially arranged to form a code stream of the same transform coefficient of the image to be encoded.
  • the acquiring multiple code stream components of the image to be encoded includes: for each macroblock of the image to be encoded, outputting code streams of different kinds of transform coefficients to different The buffer space is used to obtain code streams of different kinds of transform coefficients of the image to be encoded in different buffer spaces.
  • FIG. 11 it is a schematic diagram of a code stream generation provided by an embodiment of the present application.
  • the JPEG XR encoder can no longer compactly arrange the code streams of DC coefficients, LP coefficients, HP coefficients, and FLEX coefficients in a macroblock when outputting the code stream, but output them to 4 independent buffer spaces respectively, and
  • the DC coefficients between macroblocks and the codestream components of the DC coefficients are in a compact arrangement of the codestream bytes
  • the LP coefficients between the macroblocks and the codestream components of the LP coefficients are in a compact arrangement of the codestream bytes
  • the HP coefficients between the macroblocks It is compactly arranged with the codestream byte of the codestream component of the HP coefficient
  • the FLEX coefficients between macroblocks and the codestream of the codestream component of the FLEX coefficient are aligned and compactly arranged.
  • the code streams of the DC coefficients and the code stream components of the DC coefficients between the above-mentioned macroblocks are compactly arranged according to byte alignment, and the code stream components of the DC coefficients of the next macroblock may be immediately after the code stream components of the DC coefficients of the previous macroblock. ; Similarly, the LP coefficients between macroblocks and the codestreams of the codestream components of the LP coefficients are aligned and compactly arranged, and the codestream components of the LP coefficients of the next macroblock can be adjacent to the codestream of the LP coefficients of the previous macroblock.
  • the HP coefficients between macroblocks and the codestream byte of the codestream component of the HP coefficients are aligned and compactly arranged, and the codestream component of the HP coefficients of the next macroblock can be immediately adjacent to the HP coefficients of the previous macroblock.
  • the FLEX coefficients between macroblocks are aligned and compactly arranged with the code stream bytes of the code stream component of the FLEX coefficients, and the code stream component of the FLEX coefficients of the next macroblock can be immediately adjacent to the FLEX of the previous macroblock.
  • the code stream components of the DC coefficients, LP coefficients, HP coefficients, and FLEX coefficients between each tile are also arranged separately.
  • the DC coefficient code stream components of tile 2 can be connected to the DC system of tile 1.
  • the LP coefficient code stream component of tile 2 can be connected to the LP coefficient code stream component of tile 1
  • the HP coefficient code stream component of tile 2 can be connected to the HP coefficient code stream component of tile 1.
  • the FLEX coefficient code stream component of tile 2 can be connected to the FLEX coefficient code stream component of tile 1, and so on, until the successive arrangement of the coefficient code stream components of tile n is completed.
  • the macroblocks in tile 1 can be arranged in the following order.
  • the DC coefficient code stream component of macroblock 2 in tile 1 can be output to the first buffer space, and succeeded after the DC coefficient code stream component of macroblock 1 in tile 1 ;
  • the LP coefficient code stream component of macroblock 2 in tile 1 can be output to the second buffer space, and it is connected after the LP coefficient code stream component of macroblock 2 of tile 1; the macroblock 2 in tile 1 can be used.
  • the HP coefficient code stream component of block 2 is output to the third buffer space, and is followed by the HP coefficient code stream component of macroblock 2 of tile 1; the FLEX coefficient code stream component of macroblock 2 in tile 1 can be output To the fourth buffer space, and following the FLEX coefficient codestream component of macroblock 2 of tile 1. This is followed by analogy until the output of each coefficient code stream component of all macroblocks (m macroblocks) in tile 1 is completed.
  • the DC coefficient code stream component of macroblock 1 in tile 2 can be output to the first buffer space first, and then the DC coefficient code stream component of macroblock m in tile 1 can be connected After that; output the LP coefficient code stream component of macroblock 1 in tile 2 to the second buffer space, and continue after the LP coefficient code stream component of macroblock m in tile 1; the macroblock in tile 2
  • the HP coefficient code stream component of 1 is output to the third buffer space, and succeeds the HP coefficient code stream component of macroblock m in tile 1;
  • the FLEX coefficient code stream component of macroblock 1 in tile 2 is output to the third buffer space.
  • the four buffer spaces are followed by the FLEX coefficient code stream component of macroblock m in tile 1; and so on, until the output of each coefficient code stream component of all macroblocks in tile 2 is completed.
  • the output can be performed in the manner of tile 2 above, and for brevity, details are not repeated here.
  • the code stream storage form shown in FIG. 6 is to store the DC coefficients, LP coefficients, HP coefficients, and FLEX coefficient code streams in each tile in a centralized manner, and the components between the tiles are stored in a centralized manner.
  • the code streams are spaced apart from each other.
  • FIG. 12 is a schematic diagram of a code stream storage form provided by an embodiment of the application.
  • the DC coefficient, LP coefficient, HP coefficient, and FLEX coefficient in tile 1 are shown in the left figure in FIG. 12 .
  • the digital stream is compactly stored, and the DC coefficient, LP coefficient, HP coefficient, and FLEX coefficient code stream in tile 2 are compactly stored, but the DC coefficient code stream of tile 1 and the DC coefficient code stream of tile 2 are stored at intervals.
  • the new storage form is shown in the right graph in Figure 12.
  • the DC coefficient code streams of all tiles are stored in a centralized manner, and the LP coefficient codes of all tiles Streams are centrally stored, HP coefficient code streams of all tiles are centrally stored, and FLEX coefficient code streams of all tiles are centrally stored.
  • the advantage of the new code stream storage form (the code stream storage form shown in the figure on the right in Figure 12) is that it only needs to code the DC coefficients, LP coefficients, HP coefficients, and FLEX coefficients of each tile shown in Figure 11.
  • the streams are transported once each (4 times in total) and spliced together to obtain the code stream shown in the graph on the right side of Figure 12.
  • the codestreams of all DC coefficients (including tile 1, tile 2, . . . , tile n) shown in
  • the code stream is transferred after the code stream of all LP coefficients. Therefore, the conversion from the code stream format shown in FIG. 11 to the code stream storage format shown in the graph on the right side of FIG. 12 can only require 4 code stream transfers.
  • the code streams of all LP coefficients shown in FIG. 11 may also be moved to a suitable location, and then the code streams of all DC coefficients shown in FIG. 11 may be moved before the code streams of all LP coefficients. After the code stream of all HP coefficients shown in FIG. 11 is transferred to the code stream of all LP coefficients, finally the code stream of all FLEX coefficients shown in FIG. 11 can be transferred to the code stream of all LP coefficients. Therefore, the conversion from the code stream format shown in FIG. 11 to the code stream storage format shown in the graph on the right side of FIG. 12 still only requires 4 code stream transfers.
  • the encoding method provided by the embodiment of the present application provides a new code stream generation method and a new code stream storage form, which can complete the code stream handling in only 4 times, thereby reducing the number of code stream handling times, and further , which can improve the coding efficiency.
  • the method further includes: storing the code stream of the transform coefficients in the buffer space into a preset storage device.
  • the code stream of the multiple transform coefficients may be stored in a preset storage device, for example, may be stored in a hard disk space or a safe Digital (Secure Digital, SD) cards and other storage media are not limited.
  • a preset storage device for example, may be stored in a hard disk space or a safe Digital (Secure Digital, SD) cards and other storage media are not limited.
  • FIG. 13 is a schematic diagram of an encoding method provided by an embodiment of the present application.
  • the encoder encodes the to-be-encoded image
  • the code streams of different transform coefficients of the to-be-encoded image can be respectively cached in different buffer spaces, and finally can be uniformly stored in a preset storage device.
  • the method further includes: generating information of the to-be-coded image, where the to-be-coded image information includes TIFF encapsulation information of the to-be-coded image, the to-be-coded image information The image header information of the encoded image, the index table of the to-be-encoded image, and the code stream of the to-be-encoded image.
  • the information of the to-be-coded image may further include TIFF encapsulation information, image header information, and an index table of the to-be-coded image.
  • the image header information may store some information of the image to be encoded, for example, the width, height, and image format of the image to be encoded.
  • the index table of the image to be coded can store the starting address of each frequency band code stream of each tile included in the image to be coded, for example, the starting address of the DC coefficient code stream of each tile, the LP coefficient code stream of each tile. , the starting address of the HP coefficient code stream of each tile, and the starting address of the FLEX coefficient code stream of each tile.
  • the solutions provided by the embodiments of the present application can ensure the integrity of the encoding of the to-be-encoded image.
  • the method further comprises: setting an index of a multi-stream component of the image to be encoded.
  • the image to be encoded includes n tiles
  • the setting the indices of multiple codestream components of the image to be encoded includes: according to each of the n tiles
  • the length of each code stream component in the plurality of code stream components of the tile, the index of the plurality of code stream components of the n tiles is set according to the preset component order, and the preset component order is the DC coefficient code stream component , LP coefficient code stream component, HP coefficient code stream component and FLEX coefficient code stream component
  • n is a positive integer greater than 1 or equal to 1.
  • each data in the index table is immutable according to the standard and can be arranged in the following order: DC1 start address, LP1 start address, HP1 start address, FLEX1 start address, DC2 start address, LP2 start address Start address, HP2 start address, FLEX2 start address....
  • the present application proposes a new index table calculation method, as shown in the following equations (5) to (8).
  • the code stream lengths of the DC1 coefficient, LP1 coefficient, HP1 coefficient, and FLEX1 coefficient of tile 1 are a, b, c, and d, respectively; DC2 of tile 2
  • the code stream lengths of coefficients, LP2 coefficients, HP2 coefficients, and FLEX2 coefficients are e, f, g, and h, respectively.
  • the starting address of DC1 is 0, the starting address of LP1 is a+e, the starting address of HP1 is a+e+b+f, and the starting address of FLEX1 is a+e+b+f+ c+g, DC2 starting address is a, LP2 starting address is a+e+b, HP2 starting address is a+e+b+f+c, FLEX2 starting address is a+e+b+f +c+g+d.
  • FIG. 14 it is a schematic diagram of a new index table calculation example for an image code stream containing two tiles.
  • the index table is still arranged in the order of the DC start address, LP start address, HP start address and FLEX start address of each tile Yes, only the data in the index table has changed.
  • the new storage code stream is in the form of DC1, DC2, LP1, LP2, HP1, HP2, FLEX1, FLEX2, but the order in the index table needs to comply with the standard, the values in the index table will be correspondingly change.
  • the code stream length of each coefficient in tile 1 and tile 2 is consistent with the code stream length in FIG. 7 above, namely the DC1 coefficient, LP1 coefficient, HP1 coefficient, and FLEX1 coefficient of tile 1.
  • the code stream lengths are respectively a, b, c, and d; that is, the code stream lengths of the DC2 coefficient, LP2 coefficient, HP2 coefficient, and FLEX2 coefficient of tile 2 are e, f, g, and h, respectively.
  • the starting address of DC1 is 0, the starting address of LP1 is a+e, the starting address of HP1 is a+e+b+f,..., the starting address of FLEX2 is a+e+ b+f+c+g+d+h.
  • the lengths of the DC1 coefficient, LP1 coefficient, HP1 coefficient, and FLEX1 coefficient of tile 1 are 10, 12, 8, and 9, respectively;
  • the lengths of the DC2 coefficient, LP2 coefficient, HP2 coefficient, and FLEX2 coefficient are 11, 16, 10, and 13, respectively.
  • the values of the index tables of tile 1 and tile 2 can be obtained, that is, the starting address of DC1 is 0, the starting address of LP1 is 21, the starting address of HP1 is 49, and the starting address of FLEX1
  • the starting address of LP2 is 67, the starting address of DC2 is 10, the starting address of LP2 is 33, the starting address of HP2 is 57, and the starting address of FLEX2 is 89.
  • storing multiple code stream components in the order of the types of transform coefficients may refer to the DC coefficient code stream components, LP coefficient code stream components, HP coefficient code stream components, and FLEX included in the above-mentioned multiple code stream components.
  • the coefficient code stream components are stored in any order.
  • the code stream is stored in the order of DC coefficient, LP coefficient, HP coefficient, and FLEX coefficient.
  • the storage order of DC coefficient, LP coefficient, HP coefficient, and FLEX coefficient can be freely adjusted.
  • HP coefficient DC coefficient
  • LP coefficient LP coefficient
  • FLEX coefficient the order of HP coefficient, DC coefficient, LP coefficient, and FLEX coefficient is used as an example for description.
  • FIG. 15 is a schematic diagram of a code stream storage form provided by an embodiment of the application.
  • the HP coefficient, DC coefficient, LP coefficient, and FLEX coefficient in tile 1 are shown in the left figure in FIG. 15 .
  • the code stream is compactly stored, and the code stream of the HP coefficient, DC coefficient, LP coefficient, and FLEX coefficient in tile 2 is compactly stored, but the code stream of the DC coefficient of tile 1 and the code stream of the DC coefficient of tile 2 are spaced stored.
  • the new storage form is shown in the right graph in Figure 15.
  • the HP coefficient code streams of all tiles (including tile 1, tile 2, ..., tile n) are stored in a centralized manner, and the DC coefficient codes of all tiles are stored in a centralized manner.
  • the streams are stored centrally, the LP coefficient code streams of all tiles are centrally stored, and the FLEX coefficient code streams of all tiles are centrally stored.
  • the advantage of the new code stream storage form (the code stream storage form shown in the figure on the right in Figure 15 ) is that it only needs to convert the DC coefficient, LP coefficient, HP coefficient, The code streams of the FLEX coefficients are transported once each (4 times in total) and spliced together to obtain the code stream shown in the graph on the right side of Figure 15.
  • the code stream of all HP (including tile 1, tile 2, .
  • the code stream of all HP coefficients is transferred to the code stream of all HP coefficients, and then the code stream of all LP coefficients shown in Figure 11 is transferred to the code stream of all DC coefficients, and finally the code stream of all FLEX coefficients shown in Figure 11 can be transferred.
  • the conversion from the code stream format shown in FIG. 11 to the code stream storage format shown in FIG. 15 can only require 4 code stream transfers.
  • the encoding method provided by the embodiment of the present application can reduce the number of times of code stream handling by using a new code stream generation method and a new code stream storage form, and further, can improve the encoding efficiency.
  • each data in the index table is immutable according to the standard, they are arranged in the following order: DC1 starting address, LP1 starting address, HP1 starting address, FLEX1 starting address, DC2 starting address, LP2 starting address Start address, HP2 start address, FLEX2 start address... .
  • the data stored in the index table must still conform to the above order when the storage format of the code stream is changed.
  • the present application proposes a new index table calculation method, as shown in the following equations (9) to (12).
  • FIG. 16 it is a schematic diagram of a new index table calculation example for an image code stream containing 2 tiles.
  • the index table is still arranged in the order of the DC start address, LP start address, HP start address and FLEX start address of each tile , only the data in the index table has changed.
  • the code stream lengths of the DC1 coefficient, LP1 coefficient, HP1 coefficient, and FLEX1 coefficient in tile 1 are still a, b, c, and d, respectively;
  • the code stream lengths of the DC2 coefficient, LP2 coefficient, HP2 coefficient, and FLEX2 coefficient are still e, f, g, and h, respectively.
  • the starting address of DC1 is c+g
  • the starting address of LP1 is c+g+a+e
  • the starting address of HP1 is 0, and the starting address of FLEX1 is c+g+a+e+ b+f
  • the starting address of DC2 is c+g+a
  • the starting address of LP2 is c+g+a+e+b
  • the starting address of HP2 is c
  • the starting address of FLEX2 is c+g+a+e +b+f+d.
  • FIG. 16 it is a schematic diagram of a new index table calculation example for an image code stream containing 2 tiles.
  • the index table is still arranged in the order of the DC start address, LP start address, HP start address and FLEX start address of each tile Yes, only the data in the index table has changed.
  • the new storage code stream is in the form of DC1, DC2, LP1, LP2, HP1, HP2, FLEX1, FLEX2, but the order in the index table needs to comply with the standard, the values in the index table will be correspondingly change.
  • the code stream length of each coefficient in tile 1 and tile 2 is consistent with the code stream length in Figure 7 above, that is, the DC1 coefficient, LP1 coefficient, HP1 coefficient, and FLEX1 coefficient of tile 1.
  • the code stream lengths are respectively a, b, c, and d; that is, the code stream lengths of the DC2 coefficient, LP2 coefficient, HP2 coefficient, and FLEX2 coefficient of tile 2 are e, f, g, and h, respectively.
  • the starting address of DC1 is c+g
  • the starting address of LP1 is c+g+a+e
  • the starting address of HP1 is 0,...
  • the starting address of FLEX2 is c+g+ a+e+b+f+d.
  • the code stream lengths of the DC1 coefficient, LP1 coefficient, HP1 coefficient, and FLEX1 coefficient of tile 1 are 10, 12, 8, and 9, respectively;
  • the code stream lengths of the DC2 coefficient, LP2 coefficient, HP2 coefficient, and FLEX2 coefficient of slice 2 are 11, 16, 10, and 13, respectively.
  • the values of the index tables of tile 1 and tile 2 can be obtained, that is, the starting address of DC1 is 18, the starting address of LP1 is 39, the starting address of HP1 is 0, and the starting address of FLEX1
  • the starting address of LP2 is 67, the starting address of DC2 is 28, the starting address of LP2 is 51, the starting address of HP2 is 8, and the starting address of FLEX2 is 89.
  • the method may further include: sending the index of the multi-stream component of the to-be-encoded image to the decoder, so that the decoder assigns the index of the multi-stream component to the decoder according to the index of the multi-stream component. decode the image to be encoded.
  • the encoder may send the index of the multi-stream component of the image to be encoded to the decoder.
  • the decoder may The index of the multi-stream component to decode the image to be encoded.
  • the encoding method is applied in the JPEG XR encoding format.
  • the JPEG XR encoding format is a continuous-tone still image compression algorithm and file format that can support lossy data compression as well as lossless data compression.
  • the JPEG XR encoding format has certain advantages over the JPEG encoding format.
  • JPEG uses 8-bit encoding, enabling 256 colors, while JPEG can use 16-bit or more, providing better results and more editing flexibility.
  • the JPEG XR encoding format uses a more efficient compression algorithm.
  • the image quality can be twice that of the latter, or the same quality is only half the volume of the latter.
  • JPEG XR's highest-quality compression allows for no loss of information.
  • FIG. 17 is a schematic structural diagram of an encoding apparatus 1700 according to an embodiment of the present application.
  • the encoding apparatus 1700 may include a processor 1710 .
  • Processor 1710 is used to:
  • each of the multiple code stream components includes a code stream of a transform coefficient of the image to be encoded; assigning the multiple code stream components according to the The types of transform coefficients are stored sequentially.
  • the image to be encoded includes n tiles, the i-th tile in the n tiles includes several macroblocks, and the same transformation of the several macroblocks
  • the code streams of the coefficients are arranged in sequence to form the code stream of the same kind of transform coefficients of the i-th tile, and the code streams of the same kind of transform coefficients of the n tiles are sequentially arranged to form the code stream of the image to be encoded. the code stream of the same transform coefficient;
  • n is a positive integer greater than or equal to 1
  • i is a positive integer less than or equal to n.
  • the processor 1710 is further configured to: for each macroblock of the to-be-encoded image, output the code streams of different kinds of transform coefficients to different buffer spaces, respectively, in different buffer spaces.
  • the code streams of different kinds of transform coefficients of the to-be-coded image are respectively obtained from the buffer space.
  • the processor 1710 is further configured to: store the code stream of the transform coefficients in the buffer space into a preset storage device.
  • the processor 1710 is further configured to: generate information of the image to be encoded, where the information of the image to be encoded includes image file format encapsulation information (TIFF encapsulation) of the image to be encoded information), the image header information of the image to be encoded, the index table of the image to be encoded, and the code stream of the image to be encoded.
  • the information of the image to be encoded includes image file format encapsulation information (TIFF encapsulation) of the image to be encoded information
  • TIFF encapsulation image file format encapsulation information
  • the transform coefficients include DC coefficients (DC coefficients), low pass coefficients (LP coefficients), high pass coefficients (HP coefficients) and variable truncation coefficients (FLEX coefficients).
  • the processor 1710 is further configured to: set an index of the multi-stream component of the image to be encoded.
  • the to-be-coded image includes n tiles
  • the processor 1710 is further configured to: according to a plurality of code stream components of each of the n tiles In the length of each code stream component, the index of the multiple code stream components of the n tiles is set according to the preset component order, and the preset component order is DC coefficient code stream component, LP coefficient code stream component, HP Coefficient code stream component and FLEX coefficient code stream component, n is a positive integer greater than 1 or equal to 1.
  • the processor 1710 is further configured to: send the index of the multi-stream component of the to-be-encoded image to the decoder, so that the decoder can determine the index of the multi-stream component according to the index of the multi-stream component. Decoding the to-be-encoded image.
  • the encoding device is applied in the JPEG XR encoding format.
  • the encoding apparatus 1700 may further include a memory 1720 .
  • the encoding apparatus 1700 may further include components generally included in other video processing apparatuses, for example, the transceiver 1730, which is not limited in this embodiment of the present application.
  • Memory 1720 is used to store computer-executable instructions.
  • the processor 1710 is configured to access the memory 1720 and execute the computer-executable instructions, so as to perform the operations in the video processing methods of the embodiments of the present application.
  • the encoding device can be, for example, an encoder, a terminal (including but not limited to a mobile phone, a camera, an unmanned aerial vehicle, etc.), and the encoding device can implement the corresponding processes in the various methods of the embodiments of the present application. For brevity, It is not repeated here.
  • FIG. 18 is a schematic structural diagram of a chip according to an embodiment of the present application.
  • the chip 1800 shown in FIG. 18 includes a processor 1810, and the processor 1810 can call and run a computer program from the memory to implement the method in the embodiment of the present application.
  • the chip 1800 may further include a memory 1820 .
  • the processor 1810 may call and run a computer program from the memory 1820 to implement the methods in the embodiments of the present application.
  • the memory 1820 may be a separate device independent of the processor 1810, or may be integrated in the processor 1810.
  • the chip 1800 may further include an input interface 1830 .
  • the processor 1810 can control the input interface 1830 to communicate with other devices or chips, and specifically, can obtain information or data sent by other devices or chips.
  • the chip 1800 may further include an output interface 1840 .
  • the processor 1810 may control the output interface 1840 to communicate with other devices or chips, and specifically, may output information or data to other devices or chips.
  • the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip, a system-on-chip, or a system-on-a-chip, or the like.
  • the processor in this embodiment of the present application may be an integrated circuit image processing system, which has signal processing capability.
  • each step of the above method embodiments may be completed by a hardware integrated logic circuit in a processor or an instruction in the form of software.
  • the above-mentioned processor can be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), an off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA) or other available Programming logic devices, discrete gate or transistor logic devices, discrete hardware components.
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the steps of the method disclosed in conjunction with the embodiments of the present application may be directly embodied as executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor.
  • the software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.
  • the memory in this embodiment of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically programmable Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be Random Access Memory (RAM), which acts as an external cache.
  • RAM Static RAM
  • DRAM Dynamic RAM
  • SDRAM Synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDR SDRAM
  • enhanced SDRAM ESDRAM
  • synchronous link dynamic random access memory Synchlink DRAM, SLDRAM
  • Direct Rambus RAM Direct Rambus RAM
  • the memory in the embodiment of the present application may also be a static random access memory (static RAM, SRAM), a dynamic random access memory (dynamic RAM, DRAM), Synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection Dynamic random access memory (synch link DRAM, SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DR RAM) and so on. That is, the memory in the embodiments of the present application is intended to include but not limited to these and any other suitable types of memory.
  • the memory in the embodiments of the present application may provide instructions and data to the processor.
  • a portion of the memory may also include non-volatile random access memory.
  • the memory may also store device type information.
  • the processor may be configured to execute the instruction stored in the memory, and when the processor executes the instruction, the processor may execute each step corresponding to the terminal device in the foregoing method embodiments.
  • each step of the above-mentioned method can be completed by a hardware integrated logic circuit in a processor or an instruction in the form of software.
  • the steps of the methods disclosed in conjunction with the embodiments of the present application may be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
  • the software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art.
  • the storage medium is located in the memory, and the processor executes the instructions in the memory, and completes the steps of the above method in combination with its hardware. To avoid repetition, detailed description is omitted here.
  • the pixels in the image may be located in different rows and/or columns, wherein the length of A may correspond to the number of pixels located in the same row included in A, and the height of A may be Corresponds to the number of pixels in the same column included in A.
  • the length and height of A may also be referred to as the width and depth of A, respectively, which are not limited in this embodiment of the present application.
  • distributed at the boundary of A may refer to at least one pixel point away from the boundary of A, and may also be referred to as "not adjacent to the boundary of A” or “not located at the boundary of A”.
  • Embodiments of the present application further provide a computer-readable storage medium for storing a computer program.
  • the computer-readable storage medium can be applied to the encoding device in the embodiments of the present application, and the computer program enables the computer to execute the corresponding processes implemented by the encoding device in each method of the embodiments of the present application.
  • the computer program enables the computer to execute the corresponding processes implemented by the encoding device in each method of the embodiments of the present application.
  • Embodiments of the present application also provide a computer program product, including computer program instructions.
  • the computer program product can be applied to the encoding device in the embodiments of the present application, and the computer program instructions cause the computer to execute the corresponding processes implemented by the encoding device in the various methods of the embodiments of the present application. Repeat.
  • the embodiments of the present application also provide a computer program.
  • the computer program can be applied to the encoding device in the embodiments of the present application.
  • the computer program executes the corresponding processes implemented by the encoding device in each method of the embodiments of the present application. For the sake of brevity. , and will not be repeated here.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solutions of the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • the technical solutions of the present application are essentially or part of contributions to the prior art, or all or part of the technical solutions can be embodied in the form of software products, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk and other mediums that can store program codes.

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Abstract

一种编码方法和编码装置，包括：获取待编码图像的多个码流分量，所述多个码流分量中每一个码流分量包括所述待编码图像的一种变换系数的码流；将所述多个码流分量按照所述变换系数的种类顺序存储。本申请实施例提供的方案，由于将待编码图像的多个码流分量按照变换系数的种类顺序存储，在编码的过程中，可以减少码流搬运次数，进一步地，可以提高编码效率。

Description

编码方法和编码装置 技术领域
本申请涉及编解码领域，并且更为具体地，涉及一种编码方法和编码装置。
背景技术
联合摄影专家组扩展范围(Joint Photographic Experts Group Extended Range，JPEG XR)是一种连续色调静止图像压缩算法和文件格式。
JPEG XR码流结构可以由标签图像文件格式(Tagged Image File Format，TIFF)封装信息、图像头(Image_header)信息、索引表(Index_table)及各个瓦片的码流构成。在频率模式下，瓦片内各个宏块的码流可以按直流系数(Direct Current Coefficient，DC Coefficient)、低通系数(Low Pass Coefficient，LP Coefficient)、高通系数(High Pass Coefficient，HP Coefficient)以及可变截断系数(FLEX系数)各自独立存放。
然而在熵编码过程中，JPEG XR在编码时是以宏块为单位进行的，换句话说，编码器每编码完成1个宏块就输出对应的DC系数、LP系数、HP系数、FLEX系数的码流。若要将编码的码流输出顺序排成码流存放顺序，需要很多次码流搬运，很多次的数据读写操作对软件和硬件来说均是巨大的负担。
发明内容
本申请实施例提供一种编码方法和编码装置，可以减少码流搬运次数，进一步地，可以提高编码效率。
第一方面，本申请提供一种编码方法，包括：获取待编码图像的多个码流分量，所述多个码流分量中每一个码流分量包括所述待编码图像的一种变换系数的码流；将所述多个码流分量按照所述变换系数的种类顺序存储。
第二方面，本申请提供一种编码装置，包括：处理器，所述处理器用于：获取待编码图像的多个码流分量，所述多个码流分量中每一个码流分量包括所述待编码图像的一种变换系数的码流；将所述多个码流分量按照所述变换系数的种类顺序存储。
第三方面，提供了一种编码装置，包括处理器和存储器。该存储器用于存储计算机程序，该处理器用于调用并运行该存储器中存储的计算机程序，执行上述第一方面或其各实现方式中的方法。
第四方面，提供一种芯片，用于实现上述第一方面或其各实现方式中的方法。
具体地，该芯片包括：处理器，用于从存储器中调用并运行计算机程序，使得安装有该芯片的设备执行如上述第一方面或其各实现方式中的方法。
第五方面，提供了一种计算机可读存储介质，用于存储计算机程序，该计算机程序包括用于执行第一方面或第一方面的任意可能的实现方式中的方法的指令。
第六方面，提供了一种计算机程序产品，包括计算机程序指令，该计算机程序指令使得计算机执行上述第一方面或第一方面的各实现方式中的方法。
本申请实施例提供的方案，由于将待编码图像的多个码流分量按照变换系数的种类顺序存储，在编码的过程中，可以减少码流搬运次数，进一步地，可以提高编码效率。
附图说明
下面将对实施例使用的附图作简单地介绍。
图1是应用本申请实施例的技术方案的架构图。
图2是根据本申请实施例的视频编码框架2示意图。
图3为本申请实施例提供的JPEG XR处理图像时将图像按从大到小以下五个层次进行处理的示意性图。
图4为本申请实施例提供的JPEG XR编码器的示意性结构图。
图5为本申请实施例提供的一种基于宏块形成变换系数的示意图。
图6为本申请实施例提供的一种码流结构的示意图。
图7为本申请一实施例提供的一个包含2个瓦片的图像码流的索引表示例的示意图。
图8为本申请实施例提供的另一种码流结构的示意图。
图9为本申请实施例提供的一种编码方法的示意图。
图10a为本申请一实施例提供的一种对待编码图像划分的示意性图。
图10b为本申请另一实施例提供的一种对待编码图像划分的示意性图。
图10c为本申请又一实施例提供的一种对待编码图像划分的示意性图。
图10d为本申请再一实施例提供的一种对待编码图像划分的示意性图。
图11为本申请实施例提供的一种码流生成的示意性图。
图12为本申请一实施例提供的一种码流存储形式的示意图。
图13为本申请实施例提供的一种编码方法的示意图。
图14为本申请另一实施例提供的一个包含2个瓦片的图像码流的新的索引表计算示例的示意图。
图15为本申请另一实施例提供的一种码流存储形式的示意图。
图16为本申请又一实施例提供的一个包含2个瓦片的图像码流的新的索引表计算示例的示意图。
图17为本申请实施例提供的一种编码装置的示意性结构图。
图18本申请实施例提供的芯片的示意性结构图。
具体实施方式
下面对本申请实施例中的技术方案进行描述。
除非另有说明，本申请实施例所使用的所有技术和科学术语与本申请的技术领域的技术人员通常理解的含义相同。本申请中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请的范围。
图1是应用本申请实施例的技术方案的架构图。
如图1所示，系统100可以接收待处理数据102，对待处理数据102进行处理，产生处理后的数据108。例如，系统100可以接收待编码数据，对待编码数据进行编码以产生编码后的数据，或者，系统100可以接收待解码数据，对待解码数据进行解码以产生解码后的数据。在一些实施例中，系统100中的部件可以由一个或多个处理器实现，该处理器可以是计算设备中的处理器，也可以是移动设备(例如无人机)中的处理器。该处理器可以为任意种类的处理器，本发明实施例对此不做限定。在一些可能的设计中，该处理器可以包括编码器、解码器或编解码器等。系统100中还可以包括一个或多个存储器。该存储器可用于存储指令和数据，例如，实现本发明实施例的技术方案的计算机可执行指令、待处理数据102、处理后的数据108等。该存储器可以为任意种类的存储器，本发明实施例对此也不做限定。
待编码数据可以包括文本、图像、图形对象、动画序列、音频、视频、或者任何需要编码的其他数据。在一些情况下，待编码数据可以包括来自传感器的传感数据，该传感器可以为视觉传感器(例如，相机、红外传感器)，麦克风、近场传感器(例如，超声波传感器、雷达)、位置传感器、温度传感器、触摸传感器等。在一些情况下，待编码数据可以包括来自用户的信息，例如，生物信息，该生物信息可以包括面部特征、指纹扫描、视网膜扫描、嗓音记录、DNA采样等。
图2是根据本申请实施例的视频编码框架2示意图。如图2所示，在接收待编码视频后，从待编码视频的第一帧开始，依次对待编码视频中的每一帧进行编码。其中，当前编码帧主要经过：预测(Prediction)、变换(Transform)、量化(Quantization)和熵编码(Entropy Coding)等处理，最终输出当前编码帧的码流。对应的，解码过程通常是按照上述过程的逆过程对接收到的码流进行解码，以恢复出解码前的视频帧信息。
具体地，如图2所示，所述视频编码框架2中包括一个编码控制模块201，用于进行编码过程中的决策控制动作，以及参数的选择。例如，如图2所示，编码控制模块201控制变换、量化、反量化、反变换的中用到的参数，控制进行帧内模式或者帧间模式的选择，以及运动估计和滤波的参数控制，且编码控制模块201的控制参数也将输入至熵编码模块中，进行编码形成编码码流中的一部分。
对当前编码帧开始编码时，对编码帧进行划分202处理，具体地，首先对其进行条带(slice)划分，再进行块划分。可选地，在一个示例中，编码帧划分为多个互不重叠的最大的CTU，各CTU还可以分别按四叉树、或二叉树、或三叉树的方式迭代划分为一系列更小的编码单元(Coding Unit，CU)，一些示例中，CU还可以包含与之相关联的预测单元(Prediction Unit，PU)和变换单元(Transform Unit，TU)，其中PU为预测的基本单元，TU为变换和量化的基本单元。一些示例中，PU和TU分别是在CU的基础上划分成一个或多个块得到的，其中一个PU包含多个预测块(Prediction Block，PB)以及相关语法元素。一些示例中，PU和TU可以是相同的，或者，是由CU通过不同的划分方法得到的。一些示例中，CU、PU和TU中的至少两种是相同的，例如，不区分CU、PU和TU，全部是以CU为单位进行预测、量化和变换。为方便描述，下文中将CTU、CU或者其它形成的数据单 元均称为编码块。
应理解，在本申请实施例中，视频编码针对的数据单元可以为帧，条带，编码树单元，编码单元，编码块或以上任一种的组。在不同的实施例中，数据单元的大小可以变化。
具体地，如图2所示，编码帧划分为多个编码块后，进行预测过程，用于去除当前编码帧的空域和时域冗余信息。当前比较常用的预测编码方法包括帧内预测和帧间预测两种方法。帧内预测仅利用本帧图像中己重建的信息对当前编码块进行预测，而帧间预测会利用到之前已经重建过的其它帧图像(也被称作参考帧)中的信息对当前编码块进行预测。具体地，在本申请实施例中，编码控制模块201用于决策选择帧内预测或者帧间预测。
当选择帧内预测模式时，帧内预测203的过程包括获取当前编码块周围已编码相邻块的重建块作为参考块，基于该参考块的像素值，采用预测模式方法计算预测值生成预测块，将当前编码块与预测块的相应像素值相减得到当前编码块的残差，当前编码块的残差经过变换204、量化205以及熵编码210后形成当前编码块的码流。进一步的，当前编码帧的全部编码块经过上述编码过程后，形成编码帧的编码码流中的一部分。此外，帧内预测203中产生的控制和参考数据也经过熵编码210编码，形成编码码流中的一部分。
具体地，变换204用于去除图像块的残差的相关性，以便提高编码效率。对于当前编码块残差数据的变换通常采用二维离散余弦变换(Discrete Cosine Transform，DCT)变换和二维离散正弦变换(Discrete Sine Transform，DST)变换，例如在编码端将编码块的残差信息分别与一个N×M的变换矩阵及其转置矩阵相乘，相乘之后得到当前编码块的变换系数。
在产生变换系数之后用量化205进一步提高压缩效率，变换系数经量化可以得到量化后的系数，然后将量化后的系数进行熵编码210得到当前编码块的残差码流，其中，熵编码方法包括但不限于内容自适应二进制算术编码(Context Adaptive Binary Arithmetic Coding，CABAC)熵编码。最后将熵编码得到的比特流及进行编码后的编码模式信息进行存储或发送到解码端。在编码端，还会对量化的结果进行反量化206，对反量化结果进行反变换207。在反变换207之后，利用反变换结果以及运动补偿结果，得到重建像素。之后，对重建像素进行滤波(即环路滤波)211。在211之后，输出滤波后的重建图像(属于重建视频帧)。后续，重建图像可以作为其他帧图像的参考 帧图像进行帧间预测。本申请实施例中，重建图像又可称为重建后的图像或重构图像。
具体地，帧内预测203过程中的已编码相邻块为：当前编码块编码之前，已进行编码的相邻块，该相邻块的编码过程中产生的残差经过变换204、量化205、反量化206、和反变换207后，与该相邻块的预测块相加得到的重建块。对应的，反量化206和反变换207为量化206和变换204的逆过程，用于恢复量化和变换前的残差数据。
如图2所示，当选择帧间预测模式时，帧间预测过程包括运动估计(Motion Estimation，ME)208和运动补偿(Motion Compensation，MC)209。具体地，编码端可以根据重建视频帧中的参考帧图像进行运动估计208，在一张或多张参考帧图像中根据一定的匹配准则搜索到与当前编码块最相似的图像块作为预测块，该预测块与当前编码块的相对位移即为当前编码块的运动矢量(Motion Vector，MV)。并将该编码块像素的原始值与对应的预测块像素值相减得到编码块的残差。当前编码块的残差经过变换204、量化205以及熵编码210后形成编码帧的编码码流中的一部分。对于解码端来说，可以基于上述确定的运动矢量和预测块进行运动补偿209，获得当前编码块。
其中，如图2所示，重建视频帧为经过滤波211之后得到视频帧。重建视频帧包括一个或多个重建后的图像。滤波211用于减少编码过程中产生的块效应和振铃效应等压缩失真，重建视频帧在编码过程中用于为帧间预测提供参考帧，在解码过程中，重建视频帧经过后处理后输出为最终的解码视频。
具体地，帧间预测模式可以包括高级运动矢量预测(Advanced Motion Vector Prediction，AMVP)模式、合并(Merge)模式或跳过(skip)模式。
对于AMVP模式而言，可以先确定运动矢量预测(Motion Vector Prediction，MVP)，在得到MVP之后，可以根据MVP确定运动估计的起始点，在起始点附近，进行运动搜索，搜索完毕之后得到最优的MV，由MV确定参考块在参考图像中的位置，参考块减去当前块得到残差块，MV减去MVP得到运动矢量差值(Motion Vector Difference，MVD)，并将该MVD和MVP的索引通过码流传输给解码端。
对于Merge模式而言，可以先确定MVP，并直接将MVP确定为当前块的MV。其中，为了得到MVP，可以先构建一个MVP候选列表(merge candidate list)，在MVP候选列表中，可以包括至少一个候选MVP，每个候 选MVP可以对应有一个索引，编码端在从MVP候选列表中选择MVP之后，可以将该MVP索引写入到码流中，则解码端可以按照该索引从MVP候选列表中找到该索引对应的MVP，以实现对图像块的解码。
应理解，以上过程只是Merge模式的一种具体实现方式。Merge模式还可以具有其他的实现方式。
例如，Skip模式是Merge模式的一种特例。按照Merge模式得到MV之后，如果编码端确定当前块和参考块基本一样，那么不需要传输残差数据，只需要传递MVP的索引，以及进一步地可以传递一个标志，该标志可以表明当前块可以直接从参考块得到。
也就是说，Merge模式特点为：MV＝MVP(MVD＝0)；而Skip模式还多一个特点，即：重构值rec＝预测值pred(残差值resi＝0)。
Merge模式可以应用于几何预测技术中。在几何预测技术中，可以将待编码的图像块划分为多个形状为多边形的子图像块，可以从运动信息候选列表中，分别为每个子图像块确定运动矢量，并基于每个子图像块的运动矢量，确定每个子图像块对应的预测子块，基于每个子图像块对应的预测子块，构造当前图像块的预测块，从而实现对当前图像块的编码。
对于解码端，则进行与编码端相对应的操作。首先利用熵解码以及反量化和反变换得到残差信息，并根据解码码流确定当前图像块使用帧内预测还是帧间预测。如果是帧内预测，则利用当前帧中已重建图像块按照帧内预测方法构建预测信息；如果是帧间预测，则需要解析出运动信息，并使用所解析出的运动信息在已重建的图像中确定参考块，得到预测信息；接下来，再将预测信息与残差信息进行叠加，并经过滤波操作便可以得到重建信息。
如上所述，基于图2所示出的视频编码框架2对视频进行编码可以节约视频图像存储和传输所占用的空间或流量。一般情况下，摄像头采集所得未经压缩的原始图像数据占用的存储空间很大，以分辨率为3840×2160、存储格式为YUV4:2:2(其中，Y表示明亮度，UV表示色度)10比特的图像为例，在无压缩的情况下存储该图像需要占用约20M字节的存储空间，通常一张8G的存储卡只能存放500张上述规格的未压缩照片，同时也意味着在网络传输时一张未压缩的上述规格的照片就需要20M字节流量。因此为了节约图像存储和传输所占用的空间或流量，需要对图像数据进行编码压缩处理。
JPEG XR是一种连续色调静止图像压缩算法和文件格式，也可以称为HD Photo或网络媒体图像(Windows Media Photo)，由微软(microsoft)开发，属于网络媒体(Windows Media)家族的一部分。它支持有损数据压缩以及无损数据压缩，并且是微软的XML文本规格(XML paper specification，XPS)文档的首选图像格式，其中XML为可扩展标记语言(Extensible Markup Language)。目前支持的软件包括.NET框架(3.0或更新版本)，操作系统(windows vista/windows 7)、网络探路者(Internet Explorer，IE)9，动画播放器(flashplayer)11等。
JPEG XR是一款可以实现高动态范围图像编码，而且在压缩与解压时只需要整数运算的图像编解码器。它可以支持单色、Red Green Blue(RGB)、Cyan Magenta Yellow Black(CMYK)、16位无符号整数或者32位定点或者浮点数表示的多通道彩色格式的图像，并且它还支持RGBE Radiance图像格式。它可以选择嵌入国际色彩协会(International Color Consortium，ICC)彩色描述档以实现不同设备上的色彩一致性。阿尔法通道可以表示透明程度，同时支持可交换图像文件(Exchangeable Image File，EXIF)、可扩展元数据平台(Extensible Metadata Platform，XMP)元数据格式。这种格式还支持在一个文件中包含多幅图像。支持只对图像的进行部分解码，对于一些特定的操作如裁剪、降采样、水平竖直翻转或者旋转都无需对整幅图像进行解码。
如图3所示为本申请实施例提供的JPEG XR处理图像时将图像按从大到小以下五个层次进行处理的示意性图。其中，该图中包括图像(image)、瓦片(tile)、宏块(Macro Block，MB)、块(block)、像素(pixel)。其中一个图像可以由一个或多个瓦片组成。如果瓦片位于图像的右侧或底部边缘，则可以将其填充为整数个宏块(16×16)。每个宏块可以包含16个4×4块，并且每个块可以包含4×4像素。JPEG XR对每个4×4块和16×16宏块中的重组低通块进行两阶段变换。
如图4所示为本申请实施例提供的JPEG XR编码器的示意性结构图。该JPEG XR编码器可以包括滤波模块410、变换模块420、量化模块430、预测模块440、熵编码模块450五个模块，这五个模块的作用与上述图2中所涉及到的模块的作用相类似。具体地，滤波模块410可以通过相邻像素间的平滑减轻解码重建图像的块效应；变换模块420可以将图像信息从空域转换到频域，去除部分空域冗余信息；量化模块430可以将频域系数进行缩小， 降低需要编码的系数幅值，系数幅值降低的程度取决于指定的量化参数(Quantization Parameter，QP)的大小；预测模块440可以通过相邻块部分系数间的预测去除相邻块间部分系数的相关性；熵编码模块450可以将最终得到的系数编码成二进制码流。
下文先介绍关于JPEG XR的变换模块以及一种码流结构和码流存储形式。
1、变换模块
JPEG XR的变换是基于整数的变换，每个宏块可以参与两个阶段的变换。变换均可以基于4x4个块进行。如图5所示，为本申请实施例提供的一种基于宏块形成变换系数的示意图。
参考图5，该宏块内可以包括16个块，第一阶段变换可以应用于宏块内的16个块，产生16个LP系数和240个HP系数，即这16个块中的每一个块均产生一个LP系数和15个HP系数。第二阶段变换应用于第一阶段得到的16个LP系数的重组块，并将这16个LP系数通过再次变换最终生成1个DC系数和15个LP系数。
2、JPEG XR码流结构和码流存储形式
JPEG XR支持空域(spatial)模式码流排列和频率(frequency)模式码流排列两种方式，由于本申请涉及的是频率模式，在此仅描述关于频率模式的码流存储形式。
如图6所示，为本申请实施例提供的一种码流结构的示意图。
从图6中可以看出，JPEG XR码流结构可以由TIFF封装信息、图像头信息、索引表及各个瓦片的码流构成，其中，n可以表示该图像分为n个瓦片，m表示瓦片1内包含m个宏块。
在频率模式下，瓦片内各个宏块的码流可以按DC系数、LP系数、HP系数各自独立存放。需要注意的是，在熵编码过程中HP系数可以被拆分成两部分编码，因此最终码流中有两部分码流是来自HP系数，即HP和FLEX这两部分可以来自HP系数。
图像头信息中可以存放该幅图像的一些信息如宽、高、图像格式等。
索引表中存放的是各个瓦片的各个频段码流的起始地址(以相对DC1的字节数计算)。需要特别注意的是索引表中各个数据的含义是标准规定不可变的，可以按如下顺序排列：DC1起始地址、LP1起始地址、HP1起始地 址、FLEX1起始地址、DC2起始地址、LP2起始地址、HP2起始地址、FLEX2起始地址……DCn起始地址、LPn起始地址、HPn起始地址、FLEXn起始地址。
关于索引表值的计算，可以按照式(1)～式(4)所示进行计算，其中，n表示图像内瓦片的个数，i表示第i个瓦片，length_X_y表示X频段第y个瓦片的以字节为单位的码流长度。
Figure PCTCN2020104496-appb-000001
index_table_LP_i＝index_table_DC_i+length_DC_i  (2)
index_table_HP_i＝index_table_LP_i+length_LP_i  (3)
index_table_FLEX_i＝index_table_HP_i+length_HP_i  (4)
以待编码图像被被划分为2个瓦片为例，如图7所示，是一个包含2个瓦片的图像码流的索引表示例的示意图。从图7中可以看出，索引表是按照每一个瓦片的DC起始地址、LP起始地址、HP起始地址以及FLEX起始地址这样的顺序排列的。
需要说明的是，上述图7中的瓦片1和瓦片2中可以包括多个宏块，以瓦片1为例，若瓦片1中包括m个宏块，则DC1起始地址可以为瓦片1中的宏块1的起始地址。
虽然JPEG XR的频率模式的码流是按照图6所示的格式进行存储的，但是JPEG XR在编码时是以宏块为单位进行的，换句话说，编码器每编码完成1个宏块就输出对应的DC系数、LP系数、HP系数、FLEX系数码流，1个瓦片内的各个宏块按自然顺序产生的码流可以为如图8所示出的示意图排列。
若要将图8所示的码流重排成图6的顺序，不论是以软件实现还是硬件实现都会带来额外的时间开销从而导致编码器的效率下降。
以分辨率为7680x4320的图像为例，整幅图包含480x270＝129600个宏块，若要将图8所示的码流重排成图6所示的顺序，则需要129600x4＝518400次码流搬运，次数如此多的数据读写操作对软件和硬件来说均是巨大的负担。
针对上述问题，本申请提出一种编码方法，可以减少码流搬运次数，进 一步地，可以提高编码效率。
如图9所示，为本申请实施例提供的一种编码方法900的示意性图，该编码方法900可以包括步骤910-920。
910，获取待编码图像的多个码流分量，所述多个码流分量中每一个码流分量包括所述待编码图像的一种变换系数的码流。
可选地，本申请实施例中的多个码流分量可以包括DC系数码流分量、LP系数码流分量、HP系数码流分量以及FLEX系数码流分量。
换句话说，本申请实施例中的多个码流分量可以包括上文中提到的DC系数的码流、LP系数的码流、HP系数的码流以及FLEX系数的码流。
920，将所述多个码流分量按照所述变换系数的种类顺序存储。
本申请实施例中，将所述多个码流分量按照所述变换系数的种类顺序存储，可以是指按照上述多个码流分量中所包括的DC系数码流分量、LP系数码流分量、HP系数码流分量以及FLEX系数码流分量中的任意一种顺序进行存储。
例如，可以按照DC系数码流分量、LP系数码流分量、HP系数码流分量以及FLEX系数码流分量这样的顺序进行存储，也可以按照HP系数码流分量、DC系数码流分量、LP系数码流分量以及FLEX系数码流分量这样的顺序进行存储，还可以按照LP系数码流分量、HP系数码流分量、DC系数码流分量、LP系数码流分量以及FLEX系数码流分量这样的顺序进行存储等，不予限制。
本申请实施例提供的方案，由于将待编码图像的多个码流分量按照变换系数的种类顺序存储，在编码的过程中，可以减少码流搬运次数，进一步地，可以提高编码效率。
可选地，在一些实施例中，所述待编码图像包括n个瓦片，所述n个瓦片中的第i个瓦片包括若干个宏块，所述若干个宏块的同一种变换系数的码流顺序排列形成所述第i个瓦片的所述同一种变换系数的码流，所述n个瓦片的所述同一种变换系数的码流顺序排列形成所述待编码图像的所述同一种变换系数的码流；其中，n为大于或等于1的正整数，i为小于或等于n的正整数。
本申请实施例中的n个瓦片中可以为相同大小的图像，即在对待编码图像进行划分的时候，可以对待编码图像进行等份划分；n个瓦片也可以为不 同大小的图像，即在对待编码图像进行划分的时候，可以不对待编码图像进行等份划分。
例如，如图10a所示，为本申请一实施例提供的一种对待编码图像划分的示意性图。以n为2为例，可以从待编码图像的中心通过对待编码图像进行垂直划分得到两个瓦片，分别为瓦片1(即10a-1)和瓦片2(即10a-2)。可以看出，划分后的两个瓦片的大小是相同的，即可以理解为划分后的两个瓦片中所包括的像素的个数相同。
如图10b所示，为本申请另一种实施例提供的一种对待编码图像划分的示意性图。可以从待编码图像的中心通过对待编码图像进行水平划分得到两个瓦片，分别为瓦片1(即10b-1)和瓦片2(即10b-2)。可以看出，划分后的两个瓦片的大小是相同的。
如图10c所示，为本申请又一实施例提供的一种对待编码图像划分的示意性图。仍然以n为2为例，可以不从待编码图像的中心通过对待编码图像进行垂直划分得到两个瓦片，分别为瓦片1(即10c-1)和瓦片2(即10c-2)。可以看出，划分后的两个瓦片的大小是不同的，即可以理解为划分后的两个瓦片中所包括的像素的个数不同。
如图10d所示，为本申请再一实施例提供的一种对待编码图像划分的示意性图。仍然以n为2为例，可以不从待编码图像的中心通过对待编码图像进行水平划分得到两个瓦片，分别为瓦片1(即10d-1)和瓦片2(即10d-2)。可以看出，划分后的两个瓦片的大小是不同的。
以图10a为例，假设瓦片1(即10a-1)和瓦片2(即10a-2)分别包括16*16个宏块，对于瓦片1来说，则对这16*16个宏块的DC系数的码流进行顺序排列可以形成瓦片1的DC系数的码流，对这16*16个宏块的LP系数的码流进行顺序排列可以形成瓦片1的LP系数的码流，对这16*16个宏块的HP系数的码流进行顺序排列可以形成瓦片1的HP系数的码流，对这16*16个宏块的FLEX系数的码流进行顺序排列可以形成瓦片1的FLEX系数的码流。
类似地，对于瓦片2来说，则对这16*16个宏块的DC系数的码流进行顺序排列可以形成瓦片2的DC系数的码流，对这16*16个宏块的LP系数的码流进行顺序排列可以形成瓦片2的LP系数的码流，对这16*16个宏块的HP系数的码流进行顺序排列可以形成瓦片2的HP系数的码流，对这 16*16个宏块的FLEX系数的码流进行顺序排列可以形成瓦片2的FLEX系数的码流。
相应地，对这两个瓦片(上述瓦片1和瓦片2)的同一种变换系数的码流进行顺序排列可以形成待编码图像的同一种变换系数的码流，即对这两个瓦片的DC系数的码流进行顺序排列可以形成待编码图像的DC系数的码流，对这两个瓦片的LP系数的码流进行顺序排列可以形成待编码图像的LP系数的码流，对这两个瓦片的HP系数的码流进行顺序排列可以形成待编码图像的HP系数的码流，对这两个瓦片的FLEX系数的码流进行顺序排列可以形成待编码图像的FLEX系数的码流。
应理解，上述数值仅为举例说明，还可以为其它数值，不应对本申请造成特别限定。
本申请实施例提供的方案，在待编码图像包括n个瓦片的情况下，将这n个瓦片中的每一个瓦片中包括的若干个宏块的同一种变换系数的码流顺序排列形成对应的瓦片的同一种变换系数的码流，将这n个瓦片的同一种变换系数的码流顺序排列形成待编码图像的同一种变换系数的码流。通过这样的码流形成方式和按照变换系数进行存储的方式，可以减少码流搬运次数，进一步地，可以提高编码效率。
可选地，在一些实施例中，所述获取待编码图像的多个码流分量，包括：对于所述待编码图像的每一个宏块，将不同种变换系数的码流分别输出至不同的缓存空间，在不同的缓存空间中分别获取所述待编码图像的不同种变换系数的码流。
如图11所示，为本申请实施例提供的一种码流生成的示意性图。其中，JPEG XR编码器在输出码流时可以不再将一个宏块内的DC系数、LP系数、HP系数、FLEX系数的码流紧凑排列，而是分别输出到4个独立的缓存空间，并且宏块间的DC系数与DC系数的码流分量的码流字节对齐紧凑排列、宏块间的LP系数与LP系数的码流分量的码流字节对齐紧凑排列、宏块间的HP系数与HP系数的码流分量的码流字节对齐紧凑排列、宏块间的FLEX系数与FLEX系数的码流分量的码流字节对齐紧凑排列。
上述宏块间的DC系数与DC系数的码流分量的码流按字节对齐紧凑排列，可以是下一个宏块的DC系数的码流分量紧邻上一个宏块的DC系数的码流分量之后；类似地，宏块间的LP系数与LP系数的码流分量的码流字 节对齐紧凑排列，可以是下一个宏块的LP系数的码流分量紧邻上一个宏块的LP系数的码流分量之后；类似地，宏块间的HP系数与HP系数的码流分量的码流字节对齐紧凑排列，可以是下一个宏块的HP系数的码流分量紧邻上一个宏块的HP系数的码流分量之后；类似地，宏块间的FLEX系数与FLEX系数的码流分量的码流字节对齐紧凑排列，可以是下一个宏块的FLEX系数的码流分量紧邻上一个宏块的FLEX系数的码流分量之后。
而且，各个瓦片间的DC系数、LP系数、HP系数、FLEX系数的码流分量也是各自分开排列，需要注意的是，瓦片2的DC系数码流分量可以接续在瓦片1的DC系数码流分量后，瓦片2的LP系数码流分量可以接续在瓦片1的LP系数码流分量后，瓦片2的HP系数码流分量可以接续在瓦片1的HP系数码流分量后，瓦片2的FLEX系数码流分量可以接续在瓦片1的FLEX系数码流分量后，后续以此类推，直到瓦片n的各个系数码流分量相继排列完成。
换句话说，JPEG XR编码器在编码的过程中，对于瓦片1中的各个宏块，可以按照以下顺序排列。对于瓦片1中的宏块1，可以先将瓦片1中的宏块1的DC系数码流分量输出到第一缓存空间；将瓦片1中的宏块1的LP系数码流分量输出到第二缓存空间；将瓦片1中的宏块1的HP系数码流分量输出到第三缓存空间；将瓦片1中的宏块1的FLEX系数码流分量输出到第四缓存空间。对于瓦片1中的宏块2，可以将瓦片1中的宏块2的DC系数码流分量输出到第一缓存空间，并接续在瓦片1的宏块1的DC系数码流分量之后；可以将瓦片1中的宏块2的LP系数码流分量输出到第二缓存空间，并接续在瓦片1的宏块2的LP系数码流分量之后；可以将瓦片1中的宏块2的HP系数码流分量输出到第三缓存空间，并接续在瓦片1的宏块2的HP系数码流分量之后；可以将瓦片1中的宏块2的FLEX系数码流分量输出到第四缓存空间，并接续在瓦片1的宏块2的FLEX系数码流分量之后。后续以此类推，直到瓦片1中的所有宏块(m个宏块)的各个系数码流分量输出完成。
对于瓦片2中的宏块，可以先将瓦片2中的宏块1的DC系数码流分量输出到第一缓存空间，并接续在瓦片1中的宏块m的DC系数码流分量之后；将瓦片2中的宏块1的LP系数码流分量输出到第二缓存空间，并接续在瓦片1中的宏块m的LP系数码流分量之后；瓦片2中的宏块1的HP系数码 流分量输出到第三缓存空间，并接续在瓦片1中的宏块m的HP系数码流分量之后；瓦片2中的宏块1的FLEX系数码流分量输出到第四缓存空间，并接续在瓦片1中的宏块m的FLEX系数码流分量之后；后续以此类推，直到瓦片2中的所有宏块的各个系数码流分量输出完成。
对于瓦片n中的宏块，可以按照上述瓦片2的方式进行输出，为了简洁，这里不再赘述。
在上文的描述中，图6所示的码流存储形式是将每一个瓦片内的DC系数、LP系数、HP系数、FLEX系数码流集中存放，而瓦片与瓦片之间各分量码流是互相间隔的。
图12为本申请实施例提供的一种码流存储形式的示意图，参考图12，如图12中的左侧图形所示出的瓦片1内的DC系数、LP系数、HP系数、FLEX系数码流紧凑存储，瓦片2内的DC系数、LP系数、HP系数、FLEX系数码流紧凑存储，但瓦片1的DC系数码流与瓦片2的DC系数码流是间隔存放的。新的存储形式如图12中的右侧图形所示，所有瓦片(包括瓦片1、瓦片2、……、瓦片n)的DC系数码流集中存放，所有瓦片的LP系数码流集中存放，所有瓦片的HP系数码流集中存放，所有瓦片的FLEX系数码流集中存放。
新的码流存储形式(图12中右侧图形所示出的码流存储形式)的优点在于，只需将图11所示的各个瓦片的DC系数、LP系数、HP系数、FLEX系数码流各搬运1次(总共4次)拼接在一起就可得到图12右侧图形所示的码流。
具体地，例如，可以先将图11所示的所有DC系数(包括瓦片1、瓦片2、……、瓦片n)的码流搬运至合适的位置，再将图11所示的所有LP系数的码流搬运至所有DC系数的码流之后，再将图11所示的所有HP系数的码流搬运至所有LP系数的码流之后，最后可以将图11所示的所有FLEX系数的码流搬运至所有LP系数的码流之后。因此，从图11所示的码流形式转换到图12右侧图形所示的码流存储形式可以只需4次码流搬运即可。
在一些实施例中，也可以先将图11所示的所有LP系数的码流搬运至合适的位置，再将图11所示的所有DC系数的码流搬运至所有LP系数的码流之前，再将图11所示的所有HP系数的码流搬运至所有LP系数的码流之后，最后可以将图11所示的所有FLEX系数的码流搬运至所有LP系数的码流之 后。因此，从图11所示的码流形式转换到图12右侧图形所示的码流存储形式仍然只需4次码流搬运即可。
对于其它可能的搬运方式，与上述所列举的搬运方式类似，为了简介，这里不再赘述。
总之，不论以上述哪种方式进行搬运，从图11所示的码流形式转换到图12右侧图形所示的码流存储形式均只需4次码流搬运即可，因此，可以节省码流搬运次数。
本申请实施例提供的编码方法，提供了一种新的码流生成的方法和新的码流存储的形式，只需4次即可完成码流搬运，从而可以减少码流搬运次数，进一步地，可以提高编码效率。
可选地，在一些实施例中，所述方法还包括：将所述缓存空间内的变换系数的码流存储至预设的存储设备中。
本申请实施例中，在编码器获得待编码图像多个变换系数的码流后，可以将该多个变换系数的码流存储至预设的存储设备中，例如，可以存储至硬盘空间或安全数码(Secure Digital，SD)卡等存储介质中，不予限制。
如图13所示为本申请实施例提供的一种编码方法的示意图。从图中可以看出，编码器在对待编码图像进行编码的时候，可以将待编码图像的不同变换系数的码流分别缓存至不同的缓存空间，最后可以统一存储至预设的存储设备中。
从图13中可以看出，在存储的过程中，仍然可以按照上述所介绍的新的码流存储的形式进行存储，即将所有瓦片的DC系数的码流集中存放，所有瓦片的LP系数的码流集中存放，所有瓦片的HP系数的码流集中存放，所有瓦片的FLEX系数的码流集中存放。
可选地，在一些实施例中，其特征在于，所述方法还包括：生成所述待编码图像的信息，所述待编码图像的信息包括所述待编码图像的TIFF封装信息、所述待编码图像的图像头信息、所述待编码图像的索引表以及所述待编码图像的码流。
参考图13，在编码器在对待编码图像进行编码的过程中，待编码图像的信息中还可以包括TIFF封装信息、图像头信息和待编码图像的索引表。
如上所述，图像头信息可以存放待编码图像的的一些信息，例如，待编码图像的宽、高以及图像格式等。
待编码图像的索引表可以存放待编码图像中包括的各个瓦片的各个频段码流的起始地址，例如，各个瓦片的DC系数码流的起始地址、各个瓦片的LP系数码流的起始地址、各个瓦片的HP系数码流的起始地址以及各个瓦片的FLEX系数码流的起始地址。
本申请实施例提供的方案，可以保证对待编码图像进行编码的完整性。
可选地，在一些实施例中，所述方法还包括：设置所述待编码图像的多流分量的索引。
可选地，在一些实施例中，所述待编码图像包括n个瓦片，所述设置所述待编码图像的多个码流分量的索引，包括：根据所述n个瓦片的每一个瓦片的多个码流分量中每一个码流分量的长度，按照预设分量顺序设置所述n个瓦片的多个码流分量的索引，所述预设分量顺序为DC系数码流分量、LP系数码流分量、HP系数码流分量和FLEX系数码流分量，n为大于1或等于1的正整数。
上文指出，索引表中各个数据的含义是标准规定不可变的，可以按如下顺序排列：DC1起始地址、LP1起始地址、HP1起始地址、FLEX1起始地址、DC2起始地址、LP2起始地址、HP2起始地址、FLEX2起始地址……。为了符合JPEG XR标准，在改动码流存储形式的情况下，索引表中存储的数据需要仍然符合上述顺序。因此，本申请提出了一种新的索引表计算方法，如下式(5)～式(8)所示。
Figure PCTCN2020104496-appb-000002
Figure PCTCN2020104496-appb-000003
Figure PCTCN2020104496-appb-000004
Figure PCTCN2020104496-appb-000005
以待编码图像被划分为2个瓦片为例，假设即瓦片1的DC1系数、LP1 系数、HP1系数、FLEX1系数的码流长度分别为a、b、c、d；瓦片2的DC2系数、LP2系数、HP2系数、FLEX2系数的码流长度分别为e、f、g、h。
根据上述式(5)～式(8)可以得到瓦片1和瓦片2的索引表的数值，即：
Figure PCTCN2020104496-appb-000006
Figure PCTCN2020104496-appb-000007
Figure PCTCN2020104496-appb-000008
Figure PCTCN2020104496-appb-000009
从上述公式可以看出，DC1起始地址为0，LP1起始地址为a+e，HP1起始地址为a+e+b+f，FLEX1的起始地址为a+e+b+f+c+g，DC2起始地址为a，LP2起始地址为a+e+b，HP2起始地址为a+e+b+f+c，FLEX2的起始地址为a+e+b+f+c+g+d。
如图14所示，是一个包含2个瓦片的图像码流的新的索引表计算示例的示意图。从图14中可以看出，虽然新的存储形式有变化，但是索引表仍然是按照每一个瓦片的DC起始地址、LP起始地址、HP起始地址以及FLEX起始地址这样的顺序排列的，只是索引表中的数据有所变化。
换句话说，由于新的存储码流的形式为DC1、DC2、LP1、LP2、HP1、HP2、FLEX1、FLEX2，但是索引表中的顺序需要符合标准规定，因此，索引表中的数值相应地会发生变化。
参考图14，瓦片1和瓦片2中的每一个系数的码流长度与上文中图7 中的码流长度保持一致，即瓦片1的DC1系数、LP1系数、HP1系数、FLEX1系数的码流长度分别为a、b、c、d；即瓦片2的DC2系数、LP2系数、HP2系数、FLEX2系数的码流长度分别为e、f、g、h。
从图14中可以看出，DC1起始地址为0，LP1起始地址为a+e，HP1起始地址为a+e+b+f，……，FLEX2的起始地址为a+e+b+f+c+g+d+h。
本申请实施例提供的方案，通过按照新的索引表计算公式计算每一个瓦片中的各个系数的起始地址，可以保证本申请实施例提供的新的码流存储形式仍然符合标准规定。
示例性地，以待编码图像被划分为2个瓦片为例，假设即瓦片1的DC1系数、LP1系数、HP1系数、FLEX1系数的长度分别为10、12、8、9；瓦片2的DC2系数、LP2系数、HP2系数、FLEX2系数的长度分别为11、16、10、13。
则按照上述式(5)～式(8)可以得到瓦片1和瓦片2的索引表的数值，即DC1起始地址为0，LP1起始地址为21，HP1起始地址为49，FLEX1的起始地址为67，DC2起始地址为10，LP2起始地址为33，HP2起始地址为57，FLEX2的起始地址为89。
应理解，上述数值仅为举例说明，还可以为其它数值，不应对本申请造成特别限定。
前文指出，将多个码流分量按照变换系数的种类顺序存储，可以是指按照上述多个码流分量中所包括的DC系数码流分量、LP系数码流分量、HP系数码流分量以及FLEX系数码流分量中的任意一种顺序进行存储。
上文是以DC系数、LP系数、HP系数、FLEX系数这样的顺序存储码流的，本申请实施例中，可以自由调整DC系数、LP系数、HP系数、FLEX系数的存储顺序，例如，可以按照HP系数、DC系数、LP系数、FLEX系数，或者，LP系数、HP系数、DC系数、FLEX系数，或者，FLEX系数、LP系数、HP系数、DC系数等的顺序存储，不予限制。
下文以HP系数、DC系数、LP系数、FLEX系数的顺序为例进行说明。
图15为本申请实施例提供的一种码流存储形式的示意图，参考图15，如图15中的左侧图形所示出的瓦片1内的HP系数、DC系数、LP系数、FLEX系数的码流紧凑存储，瓦片2内的HP系数、DC系数、LP系数、FLEX系数的码流紧凑存储，但瓦片1的DC系数的码流与瓦片2的DC系数的码 流是间隔存放的。新的存储形式如图15中的右侧图形所示，所有瓦片(包括瓦片1、瓦片2、……、瓦片n)的HP系数码流集中存放，所有瓦片的DC系数码流集中存放，所有瓦片的LP系数码流集中存放，所有瓦片的FLEX系数码流集中存放。
类似地，新的码流存储形式(图15中右侧图形所示出的码流存储形式)的优点在于，只需将图11所示的各个瓦片的DC系数、LP系数、HP系数、FLEX系数的码流各搬运1次(总共4次)拼接在一起就可得到图15右侧图形所示的码流。
具体地，可以先将图11所示的所有HP(包括瓦片1、瓦片2、……、瓦片n)系数的码流搬运至合适的位置，再将图11所示的所有DC系数的码流搬运至所有HP系数的码流之后，再将图11所示的所有LP系数的码流搬运至所有DC系数的码流之后，最后可以将图11所示的所有FLEX系数的码流搬运至所有LP系数的码流之后。因此，从图11所示的码流形式转换到图15所示的码流存储形式可以只需4次码流搬运即可。
类似地，对于其他可能的搬运方式与上述方式类似，为了简洁，这里不再赘述。
本申请实施例提供的编码方法，通过新的码流生成的方法和新的码流存储的形式，可以减少码流搬运次数，进一步地，可以提高编码效率。
同样地，由于索引表中各个数据的含义是标准规定不可变的，按如下顺序排列：DC1起始地址、LP1起始地址、HP1起始地址、FLEX1起始地址、DC2起始地址、LP2起始地址、HP2起始地址、FLEX2起始地址……。为了符合JPEG XR标准，在改动码流存储形式的情况下，索引表中存储的数据必须仍然符合上述顺序。相应地，本申请提出了一种新的索引表计算方法，如下式(9)～式(12)所示。
Figure PCTCN2020104496-appb-000010
Figure PCTCN2020104496-appb-000011
Figure PCTCN2020104496-appb-000012
Figure PCTCN2020104496-appb-000013
如图16所示，是一个包含2个瓦片的图像码流的新的索引表计算示例的示意图。从图中可以看出，虽然新的存储形式有变化，但是索引表仍然是按照每一个瓦片的DC起始地址、LP起始地址、HP起始地址以及FLEX起始地址这样的顺序排列的，只是索引表中的数据有所变化。
以待编码图像被划分为2个瓦片为例，假设瓦片1中的DC1系数、LP1系数、HP1系数、FLEX1系数的码流长度仍然分别为a、b、c、d；瓦片2中的DC2系数、LP2系数、HP2系数、FLEX2系数的码流长度仍然分别为e、f、g、h。
根据上述式(9)～式(12)可以得到瓦片1和瓦片2的索引表的数值，即：
Figure PCTCN2020104496-appb-000014
Figure PCTCN2020104496-appb-000015
Figure PCTCN2020104496-appb-000016
Figure PCTCN2020104496-appb-000017
从上述公式可以看出，DC1起始地址为c+g，LP1起始地址为c+g+a+e，HP1起始地址为0，FLEX1的起始地址为c+g+a+e+b+f，DC2起始地址为c+g+a，LP2起始地址为c+g+a+e+b，HP2起始地址为c，FLEX2的起始地址 为c+g+a+e+b+f+d。
如图16所示，是一个包含2个瓦片的图像码流的新的索引表计算示例的示意图。从图16中可以看出，虽然新的存储形式有变化，但是索引表仍然是按照每一个瓦片的DC起始地址、LP起始地址、HP起始地址以及FLEX起始地址这样的顺序排列的，只是索引表中的数据有所变化。
换句话说，由于新的存储码流的形式为DC1、DC2、LP1、LP2、HP1、HP2、FLEX1、FLEX2，但是索引表中的顺序需要符合标准规定，因此，索引表中的数值相应地会发生变化。
参考图16，瓦片1和瓦片2中的每一个系数的码流长度与上文中图7中的码流长度保持一致，即瓦片1的DC1系数、LP1系数、HP1系数、FLEX1系数的码流长度分别为a、b、c、d；即瓦片2的DC2系数、LP2系数、HP2系数、FLEX2系数的码流长度分别为e、f、g、h。
从图16中可以看出，DC1起始地址为c+g，LP1起始地址为c+g+a+e，HP1起始地址为0，……，FLEX2的起始地址为c+g+a+e+b+f+d。
本申请实施例提供的方案，通过按照新的索引表计算公式计算每一个瓦片中的各个系数的起始地址，可以保证本申请实施例提供的新的码流存储形式仍然符合标准规定。
示例性地，以待编码图像被划分为2个瓦片为例，假设即瓦片1的DC1系数、LP1系数、HP1系数、FLEX1系数的码流长度分别为10、12、8、9；瓦片2的DC2系数、LP2系数、HP2系数、FLEX2系数的码流长度分别为11、16、10、13。
则按照上述式(9)～式(12)可以得到瓦片1和瓦片2的索引表的数值，即DC1起始地址为18，LP1起始地址为39，HP1起始地址为0，FLEX1的起始地址为67，DC2起始地址为28，LP2起始地址为51，HP2起始地址为8，FLEX2的起始地址为89。
应理解，上述数值仅为举例说明，还可以为其它数值，不应对本申请造成特别限定。
对于其它可能的码流存储顺序，其索引表的数值计算公式有所差别，与上文没有实质性区别，为了简洁，这里不再赘述。
可选地，在一些实施例中，所述方法还可以包括：将所述待编码图像的多流分量的索引发送至解码器，以使得所述解码器根据所述多流分量的索引 对所述待编码图像进行解码。
本申请实施例中，在编码器对待编码图形编码完成后，可以将待编码图像的多流分量的索引发送至解码器，解码器在获得待编码图像的多流分量的索引后，可以根据该多流分量的索引对待编码图像进行解码。
可选地，在一些实施例中，所述编码方法应用于JPEG XR编码格式中。
如上所述，JPEG XR编码格式是一种连续色调静止图像压缩算法和文件格式，可以支持有损数据压缩以及无损数据压缩。
JPEG XR编码格式相比JPEG编码格式具有一定的优势。
首先，JPEG使用8位元编码，实现了256色，而JPEG可以使用16位元或更多，提供了更好的效果和更多的编辑灵活性。
其次，JPEG XR编码格式使用更加高效率的压缩算法，与JPEG文件同等大小的情况下，图像质量可以是后者的两倍，或同等质量只需后者一半的体积。并且与JPEG不同，JPEG XR的最高质量压缩可以不丢失任何信息。
上文结合图1-图16，详细描述了本申请的方法实施例，下面结合图17-图18，描述本申请的装置实施例，装置实施例与方法实施例相互对应，因此未详细描述的部分可参见前面各部分方法实施例。
图17为本申请实施例提供的一种编码装置1700的示意性结构图，该编码装置1700可以包括处理器1710。
处理器1710用于：
获取待编码图像的多个码流分量，所述多个码流分量中每一个码流分量包括所述待编码图像的一种变换系数的码流；将所述多个码流分量按照所述变换系数的种类顺序存储。
可选地，在一些实施例中，所述待编码图像包括n个瓦片，所述n个瓦片中的第i个瓦片包括若干个宏块，所述若干个宏块的同一种变换系数的码流顺序排列形成所述第i个瓦片的所述同一种变换系数的码流，所述n个瓦片的所述同一种变换系数的码流顺序排列形成所述待编码图像的所述同一种变换系数的码流；
其中，n为大于或等于1的正整数，i为小于或等于n的正整数。
可选地，在一些实施例中，所述处理器1710进一步用于：对于所述待编码图像的每一个宏块，将不同种变换系数的码流分别输出至不同的缓存空间，在不同的缓存空间中分别获取所述待编码图像的不同种变换系数的码 流。
可选地，在一些实施例中，所述处理器1710进一步用于：将所述缓存空间内的变换系数的码流存储至预设的存储设备中。
可选地，在一些实施例中，所述处理器1710进一步用于：生成所述待编码图像的信息，所述待编码图像的信息包括所述待编码图像的图像文件格式封装信息(TIFF封装信息)、所述待编码图像的图像头信息、所述待编码图像的索引表以及所述待编码图像的码流。
可选地，在一些实施例中，所述变换系数包括直流系数(DC系数)、低通系数(LP系数)、高通系数(HP系数)和可变截断系数(FLEX系数)。
可选地，在一些实施例中，所述处理器1710进一步用于：设置所述待编码图像的多流分量的索引。
可选地，在一些实施例中，所述待编码图像包括n个瓦片，所述所述处理器1710进一步用于：根据所述n个瓦片的每一个瓦片的多个码流分量中每一个码流分量的长度，按照预设分量顺序设置所述n个瓦片的多个码流分量的索引，所述预设分量顺序为DC系数码流分量、LP系数码流分量、HP系数码流分量和FLEX系数码流分量，n为大于1或等于1的正整数。
可选地，在一些实施例中，所述处理器1710进一步用于：将所述待编码图像的多流分量的索引发送至解码器，以使得所述解码器根据所述多流分量的索引对所述待编码图像进行解码。
可选地，在一些实施例中，所述编码装置应用于JPEG XR编码格式中。
可选地，在一些实施例中，该编码装置1700还可以包括存储器1720。
应理解，该编码装置1700还可以包括其他视频处理装置中通常所包括的部件，例如，收发器1730等，本申请实施例对此并不限定。
存储器1720用于存储计算机可执行指令。
处理器1710用于访问该存储器1720，并执行该计算机可执行指令，以进行上述本申请实施例的视频处理方法中的操作。
可选地，该编码装置例如可以是编码器、终端(包括但不限于手机、相机、无人机等)，并且该编码装置可以实现本申请实施例的各个方法中的相应流程，为了简洁，在此不再赘述。
图18是本申请实施例的芯片的示意性结构图。图18所示的芯片1800包括处理器1810，处理器1810可以从存储器中调用并运行计算机程序，以 实现本申请实施例中的方法。
可选地，如图18所示，芯片1800还可以包括存储器1820。其中，处理器1810可以从存储器1820中调用并运行计算机程序，以实现本申请实施例中的方法。
其中，存储器1820可以是独立于处理器1810一个单独的器件，也可以集成在处理器1810中。
可选地，该芯片1800还可以包括输入接口1830。其中，处理器1810可以控制该输入接口1830与其他装置或芯片进行通信，具体地，可以获取其他装置或芯片发送的信息或数据。
可选地，该芯片1800还可以包括输出接口1840。其中，处理器1810可以控制该输出接口1840与其他装置或芯片进行通信，具体地，可以向其他装置或芯片输出信息或数据。
应理解，本申请实施例提到的芯片还可以称为系统级芯片，系统芯片，芯片系统或片上系统芯片等。
应理解，本申请实施例的处理器可能是一种集成电路图像处理系统，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
可以理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable  ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。应注意，本文描述的系统和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
应理解，上述存储器为示例性但不是限制性说明，例如，本申请实施例中的存储器还可以是静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synch link DRAM，SLDRAM)以及直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)等等。也就是说，本申请实施例中的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
本申请实施例中的存储器可以向处理器提供指令和数据。存储器的一部分还可以包括非易失性随机存取存储器。例如，存储器还可以存储设备类型的信息。该处理器可以用于执行存储器中存储的指令，并且该处理器执行该指令时，该处理器可以执行上述方法实施例中与终端设备对应的各个步骤。
在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器执行存储器中的指令，结合其硬件完成上述方法 的步骤。为避免重复，这里不再详细描述。
还应理解，在本申请实施例中，图像中的像素点可以位于不同的行和/或列，其中，A的长度可以对应于A包括的位于同一行的像素点个数，A的高度可以对应于A包括的位于同一列的像素点个数。此外，A的长度和高度也可以分别称为A的宽度和深度，本申请实施例对此不做限定。
还应理解，在本申请实施例中，“与A的边界间隔分布”可以指与A的边界间隔至少一个像素点，也可以称为“不与A的边界相邻”或者“不位于A的边界”，本申请实施例对此不做限定，其中，A可以是图像、矩形区域或子图像，等等。
还应理解，上文对本申请实施例的描述着重于强调各个实施例之间的不同之处，未提到的相同或相似之处可以互相参考，为了简洁，这里不再赘述。
本申请实施例还提供了一种计算机可读存储介质，用于存储计算机程序。
可选的，该计算机可读存储介质可应用于本申请实施例中的编码装置，并且该计算机程序使得计算机执行本申请实施例的各个方法中由编码装置实现的相应流程，为了简洁，在此不再赘述。
本申请实施例还提供了一种计算机程序产品，包括计算机程序指令。
可选的，该计算机程序产品可应用于本申请实施例中的编码装置，并且该计算机程序指令使得计算机执行本申请实施例的各个方法中由编码装置实现的相应流程，为了简洁，在此不再赘述。
本申请实施例还提供了一种计算机程序。
可选的，该计算机程序可应用于本申请实施例中的编码装置，当该计算机程序在计算机上运行时，使得计算机执行本申请实施例的各个方法中由编码装置实现的相应流程，为了简洁，在此不再赘述。
应理解，在本申请实施例中，术语“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系。例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一 般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限 于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种编码方法，其特征在于，包括：
    获取待编码图像的多个码流分量，所述多个码流分量中每一个码流分量包括所述待编码图像的一种变换系数的码流；
    将所述多个码流分量按照所述变换系数的种类顺序存储。
  2. 根据权利要求1所述的编码方法，其特征在于，所述待编码图像包括n个瓦片，所述n个瓦片中的第i个瓦片包括若干个宏块，所述若干个宏块的同一种变换系数的码流顺序排列形成所述第i个瓦片的所述同一种变换系数的码流，所述n个瓦片的所述同一种变换系数的码流顺序排列形成所述待编码图像的所述同一种变换系数的码流；
    其中，n为大于或等于1的正整数，i为小于或等于n的正整数。
  3. 根据权利要求2所述的编码方法，其特征在于，所述获取待编码图像的多个码流分量，包括：
    对于所述待编码图像的每一个宏块，将不同种变换系数的码流分别输出至不同的缓存空间，在不同的缓存空间中分别获取所述待编码图像的不同种变换系数的码流。
  4. 根据权利要求3所述的编码方法，其特征在于，所述方法还包括：
    将所述缓存空间内的变换系数的码流存储至预设的存储设备中。
  5. 根据权利要求1至4中任一项所述的编码方法，其特征在于，所述方法还包括：
    生成所述待编码图像的信息，所述待编码图像的信息包括所述待编码图像的图像文件格式封装信息(TIFF封装信息)、所述待编码图像的图像头信息、所述待编码图像的索引表以及所述待编码图像的码流。
  6. 根据权利要求1至5中任一项所述的编码方法，其特征在于，所述变换系数包括直流系数(DC系数)、低通系数(LP系数)、高通系数(HP系数)和可变截断系数(FLEX系数)。
  7. 根据权利要求1至6中任一项所述的编码方法，其特征在于，所述方法还包括：
    设置所述待编码图像的多流分量的索引。
  8. 根据权利要求7所述的编码方法，其特征在于，所述待编码图像包 括n个瓦片，所述设置所述待编码图像的多流分量的索引，包括：
    根据所述n个瓦片的每一个瓦片的多个码流分量中每一个码流分量的长度，按照预设分量顺序设置所述n个瓦片的多流分量的索引，所述预设分量顺序为DC系数码流分量、LP系数码流分量、HP系数码流分量和FLEX系数码流分量，n为大于1或等于1的正整数。
  9. 根据权利要求7或8所述的编码方法，其特征在于，所述方法还包括：
    将所述待编码图像的多流分量的索引发送至解码器，以使得所述解码器根据所述多流分量的索引对所述待编码图像进行解码。
  10. 根据权利要求1至9中任一项所述的编码方法，其特征在于，所述编码方法应用于联合摄影专家组扩展范围编码格式(JPEG XR编码格式)中。
  11. 一种编码装置，其特征在于，包括：
    处理器，所述处理器用于：
    获取待编码图像的多个码流分量，所述多个码流分量中每一个码流分量包括所述待编码图像的一种变换系数的码流；
    将所述多个码流分量按照所述变换系数的种类顺序存储。
  12. 根据权利要求11所述的编码装置，其特征在于，所述待编码图像包括n个瓦片，所述n个瓦片中的第i个瓦片包括若干个宏块，所述若干个宏块的同一种变换系数的码流顺序排列形成所述第i个瓦片的所述同一种变换系数的码流，所述n个瓦片的所述同一种变换系数的码流顺序排列形成所述待编码图像的所述同一种变换系数的码流；
    其中，n为大于或等于1的正整数，i为小于或等于n的正整数。
  13. 根据权利要求12所述的编码装置，其特征在于，所述处理器进一步用于：
    对于所述待编码图像的每一个宏块，将不同种变换系数的码流分别输出至不同的缓存空间，在不同的缓存空间中分别获取所述待编码图像的不同种变换系数的码流。
  14. 根据权利要求13所述的编码装置，其特征在于，所述处理器进一步用于：
    将所述缓存空间内的变换系数的码流存储至预设的存储设备中。
  15. 根据权利要求11至14中任一项所述的编码装置，其特征在于，所 述处理器进一步用于：
    生成所述待编码图像的信息，所述待编码图像的信息包括所述待编码图像的图像文件格式封装信息(TIFF封装信息)、所述待编码图像的图像头信息、所述待编码图像的索引表以及所述待编码图像的码流。
  16. 根据权利要求11至15中任一项所述的编码装置，其特征在于，所述变换系数包括直流系数(DC系数)、低通系数(LP系数)、高通系数(HP系数)和可变截断系数(FLEX系数)。
  17. 根据权利要求11至16中任一项所述的编码装置，其特征在于，所述处理器进一步用于：
    设置所述待编码图像的多流分量的索引。
  18. 根据权利要求17所述的编码装置，其特征在于，所述待编码图像包括n个瓦片，所述所述处理器进一步用于：
    根据所述n个瓦片的每一个瓦片的多个码流分量中每一个码流分量的长度，按照预设分量顺序设置所述n个瓦片的多流分量的索引，所述预设分量顺序为DC系数码流分量、LP系数码流分量、HP系数码流分量和FLEX系数码流分量，n为大于1或等于1的正整数。
  19. 根据权利要求17或18所述的编码装置，其特征在于，所述处理器进一步用于：
    将所述待编码图像的多流分量的索引发送至解码器，以使得所述解码器根据所述多流分量的索引对所述待编码图像进行解码。
  20. 根据权利要求11至19中任一项所述的编码装置，其特征在于，所述编码装置应用于联合摄影专家组扩展范围编码格式(JPEG XR编码格式)中。
  21. 一种计算机可读存储介质，其特征在于，包括程序指令，所述程序指令被计算机运行时，所述计算机执行如权利要求1至10中任一项所述的编码方法。
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