WO2022012191A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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WO2022012191A1
WO2022012191A1 PCT/CN2021/097399 CN2021097399W WO2022012191A1 WO 2022012191 A1 WO2022012191 A1 WO 2022012191A1 CN 2021097399 W CN2021097399 W CN 2021097399W WO 2022012191 A1 WO2022012191 A1 WO 2022012191A1
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precursor
sidewall
sub
groove
semiconductor structure
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French (fr)
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储江
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor structure and a method for forming the same.
  • RC delay resistance-capacitance delay
  • the parasitic capacitance C is proportional to the dielectric constant k of the insulating medium in the circuit, if a low-k material is used as the insulating medium layer, the parasitic effect in the circuit will be greatly reduced, thereby improving the transmission speed of the signal.
  • the dielectric constant of air is close to 1. If air is introduced into the dielectric layer, the dielectric constant k of the dielectric layer can be greatly reduced.
  • Some embodiments of the present application provide a semiconductor structure and a method for forming the same, which can introduce an air gap into a dielectric layer and reduce the dielectric constant k of the dielectric layer.
  • some embodiments of the present application provide a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate has a groove, and the sidewall of the groove includes a first groove extending upward from the bottom of the groove.
  • the first sub-side wall is located between the second sub-side wall and the bottom of the groove; blowing the first sub-side wall to the surface of the substrate at a flow rate lower than a preset value a precursor, so that the first precursor is attached to the top surface of the substrate and the second sub-sidewall; blowing a second precursor to the substrate surface, so that the second precursor and the first A precursor reacts to form a dielectric layer; alternately blowing the first precursor and the second precursor to the surface of the substrate to form multiple layers of the dielectric layer until the top opening of the groove is blocked, the The first sub-sidewall, the area surrounded by the dielectric layer and the bottom of the groove constitute a gap.
  • the first precursor is blown at a flow rate that increases layer by layer.
  • the top surface area of the dielectric layer continues to increase. Therefore, it is necessary to increase the flow rate of the first precursor layer by layer to ensure that the dielectric layers are continuously stacked in the area surrounded by the second sub-sidewalls. Then the top opening of the groove is blocked.
  • the surface of the substrate has polar groups; in the process step of blowing the first precursor, the polar groups react with the first precursor to fix the function of the first precursor group. Since the substrate surface has polar groups that can react with the first precursor, in the blowing direction of the first precursor, the first precursor will adhere to the top surface of the substrate and the second sub-sidewalls that are first contacted, thereby avoiding The first precursor is attached to the first sub-sidewall or the bottom of the groove to ensure that the region surrounded by the first sub-sidewall has a lower dielectric constant.
  • the surface of the dielectric layer has polar groups; in the process step of blowing the first precursor, the polar groups react with the first precursor to fix the first precursor. functional group. Since the surface of the dielectric layer has polar groups that can fix the first precursor, when the first precursor is alternately blown, the first precursor will preferentially attach to the surface of the dielectric layer with polar groups, thereby avoiding the need for the first precursor Deposited on the first subsidewall or the bottom of the groove.
  • the polar group includes a hydroxyl group.
  • the material of the dielectric layer includes silicon dioxide, and at least one of the first precursor or the second precursor includes a silanol group-containing organic substance.
  • the silanol group-containing organic substance includes a 3-tert-butylsilanol group.
  • the first precursor includes a metal organic compound having a catalytic function. Since the 3-tert-butylsilanol group can selectively combine with metal organics, the use of metal organics as the first precursor can ensure that the 3-tert-butylsilanol group as the second precursor is only effective with the first precursor.
  • the dielectric layer is only formed at the attachment position of the first precursor, so as to avoid the deposition of the second precursor in the area surrounded by the first sub-sidewall, so that the void area surrounded by the first sub-sidewall has a low K dielectric constant; , the metal organic matter has a catalytic effect, which can accelerate the formation of the dielectric layer and shorten the process cycle.
  • the metal material in the metal organic includes at least one of aluminum, lanthanum, zirconium, or hafnium.
  • reaction temperature at which the first precursor and the second precursor react to form the dielectric layer is 225°C to 250°C.
  • a ratio of the height of the first sub-sidewall to the height of the second sub-sidewall is 1 to 9.
  • Some embodiments of the present application further provide a semiconductor structure, comprising: a substrate and a groove in the substrate, the sidewall of the groove includes a first sub-sidewall and a second sub-sidewall extending upward from the bottom of the groove sidewall, the first sub-sidewall is located between the second sub-sidewall and the bottom of the groove; a multi-layer dielectric layer, the multi-layer dielectric layer blocks the top opening of the groove, and is located at the bottom of the groove.
  • the sidewalls of the grooves are stacked in sequence toward the direction of the center axis of the grooves; and the voids are formed by the areas surrounded by the first sub-sidewalls, the bottom of the grooves, and the multi-layer dielectric layers.
  • the substrate has conductive structures located on opposite sides of the groove.
  • the multi-layer dielectric layer includes a metal material, and the metal material includes at least one of aluminum, lanthanum, zirconium or hafnium.
  • the first precursor is blown with a flow rate lower than the preset value, so that the first precursor is only attached to the top surface of the substrate and the second sub-sidewall.
  • the first sub-sidewall, the bottom of the groove and the area enclosed by the multilayer dielectric layers can form a void.
  • FIG. 1 , FIG. 2 , FIG. 4 , and FIGS. 11 to 13 are schematic structural diagrams corresponding to each step of the method for forming a semiconductor structure provided by an embodiment of the present application;
  • FIG. 3 and FIG. 5 to FIG. 10 are schematic diagrams of chemical reactions corresponding to the method for forming the semiconductor structure provided by the embodiments of the present application.
  • FIGS. 3 and 5 to 9 are a semiconductor structure provided by an embodiment of the present application. Schematic diagram of the chemical reaction corresponding to the formation method of .
  • a substrate 11 is provided.
  • the substrate 11 has a groove 111 therein.
  • the sidewall of the groove 111 includes a first subsidewall A1 and a second subsidewall A2 extending upward from the bottom of the groove 111.
  • the first subsidewall A1 between the second sub-side wall A2 and the bottom of the groove 111 .
  • the substrate 11 has conductive structures 112 located on opposite sides of the groove 111 , and the conductive structures 112 may be components such as wires, conductive plugs, and the like.
  • the conductive structures 112 When the conductive structures 112 are energized and operated, parasitic capacitances will be generated between adjacent conductive structures 112, and the magnitude of the parasitic capacitance depends on the dielectric constant k of the dielectric material between the adjacent conductive structures 112, and the lower the dielectric constant k is , the smaller the parasitic capacitance.
  • the substrate 11 further includes a protective layer 113 located on the sidewall of the conductive structure 112 and an isolation layer 114 located on the top surface of the conductive structure 112.
  • the protective layer 113 is usually the margin left when the groove 11 is formed by etching, In order to avoid damage to the conductive structure 112 by the etchant, the area surrounded by the protective layer 113 forms the groove 111 ;
  • the material of the protective layer 113 and the material of the isolation layer 114 may be the same or different.
  • this document does not limit the characteristics such as the formation methods, materials, and positions of the protective layer 113 and the isolation layer 114 . In fact, in other embodiments, there may be no protective layer and isolation layer, that is, the top surface and at least part of the sidewall surface of the conductive structure are exposed.
  • the area surrounded by the second sub-sidewall A2 is used to fill the subsequently formed dielectric layer, so as to block the top opening of the groove 111, and the area surrounded by the first sub-sidewall A1 is used to form a gap, whereby, the purpose of reducing the dielectric constant k of the dielectric layer between adjacent conductive structures 112 is achieved.
  • the ratio of the height of the first sub-sidewall A1 to the height of the second sub-sidewall A2 is 1 ⁇ 9, such as 3, 5 or 7.
  • the thickness ratio is determined by the staff before blowing the first precursor. The setting of the thickness ratio should not only ensure that the dielectric constant k of the dielectric layer between the adjacent conductive structures 112 is low, but also consider the feasibility of the process and the stability of the structure sex.
  • the feasibility of the process means that in the process of blowing the first precursor, it cannot be guaranteed that the first precursor is only coated on the top surface of the substrate 11, that is, the first precursor will adhere to the sidewall of the groove 111.
  • the structural stability refers to the bearing capacity of the dielectric layer, since other films may be formed on the substrate 11 later layer or structure, in order to prevent the dielectric layer from collapsing due to being unable to withstand the pressure, thereby affecting the dielectric constant k of the dielectric layer between adjacent conductive structures 112, the dielectric layer needs to have a certain thickness in the direction extending upward from the bottom of the groove 111 , so as to meet the preset bearing capacity requirements.
  • the technical solutions provided herein are usually applied to the grooves 111 with an aspect ratio greater than 1.
  • the aspect ratio of the grooves 111 is less than 1, the blown precursor is likely to contact the bottom of the grooves 111, resulting in Ideal voids cannot be formed.
  • the first precursor 12 is blown to the surface of the substrate 11 at a flow rate lower than a preset value, so that the first precursor 12 is attached to the top surface of the substrate 11 and the second sub-sidewall A2 .
  • the preset value is an ideal value.
  • a flow rate greater than or equal to the preset value is used to blow the first precursor 12 to the surface of the substrate 11, the first precursor 12 can cover the top surface of the substrate 11, the second sub-sidewall A2, the first precursor 12 The sub-side wall A1 and the bottom surface of the groove 111 .
  • the first precursor 12 contacts the top surface of the substrate 11 , the second sub-sidewall A2 , the first sub-sidewall A1 and the bottom surface of the groove 111 in sequence during the blowing process.
  • the first precursor 12 will preferentially adhere to the The surface of the substrate 11, ie, the top surface of the substrate 11 and the second sub-sidewall A2.
  • the first precursor 12 (refer to FIG. 2 ) undergoes a first reaction A on the surface of the substrate 11 (refer to FIG. 2 ).
  • the first precursor 12 includes a metal organic compound having a catalytic function, specifically, trimethylaluminum (CH3)3Al.
  • the catalytic function of the first precursor 12 is mainly used to accelerate the reaction of the first precursor 12 and the subsequently blown second precursor to generate a medium layer material.
  • the metal material in the metal organic comprises at least one of aluminum, lanthanum, zirconium or hafnium.
  • the surface of the substrate 11 has polar groups.
  • the polar groups react with the first precursor 12 to fix the functional groups of the first precursor 12 .
  • the surface of the substrate 11 has hydroxyl-OH.
  • the methyl-CH3 in the trimethylaluminum will react with the hydrogen atom -H in the hydroxyl group to form methane CH4, and the remaining -CH3Al is used as The functional group is connected to the oxygen ion in the original hydroxyl group to provide catalysis for the subsequent dielectric layer reaction.
  • the first precursor 12 will adhere to the top surface of the substrate 11 and the second sub-surface first contacted sidewall A2, thereby preventing the first precursor 12 from adhering to the first sub-sidewall A1 or the bottom of the groove 111, and ensuring that the area surrounded by the first sub-sidewall A1 has a lower dielectric constant.
  • the polar groups on the surface of the substrate 11 are naturally generated due to the exposure of the substrate 11 to the environment such as air or water vapor; in other embodiments, the polar groups can also be formed through certain process steps .
  • the polar group is not limited to a hydroxyl group, and can also be any polar group that can react with the first precursor 12 and fix its functional group; further, the substance attached to the surface of the substrate may not be polar. group, but any chemical substance that can react with the first precursor 12 and retain its functional group.
  • the state of the first precursor 12 is a gaseous state; in other embodiments, the state of the first precursor 12 may also be a liquid state.
  • the liquid state has a smaller intermolecular distance, and the viscosity of the fluid motion is relatively small. The hysteresis is more obvious. Therefore, the liquid first precursor is easier to adhere to the substrate surface after contacting the substrate surface, which is beneficial to ensure that the first precursor only adheres to the top surface of the substrate and the second sub-sidewall, so that the first precursor The region enclosed by the sub-sidewalls has a lower dielectric constant k.
  • the second precursor 13 is blown to the surface of the substrate 11 , so that the second precursor 13 reacts with the second precursor 12 (refer to FIG. 2 ) to form a dielectric layer 14 .
  • the material of the dielectric layer 14 is silicon dioxide
  • the silicon source of silicon dioxide includes a silanol group, that is, at least one of the first precursor 12 or the second precursor 13 includes an organic compound containing a silanol group .
  • Silicon dioxide has a low dielectric constant k, and silicon dioxide is selected as the material of the dielectric layer 14, which is beneficial to ensure that the area surrounded by the second sub-sidewall A2 (the area filled with the dielectric layer 14) has a low dielectric constant k.
  • the material of the second precursor 13 includes a 3-tert-butylsilanol group.
  • the 3-tert-butylsilanol group can selectively combine with metal organics, and the metal organics are used as the first precursor 12, and the 3-tert-butylsilanol group is used as the second precursor 13, which can ensure that the second precursor 13 is only Effectively combined with the first precursor 12, that is, the dielectric layer 14 is only formed at the attachment position of the first precursor 12, and the second precursor 13 is prevented from being attached to the first sub-sidewall A1 or the bottom surface of the groove 111, so that the first sub-side The area enclosed by the wall A1 has a lower dielectric constant k.
  • the first precursor 12 reacts with the second precursor 13 (refer to FIG. 4 ) to form the dielectric layer 14 (refer to FIG. 4 ).
  • the reaction process mainly includes the second reaction B, the third reaction Reaction C, fourth reaction D, fifth reaction E, sixth reaction F, and seventh reaction G.
  • the second reaction B and the third reaction C are the reactions between the 3-tert-butylsilanol group as a chain macromolecule and the surface substance of the substrate 11, and the surface substance of the substrate 11 will change as the reaction proceeds, and the fourth reaction D is The polymerization reactions, the fifth reaction E and the sixth reaction F produce two intermediate compounds side by side, and the seventh reaction G produces the final product silica.
  • a silicon dioxide film layer is formed through the reaction between chain macromolecules, which greatly improves the film formation efficiency of silicon dioxide. 50 to 100 times the film-forming efficiency.
  • the reaction temperature at which the first precursor 12 and the second precursor 13 react to form the dielectric layer 14 is 225° C. ⁇ 250° C., for example, 230° C., 237° C. or 245° C. At this reaction temperature, the first precursor 12 and the second precursor 13 have higher reaction rates, which is beneficial to shorten the process cycle.
  • a cleaning process is used to remove the redundant first precursor 12 , the second precursor 13 and various intermediate products generated by the reaction. Avoid excess unreacted precursors and reaction intermediates to affect the formation of the subsequent dielectric layer 14 and to avoid affecting the performance parameters of the finally formed multilayer dielectric layer 14, including dielectric constant k and bearing capacity.
  • the reaction temperature in the entire process flow is 225° C. ⁇ 250° C.
  • gaseous precursors and intermediates can be efficiently removed by passing inert gas.
  • the reaction temperature in the process flow can be adjusted according to the materials actually participating in the reaction and the intermediate products generated by the reaction, so as to achieve the preset purpose.
  • the first precursor 12 and the second precursor 13 are alternately blown to the surface of the substrate 11 to form the multilayer dielectric layer 14 until the top opening of the sealing groove 111 and the first sub-sidewall A1 (refer to FIG. 4 ) forms a void with the bottom of the groove 111 and the area surrounded by the multilayer dielectric layer 14 .
  • the surface of the dielectric layer 14 has polar groups.
  • the polar groups react with the first precursor 12 to fix the functional groups of the first precursor 12 . Since the surface of the dielectric layer 14 has polar groups that can fix the first precursor 12 , when the first precursor 12 is blown alternately, the first precursor 12 will adhere to the first contact surface, that is, the top surface and the side of the dielectric layer 14 . the wall surface, so as to prevent the first precursor 12 from adhering to the first sub-sidewall A1 or the bottom of the groove 111 .
  • the polar groups on the surface of the dielectric layer 14 can be either naturally generated by exposure to air or water vapor, or formed by processing; in addition, the surface of the dielectric layer 14 can also have polar groups other than polar groups. other substances to fix the functional group of the first precursor 12 .
  • the first precursor 12 in the process of forming the multilayer dielectric layer 14 , is blown at a gradually increasing flow rate. Since the surface area of the dielectric layer 14 gradually increases during the process of forming the multilayer dielectric layer 14 with the same thickness, the first precursor 12 needs to be blown at a gradually increasing flow rate so that the first precursor 12 can adhere to the dielectric layer. 14 , so as to seal the top opening of the groove 111 .
  • the dielectric layer 14 formed later covers the entire sidewall surface of the dielectric layer 14 formed earlier, so that the finally formed multilayer dielectric layer 14 fills the area surrounded by the second sub-sidewall A2,
  • This structure has high structural stability, and the multilayer dielectric layer 14 will not be broken due to the stress concentration problem when receiving the force from the conductive structure toward the groove 111 .
  • the later-formed dielectric layer 24 covers part of the sidewall surface of the earlier-formed dielectric layer 24 .
  • the blowing can be performed according to the same flow parameters.
  • the first precursor is beneficial to reduce the difficulty of the process.
  • a flow rate lower than a preset value is used to blow the first precursor, so that the first precursor is only attached to the top surface of the substrate and the second sub-sidewall.
  • a flow rate lower than a preset value is used to blow the first precursor, so that the first precursor is only attached to the top surface of the substrate and the second sub-sidewall.
  • the area surrounded by the first sub-sidewall, the bottom of the groove and the multi-layer dielectric layers can form a gap.
  • the embodiments of the present application further provide a semiconductor structure, and the semiconductor structure can be fabricated by using the above-mentioned method for forming a semiconductor structure.
  • the semiconductor structure includes: a substrate 11 and a groove 111 located in the substrate 11 , the groove 111 includes a first subsidewall and a second subsidewall extending upward from the bottom of the groove 111 , and the first subsidewall is located at the bottom of the groove 111 .
  • the multi-layer dielectric layer 14 blocks the top opening of the groove 111, and is sequentially stacked in the direction of the side wall of the groove 111 toward the center axis of the groove 111;
  • the void is formed by the first sub-sidewall, the bottom of the groove 111 and the area surrounded by the multi-layer dielectric layer 14 .
  • the substrate 11 has conductive structures 112 on opposite sides of the groove 111 .
  • the multilayer dielectric layer 14 includes a metal material, and the metal material includes at least one of aluminum, lanthanum, zirconium, or hafnium. The metal material does not affect the dielectric function of the dielectric layer 14 .
  • a new semiconductor structure is provided, and the semiconductor structure has a multi-layer dielectric layer that blocks the opening at the top of the groove and a gap surrounded by the first sub-sidewall, the bottom of the groove and the multi-layer dielectric layer, When voids are introduced into the dielectric layer, the dielectric layer has a lower dielectric constant k.

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Abstract

本申请实施例提供一种半导体结构及其形成方法，半导体结构的形成方法包括：提供基底，基底内具有凹槽，凹槽侧壁包括自凹槽底部向上延伸的第一子侧壁以及第二子侧壁，第一子侧壁位于第二子侧壁与凹槽底部之间；以低于预设值的流量向基底表面吹送第一前驱物，以使第一前驱物附着在基底顶部表面以及第二子侧壁；向基底表面吹送第二前驱物，以使第二前驱物与第一前驱物反应生成介质层；向基底表面交替吹送第一前驱物和第二前驱物，以形成多层介质层，直至填充满第二子侧壁围成的区域，第一子侧壁与介质层以及凹槽底部围成的区域构成空隙。

Description

半导体结构及其形成方法
交叉引用
本申请要求于2020年7月16日递交的名称为“半导体结构及其形成方法”、申请号为2020106871694的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体领域，特别涉及一种半导体结构及其形成方法。
背景技术
随着半导体技术的不断进步，影响电路传输速度的电阻电容延迟现象(RC delay)逐渐凸显。当前可以通过调整导体连线材料的方式降低寄生电阻R，而由于工艺上的限制，无法通过改变导体连线几何结构来降低寄生电容C。
由于寄生电容C正比于电路中绝缘介质的介电常数k，若使用低k材料作为绝缘介质层，会大大降低电路中的寄生效应，从而提高信号的传送速度。空气的介电常数接近1，若将空气引入介电层，则能够大大降低介电层的介电常数k。
发明内容
本申请部分实施例提供一种半导体结构及其形成方法，能够将空气间隙引入介电层，降低介电层的介电常数k。
为解决上述问题，本申请部分实施例提供一种半导体结构的形成方法，包括：提供基底，所述基底内具有凹槽，所述凹槽侧壁包括自所述凹槽底部向上延伸的第一子侧壁以及第二子侧壁，所述第一子侧壁位于所述第二子侧壁与所述凹槽底部之间；以低于预设值的流量向所述基底表面吹送第一前驱物，以使所述第一前驱物附着在所述基底顶部表面以及所述第二子侧壁；向所述基底表面吹送第二前驱物，以使所述第二前驱物与所述第一前驱物反应生成介质层；向所述基底表面交替吹送所述第一前驱物和所述第二前驱物，以形成多层所述介质层，直至封堵所述凹槽顶部开口，所述第一子侧壁与所述介质层以及所述凹槽底部围成的区域构成空隙。
另外，在形成多层所述介质层的过程中，以逐层递增的流量吹送所述第一前驱物。由于在逐层形成介质层的过程中，介质层顶面面积不断增大，因此，需要逐层增加第一前驱物的流量，才能保证介质层在第二子侧壁包围的区域内不断堆叠，进而封堵凹槽顶部开口。
另外，所述基底表面具有极性基团；在吹送所述第一前驱物的工艺步骤中，所述极性基团与所述第一前驱物发生反应，固定所述第一前驱物的功能基团。由于基底表面具有可与第一前驱物反应的极性基团，在第一前驱物在吹送方向上，第一前驱物会附着在先接触到的基底顶部表面以及第二子侧壁，从而避免第一前驱物在第一子侧壁或者凹槽底部附着，保证第一子侧壁所包围的区域具有较低的介电常数。
另外，所述介质层表面具有极性基团；在吹送所述第一前驱物的工艺步骤中，所述极性基团与所述第一前驱物发生反应，固定所述第一前驱物的功能基团。由于介质层表面具有可固定第一前驱物的极性基团，在交替吹送第一前驱物时，第一前驱物会优先附着在具有极性基团的介质层表面，从而避免第一前驱物在第一子侧壁或者凹槽底部沉积。
另外，所述极性基团包括羟基。
另外，所述介质层的材料包括二氧化硅，所述第一前驱物或所述第二前驱物中的至少一者包括含硅烷醇基的有机物。
另外，所述含硅烷醇基的有机物包括3-叔丁基硅烷醇基。
另外，所述第一前驱物包括具有催化作用的金属有机物。由于3-叔丁基硅烷醇基可选择性结合金属有机物，因此，采用金属有机物作为第一前驱物，能够保证作为第二前驱物的3-叔丁基硅烷醇基仅与第一前驱物有效结合，即仅在第一前驱物的附着位置形成介质层，避免第二前驱物沉积在第一子侧壁包围的区域，使得第一子侧壁包围的空隙区域具有低K介电常数；此外，金属有机物具有催化作用，能够加速介质层的形成，缩短工艺周期。
另外，所述金属有机物中的金属材料包括铝、镧、锆或铪中的至少一者。
另外，所述第一前驱物和所述第二前驱物反应形成所述介质层的反应温度为225℃～250℃。
另外，在垂直于所述基底表面的方向上，所述第一子侧壁的高度与第二子侧壁的高度比为1至9。通过控制第一前驱物的流量，控制第一子侧壁和第二子侧壁的厚度比，进而控制凹槽作为介电层时的介电常数。
本申请部分实施例还提供一种半导体结构，包括：基底和位于所述基底内的凹槽，所述凹槽侧壁包括自所述凹槽底部向上延伸的第一子侧壁以及第二子侧壁，所述第一子侧壁位于所述第二子侧壁和所述凹槽底部之间；多层介质层，所述多层介质层封堵所述凹槽顶部开口，且在所述凹槽侧壁朝向所述凹槽中心轴线的方向上依次层叠；空隙，所述空隙由所述第一子侧壁与所述凹槽底部以及所述多层介质层围成的区域构成。
另外，所述基底内具有位于所述凹槽相对两侧的导电结构。
另外，所述多层介质层内包含金属材料，所述金属材料包括铝、镧、锆或铪中的至少一者。
与现有技术相比，本申请部分实施例提供的技术方案具有以下优点：
上述技术方案中，采用低于预设值的流量吹送第一前驱物，使得第一前驱物仅附着在基底顶部表面以及第二子侧壁，如此，在形成封堵凹槽顶部开口的多层介质层时，第一子侧壁、凹槽底部以及多层介质层围成的区域能够构成空隙。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1、图2、图4以及图11至图13为本申请实施例提供的半导体结构的形成方法各步骤对应的结构示意图；
图3以及图5至图10为本申请实施例提供的半导体结构的形成方法对应的化学反应示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解， 在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1、图2、图4以及图10至图12为本申请实施例提供的半导体结构的形成方法各步骤对应的结构示意图；图3以及图5至图9为本申请实施例提供的半导体结构的形成方法对应的化学反应示意图。
参考图1，提供基底11，基底11内具有凹槽111，凹槽111侧壁包括自凹槽111底部向上延伸的第一子侧壁A1和第二子侧壁A2，第一子侧壁A1位于第二子侧壁A2和凹槽111底部之间。
本实施例中，基底11内具有位于凹槽111相对两侧的导电结构112，导电结构112可以是导线、导电插塞等部件。当导电结构112通电运行时，相邻导电结构112之间就会产生寄生电容，寄生电容的大小取决于相邻导电结构112之间的介电材料的介电常数k，介电常数k越低，寄生电容越小。
本实施例中，基底11还包括位于导电结构112侧壁的保护层113和位于导电结构112顶部表面的隔离层114，保护层113通常是在刻蚀形成凹槽11时留下的余量，以避免刻蚀剂对导电结构112造成损伤，保护层113包围的区域构成凹槽111；隔离层114主要起到刻蚀停止层的作用，避免刻蚀剂贯穿隔离层114而损伤导电结构112。保护层113的材料和隔离层114的材料可以相同也可以不同。
需要说明的是，本文并不对保护层113以及隔离层114的形成方法、材料以及位置等特征进行限定。实际上，在其他实施例中，也可以没有保护层和隔离层，即导电结构的顶面和至少部分侧壁表面是暴露出来的。
本实施例中，第二子侧壁A2包围的区域用于填充后续形成的介质层，从而起到封堵凹槽111顶部开口的目的，第一子侧壁A1包围的区域用于构成空隙，从而起到降低相邻导电结构112之间的介电层的介电常数k的目的。
本实施例中，在垂直于基底11表面的方向上，第一子侧壁A1的高度与第二子侧壁A2的高度比为1～9，例如3、5或7。该厚度比是工作人员在吹送第一前驱物之前确定的，厚度比的设置既要保证相邻导电结构112之间的介电层介电常数k较低，又要考虑工艺可行性以及结构稳定性。
工艺可行性指的是在吹送第一前驱物的过程中，无法保证第一前驱物仅涂覆在基底11顶部表面，即第一前驱物会附着在凹槽111部分侧壁，因此，在设定厚度比时，需要考虑第一前驱物的最小附着深度，从而设定合理有效的厚度比；此外，结构稳定性指的是介质层的承载能力，由于后续可能会在基底11上形成其他膜层或结构，为避免介质层因无法承受压力而坍塌，进而影响相邻导电结构112之间的介电层介电常数k，介质层在凹槽111底部向上延伸的方向上需要具有一定的厚度，从而满足预设的承载能力要求。
需要说明的是，本文提供的技术方案通常应用于深宽比大于1的凹槽111中，当凹槽111的深宽比小于1时，吹送的前驱物容易与凹槽111底部接触，从而导致无法形成理想的空隙。
参考图2，以低于预设值的流量向基底11表面吹送第一前驱物12，以使第一前驱物12附着在基底11顶部表面以及第二子侧壁A2。
预设值为一理想数值，采用大于或等于预设值的流量向基底11表面吹送第一前驱物12时，第一前驱物12能够覆盖基底11顶部表面、第二子侧壁A2、第一子侧壁A1以及凹槽111底面。其中，第一前驱物12在吹送过程中依次接触基底11顶部表面、第二子侧壁A2、第一子侧壁A1以及凹槽111底面。
在采用低于预设值的流量向基底11表面吹送第一前驱物12时，由于单位时间内的第一前驱物12的物质的量不足，第一前驱物12会优先附着在先接触到的基底11表面，即基底11顶部表面以及第二子侧壁A2。
参考图3，第一前驱物12(参考图2)在基底11(参考图2)表面发生第一反应A。
本实施例中，第一前驱物12包括具有催化作用的金属有机物，具体为三甲基铝(CH3)3Al。第一前驱物12的催化作用主要用于加速第一前驱物12和后续吹送的第二前驱物反应生成介质层材料。
其中，金属有机物中的金属材料包括铝、镧、锆或铪中的至少一者。
本实施例中，基底11表面具有极性基团，在吹送第一前驱物12的过程中，极性基团与第一前驱物12发生反应，固定第一前驱物12的功能基团。例如，基底11表面具有羟基-OH，在吹送三甲基铝的过程中，三甲基铝中的甲基 -CH3会与羟基中的氢原子-H发生反应生成甲烷CH4，剩余的-CH3Al作为功能基团与原羟基中的氧离子连接，为后续的介质层反应提供催化作用。
由于基底11表面具有可与第一前驱物12反应的极性基团，在第一前驱物12在吹送方向上，第一前驱物12会附着在先接触到的基底11顶部表面以及第二子侧壁A2，从而避免第一前驱物12在第一子侧壁A1或者凹槽111底部附着，保证第一子侧壁A1包围的区域具有较低的介电常数。
本实施例中，基底11表面的极性基团是由于基底11暴露在空气或水蒸气等环境下自然产生的；在其他实施例中，极性基团也可以是通过一定的工艺步骤形成的。此外，极性基团不限于羟基，也可以是任意一种可与第一前驱物12发生反应并固定其功能基团的极性基团；进一步地，基底表面附着的物质也可以不是极性基团，而是任一种可与第一前驱物12发生反应并保留其功能基团的化学物质。
本实施例中，第一前驱物12的状态为气态；在其他实施例中，第一前驱物的状态也可以是液态，液态相对于气态来说，由于分子间间距较小，流体运动的粘滞性更加明显，因此，液态的第一前驱物在接触到基底表面后更容易附着在基底表面，有利于保证第一前驱物仅附着在基底顶部表面和第二子侧壁上，使得第一子侧壁围成的区域具有较低的介电常数k。
参考图4，向基底11表面吹送第二前驱物13，以使第二前驱物13与第二前驱物12(参考图2)反应生成介质层14。
本实施例中，介质层14的材料为二氧化硅，二氧化硅的硅源包括硅烷醇基，即第一前驱物12或第二前驱物13中的至少一者包括含硅烷醇基的有机物。二氧化硅具有较低的介电常数k，选用二氧化硅作为介质层14的材料，有利于保证第二子侧壁A2围成的区域(介质层14填充该区域)具有较低的介电常数k。
本实施例中，第二前驱物13的材料包括3-叔丁基硅烷醇基。3-叔丁基硅烷醇基可选择性地结合金属有机物，采用金属有机物作为第一前驱物12，采用3-叔丁基硅烷醇基作为第二前驱物13，能够保证第二前驱物13仅与第一前驱物12有效结合，即仅在第一前驱物12的附着位置形成介质层14，避免第二前驱物13附着在第一子侧壁A1或者凹槽111底面，使得第一子侧壁A1包围的区域 具有较低的介电常数k。
参考图5至图10，第一前驱物12(参考图2)与第二前驱物13(参考图4)反应生成介质层14(参考图4)，反应过程主要包括第二反应B、第三反应C、第四反应D、第五反应E、第六反应F以及第七反应G。
第二反应B和第三反应C为作为链状大分子的3-叔丁基硅烷醇基与基底11表面物质发生的反应，基底11表面物质随着反应进行会发生变化，第四反应D为聚合反应，第五反应E和第六反应F生成了并列的两种中间化合物，第七反应G生成了最终产物二氧化硅。
本申请通过链状大分子之间的反应形成二氧化硅膜层，极大地提高了二氧化硅的成膜效率，本申请中的二氧化硅成膜效率是普通原子层沉积工艺的二氧化硅成膜效率的50至100倍。
本实施例中，第一前驱物12和第二前驱物13反应形成介质层14的反应温度为225℃～250℃，例如230℃、237℃或245℃。在该反应温度下，第一前驱物12和第二前驱物13具有较高的反应速率，有利于缩短工艺周期。
本实施例中，在形成一层介质层14之后，采用清洁工艺去除多余的第一前驱物12、第二前驱物13以及反应生成的多种中间产物。避免多余的未进行反应的前驱物以及反应中间产物影响后续介质层14的形成，以及避免影响最终形成的多层介质层14的性能参数，性能参数包括介电常数k和承载能力。
本实施例中，从开始吹送第一前驱物12到反应形成介质层14，整个工艺流程中的反应温度都是225℃～250℃。如此，有利于提高工艺流程中化学反应的反应速率，以及有利于使得前驱物和中间产物挥发为气态或保持气态，避免液态的前驱物和中间产物沉积在基底11表面而影响化学反应的进行；另外，气态的前驱物和中间产物能够通过通入惰性气体有效清除。
工艺流程中的反应温度可以根据实际参与反应的材料和反应生成的中间产物进行调整，以实现预设目的。
参考图11和图12，向基底11表面交替吹送第一前驱物12和第二前驱物13，以形成多层介质层14，直至封堵凹槽111顶部开口，第一子侧壁A1(参考图4)与凹槽111底部以及多层介质层14围成的区域构成空隙。
本实施例中，介质层14表面具有极性基团，在吹送第一前驱物12的过程中，极性基团与第一前驱物12发生反应，固定第一前驱物12的功能基团。由于介质层14表面具有可固定第一前驱物12的极性基团，在交替吹送第一前驱物12时，第一前驱物12会附着在先接触到表面，即介质层14顶面和侧壁表面，从而避免第一前驱物12在第一子侧壁A1或者凹槽111底部附着。
相应地，介质层14表面的极性基团既可以是暴露在空气或水蒸气等环境下自然产生的，也可以是加工形成的；此外，介质层14表面也可以具有除极性基团以外的其他物质，以固定第一前驱物12的功能基团。
本实施例中，在形成多层介质层14的过程中，以逐渐递增的流量吹送第一前驱物12。由于在形成厚度相同的多层介质层14的过程中，介质层14的表面积逐渐增大，因此，需要以逐渐递增的流量吹送第一前驱物12，使得第一前驱物12能够附着在介质层14的侧壁，进而实现封堵凹槽111的顶部开口。
本实施例中，在后形成的介质层14覆盖在先形成的介质层14的整个侧壁表面，如此，使得最终形成的多层介质层14填充满第二子侧壁A2围成的区域，这一结构具有较高的结构稳定性，在受到来自于导电结构朝向凹槽111的力时，多层介质层14不会因为应力集中问题发生破裂。
在其他实施例中，参考图13，在后形成的介质层24覆盖在先形成的介质层24的部分侧壁表面，如此，在逐层形成介质层24的过程中，可按照同一流量参数吹送第一前驱物，有利于降低工艺难度。
本实施例中，采用低于预设值的流量吹送第一前驱物，使得第一前驱物仅附着在基底顶部表面以及第二子侧壁，如此，在形成封堵凹槽顶部开口的多层介质层时，第一子侧壁与凹槽底部以及多层介质层围成的区域能够构成空隙。
相应地，本申请实施例还提供一种半导体结构，该半导体结构可采用上述半导体结构的形成方法制成。
参考图12，半导体结构包括：基底11和位于基底11内的凹槽111，凹槽111包括自凹槽111底部向上延伸的第一子侧壁和第二子侧壁，第一子侧壁位于第二子侧壁和凹槽111底部之间；多层介质层14，多层介质层14封堵凹槽111顶部开口，且在凹槽111侧壁朝向凹槽111中心轴线的方向依次层叠；空隙，空隙有第一子侧壁与凹槽111底部以及多层介质层14围成的区域构成。
本实施例中，基底11内具有位于凹槽111相对两侧的导电结构112。
本实施例中，多层介质层14内包含金属材料，金属材料包括铝、镧、锆或铪中的至少一者。金属材料不会影响介质层14的介电作用。
本实施例中，提供了一种新的半导体结构，该半导体结构具有封堵凹槽顶部开口的多层介质层以及由第一子侧壁、凹槽底部以及多层介质层围成的空隙，将空隙引入介电层时，介电层具有较低的介电常数k。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (14)

  1. 一种半导体结构的形成方法，包括：
    提供基底，所述基底内具有凹槽，所述凹槽侧壁包括自所述凹槽底部向上延伸的第一子侧壁以及第二子侧壁，所述第一子侧壁位于所述第二子侧壁与所述凹槽底部之间；
    以低于预设值的流量向所述基底表面吹送第一前驱物，以使所述第一前驱物附着在所述基底顶部表面以及所述第二子侧壁；
    向所述基底表面吹送第二前驱物，以使所述第二前驱物与所述第一前驱物反应生成介质层；
    向所述基底表面交替吹送所述第一前驱物和所述第二前驱物，以形成多层所述介质层，直至封堵所述凹槽顶部开口，所述第一子侧壁与所述介质层以及所述凹槽底部围成的区域构成空隙。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，在形成多层所述介质层的过程中，以逐层递增的流量吹送所述第一前驱物。
  3. 根据权利要求1所述的半导体结构的形成方法，其中，所述基底表面具有极性基团；在吹送所述第一前驱物的工艺步骤中，所述极性基团与所述第一前驱物发生反应，固定所述第一前驱物的功能基团。
  4. 根据权利要求1所述的半导体结构的形成方法，其中，所述介质层表面具有极性基团；在吹送所述第一前驱物的工艺步骤中，所述极性基团与所述第一前驱物发生反应，固定所述第一前驱物的功能基团。
  5. 根据权利要求3或4所述的半导体结构的形成方法，其中，所述极性基团包括羟基。
  6. 根据权利要求1所述的半导体结构的形成方法，其中，所述介质层的材料包括二氧化硅，所述第一前驱物或所述第二前驱物中的至少一者包括含硅烷醇基的有机物。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，所述含硅烷醇基的有机物包括3-叔丁基硅烷醇基。
  8. 根据权利要求1或7所述的半导体结构的形成方法，其中，所述第一前驱物包括具有催化作用的金属有机物。
  9. 根据权利要求8所述的半导体结构的形成方法，其中，所述金属有机物中的金属材料包括铝、镧、锆或铪中的至少一者。
  10. 根据权利要求1所述的半导体结构的形成方法，其中，所述第一前驱物和所述第二前驱物反应形成所述介质层的反应温度为225℃～250℃。
  11. 根据权利要求1所述的半导体结构的形成方法，其中，在垂直于所述基底表面的方向上，所述第一子侧壁的高度与第二子侧壁的高度比为1～9。
  12. 一种半导体结构，包括：
    基底和位于所述基底内的凹槽，所述凹槽侧壁包括自所述凹槽底部向上延伸的第一子侧壁以及第二子侧壁，所述第一子侧壁位于所述第二子侧壁和所述凹槽底部之间；
    多层介质层，所述多层介质层封堵所述凹槽顶部开口，且在所述凹槽侧壁朝向所述凹槽中心轴线的方向上依次层叠；
    空隙，所述空隙由所述第一子侧壁与所述凹槽底部以及所述多层介质层围成的区域构成。
  13. 根据权利要求12所述的半导体结构，其中，所述基底内具有位于所述凹槽相对两侧的导电结构。
  14. 根据权利要求13所述的半导体结构，其中，所述多层介质层内包含金属材料，所述金属材料包括铝、镧、锆或铪中的至少一者。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110021036A1 (en) * 2008-04-17 2011-01-27 Greg Braecklmann Method of sealing an air gap in a layer of a semiconductor structure and semiconductor structure
US20160086966A1 (en) * 2014-09-24 2016-03-24 Macronix International Co., Ltd. Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same
CN106935544A (zh) * 2015-12-30 2017-07-07 台湾积体电路制造股份有限公司 半导体装置与其形成方法
CN109478534A (zh) * 2016-08-09 2019-03-15 国际商业机器公司 纳米尺度的半导体器件的气隙间隔物构造

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531412B2 (en) 2001-08-10 2003-03-11 International Business Machines Corporation Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications
US8399349B2 (en) * 2006-04-18 2013-03-19 Air Products And Chemicals, Inc. Materials and methods of forming controlled void
JP5679581B2 (ja) * 2011-12-27 2015-03-04 東京エレクトロン株式会社 成膜方法
US8901706B2 (en) * 2012-01-06 2014-12-02 International Business Machines Corporation Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches
KR101477494B1 (ko) * 2013-07-08 2014-12-30 주식회사 테스 비정질 탄소막의 에어갭 형성방법
CN106033741B (zh) 2015-03-20 2020-09-15 联华电子股份有限公司 金属内连线结构及其制作方法
KR102695659B1 (ko) * 2018-01-19 2024-08-14 에이에스엠 아이피 홀딩 비.브이. 플라즈마 보조 증착에 의해 갭 충진 층을 증착하는 방법
CN108807339B (zh) 2018-06-04 2020-04-10 上海华虹宏力半导体制造有限公司 金属连线间形成空气隙的方法和金属连线结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110021036A1 (en) * 2008-04-17 2011-01-27 Greg Braecklmann Method of sealing an air gap in a layer of a semiconductor structure and semiconductor structure
US20160086966A1 (en) * 2014-09-24 2016-03-24 Macronix International Co., Ltd. Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same
CN106935544A (zh) * 2015-12-30 2017-07-07 台湾积体电路制造股份有限公司 半导体装置与其形成方法
CN109478534A (zh) * 2016-08-09 2019-03-15 国际商业机器公司 纳米尺度的半导体器件的气隙间隔物构造

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