WO2022004639A1 - Detection circuit - Google Patents

Detection circuit Download PDF

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WO2022004639A1
WO2022004639A1 PCT/JP2021/024318 JP2021024318W WO2022004639A1 WO 2022004639 A1 WO2022004639 A1 WO 2022004639A1 JP 2021024318 W JP2021024318 W JP 2021024318W WO 2022004639 A1 WO2022004639 A1 WO 2022004639A1
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signal
circuit
time
input
outputs
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PCT/JP2021/024318
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French (fr)
Japanese (ja)
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忠 織田
健次 島添
水紀 上ノ町
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国立大学法人東京大学
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Priority to JP2022533981A priority Critical patent/JP7386577B2/en
Publication of WO2022004639A1 publication Critical patent/WO2022004639A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01TMEASUREMENT OF NUCLEAR OR X-RADIATION
    • G01T1/00Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
    • G01T1/16Measuring radiation intensity
    • G01T1/17Circuit arrangements not adapted to a particular type of detector

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  • the present invention relates to a detection circuit that detects a sensor signal.
  • the Time-over-Threshold method is known as a sensor signal detection method (see, for example, Patent Document 1).
  • the ToT detection circuit that employs the ToT method measures a time width that exceeds a set threshold value for an input sensor signal.
  • the sensor signal is a short-time width current pulse signal
  • the adjustment signal passed through the primary semi-Gaussian waveform shaping circuit is input to the ToT detection circuit. If the time width is measured in this way, the peak value of the adjustment signal can be measured from the measured time width without using an ADC (Analog-to-Digital Converter).
  • the peak value of the adjustment signal can be used to estimate the amount of signal captured by the sensor. Since the ToT detection circuit does not need to mount an ADC, it can be realized relatively simply and on a small scale.
  • the detected time width is determined by the peak value of the adjustment signal adjusted through the semi-Gaussian waveform shaping circuit and the non-linearity of the time width.
  • the process of converting to a peak value was complicated.
  • there is also a problem of a time walk in which a difference in the rise of the signal occurs due to a difference in the wave height of the adjustment signal, and the time until the adjustment signal reaches the threshold value varies.
  • the present invention has been made to solve such a problem, and provides a detection circuit that suppresses the influence of the time walk while ensuring the line formation of the peak value and the time width.
  • the detection circuit includes a current mirror circuit that copies an input sensor signal and outputs the first input signal and the second input signal in parallel, and a voltage with respect to the elapsed time when the first input signal is input.
  • a waveform shaping circuit that adjusts the fluctuation according to the set reference fluctuation and outputs the adjustment signal, a voltage comparator that compares the voltage value of the adjustment signal with the reference voltage value, and outputs the first comparison signal, and the second. From the start of the second comparison signal, the current comparator that compares the current value of the input signal with the reference current value and outputs the second comparison signal, and the first comparison signal and the second comparison signal are subjected to logical calculations. It is provided with a logic calculation circuit that outputs a detection signal that continues until the end of the first comparison signal.
  • FIG. 1 is a graph showing an example of the waveform of the sensor signal S in handled in this embodiment.
  • the sensor signal S in is, for example, a short-time width current pulse signal which is an output signal of a photodetector for detecting scintillation light.
  • the horizontal axis shows the elapsed time, and the vertical axis shows the current value of the sensor signal.
  • the sensor signal S in three examples of the signals S a , S b , and S c are shown. Each sensor signal indicates a peak current value corresponding to the signal amount q detected by the sensor.
  • the peak current value of the signal S a is proportional to the amount of signal q a
  • the peak current value of the signal S b is proportional to the signal amount q b (> q a)
  • the peak of the signal S c current The value is proportional to the signal amount q c (> q b).
  • FIG. 2 shows an example of an output waveform obtained when the sensor signals (signals S a , S b , S c ) shown in FIG. 1 are input to a first-order semi-Gaussian waveform shaping circuit generally used in the prior art. Is shown.
  • the signal output by the waveform shaping circuit is referred to as an "adjustment signal".
  • the horizontal axis shows the elapsed time
  • the vertical axis shows the voltage value of the adjustment signal.
  • Signals S a, S b, S c by passing through the semi-Gaussian waveform shaping circuit, the adjustment signal S ra having a waveform defined by the time constant with the shaping circuit itself, is converted S rb, the S rc ..
  • Peak value is a peak value of the adjustment signal S ra is h a
  • the peak value of the adjustment signal S rb is h b a (> h a)
  • the peak value of the adjustment signal S rc is h c (> h b) Is.
  • These peak values h a , h b , and h c are proportional to the signal amount q a , the signal amount q b , and the signal amount q c.
  • the adjustment signal has a property that the signal having a larger peak value h rises sharper.
  • the time width of the adjustment signal S ra is t wa and the time width of the adjustment signal S rb is t wb (. > T wa ), and the time width of the adjustment signal S rc is t wc (> t wb ).
  • the linearity of the time width measured simply separated by the threshold value Vth is not guaranteed with respect to the peak value. That is, the amount of change in the time width with respect to the amount of change in the peak value is not constant.
  • FIG. 3 is a graph in which the rising region of the graph of FIG. 2 is enlarged. Even if the timing at which the adjustment signals rise is the same, the time required for each adjustment signal to reach the threshold value Vth differs due to the property that the adjustment signal with a larger peak value rises steeper.
  • the timings at which the illustrated adjustment signals S ra , S rb , and S rc rise are the same, but for example, the time until the adjustment signal S ra reaches the threshold value V th and the adjustment signal S rc reach the threshold value V th.
  • a so-called time walk occurs, as shown by the double-headed arrow.
  • the occurrence of time walk is an obstacle in order to accurately detect the occurrence timing of the sensor signal S in.
  • the detection circuit according to the present embodiment corresponds to such a problem, and is a detection circuit that suppresses the influence of the time walk while ensuring the line formation of the peak value and the time width.
  • FIG. 4 is a circuit diagram showing the overall configuration of the detection circuit 100 according to the present embodiment.
  • the detection circuit 100 is mainly composed of a current mirror circuit 110, a waveform shaping circuit 120, a voltage comparator 130, a current comparator 140, a one-shot circuit 150, and a logic operation circuit 160.
  • the detection circuit 100 is a circuit that detects a short-time width current pulse signal as a sensor signal, and outputs a pulse signal having a time width corresponding to the input sensor signal.
  • the current mirror circuit 110 copies the input sensor signal S in and outputs the first input signal S m1 and the second input signal S m2 in parallel.
  • the waveform shaping circuit 120 adjusts the voltage fluctuation with respect to the elapsed time so as to be in line with the set reference fluctuation, and outputs the adjustment signal S r1.
  • the voltage comparator 130 compares the voltage value V r1 of the adjustment signal S r1 with the reference voltage value V th , and outputs the first comparison signal Sc1.
  • the current comparator 140 compares the current value I m2 of the second input signal S m2 with the reference current value I th , and outputs the second comparison signal S c2.
  • One-shot circuit 150 generates and outputs an extension signal S p2 obtained by extending the signal duration of the second comparison signal S c2 input.
  • the logical operation circuit 160 performs a logical operation on the first comparison signal S c1 , the second comparison signal S c2, and the extension signal S p2 , and performs a logical operation on the first comparison signal S c1 from the start time of the second comparison signal S c2 .
  • the detection signal S out that continues until the end point is output.
  • FIG. 5 is a specific circuit example of the current mirror circuit 110.
  • the current mirror circuit 110 copies the sensor signal S in and parallels the first input signal S m1 from the OUT 1 terminal and the second input signal S m 2 from the OUT 2 terminal. And output.
  • the current mirror circuit 110 also functions as a current buffer circuit, and adjusts the current ratios of the first input signal S m1 and the second input signal S m2 to the sensor signal S in.
  • the first input signal S m1 is then input to the voltage comparator 130 via the waveform shaping circuit 120, a large current is not required, and the second input signal S m2 is then input to the current comparator 140, so that it is relatively relatively. It is convenient to have a large current. Therefore, in this embodiment, it is set so that 1> ⁇ > ⁇ .
  • FIG. 6 is a specific circuit example of the waveform shaping circuit 120.
  • the waveform shaping circuit 120 adjusts the voltage fluctuation with respect to the elapsed time so as to be in line with the set reference fluctuation, and outputs the adjustment signal S r1.
  • the reference fluctuation is set as a voltage fluctuation in which the amount of change in the voltage value with respect to the passage of time at the time of rising and the amount of change in the voltage value with respect to the passage of time at the time of falling are constant.
  • the waveform shaping circuit 120 is mainly composed of an operational amplifier, a capacitor, and a slew rate limiting resistance circuit 121 as shown in the figure, and the reference variation is determined by the circuit configuration of the slew rate limiting resistance circuit 121.
  • FIG. 7 is a graph showing a waveform example of the adjustment signal Sr1 , which is an output signal of the waveform shaping circuit 120. Similar to the graph of FIG. 2, the horizontal axis shows the elapsed time, and the vertical axis shows the voltage value of the sensor signal.
  • S b, S c is copied by the current mirror circuit 110, these signal output, respectively S 'ra, S' rb, and S 'rc.
  • Signal S 'peak value of ra is h a
  • the signal S' peak value of rb is h b
  • the peak value of the signal S 'rc is h c.
  • the signal S 'ra, S' rb, S 'rc varies almost linearly even when the rise time is also falling, the slope also coincide approximately with one another.
  • the signal S 'duration of ra is t' is wa
  • the time width of rb t' signal S wb (> t 'is a wa)
  • signal S' is the duration of the rc is t 'wc (>t' wb ).
  • Signal S 'ra, S' rb, S 'rc changes almost linearly even when the rise time is also falling, since the slope also coincide approximately with each other, the detected time width t ' W shows good linearity with respect to the peak value h. That is, the amount of change in the time width with respect to the amount of change in the crest value is almost constant, and the time width is proportional to the crest value.
  • FIG. 8 is a specific circuit example of the slew rate limiting resistance circuit 121.
  • the slew rate limiting resistor circuit 121 contributes to the setting of the reference variation that determines the circuit characteristics of the waveform shaping circuit 120. Specifically, depending on how the slew rate limiting resistance circuit 121 is configured, it is possible to adjust the inclination of the input first input signal S m1 at the rising edge and the tilt at the falling edge.
  • the slew rate limiting resistance circuit 121 includes a change unit 122 that adjusts the gate voltage of two FETs to which the end of the resistance element R is connected to the source.
  • the change unit 122 mainly has a variable resistor.
  • the resistance value of the variable resistor may be adjusted by an operator at the time of manufacturing the detection circuit 100, or may be changed by, for example, a control signal from a control device.
  • the variable resistance of the changing unit 122 by adjusting the variable resistance of the changing unit 122, the inclination of the input first input signal S m1 at the rising edge and the tilting at the falling edge are adjusted. These slopes are adjusted in consideration of the processing capacity per unit time (the number of sensor signals that can be processed in a unit time) required for the detection circuit 100, the stability of the circuit, and the like.
  • FIG. 9 is a specific circuit example of the one-shot circuit 150.
  • the one-shot circuit 150 When the second comparison signal Sc2 , which is a pulse signal output from the current comparator 140, is input to the one-shot circuit 150, the one-shot circuit 150 generates and outputs an extension signal Sp2 in which the signal end time is extended while maintaining the signal start time. do.
  • the one-shot circuit 150 is a circuit equivalent to a monostable multivibrator using a logic gate, and the extension time of the pulse signal is determined by the capacitance of the capacitor and the resistance value of the variable resistor included in the time adjustment unit 151.
  • the resistance value of the variable resistor may be adjusted by an operator at the time of manufacturing the detection circuit 100, or may be changed by, for example, a control signal from a control device.
  • FIG. 10 is a diagram showing specific examples of the input waveform and the output waveform of the logical operation circuit 160.
  • the logic operation circuit 160 in this embodiment is an OR logic gate having three input gates.
  • the first comparison signal S c1 , the second comparison signal S c2 , and the extension signal S p2 are input to the three input gates, respectively.
  • 10 (a) shows the waveform of the first comparison signal S c1
  • FIG. 10 (b) shows the waveform of the second comparison signal S c2
  • FIG. 10 (c) shows the waveform of the extension signal S p2 .
  • the horizontal axis shows the elapsed time
  • First comparison signal S c1 is also possible to limit the slew rate wave-shaping circuit 120, slightly delayed rising relative time of occurrence t 0 of the signal, changes from Low to High is the time t 2 There is. And, High is continued until the time t 4.
  • the duration from time t 2 to time t 4 is proportional to the peak value of the adjustment signal S r1 as described above.
  • the second comparison signal Sc2 is an output signal of the current comparator 140. Since the current comparator 140 targets the current value that rises sharply at the same time as the signal is generated, the second comparison signal Sc2 changes from Low to High at substantially the same time as the signal generation time t 0. However, since the current value rises sharply falls immediately without sustained, the second comparison signal S c2 is changed from High to Low to before time t 1 from time t 2.
  • the extension signal Sp2 is an output signal of the one-shot circuit 150.
  • the output wiring of the current comparator 140 is branched in the middle, one of which is connected to the input gate of the logical operation circuit 160 and the other of which is connected to the input terminal of the one-shot circuit 150.
  • the extension signal S p2 rises at approximately time t 0 at the same time as the second comparison signal Sc 2, and High continues until time t 3 after time t 2.
  • the extension time by the one-shot circuit 150 is such that the time t 3 is a time after the time t 2 which is the rising time of the first comparison signal S c1 and the falling time of the first comparison signal S c1 . it is adjusted to be the previous time from the time t 4 is the time.
  • the time t 4 referred to when adjusting the time t 3 is the falling time of the first comparison signal S c1 when the minimum peak value of the adjustment signals S r1 that can be the target is observed.
  • the logic operation circuit 160 in the present embodiment is an OR logic gate
  • any one of the first comparison signal Sc1 , the second comparison signal Sc2 , and the extension signal Sp2 is High. If so, the detection signal Out is also High.
  • the detection signal S out is Low.
  • the detection signal S out changes from Low to High at approximately time t 0 , and becomes a waveform in which the High state is continued until time t 4. That is, the logic operation circuit 160 starts at time t 0, and outputs a pulse signal having a time width Tw from time t 0 to time t 4.
  • FIG. 11 is a graph showing the correlation between the peak value h of the adjustment signal S r1 and the time width Tw of the detection signal S out.
  • the horizontal axis shows the peak value
  • the vertical axis shows the time width.
  • the time width Tw of the detection signal S out is proportional to the peak value of the adjustment signal S r1.
  • the peak value h a in FIG, h b, h c is the signal S 'ra, S' rb shown in FIG. 6, a respective peak value in the three examples of S 'rc
  • the time width Tw a , Tw b and Tw c are the time widths of the detection signals S out corresponding to each.
  • the time width Tw can be converted into numerical data. Further, the converted numerical data can be immediately converted into the peak value h by using the linearity shown in FIG.
  • the peak value h of the adjustment signal S r1 is proportional to the signal amount q of the sensor signal S in. Accordingly, terms have been peak value h can be converted into a signal quantity q of the input sensor signal S in. Since it is not necessary to mount an ADC in such a detection circuit 100 and a digital processing device around it, it can be realized relatively simply and on a small scale. That is, the entire device can be constructed at low cost, and the number of sensor signals that can be processed per unit time can be increased.
  • the time width Tw of the detection signal S out detection circuit 100 is output than equivalent to the time width t 'w adjusted by the waveform shaping circuit 120, showed good linearity with respect to the peak value h shows a good linearity with respect to the signal quantity q of turn sensor signal S in.
  • the rise time of the detection signal S out output by the detection circuit 100 is the rise time of the second comparison signal Sc2 , it is almost unaffected by the time walk and is extremely close to the generation timing of the sensor signal S in. .. That is, the processing device in the subsequent stage that processes the detection signal S out output by the detection circuit 100 can analyze the generation timing and the signal amount of the sensor signal with high accuracy.
  • Such a detection circuit 100 outputs a short-time width current pulse signal as a sensor signal, for example, a device such as Positron Emission Tomography (PET), Time-of-Fright PET, and photon counting CT used for cancer diagnosis. It has high utility value when it is incorporated as a signal processing circuit. It is not limited to a sensor that outputs a short-time width current pulse signal, but can also be used as a signal processing circuit for a sensor that outputs a signal that has a correlation between the peak value and the time width, such as monotonically increasing and then monotonically decreasing. It is possible.
  • PET Positron Emission Tomography
  • Time-of-Fright PET Time-of-Fright PET
  • CT photon counting CT used for cancer diagnosis. It has high utility value when it is incorporated as a signal processing circuit. It is not limited to a sensor that outputs a short-time width current pulse signal, but can also be used as a signal processing circuit for a sensor that outputs a signal that has a correlation between the peak value
  • the detection circuit 100 includes a one-shot circuit 150.
  • One-shot circuit 150 as described above, to generate an extended signal S p2 obtained by extending the signal end of the second comparison signal S c2. If the one-shot circuit 150 is not provided and t 2 is later than t 1 as shown in FIG. 10, the period from t 1 to t 2 in the detection signal S out is the Low level. Will be. To prevent such discontinuities, it generates a long signal S p2 delayed until t 3 is a time later than t 2 by a one-shot circuit 150, and is inputted to the logic operation circuit 160.
  • the one-shot circuit 150 can be omitted.
  • the signals input to the gate of the logical operation circuit 160 are two signals, the first comparison signal Sc1 and the second comparison signal Sc2 .
  • the logic operation circuit 160 of the detection circuit 100 is an OR logic gate of three signals, the first comparison signal Sc1 , the second comparison signal Sc2 , and the extension signal Sp2.
  • the second comparison signal S c2 is also input when the rise of the extension signal S p2 is delayed with respect to the rise of the second comparison signal S c2 depending on the configuration of the one-shot circuit 150. Because there is. However, if the delay is evaluated to be negligible, the logic operation circuit 160 may be an OR logic gate for inputting two signals , the first comparison signal Sc1 and the extension signal Sp2.
  • the OR logic gate is used in the logic operation circuit 160 described above , the period with signals in each of the first comparison signal S c1 , the second comparison signal S c2 , and the extension signal Sp 2 is set to the High level.
  • the logic gate to be used may be selected depending on whether the level is Low or Low. Of course, some logic gates may be combined to generate a detection signal S out.
  • FIG. 12 is an example of the detection result in the conventional ToT detection circuit.
  • the horizontal axis is represented by energy (keV) as a signal amount proportional to the peak value
  • the vertical axis is represented by time width (ns) as in FIG.
  • the 59.6 keV plot is the measurement result of 241 Am
  • 356 keV plot is the 133 Ba measurement result
  • the 122 keV plot is the 57 Co measurement result, 604.
  • the plots of 7 keV and 795.9 keV are the measurement results of 134 Cs, and the plots of 551 keV and 1275 keV are the measurement results of 22 Na. As shown in the figure, the obtained measurement results draw an upwardly convex curve, and the linearity of energy ( ⁇ peak value) and time width is not good.
  • FIG. 13 is an example of the detection result in one embodiment of the detection circuit 100 according to the present embodiment. Similar to FIG. 12, the horizontal axis is represented by energy (keV) and the vertical axis is represented by time width (ns).
  • the plot of 22 keV is the measurement result of 100 Cd
  • the plot of 59.6 keV is the measurement result of 241 Am
  • the plot of 30.9 keV, 81 keV, 356 keV is the measurement result of 133 Ba.
  • the 122 keV plot is the 57 Co measurement result
  • the 662 keV plot is the 137 Cs measurement result
  • the 551 keV plot is the 22 Na measurement result.
  • the obtained measurement results are almost straight lines, and good linearity of energy ( ⁇ peak value) and time width is obtained.

Abstract

Provided is a detection circuit including: a current mirror circuit that copies an input sensor signal to output a first input signal and a second input signal in parallel; a waveform shaping circuit that outputs, when the first input signal is input thereto, an adjustment signal in which a voltage variation with respect to elapsed time is adjusted so as to follow a set reference variation; a voltage comparator that compares the voltage value of the adjustment signal and a reference voltage value and that outputs a first comparison signal; a current comparator that compares the current value of the second input signal and a reference current value and that outputs a second comparison signal; and a logical operation circuit that performs a logical operation on the first comparison signal and the second comparison signal and that outputs a detection signal that continues from a start point in time of the second comparison signal to an end point in time of the first comparison signal. According to this detection circuit, it is possible to suppress the influence of time walk while ensuring linearity of the peak value and time width.

Description

検出回路Detection circuit
 本発明は、センサー信号を検出する検出回路に関する。 The present invention relates to a detection circuit that detects a sensor signal.
 センサー信号の検出手法として、Time-over-Threshold法(ToT法)が知られている(例えば、特許文献1参照)。ToT法を採用するToT検出回路は、入力されたセンサー信号に対して設定された閾値を越えた時間幅を計測する。センサー信号が短時間幅電流パルス信号である場合には、1次のセミガウシアン波形整形回路を通過させた調整信号をToT検出回路に入力する。このようにして時間幅を計測すれば、ADC(Analog-to-Digital Converter)を用いることなく、計測された時間幅から調整信号の波高値を計測することができる。調整信号の波高値は、センサーが捉えた信号量の推定に利用し得る。ToT検出回路は、ADCを実装する必要がないので、比較的シンプルかつ小規模に実現し得る。 The Time-over-Threshold method (ToT method) is known as a sensor signal detection method (see, for example, Patent Document 1). The ToT detection circuit that employs the ToT method measures a time width that exceeds a set threshold value for an input sensor signal. When the sensor signal is a short-time width current pulse signal, the adjustment signal passed through the primary semi-Gaussian waveform shaping circuit is input to the ToT detection circuit. If the time width is measured in this way, the peak value of the adjustment signal can be measured from the measured time width without using an ADC (Analog-to-Digital Converter). The peak value of the adjustment signal can be used to estimate the amount of signal captured by the sensor. Since the ToT detection circuit does not need to mount an ADC, it can be realized relatively simply and on a small scale.
特許第5531021号公報Japanese Patent No. 5531021
 従来のToT法によると、センサー信号が短時間幅電流パルス信号である場合には、セミガウシアン波形整形回路を経て調整された調整信号の波高値と時間幅の非線形性により、検出した時間幅を波高値へ変換する処理が複雑であった。また、当該調整信号の波高の違いによって信号の立ち上がりに差が生じ、調整信号が閾値に到達するまでの時間にばらつきが生じるタイムウォークの問題もあった。 According to the conventional ToT method, when the sensor signal is a short-time width current pulse signal, the detected time width is determined by the peak value of the adjustment signal adjusted through the semi-Gaussian waveform shaping circuit and the non-linearity of the time width. The process of converting to a peak value was complicated. Further, there is also a problem of a time walk in which a difference in the rise of the signal occurs due to a difference in the wave height of the adjustment signal, and the time until the adjustment signal reaches the threshold value varies.
 本発明は、このような問題を解決するためになされたものであり、波高値と時間幅の線形成を確保しつつ、タイムウォークの影響を抑制した検出回路を提供するものである。 The present invention has been made to solve such a problem, and provides a detection circuit that suppresses the influence of the time walk while ensuring the line formation of the peak value and the time width.
 本発明の一態様における検出回路は、入力されたセンサー信号をコピーして第1入力信号と第2入力信号を並列して出力するカレントミラー回路と、第1入力信号を入力すると経過時間に対する電圧変動を設定された基準変動に沿うように調整して調整信号を出力する波形整形回路と、調整信号の電圧値と基準電圧値を比較して第1比較信号を出力する電圧コンパレータと、第2入力信号の電流値と基準電流値を比較して第2比較信号を出力する電流コンパレータと、第1比較信号と第2比較信号に対して論理演算を行って、第2比較信号の開始時点から第1比較信号の終了時点まで継続する検出信号を出力する論理演算回路とを備える。 The detection circuit according to one aspect of the present invention includes a current mirror circuit that copies an input sensor signal and outputs the first input signal and the second input signal in parallel, and a voltage with respect to the elapsed time when the first input signal is input. A waveform shaping circuit that adjusts the fluctuation according to the set reference fluctuation and outputs the adjustment signal, a voltage comparator that compares the voltage value of the adjustment signal with the reference voltage value, and outputs the first comparison signal, and the second. From the start of the second comparison signal, the current comparator that compares the current value of the input signal with the reference current value and outputs the second comparison signal, and the first comparison signal and the second comparison signal are subjected to logical calculations. It is provided with a logic calculation circuit that outputs a detection signal that continues until the end of the first comparison signal.
 本発明により、波高値と時間幅の線形成を確保しつつ、タイムウォークの影響を抑制した検出回路を提供することができる。  INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a detection circuit that suppresses the influence of the time walk while ensuring the line formation of the peak value and the time width. It was
本実施形態で扱うセンサー信号の波形例を示すグラフである。It is a graph which shows the waveform example of the sensor signal handled in this embodiment. 従来技術において一般的に用いられる1次のセミガウシアン波形整形回路へ入力した場合に得られる出力波形の例を示す。An example of an output waveform obtained when inputting to a first-order semi-Gaussian waveform shaping circuit generally used in the prior art is shown. 図2のグラフの立ち上がり領域を拡大したグラフである。It is a graph which enlarged the rising area of the graph of FIG. 本実施形態に係る検出回路の全体構成を示す回路図である。It is a circuit diagram which shows the whole structure of the detection circuit which concerns on this embodiment. カレントミラー回路の具体的な回路例である。This is a specific circuit example of the current mirror circuit. 波形整形回路の具体的な回路例である。This is a specific circuit example of a waveform shaping circuit. 波形整形回路の出力信号である調整信号の波形例を示すグラフである。It is a graph which shows the waveform example of the adjustment signal which is an output signal of a waveform shaping circuit. スルーレート制限抵抗回路の具体的な回路例である。This is a specific circuit example of a slew rate limiting resistor circuit. ワンショット回路の具体的な回路例である。This is a concrete circuit example of a one-shot circuit. 論理演算回路の入力波形と出力波形の具体例を示す図である。It is a figure which shows the specific example of the input waveform and the output waveform of a logic operation circuit. 波高値と時間幅の相関を示すグラフである。It is a graph which shows the correlation of a crest value and a time width. 従来のToT検出回路における検出結果の例である。This is an example of the detection result in the conventional ToT detection circuit. 本実施形態に係る検出回路の一実施例における検出結果の例である。It is an example of the detection result in one Example of the detection circuit which concerns on this embodiment.
 以下、発明の実施の形態を通じて本発明を説明するが、特許請求の範囲に係る発明を以下の実施形態に限定するものではない。また、実施形態で説明する構成の全てが課題を解決するための手段として必須であるとは限らない。 Hereinafter, the present invention will be described through embodiments of the invention, but the invention according to the claims is not limited to the following embodiments. Moreover, not all of the configurations described in the embodiments are indispensable as means for solving the problem.
 図1は、本実施形態で扱うセンサー信号Sinの波形例を示すグラフである。センサー信号Sinは、例えばシンチレーション光を検出する光検出器の出力信号である短時間幅電流パルス信号である。横軸は経過時間を示し、縦軸はセンサー信号の電流値を示す。ここではセンサー信号Sinとして、信号S、S、Sの3つの例を示す。それぞれのセンサー信号は、センサーで検出された信号量qに応じたピーク電流値を示す。具体的には、信号Sのピーク電流値はその信号量qに比例し、信号Sのピーク電流値はその信号量q(>q)に比例し、信号Sのピーク電流値はその信号量q(>q)に比例する。 Figure 1 is a graph showing an example of the waveform of the sensor signal S in handled in this embodiment. The sensor signal S in is, for example, a short-time width current pulse signal which is an output signal of a photodetector for detecting scintillation light. The horizontal axis shows the elapsed time, and the vertical axis shows the current value of the sensor signal. Here, as the sensor signal S in , three examples of the signals S a , S b , and S c are shown. Each sensor signal indicates a peak current value corresponding to the signal amount q detected by the sensor. Specifically, the peak current value of the signal S a is proportional to the amount of signal q a, the peak current value of the signal S b is proportional to the signal amount q b (> q a), the peak of the signal S c current The value is proportional to the signal amount q c (> q b).
 図2は、図1で示すセンサー信号(信号S、S、S)を、従来技術において一般的に用いられる1次のセミガウシアン波形整形回路へ入力した場合に得られる出力波形の例を示す。本実施形態においては、波形整形回路が出力する信号を「調整信号」と称する。図において横軸は経過時間を示し、縦軸は調整信号の電圧値を示す。信号S、S、Sは、セミガウシアン波形整形回路を通過することにより、整形回路自身が持つ時定数によって規定される波形をもつ調整信号Sra、Srb、Srcへ変換される。 FIG. 2 shows an example of an output waveform obtained when the sensor signals (signals S a , S b , S c ) shown in FIG. 1 are input to a first-order semi-Gaussian waveform shaping circuit generally used in the prior art. Is shown. In the present embodiment, the signal output by the waveform shaping circuit is referred to as an "adjustment signal". In the figure, the horizontal axis shows the elapsed time, and the vertical axis shows the voltage value of the adjustment signal. Signals S a, S b, S c, by passing through the semi-Gaussian waveform shaping circuit, the adjustment signal S ra having a waveform defined by the time constant with the shaping circuit itself, is converted S rb, the S rc ..
 調整信号Sraのピーク値である波高値はhであり、調整信号Srbの波高値はh(>h)であり、調整信号Srcの波高値はh(>h)である。これらの波高値h、h、hは、信号量q、信号量q、信号量qと比例関係にある。また、図示するように、調整信号は、波高値hが大きい信号ほど急峻に立ち上がる性質を有する。 Peak value is a peak value of the adjustment signal S ra is h a, the peak value of the adjustment signal S rb is h b a (> h a), the peak value of the adjustment signal S rc is h c (> h b) Is. These peak values h a , h b , and h c are proportional to the signal amount q a , the signal amount q b , and the signal amount q c. Further, as shown in the figure, the adjustment signal has a property that the signal having a larger peak value h rises sharper.
 閾値Vthを設定し、閾値Vthを越えている継続時間をそれぞれの信号の時間幅とすると、調整信号Sraの時間幅はtwaであり、調整信号Srbの時間幅はtwb(>twa)であり、調整信号Srcの時間幅はtwc(>twb)である。図からも理解されるように、単に閾値Vthで区切って計測される時間幅は、波高値に対して線形性が担保されない。すなわち、波高値の変化量に対する時間幅の変化量が一定でない。波高値に対する時間幅の線形性が担保されていないと、検出回路によって時間幅が検出されても、時間幅を波高値に変換するための後処理が複雑になり、多大な処理時間を要してしまう。 Assuming that the threshold value V th is set and the duration exceeding the threshold value V th is the time width of each signal, the time width of the adjustment signal S ra is t wa and the time width of the adjustment signal S rb is t wb (. > T wa ), and the time width of the adjustment signal S rc is t wc (> t wb ). As can be understood from the figure , the linearity of the time width measured simply separated by the threshold value Vth is not guaranteed with respect to the peak value. That is, the amount of change in the time width with respect to the amount of change in the peak value is not constant. If the linearity of the time width with respect to the crest value is not guaranteed, even if the time width is detected by the detection circuit, the post-processing for converting the time width to the crest value becomes complicated and requires a large amount of processing time. Will end up.
 図3は、図2のグラフの立ち上がり領域を拡大したグラフである。調整信号が立ち上がるタイミングは同一であっても、上述した波高値が大きい調整信号ほど急峻に立ち上がる性質により、それぞれの調整信号が閾値Vthに到達するまでの時間は異なってしまう。図示する調整信号Sra、Srb、Srcが立ち上がるタイミングは同一であるが、例えば、調整信号Sraが閾値Vthに到達するまでの時間と、調整信号Srcが閾値Vthに到達するまでの時間の間には、両矢印で示すように、いわゆるタイムウォークが生じている。タイムウォークの発生は、センサー信号Sinの発生タイミングを正確に検知するうえで障害となる。 FIG. 3 is a graph in which the rising region of the graph of FIG. 2 is enlarged. Even if the timing at which the adjustment signals rise is the same, the time required for each adjustment signal to reach the threshold value Vth differs due to the property that the adjustment signal with a larger peak value rises steeper. The timings at which the illustrated adjustment signals S ra , S rb , and S rc rise are the same, but for example, the time until the adjustment signal S ra reaches the threshold value V th and the adjustment signal S rc reach the threshold value V th. During the time until, a so-called time walk occurs, as shown by the double-headed arrow. The occurrence of time walk is an obstacle in order to accurately detect the occurrence timing of the sensor signal S in.
 本実施形態に係る検出回路は、このような課題に対応するものであり、波高値と時間幅の線形成を確保しつつ、タイムウォークの影響を抑制する検出回路である。図4は、本実施形態に係る検出回路100の全体構成を示す回路図である。検出回路100は、主に、カレントミラー回路110、波形整形回路120、電圧コンパレータ130、電流コンパレータ140、ワンショット回路150、論理演算回路160によって構成される。 The detection circuit according to the present embodiment corresponds to such a problem, and is a detection circuit that suppresses the influence of the time walk while ensuring the line formation of the peak value and the time width. FIG. 4 is a circuit diagram showing the overall configuration of the detection circuit 100 according to the present embodiment. The detection circuit 100 is mainly composed of a current mirror circuit 110, a waveform shaping circuit 120, a voltage comparator 130, a current comparator 140, a one-shot circuit 150, and a logic operation circuit 160.
 本実施形態において検出回路100は、センサー信号としての短時間幅電流パルス信号を検出する回路であり、入力されたセンサー信号に応じた時間幅を持つパルス信号を出力する。カレントミラー回路110は、入力されたセンサー信号Sinをコピーして第1入力信号Sm1と第2入力信号Sm2を並列して出力する。波形整形回路120は、第1入力信号Sm1を入力すると、経過時間に対する電圧変動を設定された基準変動に沿うように調整して調整信号Sr1を出力する。電圧コンパレータ130は、調整信号Sr1の電圧値Vr1と基準電圧値Vthを比較して第1比較信号Sc1を出力する。 In the present embodiment, the detection circuit 100 is a circuit that detects a short-time width current pulse signal as a sensor signal, and outputs a pulse signal having a time width corresponding to the input sensor signal. The current mirror circuit 110 copies the input sensor signal S in and outputs the first input signal S m1 and the second input signal S m2 in parallel. When the first input signal S m1 is input, the waveform shaping circuit 120 adjusts the voltage fluctuation with respect to the elapsed time so as to be in line with the set reference fluctuation, and outputs the adjustment signal S r1. The voltage comparator 130 compares the voltage value V r1 of the adjustment signal S r1 with the reference voltage value V th , and outputs the first comparison signal Sc1.
 電流コンパレータ140は、第2入力信号Sm2の電流値Im2と基準電流値Ithを比較して第2比較信号Sc2を出力する。ワンショット回路150は、入力された第2比較信号Sc2の信号継続時間を延長させた延長信号Sp2を生成して出力する。論理演算回路160は、第1比較信号Sc1と第2比較信号Sc2と延長信号Sp2に対して論理演算を行って、第2比較信号Sc2の開始時点から第1比較信号Sc1の終了時点まで継続する検出信号Soutを出力する。各要素の具体的な作用等について、以下に順次説明する。 The current comparator 140 compares the current value I m2 of the second input signal S m2 with the reference current value I th , and outputs the second comparison signal S c2. One-shot circuit 150 generates and outputs an extension signal S p2 obtained by extending the signal duration of the second comparison signal S c2 input. The logical operation circuit 160 performs a logical operation on the first comparison signal S c1 , the second comparison signal S c2, and the extension signal S p2 , and performs a logical operation on the first comparison signal S c1 from the start time of the second comparison signal S c2 . The detection signal S out that continues until the end point is output. The specific actions of each element will be described below in sequence.
 図5は、カレントミラー回路110の具体的な回路例である。カレントミラー回路110は、センサー信号SinがIN端子に入力されると、センサー信号SinがコピーされてOUT1端子から第1入力信号Sm1を、OUT2端子から第2入力信号Sm2を並列して出力する。カレントミラー回路110は、電流バッファ回路としても機能し、センサー信号Sinに対する第1入力信号Sm1および第2入力信号Sm2のそれぞれの電流比を調整する。 FIG. 5 is a specific circuit example of the current mirror circuit 110. When the sensor signal S in is input to the IN terminal, the current mirror circuit 110 copies the sensor signal S in and parallels the first input signal S m1 from the OUT 1 terminal and the second input signal S m 2 from the OUT 2 terminal. And output. The current mirror circuit 110 also functions as a current buffer circuit, and adjusts the current ratios of the first input signal S m1 and the second input signal S m2 to the sensor signal S in.
 センサー信号Sinの電流値をIin、第1入力信号Sm1および第2入力信号Sm2の電流値をそれぞれIm1、Im2とすると、Im1=α×Iin、Im2=β×Iinと表される。すなわち、センサー信号Sinに対する第1入力信号Sm1の電流比はαであり、センサー信号Sinに対する第2入力信号Sm2の電流比はβに調整されている。具体的には、互いのゲートが接続されている3つのFET(Field Effect Transistor)が、それぞれのチャンネル幅が1:α:βとなるように選択され、採用されている。第1入力信号Sm1は、その後波形整形回路120を経て電圧コンパレータ130へ入力されるので大きな電流は不要であり、第2入力信号Sm2は、その後電流コンパレータ140へ入力されるので、比較的大きな電流であったほうが都合が良い。したがって、本実施形態においては、1>β>αとなるように設定されている。 Assuming that the current values of the sensor signal S in are I in and the current values of the first input signal S m1 and the second input signal S m2 are I m1 and I m2 , respectively, I m1 = α × I in and I m2 = β ×. Expressed as I in . That is, the current ratio of the first input signal S m1 to the sensor signal S in is alpha, the current ratio of the second input signal S m @ 2 to the sensor signal S in is adjusted to beta. Specifically, three FETs (Field Effect Transistors) to which the gates of each other are connected are selected and adopted so that the channel width of each FET is 1: α: β. Since the first input signal S m1 is then input to the voltage comparator 130 via the waveform shaping circuit 120, a large current is not required, and the second input signal S m2 is then input to the current comparator 140, so that it is relatively relatively. It is convenient to have a large current. Therefore, in this embodiment, it is set so that 1>β> α.
 図6は、波形整形回路120の具体的な回路例である。上述のように、これまで一般的に用いられていた1次のセミガウシアン波形整形回路を用いると、図2で示したように、センサー信号Sinの信号量に比例して波高値が変化するものの、互いの波高値が異なれば時間経過に対する電圧値の変化量も異なっていた。したがって、波高値に対する時間幅の線形性が失われていた。そこで、本実施形態においては、波形整形回路120として、スルーレート制限型の波形整形回路を採用する。 FIG. 6 is a specific circuit example of the waveform shaping circuit 120. As described above, the use of primary semi Gaussian waveform shaping circuit used generally so far, as shown in FIG. 2, the peak value varies in proportion to the signal amount of the sensor signal S in However, if the peak values were different from each other, the amount of change in the voltage value with the passage of time was also different. Therefore, the linearity of the time width with respect to the crest value was lost. Therefore, in the present embodiment, a slew rate limiting type waveform shaping circuit is adopted as the waveform shaping circuit 120.
 波形整形回路120は、第1入力信号Sm1を入力すると、経過時間に対する電圧変動を設定された基準変動に沿うように調整して調整信号Sr1を出力する。基準変動は、立ち上がり時における時間経過に対する電圧値の変化量と、立ち下がり時における時間経過に対する電圧値の変化量とが、それぞれ一定値となる電圧変動として設定されている。具体的には、波形整形回路120は、図示するように主にオペアンプ、コンデンサ、スルーレート制限抵抗回路121によって構成され、基準変動は、スルーレート制限抵抗回路121の回路構成によって決定される。 When the first input signal S m1 is input, the waveform shaping circuit 120 adjusts the voltage fluctuation with respect to the elapsed time so as to be in line with the set reference fluctuation, and outputs the adjustment signal S r1. The reference fluctuation is set as a voltage fluctuation in which the amount of change in the voltage value with respect to the passage of time at the time of rising and the amount of change in the voltage value with respect to the passage of time at the time of falling are constant. Specifically, the waveform shaping circuit 120 is mainly composed of an operational amplifier, a capacitor, and a slew rate limiting resistance circuit 121 as shown in the figure, and the reference variation is determined by the circuit configuration of the slew rate limiting resistance circuit 121.
 図7は、波形整形回路120の出力信号である調整信号Sr1の波形例を示すグラフである。図2のグラフと同じく、横軸は経過時間を示し、縦軸はセンサー信号の電圧値を示す。ここでは、波形整形回路120へ入力される第1入力信号Sm1として図1で示す信号S、S、Sがカレントミラー回路110でコピーされた第1入力信号を想定し、これらの出力をそれぞれ信号S’ra、S’rb、S’rcとする。 FIG. 7 is a graph showing a waveform example of the adjustment signal Sr1 , which is an output signal of the waveform shaping circuit 120. Similar to the graph of FIG. 2, the horizontal axis shows the elapsed time, and the vertical axis shows the voltage value of the sensor signal. Here, assuming the first input signal a first input signal S m1 as the signal S a shown in FIG. 1 to be input to the waveform shaping circuit 120, S b, S c is copied by the current mirror circuit 110, these signal output, respectively S 'ra, S' rb, and S 'rc.
 信号S’raの波高値はhであり、信号S’rbの波高値はhであり、信号S’rcの波高値はhである。信号S’ra、S’rb、S’rcの立ち上がり時における時間経過に対する電圧値の変化量はいずれもほぼ等しくなるように調整されており、同様に、立ち下がり時における時間経過に対する電圧値の変化量もいずれもほぼ等しくなるように調整されている。換言すれば、信号S’ra、S’rb、S’rcは、立ち上がり時も立ち下がり時もほぼ直線状に変化し、その傾きも互いにおよそ一致している。 Signal S 'peak value of ra is h a, the signal S' peak value of rb is h b, the peak value of the signal S 'rc is h c. Signal S 'ra, S' rb, S ' variation of the voltage value over time when the rise of rc is adjusted to either substantially equal, likewise, the voltage value over time at the fall The amount of change is also adjusted so that they are almost equal. In other words, the signal S 'ra, S' rb, S 'rc varies almost linearly even when the rise time is also falling, the slope also coincide approximately with one another.
 設定された閾値Vthを越えている継続時間をそれぞれの信号の時間幅とすると、信号S’raの時間幅はt’waであり、信号S’rbの時間幅はt’wb(>t’wa)であり、信号S’rcの時間幅はt’wc(>t’wb)である。信号S’ra、S’rb、S’rcは、上述のように、立ち上がり時も立ち下がり時もほぼ直線状に変化し、その傾きも互いにおよそ一致しているので、検出された時間幅t’は、波高値hに対して良好な線形性を示す。すなわち、波高値の変化量に対する時間幅の変化量がほぼ一定となり、時間幅は波高値に比例することになる。 When set threshold V th in which duration exceeds the a and duration of each signal, the signal S 'duration of ra is t' is wa, 'the time width of rb t' signal S wb (> t 'is a wa), signal S' is the duration of the rc is t 'wc (>t' wb ). Signal S 'ra, S' rb, S 'rc , as described above, changes almost linearly even when the rise time is also falling, since the slope also coincide approximately with each other, the detected time width t ' W shows good linearity with respect to the peak value h. That is, the amount of change in the time width with respect to the amount of change in the crest value is almost constant, and the time width is proportional to the crest value.
 図8は、スルーレート制限抵抗回路121の具体的な回路例である。スルーレート制限抵抗回路121は、波形整形回路120の回路特性を決定する基準変動の設定に寄与する。具体的には、スルーレート制限抵抗回路121をどのように構成するかによって、入力される第1入力信号Sm1の立ち上がり時の傾きと、立ち下がり時の傾きを調整することができる。 FIG. 8 is a specific circuit example of the slew rate limiting resistance circuit 121. The slew rate limiting resistor circuit 121 contributes to the setting of the reference variation that determines the circuit characteristics of the waveform shaping circuit 120. Specifically, depending on how the slew rate limiting resistance circuit 121 is configured, it is possible to adjust the inclination of the input first input signal S m1 at the rising edge and the tilt at the falling edge.
 スルーレート制限抵抗回路121は、図示するように、ソースに抵抗素子Rの端が接続された2つのFETのゲート電圧を調整する変更部122を備える。変更部122は、主に可変抵抗を有する。可変抵抗の抵抗値は、検出回路100の製造時に作業者によって調整されてもよいし、例えば制御装置からの制御信号によって変更される構成であってもよい。本実施形態においては、変更部122の可変抵抗を調整することにより、入力される第1入力信号Sm1の立ち上がり時の傾きと、立ち下がり時の傾きを調整する。これらの傾きは、検出回路100に求める単位時間当たりの処理能力(単位時間で処理可能なセンサー信号数)や、回路の安定性等を考慮して調整される。 As shown in the figure, the slew rate limiting resistance circuit 121 includes a change unit 122 that adjusts the gate voltage of two FETs to which the end of the resistance element R is connected to the source. The change unit 122 mainly has a variable resistor. The resistance value of the variable resistor may be adjusted by an operator at the time of manufacturing the detection circuit 100, or may be changed by, for example, a control signal from a control device. In the present embodiment, by adjusting the variable resistance of the changing unit 122, the inclination of the input first input signal S m1 at the rising edge and the tilting at the falling edge are adjusted. These slopes are adjusted in consideration of the processing capacity per unit time (the number of sensor signals that can be processed in a unit time) required for the detection circuit 100, the stability of the circuit, and the like.
 図9は、ワンショット回路150の具体的な回路例である。ワンショット回路150は、電流コンパレータ140から出力されたパルス信号である第2比較信号Sc2を入力すると、信号開始時点を維持したまま信号終了時点を延長させた延長信号Sp2を生成して出力する。ワンショット回路150は、論理ゲートを用いた単安定マルチバイブレータと同等の回路であり、パルス信号の延長時間は、コンデンサの容量と、時間調整部151が含む可変抵抗の抵抗値によって定まる。可変抵抗の抵抗値は、検出回路100の製造時に作業者によって調整されてもよいし、例えば制御装置からの制御信号によって変更される構成であってもよい。 FIG. 9 is a specific circuit example of the one-shot circuit 150. When the second comparison signal Sc2 , which is a pulse signal output from the current comparator 140, is input to the one-shot circuit 150, the one-shot circuit 150 generates and outputs an extension signal Sp2 in which the signal end time is extended while maintaining the signal start time. do. The one-shot circuit 150 is a circuit equivalent to a monostable multivibrator using a logic gate, and the extension time of the pulse signal is determined by the capacitance of the capacitor and the resistance value of the variable resistor included in the time adjustment unit 151. The resistance value of the variable resistor may be adjusted by an operator at the time of manufacturing the detection circuit 100, or may be changed by, for example, a control signal from a control device.
 図10は、論理演算回路160の入力波形と出力波形の具体例を示す図である。本実施形態における論理演算回路160は、3つの入力ゲートを有するOR論理ゲートである。3つの入力ゲートには、それぞれ第1比較信号Sc1、第2比較信号Sc2、延長信号Sp2が入力される。図10(a)は第1比較信号Sc1の波形を表し、図10(b)は第2比較信号Sc2の波形を表し、図10(c)は、延長信号Sp2の波形を表わす。横軸は経過時間を示し、縦軸は、信号レベル(High=1、Low=0)を示す。 FIG. 10 is a diagram showing specific examples of the input waveform and the output waveform of the logical operation circuit 160. The logic operation circuit 160 in this embodiment is an OR logic gate having three input gates. The first comparison signal S c1 , the second comparison signal S c2 , and the extension signal S p2 are input to the three input gates, respectively. 10 (a) shows the waveform of the first comparison signal S c1 , FIG. 10 (b) shows the waveform of the second comparison signal S c2 , and FIG. 10 (c) shows the waveform of the extension signal S p2 . The horizontal axis shows the elapsed time, and the vertical axis shows the signal level (High = 1, Low = 0).
 第1比較信号Sc1は、波形整形回路120でスルーレートを制限することもあり、信号の発生時刻tに対して立ち上がりが若干遅延し、時刻tになってLowからHighへ変化している。そして、時刻tまでHighが継続している。時刻tから時刻tまでの継続時間は、上述のように、調整信号Sr1の波高値に比例する。 First comparison signal S c1 is also possible to limit the slew rate wave-shaping circuit 120, slightly delayed rising relative time of occurrence t 0 of the signal, changes from Low to High is the time t 2 There is. And, High is continued until the time t 4. The duration from time t 2 to time t 4 is proportional to the peak value of the adjustment signal S r1 as described above.
 第2比較信号Sc2は、電流コンパレータ140の出力信号である。電流コンパレータ140は、信号の発生と同時に急峻に立ち上がる電流値を比較対象としているので、第2比較信号Sc2は、信号の発生時刻tとほぼ同時刻にLowからHighへ変化している。ただし、急峻に立ち上がった電流値は持続せず即座に立ち下がるので、第2比較信号Sc2は、時刻tよりも前の時刻tにHighからLowへ変化している。 The second comparison signal Sc2 is an output signal of the current comparator 140. Since the current comparator 140 targets the current value that rises sharply at the same time as the signal is generated, the second comparison signal Sc2 changes from Low to High at substantially the same time as the signal generation time t 0. However, since the current value rises sharply falls immediately without sustained, the second comparison signal S c2 is changed from High to Low to before time t 1 from time t 2.
 延長信号Sp2は、ワンショット回路150の出力信号である。電流コンパレータ140の出力配線は、途中で分岐されて一方が論理演算回路160の入力ゲートに接続され、他方がワンショット回路150の入力端子へ接続されている。延長信号Sp2は、第2比較信号Sc2と同時にほぼ時刻tに立ち上がり、Highが時刻tよりも後の時刻tまで継続している。換言すると、ワンショット回路150による延長時間は、時刻tが第1比較信号Sc1の立ち上がり時刻である時刻tより後の時刻となるように、また、第1比較信号Sc1の立ち下がり時刻である時刻tより前の時刻となるように調整されている。なお、時刻tを調整する場合に参照される時刻tは、対象となり得る調整信号Sr1のうち最小の波高値が観察される場合の第1比較信号Sc1の立下り時刻である。 The extension signal Sp2 is an output signal of the one-shot circuit 150. The output wiring of the current comparator 140 is branched in the middle, one of which is connected to the input gate of the logical operation circuit 160 and the other of which is connected to the input terminal of the one-shot circuit 150. The extension signal S p2 rises at approximately time t 0 at the same time as the second comparison signal Sc 2, and High continues until time t 3 after time t 2. In other words, the extension time by the one-shot circuit 150 is such that the time t 3 is a time after the time t 2 which is the rising time of the first comparison signal S c1 and the falling time of the first comparison signal S c1 . it is adjusted to be the previous time from the time t 4 is the time. The time t 4 referred to when adjusting the time t 3 is the falling time of the first comparison signal S c1 when the minimum peak value of the adjustment signals S r1 that can be the target is observed.
 図10(d)は、論理演算回路160の出力信号である検出信号Soutの波形を表す。図10(a)~(c)と同様に、横軸は経過時間を示し、縦軸は、信号レベル(High=1、Low=0)を示す。 FIG. 10D shows the waveform of the detection signal S out , which is the output signal of the logical operation circuit 160. Similar to FIGS. 10 (a) to 10 (c), the horizontal axis indicates the elapsed time, and the vertical axis indicates the signal level (High = 1, Low = 0).
 上述のように、本実施形態における論理演算回路160はOR論理ゲートであるので、ある時刻tにおいて、第1比較信号Sc1、第2比較信号Sc2、延長信号Sp2のいずれかがHighであれば、検出信号SoutもHighである。一方、第1比較信号Sc1、第2比較信号Sc2、延長信号Sp2のいずれもLowであれば、検出信号SoutはLowである。 As described above, since the logic operation circuit 160 in the present embodiment is an OR logic gate, at a certain time t, any one of the first comparison signal Sc1 , the second comparison signal Sc2 , and the extension signal Sp2 is High. If so, the detection signal Out is also High. On the other hand, if all of the first comparison signal S c1 , the second comparison signal S c2 , and the extension signal Sp 2 are Low, the detection signal S out is Low.
 検出信号Soutは、ほぼ時刻tにLowからHighへ変化し、そのままHighの状態が時刻tまで継続された波形となる。すなわち、論理演算回路160は、時刻tに開始し、時刻tから時刻tまでの時間幅Twを有するパルス信号を出力する。 The detection signal S out changes from Low to High at approximately time t 0 , and becomes a waveform in which the High state is continued until time t 4. That is, the logic operation circuit 160 starts at time t 0, and outputs a pulse signal having a time width Tw from time t 0 to time t 4.
 波形整形回路120の出力信号である調整信号Sr1は、上述のように、信号発生時点から設定された閾値Vthに到達するまでの時間が波高値によらずほぼ一定(=t~t)となるように調整されている。したがって、第1比較信号Sc1の時間幅が、調整信号Sr1の波高値に比例するのであれば、検出信号Soutの時間幅Twも、調整信号Sr1の波高値に比例する。 As described above, the adjustment signal S r1, which is the output signal of the waveform shaping circuit 120, has a substantially constant time from the time of signal generation until the set threshold value Vth is reached (= t 0 to t) regardless of the peak value. It is adjusted to be 2). Therefore, if the time width of the first comparison signal S c1 is proportional to the peak value of the adjustment signal S r1 , the time width Tw of the detection signal S out is also proportional to the peak value of the adjustment signal S r1.
 図11は、調整信号Sr1の波高値hと検出信号Soutの時間幅Twの相関を示すグラフである。横軸は波高値を示し、縦軸は時間幅を示す。図示するように、検出信号Soutの時間幅Twは、調整信号Sr1の波高値に比例する。なお、図中の波高値h、h、hは、図6で示した信号S’ra、S’rb、S’rcの3つの例におけるそれぞれの波高値であり、時間幅Tw、Tw、Twは、それぞれに対応する検出信号Soutの時間幅である。 FIG. 11 is a graph showing the correlation between the peak value h of the adjustment signal S r1 and the time width Tw of the detection signal S out. The horizontal axis shows the peak value, and the vertical axis shows the time width. As shown in the figure, the time width Tw of the detection signal S out is proportional to the peak value of the adjustment signal S r1. Incidentally, the peak value h a in FIG, h b, h c is the signal S 'ra, S' rb shown in FIG. 6, a respective peak value in the three examples of S 'rc, the time width Tw a , Tw b and Tw c are the time widths of the detection signals S out corresponding to each.
 検出回路100が出力する検出信号Soutを、例えば一定の周期で入力されるクロック信号に従ってカウンターでカウントすれば、時間幅Twを数値データに変換できる。さらに、変換された数値データを、図11に示す線形性を利用して波高値hに直ちに換算することができる。 If the detection signal S out output by the detection circuit 100 is counted by a counter according to, for example, a clock signal input at a fixed cycle, the time width Tw can be converted into numerical data. Further, the converted numerical data can be immediately converted into the peak value h by using the linearity shown in FIG.
 上述のように、調整信号Sr1の波高値hは、センサー信号Sinの信号量qに比例する。したがって、換算された波高値hは、入力されたセンサー信号Sinの信号量qに変換することができる。このような検出回路100とその周辺のデジタル処理装置は、ADCを実装する必要がないので、比較的シンプルかつ小規模に実現し得る。すなわち、装置全体を安価に構成することができると共に、単位時間当たりに処理できるセンサー信号数を増やすことができる。 As described above, the peak value h of the adjustment signal S r1 is proportional to the signal amount q of the sensor signal S in. Accordingly, terms have been peak value h can be converted into a signal quantity q of the input sensor signal S in. Since it is not necessary to mount an ADC in such a detection circuit 100 and a digital processing device around it, it can be realized relatively simply and on a small scale. That is, the entire device can be constructed at low cost, and the number of sensor signals that can be processed per unit time can be increased.
 以上のように、検出回路100が出力する検出信号Soutの時間幅Twは、波形整形回路120で調整された時間幅t’に準ずるので、波高値hに対して良好な線形性を示し、ひいてはセンサー信号Sinの信号量qに対して良好な線形性を示す。また、検出回路100が出力する検出信号Soutの立ち上がり時刻は、第2比較信号Sc2の立ち上がり時刻であるので、タイムウォークの影響をほとんど受けることなく、センサー信号Sinの発生タイミングに極めて近い。すなわち、検出回路100が出力する検出信号Soutを処理する後段の処理装置は、センサー信号の発生タイミングと信号量を高い精度で解析することができる。このような検出回路100は、センサー信号として短時間幅電流パルス信号を出力する、例えばがん診断に使用されているPositron Emission Tomography(PET)、Time-of-Flight PET、フォトンカウンティングCT等の装置に信号処理回路として組み込まれる場合に、利用価値が高い。また、短時間幅電流パルス信号を出力するセンサーに限らず、単調増加した後に単調減少するような、波高値と時間幅に相関性を有する信号を出力するセンサーの信号処理回路として利用することも可能である。 As described above, the time width Tw of the detection signal S out detection circuit 100 is output than equivalent to the time width t 'w adjusted by the waveform shaping circuit 120, showed good linearity with respect to the peak value h shows a good linearity with respect to the signal quantity q of turn sensor signal S in. Further, since the rise time of the detection signal S out output by the detection circuit 100 is the rise time of the second comparison signal Sc2 , it is almost unaffected by the time walk and is extremely close to the generation timing of the sensor signal S in. .. That is, the processing device in the subsequent stage that processes the detection signal S out output by the detection circuit 100 can analyze the generation timing and the signal amount of the sensor signal with high accuracy. Such a detection circuit 100 outputs a short-time width current pulse signal as a sensor signal, for example, a device such as Positron Emission Tomography (PET), Time-of-Fright PET, and photon counting CT used for cancer diagnosis. It has high utility value when it is incorporated as a signal processing circuit. It is not limited to a sensor that outputs a short-time width current pulse signal, but can also be used as a signal processing circuit for a sensor that outputs a signal that has a correlation between the peak value and the time width, such as monotonically increasing and then monotonically decreasing. It is possible.
 以上説明した本実施形態に係る検出回路100は、ワンショット回路150を備えている。ワンショット回路150は、上述のように、第2比較信号Sc2の信号終了時点を延長させた延長信号Sp2を生成する。もし、ワンショット回路150を備えないとすれば、図10に示すようにtがtよりも遅い時刻である場合には、検出信号Soutにおいてtからtまでの期間がLowレベルとなってしまう。このような断絶を防ぐために、ワンショット回路150によってtよりも遅い時刻であるtまで遅延させた長信号Sp2を生成し、論理演算回路160へ入力させている。 The detection circuit 100 according to the present embodiment described above includes a one-shot circuit 150. One-shot circuit 150, as described above, to generate an extended signal S p2 obtained by extending the signal end of the second comparison signal S c2. If the one-shot circuit 150 is not provided and t 2 is later than t 1 as shown in FIG. 10, the period from t 1 to t 2 in the detection signal S out is the Low level. Will be. To prevent such discontinuities, it generates a long signal S p2 delayed until t 3 is a time later than t 2 by a one-shot circuit 150, and is inputted to the logic operation circuit 160.
 しかし、波形整形回路120または電流コンパレータ140を調整することによって、tをtよりも常に早い時刻にすることができるなら、ワンショット回路150を省くことができる。この場合、論理演算回路160のゲートに入力される信号は、第1比較信号Sc1と第2比較信号Sc2の2信号となる。 However, if t 2 can always be set to a time earlier than t 1 by adjusting the waveform shaping circuit 120 or the current comparator 140, the one-shot circuit 150 can be omitted. In this case, the signals input to the gate of the logical operation circuit 160 are two signals, the first comparison signal Sc1 and the second comparison signal Sc2 .
 上述のように、検出回路100の論理演算回路160は、第1比較信号Sc1、第2比較信号Sc2、延長信号Sp2の3つの信号のOR論理ゲートである。延長信号Sp2加えて第2比較信号Sc2も入力対象とするのは、ワンショット回路150の構成によっては、延長信号Sp2の立ち上がりが第2比較信号Sc2の立ち上がりに対して遅延する場合があるからである。しかし、当該遅延が無視し得る程度であると評価されるのであれば、論理演算回路160は、第1比較信号Sc1と延長信号Sp2の2信号を入力するOR論理ゲートとしてもよい。 As described above, the logic operation circuit 160 of the detection circuit 100 is an OR logic gate of three signals, the first comparison signal Sc1 , the second comparison signal Sc2 , and the extension signal Sp2. In addition to the extension signal S p2 , the second comparison signal S c2 is also input when the rise of the extension signal S p2 is delayed with respect to the rise of the second comparison signal S c2 depending on the configuration of the one-shot circuit 150. Because there is. However, if the delay is evaluated to be negligible, the logic operation circuit 160 may be an OR logic gate for inputting two signals , the first comparison signal Sc1 and the extension signal Sp2.
 また、以上説明した論理演算回路160は、OR論理ゲートを用いたが、第1比較信号Sc1、第2比較信号Sc2、延長信号Sp2のそれぞれにおいて、信号有りの期間をHighレベルとするかLowレベルとするかに応じて用いる論理ゲートを選択すればよい。もちろんいくつかの論理ゲートを組み合わせて検出信号Soutを生成するように構成してもよい。 Further, although the OR logic gate is used in the logic operation circuit 160 described above , the period with signals in each of the first comparison signal S c1 , the second comparison signal S c2 , and the extension signal Sp 2 is set to the High level. The logic gate to be used may be selected depending on whether the level is Low or Low. Of course, some logic gates may be combined to generate a detection signal S out.
 ここで、従来のToT検出回路における検出結果と、本実施形態に係る検出回路100の一実施例における検出結果を比較する。図12は、従来のToT検出回路における検出結果の例である。ここでは、横軸を波高値と比例関係にある信号量としてエネルギー(keV)で表し、縦軸を図11と同じく時間幅(ns)で表す。図において、59.6keVのプロットは、241Amの測定結果であり、81keV、304keV、356keVのプロットは、133Baの測定結果であり、122keVのプロットは、57Coの測定結果であり、604.7keV、795.9keVのプロットは、134Csの測定結果であり、551keV、1275keVのプロットは、22Naの測定結果である。図示するように、得られた測定結果は上凸の曲線を描き、エネルギー(∝波高値)と時間幅の線形性は芳しくない。 Here, the detection result in the conventional ToT detection circuit and the detection result in one embodiment of the detection circuit 100 according to the present embodiment are compared. FIG. 12 is an example of the detection result in the conventional ToT detection circuit. Here, the horizontal axis is represented by energy (keV) as a signal amount proportional to the peak value, and the vertical axis is represented by time width (ns) as in FIG. In the figure, the 59.6 keV plot is the measurement result of 241 Am, the 81 keV, 304 keV, 356 keV plot is the 133 Ba measurement result, and the 122 keV plot is the 57 Co measurement result, 604. The plots of 7 keV and 795.9 keV are the measurement results of 134 Cs, and the plots of 551 keV and 1275 keV are the measurement results of 22 Na. As shown in the figure, the obtained measurement results draw an upwardly convex curve, and the linearity of energy (∝ peak value) and time width is not good.
 図13は、本実施形態に係る検出回路100の一実施例における検出結果の例である。図12と同様に、横軸をエネルギー(keV)で表し、縦軸を時間幅(ns)で表す。図において、22keVのプロットは、100Cdの測定結果であり、59.6keVのプロットは、241Amの測定結果であり、30.9keV、81keV、356keVのプロットは、133Baの測定結果であり、122keVのプロットは、57Coの測定結果であり、662keVのプロットは、137Csの測定結果であり551keVのプロットは、22Naの測定結果である。図示するように、得られた測定結果はほぼ直線を描き、エネルギー(∝波高値)と時間幅の良好な線形性が得られている。 FIG. 13 is an example of the detection result in one embodiment of the detection circuit 100 according to the present embodiment. Similar to FIG. 12, the horizontal axis is represented by energy (keV) and the vertical axis is represented by time width (ns). In the figure, the plot of 22 keV is the measurement result of 100 Cd, the plot of 59.6 keV is the measurement result of 241 Am, and the plot of 30.9 keV, 81 keV, 356 keV is the measurement result of 133 Ba. The 122 keV plot is the 57 Co measurement result, the 662 keV plot is the 137 Cs measurement result, and the 551 keV plot is the 22 Na measurement result. As shown in the figure, the obtained measurement results are almost straight lines, and good linearity of energy (∝ peak value) and time width is obtained.
100…検出回路、110…カレントミラー回路、120…波形整形回路、121…スルーレート制限抵抗回路、122…変更部、130…電圧コンパレータ、140…電流コンパレータ、150…ワンショット回路、151…時間調整部、160…論理演算回路 100 ... Detection circuit, 110 ... Current mirror circuit, 120 ... Waveform shaping circuit, 121 ... Slew rate limiting resistor circuit, 122 ... Change part, 130 ... Voltage comparator, 140 ... Current comparator, 150 ... One-shot circuit, 151 ... Time adjustment Part, 160 ... Logical operation circuit

Claims (5)

  1.  入力されたセンサー信号をコピーして第1入力信号と第2入力信号を並列して出力するカレントミラー回路と、
     前記第1入力信号を入力すると経過時間に対する電圧変動を設定された基準変動に沿うように調整して調整信号を出力する波形整形回路と、
     前記調整信号の電圧値と基準電圧値を比較して第1比較信号を出力する電圧コンパレータと、
     前記第2入力信号の電流値と基準電流値を比較して第2比較信号を出力する電流コンパレータと、
     前記第1比較信号と前記第2比較信号に対して論理演算を行って、前記第2比較信号の開始時点から前記第1比較信号の終了時点まで継続する検出信号を出力する論理演算回路と
    を備える検出回路。
    A current mirror circuit that copies the input sensor signal and outputs the first input signal and the second input signal in parallel,
    A waveform shaping circuit that adjusts the voltage fluctuation with respect to the elapsed time according to the set reference fluctuation when the first input signal is input and outputs the adjusted signal, and
    A voltage comparator that compares the voltage value of the adjustment signal with the reference voltage value and outputs the first comparison signal.
    A current comparator that compares the current value of the second input signal with the reference current value and outputs the second comparison signal.
    A logic operation circuit that performs a logical operation on the first comparison signal and the second comparison signal and outputs a detection signal that continues from the start time of the second comparison signal to the end time of the first comparison signal. Includes detection circuit.
  2.  入力された前記第2比較信号の信号継続時間を延長させた延長信号を生成して出力するワンショット回路を備え、
     前記論理演算回路は、少なくとも前記第1比較信号および前記延長信号に対して論理演算を行って前記検出信号を出力する請求項1に記載の検出回路。
    It is provided with a one-shot circuit that generates and outputs an extension signal that extends the signal duration of the input second comparison signal.
    The detection circuit according to claim 1, wherein the logic operation circuit performs a logic operation on at least the first comparison signal and the extension signal and outputs the detection signal.
  3.  前記ワンショット回路は、前記信号継続時間の延長時間を調整する時間調整部を有する請求項2に記載の検出回路。 The detection circuit according to claim 2, wherein the one-shot circuit has a time adjusting unit for adjusting an extension time of the signal duration.
  4.  前記波形整形回路は、前記基準変動を変更する変更部を有する請求項1から3のいずれか1項に記載の検出回路。 The detection circuit according to any one of claims 1 to 3, wherein the waveform shaping circuit has a change unit for changing the reference variation.
  5.  前記カレントミラー回路は、前記センサー信号に対する前記第1入力信号の電流比が、1より小さく、かつ、前記センサー信号に対する前記第2入力信号の電流比よりも小さく設定されている請求項1から4のいずれか1項に記載の検出回路。 Claims 1 to 4 of the current mirror circuit are set so that the current ratio of the first input signal to the sensor signal is smaller than 1 and smaller than the current ratio of the second input signal to the sensor signal. The detection circuit according to any one of the above items.
PCT/JP2021/024318 2020-07-03 2021-06-28 Detection circuit WO2022004639A1 (en)

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