WO2022003845A1 - Display device and method for manufacturing display device - Google Patents

Abstract

This display device comprises: a display region for an image; a terminal region in which a plurality of terminals are provided; and a folded region which is a region between the display region and the terminal region and is folded, wherein the folded region has a first resin layer, a plurality of relay wires which are provided on the first resin layer and provided between the display region and the terminal region, and a second resin layer which covers the plurality of relay wires and is provided on the first resin layer, and the first resin layer and the second resin layer in the folded region have formed therein a plurality of slits, which are outside from the relay wires on both ends thereof among the plurality of relay wires when viewed in a plan view, and which have a depth from the surface of the second resin layer up to the first resin layer.

Description

Display device and manufacturing method of display device

This disclosure relates to a display device and a method for manufacturing the display device.

Patent Document 1 discloses a display device that bends the vicinity of the end portion.

Japanese Unexamined Patent Publication No. 2016-170266

The bent area of the display device is provided with a lead-out wiring that electrically connects the display area and the terminal provided at the end of the frame area. However, when the display device is cut to a desired size, the cut surface of the bent region may be cracked and the lead-out wiring provided in the bent region may be broken. One aspect of the present disclosure is to obtain a display device and a method for manufacturing a display device in which wiring is unlikely to be broken even if a crack is formed in the bent region.

The display device according to one aspect of the present disclosure includes a display area for an image, a terminal area provided with a plurality of terminals, and a bending area that is a region between the display area and the terminal area and is bendable. The bent region covers a first resin layer, a plurality of relay wirings provided on the first resin layer and provided between the display region and the terminal region, and the plurality of relay wirings. It has a second resin layer provided on the first resin layer, and the first resin layer and the second resin layer in the bent region are relayed at both ends of the plurality of relay wirings in a plan view. A plurality of slits having a depth from the surface of the second resin layer to the first resin layer are formed outside the wiring.

A method of manufacturing a display device according to one aspect of the present disclosure includes a display area of an image, a terminal area provided with a plurality of terminals, and a bent area that is a region between the display area and the terminal area and is bent. A method for manufacturing a display device comprising the above, wherein the process includes a step of forming the bent region, and the step of forming the bent region includes a step of forming a first resin layer and a step of forming the display on the first resin layer. The second step includes a step of forming a plurality of relay wires between the region and the terminal region, and a step of covering the plurality of relay wires and forming a second resin layer on the first resin layer. In the step of forming the resin layer, the first resin layer and the second resin layer are formed on the first resin layer and the second resin layer from the surface of the second resin layer to the outside of the relay wirings at both ends of the plurality of relay wirings in a plan view. A plurality of slits having a depth reaching one resin layer are formed.

According to one aspect of the present disclosure, it is possible to obtain a display device and a method for manufacturing a display device in which wiring is unlikely to be broken even if a crack is formed in the bent region.

It is a top view which shows the outline of the display panel provided in the display device which concerns on Embodiment 1. FIG. It is sectional drawing of the vicinity of a sub pixel in the display panel of the display device which concerns on Embodiment 1. FIG. It is schematic cross-sectional view which shows the state which the display panel of the display device which concerns on Embodiment 1 is bent. It is a top view which shows the schematic structure of the vicinity of both ends of the bent area of the display panel which concerns on embodiment. It is sectional drawing cut in the B1-B1 line shown in FIG. It is sectional drawing cut in the C1-C1 line shown in FIG. It is a figure which shows the state of the process of individualizing the display device which concerns on Embodiment 1. FIG. It is sectional drawing of the bending area which concerns on the modification of Embodiment 1. FIG. It is a figure which shows the flow of the manufacturing process of the display device which concerns on Embodiment 1. FIG. It is sectional drawing of the vicinity of a sub pixel in the display panel of the display device which concerns on Embodiment 2. FIG. FIG. 5 is a cross-sectional view in which the lead-out wiring at one end near the bent region according to the second embodiment is cut in the Y direction. FIG. 5 is a cross-sectional view in which a lead-out wiring at one end in the bent region according to the second embodiment is cut in the X direction. It is a top view which shows the schematic structure of the vicinity of both ends of the bending region of the display panel which concerns on the modification of Embodiment 2. It is sectional drawing of the bending area which concerns on the modification of Embodiment 2. It is sectional drawing of the bending area which concerns on other modification of Embodiment 2.

[Embodiment 1]
The first embodiment of the present disclosure will be described. In the following description, "same layer" means that the same material is used in the same process.

FIG. 1 is a plan view showing an outline of a display panel 2 included in the display device 1 according to the first embodiment. As shown in FIG. 1, the display device 1 according to the present embodiment includes a display panel 2.

The display panel 2 includes an image display area DA and a frame-shaped frame area (non-display area) NA surrounding the display area DA. Further, the display panel 2 includes a terminal area TA provided in the frame area NA, a plurality of lead-out wirings 61, and a bent area BA. Further, a plurality of slits SL are formed in the bent region BA.

The display panel 2 is surrounded by, for example, four ends EB1, EB2, EB3, and EB4, and is a quadrangle in a plan view. In a plan view, the end EB1 and the end EB2 are long sides facing each other, and the end EB3 and the end EB4 are short sides facing each other. The planar shape of the display panel 2 is not limited to a quadrangle, and may be another shape. As will be described later, the display panel 2 is formed as a panel having a size larger than that of the display panel 2, and then the end portions EB1, EB2, EB3, and EB4 are cut by a laser or the like in the step of individualizing the display panel 2. As a result, it is formed to have a desired size.

In this embodiment, the direction from the display area DA to the terminal area TA (the direction in which each of the ends EB1 and EB2 extends, the vertical direction from the top of the paper to the bottom in FIG. 1) is the Y direction (first direction). , The direction in which each of the end portions EB3 and EB4 extends (horizontal direction from left to right toward the paper surface in FIG. 1) is defined as the X direction (second direction). The Y direction and the X direction are orthogonal to each other.

A plurality of sub-pixel SPs are arranged in a matrix in the display area DA. The plurality of sub-pixels SP include, for example, a red sub-pixel that emits red light, a green sub-pixel that emits green light, a blue sub-pixel that emits blue light, and the like.

The terminal area TA is an area in which a plurality of terminals 60 are provided side by side. The terminal region TA is, for example, in the vicinity of one end EB4 of the display panel 2 and extends along the end EB4. As will be described later, the plurality of terminals 60 provided in the terminal area TA are electrically connected to a plurality of terminals such as a circuit provided outside the display panel 2 or a plurality of wirings. The plurality of terminals 60 are, for example, in the vicinity of one end EB4 of the display panel 2 and are arranged along the end EB4.

A region between the bent region BA, the display region DA, and the terminal region TA, which is a region that can be bent. For example, the bent region BA extends continuously so as to connect both ends EB1 and EB2. The bent region BA is provided so as to extend in the X direction. In other words, the longitudinal direction of the bent region BA is the X direction, and the lateral direction orthogonal to the longitudinal direction is the Y direction.

For example, the display panel 2 can bend the bent region BA by, for example, 180 ° by including a flexible base material having flexibility. The display panel 2 does not include a flexible base material having flexibility on the entire surface, but includes at least a flexible base material having flexibility in the bending region BA so that the bending region BA can be bent. It may be.

Each of the plurality of lead-out wiring 61s is provided between the display area DA and the terminal area TA. Each of the plurality of lead-out wiring 61 extends from the display area DA to the frame area NA, passes through the bending area BA, and is electrically connected to the plurality of terminals 60 in the terminal area TA. As a result, the input signals input to the plurality of terminals 60 from the external circuit of the display panel 2 may be supplied to the display area DA, or the output signals output from the display area DA may be supplied to the display area DA via the plurality of lead wires 61. It can be supplied to the terminal 60.

Each of the plurality of lead-out wiring 61 extends in the Y direction and is provided side by side in the X direction. Each of the plurality of lead-out wiring 61 includes a first lead-out wiring W1, a second lead-out wiring W2, and a relay wiring W3, respectively.

One end of each of the plurality of first lead-out wirings W1 is electrically connected to a wiring or a thin film transistor provided in the display area DA, extends from the display area DA toward the bending region BA, and ends at the other end. The portion is provided in the frame region NA near the bending region BA. One end of each of the plurality of second lead-out wires W2 is electrically connected to the terminal 60, extends from the terminal 60 in the direction of the bending region BA, and the other end is a frame near the bending region BA. It is provided in the area NA. A plurality of relay wirings W3 are provided between the display area DA and the terminal area TA. Each of the plurality of relay wirings W3 has one end electrically connected to the other end of the first lead-out wiring W1 and extends through the bending region BA, and the other end is the second lead-out wiring. It is electrically connected to the other end of W2. As a result, the relay wiring W3 electrically connects the first lead-out wiring W1 and the second lead-out wiring W2. Each of the plurality of relay wirings W3 extends so as to intersect the longitudinal direction (X direction) of the bending region BA.

Of the plurality of lead-out wires 61 arranged in the Y direction, the lead-out wires 61 at both ends may be referred to as lead-out wires 61B1 and 61B2. Of the lead-out wirings 61 at both ends, the side closer to the end portion EB1 is referred to as a lead-out wiring 61B1, and the side closer to the end portion EB2 is referred to as a lead-out wiring 61B2.

Further, the first lead-out wiring W1 of the lead-out wiring 61B1 may be referred to as a first lead-out wiring W1B1, the second lead-out wiring W2 may be referred to as a second lead-out wiring W2B1, and the relay wiring W3 may be referred to as a relay wiring W3B1. Further, the first lead-out wiring W1 of the lead-out wiring 61B2 may be referred to as a first lead-out wiring W1B1, the second lead-out wiring W2 may be referred to as a second lead-out wiring W2B2, and the relay wiring W3 may be referred to as a relay wiring W3B2.

The plurality of slits SL are formed outside the lead-out wirings 61B1 and 61B2 at both ends of the bending region BA. That is, the plurality of slits SL are formed in the bent region BA between the lead-out wiring 61B1 and the end portion EB1 of the end portions EB1 to EB4 close to the lead-out wiring 61B1. Further, the plurality of slits SL are formed in the bent region BA between the lead-out wiring 61B2 and the end portion EB2 of the end portions EB1 to EB4 close to the lead-out wiring 61B2. The plurality of slits SL prevent the cracks formed when the end portions EB1 and EB2 are cut from reaching the lead-out wirings 61B1 and 61B2 and causing disconnection. Details of the plurality of slits SL will be described later.

FIG. 2 is a cross-sectional view of the vicinity of the sub-pixel SP in the display panel 2 of the display device 1 according to the first embodiment. The display panel 2 includes, for example, a second film 10, a base material 3 provided on the second film 10, a base coat layer 14 provided on the base material 3, and a TFT provided on the base coat layer 14. Thin Film Transistor) layer 4, a plurality of light emitting elements 5 and banks 25 provided on the TFT layer 4, a sealing layer 6 provided on the plurality of light emitting elements 5 and banks 25, and a sealing layer 6 on top. The first film 7 provided in the above is provided.

The second film 10 protects the back surface (lower surface) of the display panel 2 and has flexibility. The second film 10 is configured to contain, for example, a resin material such as polyethylene terephthalate (PET).

The base material 3 is continuously provided on the entire surface of the display panel 2 and is a base member in the display panel 2. The base material 3 has flexibility. In the present embodiment, the base material 3 is placed on the first base material resin layer 11 provided on the second film 10, the buffer layer 12 provided on the first base material resin layer 11, and the buffer layer 12. It is a multi-layer structure including the provided second base material resin layer 13.

The first base material resin layer 11 and the second base material resin layer 13 are each composed of a resin material such as polyimide. The buffer layer 12 is an inorganic insulating layer composed of, for example, an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

Since the first base material resin layer 11 and the second base material resin layer 13 are base members provided on the entire surface of the display panel 2, for example, they do not have to be patterned. That is, the first base material resin layer 11 and the second base material resin layer 13 may not contain the photosensitive material. Therefore, the first base material resin layer 11 and the second base material resin layer 13 have stronger heat resistance than the resin layer containing the photosensitive material, and can be cured at a high temperature. As a result, the first base material resin layer 11 and the second base material resin layer 13 are less likely to crack on the cut surface when cut by a laser or the like, as compared with the resin layer containing a photosensitive material. ..

The base material 3 may have, for example, a single-layer structure composed of only the first base material resin layer 11 or a multi-layer structure having four or more layers.

The base coat layer 14 prevents moisture or impurities from being mixed into the TFT layer 4 and the light emitting element 5. The base coat layer 14 is an inorganic insulating layer composed of, for example, an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

The TFT layer 4 includes a semiconductor layer 20, a gate insulating layer 21, a gate electrode GE, a first inorganic insulating layer 22, a capacitive electrode CE, a second inorganic insulating layer 23, a source electrode SE, and a drain electrode DE. , The first flattening layer 24 and the like. Further, the TFT layer 4 includes a gate wiring GW which is the same layer as the gate electrode GE, and further includes a source wiring (not shown) which is the same layer as the source electrode SE and the drain electrode DE.

The sub-pixel SP is driven by the semiconductor layer 20, the gate insulating layer 21, the gate electrode GE, the first inorganic insulating layer 22, the second inorganic insulating layer 23, the source electrode SE, and the drain electrode DE. A plurality of thin film transistors Tr are configured.

The semiconductor layer 20 is on the base coat layer 14 and is formed at least in the formation region of the thin film transistor Tr. The semiconductor layer 20 is configured to include, for example, low-temperature Poly Silicon (LTPS) or an oxide semiconductor. The oxide semiconductor contains at least one metal element among In, Ga and Zn.

The gate insulating layer 21 covers the semiconductor layer 20 and is provided on the base coat layer 14. A plurality of gate electrodes GE are provided on the gate insulating layer 21 in the formation region of the thin film transistor Tr. Further, a plurality of gate wiring GWs which are the same layer as the gate electrode GE are provided on the gate insulating layer 21. Each of the plurality of gate wiring GWs is connected to the gate electrode GE.

The first inorganic insulating layer 22 covers the gate electrode GE and the gate wiring GW, and is provided on the gate insulating layer 21. The capacitive electrode CE is provided on the first inorganic insulating layer 22 so as to overlap a part of the gate wiring GW. The capacitance electrode CE forms a capacitance with the overlapping gate wiring GW. The second inorganic insulating layer 23 covers the capacitive electrode CE and is provided on the first inorganic insulating layer 22 on the entire surface of the display region DA.

The gate insulating layer 21, the first inorganic insulating layer 22, and the second inorganic insulating layer 23 are each composed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

The drain electrode DE and the source electrode SE are in the same layer, and are provided on the second inorganic insulating layer 23 in a plurality of regions where the thin film transistor Tr is formed. The drain electrode DE is connected to the drain region of the semiconductor layer 20 and the source electrode SE is connected to the source region of the semiconductor layer 20 through the contact holes formed in the first inorganic insulating layer 22 and the second inorganic insulating layer 23. .. Further, on the second inorganic insulating layer 23, a plurality of source wirings (not shown) which are the same layers as the drain electrode DE and the source electrode SE are provided. Each of the plurality of source wirings is connected to the source electrode SE.

A plurality of source wirings and a plurality of gate wiring GWs are provided so as to intersect each other in the display area DA in a plan view. The plurality of source wirings are connected to a source driver (not shown), and the source driver supplies a source signal corresponding to the emission luminance of each of the plurality of sub-pixel SPs. The plurality of gate wiring GWs are connected to a gate driver (not shown), and a gate signal for selecting a sub-pixel SP to emit light from the plurality of sub-pixel SPs is supplied from the gate driver.

The gate electrode GE, the gate wiring GW, the capacitance electrode CE, the drain electrode DE, the source electrode SE, and the source wiring are each composed of a conductive material. As the conductive material, for example, a metal material such as aluminum, tungsten, molybdenum, tantalum, chromium, titanium, copper or an alloy thereof can be used.

The first flattening layer 24 covers the drain electrode DE, the source electrode SE, and the source wiring, is on the second inorganic insulating layer 23, and is provided on the entire surface of the display area DA. That is, the first flattening layer 24 covers a plurality of thin film transistor Trs. The first flattening layer 24 is a resin layer composed of, for example, a resin material such as polyimide or acrylic. Further, the first flattening layer 24 is patterned by, for example, a photolithography method by containing a photosensitive material.

The plurality of light emitting elements 5 and the bank 25 are provided on the first flattening layer 24. Each of the plurality of light emitting elements 5 is provided for each sub-pixel SP. Each of the plurality of light emitting elements 5 is, for example, a first electrode 30, a first charge injection layer 31, a light emitting layer 32, a second charge injection layer 33, and a second electrode, which are sequentially laminated on the first flattening layer 24. Includes 34. For example, the first electrode 30, the first charge injection layer 31, the light emitting layer 32, and the second charge injection layer 33 are provided in an island shape for each light emitting element 5. For example, the second electrode 34 is provided on the entire surface of the second charge injection layer 33 and the bank 25.

The bank 25 covers the peripheral end portion (edge portion) of the first electrode 30. As a result, the bank 25 prevents the peripheral end portion of the first electrode 30 and the second electrode 34 from being short-circuited. The banks 25 are provided in a grid pattern in the display area DA (see FIG. 1) in a plan view. That is, the light emitting element 5 provided in the opening surrounded by the bank 25 corresponds to the sub-pixel SP. The bank 25 is a resin layer composed of, for example, a resin material such as polyimide or acrylic. Further, the bank 25 is patterned by, for example, a photolithography method by containing a photosensitive material.

The first electrode 30 is connected to the source electrode SE through a contact hole formed in the first flattening layer 24. The first electrode 30 is, for example, an anode.

The first electrode 30 is, for example, a reflective electrode that reflects visible light. The first electrode 30 has, for example, a reflective layer containing a metal material such as aluminum, copper, gold, or silver having a high reflectance of visible light, and a transparent conductive material such as ITO, IZO, ZnO, AZO, BZO, or GZO. It is configured as a laminated structure with a transparent layer including. The first electrode 30 may have a single-layer structure including a reflective layer.

The second electrode 34 is, for example, a cathode. The second electrode 34 is, for example, a transparent electrode that transmits visible light. The second electrode 34 includes, for example, a transparent conductive material such as ITO, IZO, ZnO, AZO, BZO, or GZO.

The first charge injection layer 31 is provided between the first electrode 30 and the light emitting layer 32. The first charge injection layer 31 is, for example, a hole injection layer for injecting holes into the light emitting layer 32.

The second charge injection layer 33 is provided between the second electrode 34 and the light emitting layer 32. The second charge injection layer 33 is, for example, an electron injection layer for injecting electrons into the light emitting layer 32. In addition, another layer such as a hole transport layer may be provided between the first charge injection layer 31 and the light emitting layer 32. Further, another layer such as an electron transport layer may be provided between the second charge injection layer 33 and the light emitting layer 32. Further, at least one of the first charge injection layer 31 and the second charge injection layer 33 may be omitted.

The light emitting layer 32 is provided between the first electrode 30 and the second electrode 34. In the present embodiment, the light emitting layer 32 is provided between the first charge injection layer 31 and the second charge injection layer 33. The light emitting layer 32 emits visible light based on, for example, the holes injected from the first charge injection layer 31 and the electrons injected from the second charge injection layer 33. For example, the light emitting layer 32 emits red light, green light, or blue light. The light emitting layer 32 may be, for example, an organic EL layer containing an organic EL (electro-luminescence) material, or a quantum dot layer containing a plurality of quantum dots that emit EL light.

The stacking order of the light emitting elements 5 is not limited to the order described above, and for example, the second electrode 34, the second charge injection layer 33, the light emitting layer 32, and the first charge injection layer are placed on the first flattening layer 24 in this order. 31 and the first electrode 30 may be laminated. Further, for example, even if the first electrode 30 is a cathode, the first charge injection layer 31 is an electron injection layer, the second charge injection layer 33 is a hole injection layer, and the second electrode 34 is an anode. good. Further, the first electrode 30 may be a transparent electrode and the second electrode 34 may be a reflecting electrode.

The sealing layer 6 prevents moisture, impurities, etc. from being mixed into the light emitting element 5. The sealing layer 6 covers the entire surface of the display area DA. The sealing layer 6 includes, for example, an inorganic film 40 provided on the second electrode 34, an organic film 41 provided on the inorganic film 40, and an inorganic film 42 provided on the organic film 41. The inorganic films 40 and 42 are inorganic insulating layers composed of, for example, an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The organic film 41 is a resin layer composed of, for example, a resin material such as polyimide or acrylic.

The first film 7 is provided on the sealing layer 6. The first film 7 protects the surface (upper surface) of the display panel 2 and has flexibility. The first film 7 is configured to contain, for example, a resin material such as polyethylene terephthalate (PET).

FIG. 3 is a schematic cross-sectional view showing a state in which the display panel 2 of the display device 1 according to the first embodiment is bent. Note that FIG. 3 omits the illustration of the first film 7. As shown in FIG. 3, the display device 1 includes a circuit board 70 electrically connected to the display panel 2 in addition to the display panel 2. The circuit board 70 is, for example, a board on which an IC chip is mounted, and is arranged so as to overlap the back surface of the display panel 2. Then, in the display panel 2, the bending region BA is bent by, for example, 180 °. As a result, the plurality of terminals 60 on the display panel 2 are electrically connected to each of the plurality of terminals provided on the circuit board 70 provided on the back surface side of the display panel 2. The curvature for bending the bending region BA may be arbitrarily designed, but as an example, it is about 0.1 mm or more and 1.0 mm or less. Thereby, the display device 1 having a narrow frame can be obtained.

Next, the configuration of the frame region NA in the vicinity of the bending region BA will be described with reference to FIGS. 4 and 5. FIG. 4 is a plan view showing a schematic configuration in the vicinity of both ends EB1 and EB2 of the bent region BA of the display panel 2 according to the first embodiment. FIG. 5 is a cross-sectional view taken along the line B1-B1 shown in FIG.

For example, of the lead-out wiring 61, the first lead-out wiring W1 and the second lead-out wiring W2 are in the same layer as the gate electrode GE, and the relay wiring W3 is in the same layer as the drain electrode DE and the source electrode SE.

The relay wiring W3 has a first contact having one end formed on a first inorganic insulating layer (first insulating layer) 22 and a second inorganic insulating layer (first insulating layer) 23 covering the first lead-out wiring W1. It is electrically connected to the end of the first lead-out wiring W1 through the hole CH1. Further, the other end of the relay wiring W3 is formed on a second inorganic insulating layer (first insulating layer) 22 and a second inorganic insulating layer (first insulating layer) 23 that cover the second lead-out wiring W2. It is electrically connected to the end of the second lead-out wiring W2 through the contact hole CH2.

In the frame region NA, the base material 3 provided on the second film 10 (that is, the first base material resin layer 11, the buffer layer 12, and the second base material resin layer 13) is provided, and the base material 3 is provided. A base coat layer 14 is provided on the base coat layer 14, a gate insulating layer 21 is provided on the base coat layer 14, and a first lead-out wiring W1 and a second lead-out wiring W2 are provided on the gate insulating layer 21. Further, the first inorganic insulating layer 22 is provided on the gate insulating layer 21 and the second inorganic insulating layer 23 is provided on the first inorganic insulating layer 22 so as to cover the first lead-out wiring W1 and the second lead-out wiring W2. The first flattening layer 24 is provided on the second inorganic insulating layer 23, and the resin layer 25B which is the same layer as the bank 25 is provided on the first flattening layer 24. Further, the bent region BA is provided with a packed bed 65 in which a plurality of relay wirings W3 are laminated on the surface.

In the second film 10, an opening HA is formed in a region overlapping the bent region BA. The first base material resin layer 11, the buffer layer 12, and the second base material resin layer 13, which are the base materials 3, are continuously provided on the entire surface of the display panel 2 including the bent region BA. The back surface of the first base material resin layer 11 is exposed in the bent region BA by the opening HA formed in the second film 10.

The base coat layer (second insulating layer) 14 provided under the first lead-out wiring W1 and the second lead-out wiring W2 has an opening HB formed in a region overlapping the bent region BA. In the gate insulating layer (second insulating layer) 21 provided under the first lead-out wiring W1 and the second lead-out wiring W2, an opening HC is formed in a region overlapping the bent region BA. In the first inorganic insulating layer (first insulating layer) 22 provided on the upper layer of the first lead-out wiring W1 and the second lead-out wiring W2, an opening HD is formed in a region overlapping the bent region BA. In the second inorganic insulating layer (first insulating layer) 23 provided on the upper layer of the first lead-out wiring W1 and the second lead-out wiring W2, an opening HE is formed in a region overlapping the bent region BA.

The surface of the second base material resin layer 13 in the bent region BA is exposed by the openings HB to HE.

For example, the lengths of the openings HB to HE in the Y direction are substantially the same. Further, for example, the length of the opening HB to HE in the Y direction is substantially the same as the length of the opening HA in the Y direction. As an example, the length BAa of the bent region BA in the Y direction is substantially the same as the length of the openings HA to HE in the Y direction. Further, the openings HA to HE extend continuously in the X direction so as to connect both ends EB1 and EB2. That is, in the bent region BA, the openings HA to HE extend in a direction intersecting the plurality of relay wirings W3.

For example, the length in the Y direction between the end of the first lead-out wiring W1 (the end near the bending region BA) and the end of the second lead-out wiring W2 (the end near the bending region BA) is It is longer than the length of the openings HB to HE in the Y direction. That is, the end of the first lead-out wiring W1 (the end on the side close to the bent region BA) and the end of the second lead-out wiring W2 (the end on the side close to the bent region BA) are the first inorganic insulating layers, respectively. It is covered with 22 and the second inorganic insulating layer 23.

The packed layer 65 includes the surface of the second base material resin layer 13 exposed in the bent region BA, the opening HB formed in the base coat layer 14, and the opening HC formed in the gate insulating layer 21. 1 It is provided in a region surrounded by the opening HD formed in the inorganic insulating layer 22 and the opening HE formed in the second inorganic insulating layer 23. The packed bed 65 extends continuously in the X direction so as to connect both ends EB1 and EB2.

The packed layer 65 is a resin layer composed of, for example, a resin material such as polyimide or acrylic. Further, the packed bed 65 is patterned by, for example, a photolithography method by containing a photosensitive material. A relay wiring W3 extending in the Y direction is provided on the packed bed 65.

The first flattening layer 24 covers the relay wiring W3 and is provided on the packed layer 65 and the second inorganic insulating layer 23.

The resin layer 25B is provided in the bending region BA in order to reinforce the bending region BA. The resin layer 25B is, for example, the same layer as the bank 25 in the display area DA, and is provided separately from the bank 25. The resin layer 25B in the bent region BA may be omitted.

As described above, for example, in the bending region BA, a layer (base coat layer 14, gate insulating layer 21, first inorganic insulating layer 22 and second inorganic insulating layer 22) formed by using an inorganic material having a weaker resistance to bending than a resin layer. It is preferable that the inorganic insulating layer 23) is not formed except for the buffer layer 12 contained in the base material 3.

Next, the details of the plurality of slits SL formed in the bending region BA will be described with reference to FIGS. 4 to 7. FIG. 6 is a cross-sectional view taken along the line C1-C1 shown in FIG. FIG. 7 is a diagram showing a state of a process of individualizing the display device 1 according to the embodiment.

As shown in FIGS. 4 and 5, in the bent region BA, for example, the packed bed 65, the first flattening layer 24, and the resin layer 25B are laminated in this order on the base material 3 as described above. There is. That is, the bent region BA has a laminated structure in which a plurality of resin layers are laminated.

Then, as shown in FIG. 7, the display panel 2 is formed into a size larger than a desired size, and then the four ends EB1 to EB4 are brought into a desired size by a laser or the like in the step of disassembling the display panel 2. Be disconnected.

Here, the packed layer 65, the first flattening layer 24, and the resin layer 25B each contain a photosensitive material for patterning. Therefore, the packed layer 65, the first flattening layer 24, and the resin layer 25B have a resin layer that does not contain a photosensitive material (for example, the first base material resin layer 11 and the second base material resin layer 13). In comparison, the heat resistance is weak, and it cannot be cured at a relatively high temperature, for example, about 250 ° C.

As a result, the packed layer 65, the first flattening layer 24, and the resin layer 25B are combined with the resin layer containing no photosensitive material (for example, the first base material resin layer 11 and the second base material resin layer 13). In comparison, in the bent region BA, crack CR may be formed in the inward direction of each of the packed bed 65 and the first flattening layer 24 from the end portions EB1 and EB2 which are cut surfaces.

Therefore, as shown in FIGS. 4 and 6, in the display panel 2 according to the present embodiment, the packed layer 65 (first resin layer) and the first flattening layer 24 (second resin layer) in the bent region BA are formed. From the surface of the first flattening layer 24 (second resin layer) to the packed layer 65 (first resin layer) outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W in a plan view. A plurality of slits SL having a depth are formed.

As a result, when the display panel 2 is cut to a desired size in the step of individualizing, the directions from the ends EB1 and EB2 toward the inside of each of the packed bed 65 and the first flattening layer 24 in the bent region BA. Even if the crack CR is formed in, it is possible to suppress the crack CR from entering the inside more than the plurality of slits SL. As a result, it is possible to prevent the plurality of relay wirings W3 from being disconnected due to the crack CR.

As an example, the end portions EB1 and EB2 in the bent region BA overlap with the slits SL at both ends of the slit SL, respectively. That is, the end portions EB1 and EB2 in the bent region BA are not covered with the packed bed 65 and are exposed. In other words, the slits SL at both ends coincide with the cutting line when cutting the ends EB1 and EB2. The ends EB1 and EB2 in the bent region BA may be covered with the packed bed 65.

As described above, when the end portions EB1 and EB2 each overlap the slit SL, when the end portions EB1 and EB2 are cut, crack CRs are generated in the inward directions of the packed bed 65 and the first flattening layer 24, respectively. It is possible to prevent entry more reliably.

Further, in the present embodiment, it is preferable that at least one of the plurality of slits SL penetrates the packed bed 65 in the Y direction. In other words, the plurality of slits SL are formed so as to extend along the Y direction (that is, along the ends EB1 and EB2), and at least one of the plurality of slits SLs is a length SLa in the Y direction. Is preferably the same as the length 65a of the packed bed 65 in the Y direction. According to this, the crack CR from entering the inside of the packed bed 65 from the ends EB1 and EB2 of the packed bed 65 can be more reliably suppressed by at least one of the plurality of slits SL. Therefore, it is possible to more reliably suppress the disconnection of the plurality of relay wirings W3 due to the crack CR.

It is preferable that all of the plurality of slits SL penetrate the packed bed 65 in the Y direction, but at least one of the plurality of slit SLs may penetrate the packed bed 65 in the Y direction.

Further, in the present embodiment, at least one of the plurality of slits SL has a depth that penetrates the first flattening layer 24 (second resin layer) and the packed layer 65 (first resin layer). preferable. In other words, in the bent region BA, it is preferable that at least one bottom surface SLb of the plurality of slits SL is the surface of the second base material resin layer 13. As a result, in the bent region BA, a plurality of crack CRs are prevented from entering the inside of each of the first flattening layer 24 and the packed layer 65 from the ends EB1 and EB2 of the first flattening layer 24 and the packed layer 65, respectively. It can be more reliably suppressed by at least one of the slits SL. Therefore, it is possible to more reliably suppress the disconnection of the plurality of relay wirings W3 due to the crack CR.

Here, in the present embodiment, it has been described that the resin layer 25B is further provided on the first flattening layer 24 in the bent region BA. Therefore, it is preferable that at least one of the plurality of slits SL has a depth that allows the resin layer 25B to penetrate in addition to the first flattening layer 24 and the packed bed 65. As a result, it is possible to more reliably suppress the crack CR that has entered from the end portions EB1 and EB2 from entering further inward, and to prevent the plurality of relay wirings W3 from being disconnected.

It is preferable that all of the plurality of slits SLs have a depth that penetrates the first flattening layer 24 and the packed layer 65, but at least one of the plurality of slits SLs has the first flattening layer 24 and the packed bed. The depth may be any as long as it penetrates the layer 65.

As shown in FIGS. 4 and 6, for example, the packed bed 65 in the bent region BA has a thickness of 65T2 outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W3, and the relay wirings W3B1 at both ends. The thickness of the area surrounded by W3B2 is the same as 65T1. Further, for example, the first flattening layer 24 in the bent region BA is a region surrounded by the thickness 24T2 outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W3 and the relay wirings W3B1 and W3B2 at both ends. The thickness is the same as 24T1. Further, the resin layer 25B in the bent region BA has a thickness of 25BT2 outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W3 and a thickness of 25BT1 in the region surrounded by the relay wirings W3B1 and W3B2 at both ends. Is the same.

FIG. 8 is a cross-sectional view of a bent region according to a modified example of the first embodiment. FIG. 8 shows a modified example of the cross section cut along the C1-C1 line shown in FIG.

As shown in FIGS. 4 and 8, in the packed bed 65 in the bent region BA, the thickness 65T2 outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W3 is surrounded by the relay wirings W3B1 and W3B2 at both ends. The thickness of the area may be thinner than 65T1. As a result, in the packed bed 65 of the bent region BA, the crack CR entered from the end portions EB1 and EB2 is more reliably suppressed from entering further inward, and the disconnection of the plurality of relay wirings W3 is suppressed. Can be done.

Further, in the first flattening layer 24 in the bent region BA, the thickness 24T2 outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W3 is the thickness of the region surrounded by the relay wirings W3B1 and W3B2 at both ends. It may be thinner than 24T1. As a result, in the first flattening layer 24 of the bent region BA, the crack CR entered from the end portions EB1 and EB2 is more reliably suppressed from entering further inward, and the plurality of relay wirings W3 are disconnected. It can be suppressed.

Further, the resin layer 25B in the bent region BA has a thickness 25BT2 outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W3 from the thickness 25BT1 in the region surrounded by the relay wirings W3B1 and W3B2 at both ends. May be thin. As a result, in the resin layer 25B of the bent region BA, the crack CR entered from the end portions EB1 and EB2 is more reliably suppressed from entering further inward, and the disconnection of the plurality of relay wirings W3 is suppressed. Can be done.

In order to reduce the thickness of a part of each of the resin layer 25B, the first flattening layer 24, and the packed bed 65, for example, a photolithography method using a gray tone mask or a halftone mask is used. It can be carried out.

Further, a part of the relay wiring W3 may be thinner than the drain electrode, the source electrode and the source wiring in the same layer as the relay wiring W3.

Next, the manufacturing method of the display device 1 will be described. FIG. 9 is a diagram showing a flow of a manufacturing process of the display device 1 according to the embodiment.

First, the base material 3 is formed on a translucent support substrate (for example, mother glass) (step S11). That is, the first base material resin layer 11 is formed by applying a resin material such as polyimide to the surface of the support substrate and heating it. Next, the buffer layer 12 is formed on the surface of the first base material resin layer 11 by a CVD method using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Next, the second base material resin layer 13 is formed on the surface of the buffer layer 12 by applying a resin material such as polyimide and heating it. The first base material resin layer 11 and the second base material resin layer 13 do not contain, for example, a photosensitive material, and are formed by heating at a relatively high temperature of about 500 ° C.

Next, the base coat layer 14 is formed on the surface of the base material 3 by a CVD method using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (step S12). Next, the semiconductor layer 16 is formed in the formation region of the thin film transistor Tr by using polysilicon, an oxide semiconductor material, or the like (step S13).

Next, the gate insulating layer 21 is formed on the surface of the base coat layer 14 by covering the semiconductor layer 16 by a CVD method using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (step S14). Next, a metal material such as aluminum, tungsten, molybdenum, tantalum, chromium, titanium, or copper or an alloy thereof is formed on the surface of the gate insulating layer 21 by a sputtering method or the like, and the gate electrode GE is formed by a photolithography method. The gate wiring GW, the first lead-out wiring W1, and the second lead-out wiring W2 are formed (step S15). As described above, the gate electrode GE, the gate wiring GW, the first lead-out wiring W1, and the second lead-out wiring W2 are formed of the same material in the same process, that is, in the same layer.

Next, the gate electrode GE, the gate wiring GW, the first lead-out wiring W1, and the second lead-out wiring W2 are covered by CVD using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride to cover the gate. The first inorganic insulating layer 22 is formed on the surface of the insulating layer 21 (step S16). Next, a metal material such as aluminum, tungsten, molybdenum, tantalum, chromium, titanium, or copper or an alloy thereof is formed on the surface of the first inorganic insulating layer 22 by a sputtering method or the like, and a capacitance is formed by a photolithography method. The electrode CE is formed (step S17). Next, the second inorganic insulating layer 23 is formed on the surface of the first inorganic insulating layer 22 by covering the capacitive electrode CE by CVD using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. (Step S18).

Next, the second inorganic insulating layer 23, the first inorganic insulating layer 22, the gate insulating layer 21, and the base coat layer 14 in the bent region BA are removed by etching to collectively form the openings HB to HE. (Step S19). As a result, the surface of the second base material resin layer 13 is exposed in the bent region BA.

Next, by a photolithography method using a resin material such as polyimide or acrylic, the inside of the region surrounded by the openings HB to HE on the exposed surface of the second base material resin layer 13 in the bent region BA. The packed bed 65 is formed in (step S20).

Next, a metal material such as aluminum, tungsten, molybdenum, tantalum, chromium, titanium, or copper or an alloy thereof is formed on the surface of the second inorganic insulating layer 23 by a sputtering method or the like, and a drain electrode is formed by a photolithography method. The DE, the source electrode SE, and the source wiring are formed, and the relay wiring W3 is formed on the surface of the packed layer 65 in the same layer (step S21). As a result, a plurality of relay wirings W3 are formed between the display area DA and the terminal area TA. As described above, the drain electrode DE, the source electrode SE, the source wiring, and the relay wiring W3 are formed of the same material, that is, in the same layer in the same process.

Here, in the display region DA, the drain electrode DE is connected to the drain region of the semiconductor layer 20 through a contact hole previously formed so as to penetrate the first inorganic insulating layer 22 and the second inorganic insulating layer 23. The source electrode SE is connected to the source region of the semiconductor layer 20. As a result, the thin film transistor Tr is formed in the display area DA.

Further, in the vicinity of the bent region BA, one end of the relay wiring W3 is the first through the first contact hole CH1 formed in advance so as to penetrate the first inorganic insulating layer 22 and the second inorganic insulating layer 23. It is connected to one end of the lead-out wiring W1, and through the second contact hole CH2, the other end of the relay wiring W3 is connected to one end of the second lead-out wiring W2. A plurality of relay wirings W3 are arranged side by side in the direction in which the bent region BA extends, and are formed on the surface of the packed bed 65. As a result, the plurality of relay wirings W3 electrically connect the display area DA and the terminal area TA through the bending area BA. As a result, a plurality of lead-out wirings 61 are formed in the frame area NA.

Next, the thin film transistor Tr and the relay wiring W3 are covered with a photolithography method using polyimide or a resin material such as acrylic, and the first flat surface is formed on the surface of the second inorganic insulating layer 23 and the surface of the packed layer 65. The packed bed 24 is formed (step S22).

Next, the first electrode 30, the bank 25, the light emitting element 5, and the resin layer 25B are formed on the surface of the first flattening layer 24 (step S23).

That is, for example, a reflective layer containing a metal material such as aluminum, copper, gold, or silver and a transparent layer containing ITO, IZO, ZnO, AZO, BZO, GZO, or the like are provided in the first flattening layer 24, respectively. The first electrode 30 is formed in the formation region of the light emitting element 5 by patterning on the surface by a photolithography method. As a result, the first electrode 30 is connected to the drain electrode DE through a contact hole previously formed so as to penetrate the first flattening layer 24.

Then, by a photolithography method using a resin material such as polyimide or acrylic, in the display region DA, the peripheral end portion (edge portion) of the first electrode 30 is covered and the surface of the first flattening layer 24 is covered. The banks 25 are formed in a grid pattern, and the resin layer 25B is formed on the surface of the first flattening layer 24 in the vicinity of the bent region BA.

Then, in the display region DA, the first charge injection layer 31, the light emitting layer 32, and the second charge injection layer 33 are sequentially placed in the region on the first electrode 30 and surrounded by the banks 25 by, for example, a thin-film deposition method. Form. Then, a second electrode 34 is formed on the surface of the bank 25 and the surface of the second charge injection layer 33 by a transparent conductive material such as ITO, IZO, ZnO, AZO, BZO, or GZO by a vapor deposition method or the like. As a result, a plurality of light emitting elements 5 are formed in the display region DA.

Next, in the vicinity of the bent region BA, the packed layer 65, the first flattening layer 24, and the resin layer 25B are placed on the resin layer 25B outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W3 in a plan view. A plurality of slits SL having a depth extending from the surface of the to the packed bed 65 are formed (step S24). The plurality of slits SL can be formed by, for example, etching.

When the resin layer 25B is not formed in the bent region BA, a plurality of slits SL are formed so as to have a depth from the surface of the first flattening layer 24 to the packed bed 65. In the present embodiment, the packed layer 65 is cut out in the depth direction so that the surface of the second base material resin layer 13 under the packed layer 65 is exposed on the bottom surface SLb of the plurality of slits SL. Slit SL is formed. The step S24 for forming the plurality of slits SL may be performed after forming the bank 25 and the resin layer 25B and before the step S30 for individualizing, which will be described later.

Next, the sealing layer 6 is formed (step S25). That is, the inorganic film 40, the organic film 41, and the inorganic film 42 are laminated in order on the surfaces of the second electrode 34 and the first flattening layer 24. The inorganic films 40 and 42 are formed by, for example, by a CVD method or the like, using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The organic film 41 is formed by an inkjet method or the like using a resin material such as polyimide or acrylic.

Next, the first film 7 containing a resin material such as polyethylene terephthalate (PET) is attached to the surface of the sealing layer 6 (step S26). Next, the support substrate is peeled off from the back surface of the first base material resin layer 11 by irradiating the first base material resin layer 11 from the back surface side of the support substrate through, for example, a laser (step S27). ). Next, the second film 10 containing a resin material such as polyethylene terephthalate (PET) is attached to the back surface of the first base material resin layer 11 from which the support substrate has been peeled off (step S28).

Next, the ends EB1 to EB4, which are the outer edges of the display panel 2, are cut by a laser or the like so that the display panel 2 has a desired size. As a result, the display panel 2 is fragmented into a desired size (step S29). Here, in the vicinity of the bent region BA, the packed layer 65, the first flattening layer 24, and the resin layer 25B are covered with the resin layer 25B outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W3 in a plan view. Since a plurality of slits SL having a depth from the surface to the packed bed 65 are formed, even if crack CR enters from the end portions EB1 and EB2, the crack CR causes a plurality of relay wirings W3 in the bent region BA. Can be prevented from breaking.

Next, the opening HA is formed in the region of the second film 10 that overlaps with the bent region BA (step S30). Next, the bent region BA of the individualized display panel 2 is bent by, for example, 180 ° (step S31). Then, the plurality of terminals 60 in the terminal region TA are electrically connected to each of the plurality of terminals provided on the circuit board 70 provided on the back surface side of the display panel 2. As a result, the display device 1 is completed.

[Embodiment 2]
The second embodiment of the present disclosure will be described. The points different from those of the first embodiment will be mainly described, and the description of the contents overlapping with the first embodiment will be omitted. FIG. 10 is a cross-sectional view of the vicinity of the sub-pixel SP in the display panel 2 of the display device 1 according to the second embodiment. The planar shape of the display panel 2 of the display device 1 according to the second embodiment is the same as that of FIG.

As shown in FIG. 10, the TFT layer 4 in the display panel 2 may further include an intermediate electrode M4 and a second flattening layer 26.

The intermediate electrode M4 is provided in an island shape on the first flattening layer 24, and is electrically connected to the drain electrode DE through a contact hole formed in the first flattening layer 24. The intermediate electrode M4 electrically connects the drain electrode DE and the first electrode 30. Further, in the frame region NA, wiring such as lead-out wiring is provided in the same layer as the intermediate electrode M4. The wiring of the intermediate electrode M4 and the same layer as the intermediate electrode M4 is configured to include a conductive material. As the conductive material, for example, a metal material such as aluminum, tungsten, molybdenum, tantalum, chromium, titanium, copper or an alloy thereof can be used.

The second flattening layer 26 covers the intermediate electrode M4 and is provided on the first flattening layer 24 on the entire surface of the display area DA. The second flattening layer 26 is a resin layer composed of, for example, a resin material such as polyimide or acrylic. Further, the second flattening layer 26 contains, for example, a photosensitive material, and is patterned by, for example, a photolithography method.

The plurality of light emitting elements 5 and the bank 25 are provided on the second flattening layer 26 in the present embodiment. The first electrode 30 is connected to the intermediate electrode M4 through a contact hole formed in the second flattening layer 26. That is, the first electrode 30 is electrically connected to the drain electrode DE via the intermediate electrode M4.

FIG. 11 is a cross-sectional view of the lead-out wiring 61B1 at one end in the vicinity of the bending region BA according to the second embodiment cut in the Y direction.

In the second embodiment, for example, of the lead-out wiring 61, the first lead-out wiring W1 and the second lead-out wiring W2 are in the same layer as the source electrode SE and the drain electrode DE, and the relay wiring W3 is in the same layer as the intermediate electrode M4. be.

The relay wiring W3 has one end passing through the first contact hole CH1 formed in the first flattening layer (first insulating layer) 24 covering the first lead-out wiring W1 and the end portion of the first lead-out wiring W1. It is electrically connected. Further, the other end of the relay wiring W3 passes through the second contact hole CH2 formed in the first flattening layer (first insulating layer) 24 covering the second lead wiring W2, and the end of the second lead wiring W2. Is electrically connected to.

In the frame region NA, the base material 3 provided on the second film 10 (that is, the first base material resin layer 11, the buffer layer 12, and the second base material resin layer 13) is provided, and the base material 3 is provided. A base coat layer 14 is provided on the base coat layer 14, a gate insulating layer 21 is provided on the base coat layer 14, a first inorganic insulating layer 22 is provided on the gate insulating layer 21, and a second inorganic insulating layer 22 is provided on the first inorganic insulating layer 22. A layer 23 is provided, and a first lead-out wiring W1 and a second lead-out wiring W2 are provided on the second inorganic insulating layer 23. Further, a first flattening layer 24 is provided so as to cover the first lead-out wiring W1 and the second lead-out wiring W2, a second flattening layer 26 is provided on the first flattening layer 24, and a second flattening layer is provided. A resin layer 25B which is the same layer as the bank 25 is provided on the 26. Further, the bent region BA is provided with a first flattening layer 24 on which a plurality of relay wirings W3 are laminated on the surface.

The base coat layer (second insulating layer) 14 provided under the first lead-out wiring W1 and the second lead-out wiring W2 has an opening HB formed in a region overlapping the bent region BA. In the gate insulating layer (second insulating layer) 21 provided under the first lead-out wiring W1 and the second lead-out wiring W2, an opening HC is formed in a region overlapping the bent region BA. In the first inorganic insulating layer (second insulating layer) 22 provided under the first lead-out wiring W1 and the second lead-out wiring W2, an opening HD is formed in a region overlapping the bent region BA. In the second inorganic insulating layer (second insulating layer) 23 provided under the first lead-out wiring W1 and the second lead-out wiring W2, an opening HE is formed in a region overlapping the bent region BA.

In the bent region BA, the first flattening layer 24 is formed on the surface of the second base material resin layer 13 exposed in the bent region BA, the opening HB formed in the base coat layer 14, and the gate insulating layer 21. It is provided in a region surrounded by the opening HC formed, the opening HD formed in the first inorganic insulating layer 22, and the opening HE formed in the second inorganic insulating layer 23. The first flattening layer 24 in the bent region BA extends continuously in the X direction so as to connect both ends EB1 and EB2. A relay wiring W3 extending in the Y direction is provided on the first flattening layer 24 in the bent region BA.

The first flattening layer 24 provided in the bent region BA and the first flattening layer 24 provided in the display region DA are not connected and are separated.

The second flattening layer 26 is provided on the first flattening layer 24 so as to cover the relay wiring W3 in the same layer as the intermediate electrode M4. The second flattening layer 26 provided in the display area DA and the second flattening layer 26 provided in the vicinity of the bent area BA may not be connected to each other.

The resin layer 25B is, for example, the same layer as the bank 25 in the display area DA, and is provided separately from the bank 25. The resin layer 25B in the bent region BA may be omitted.

FIG. 12 is a cross-sectional view of the lead-out wiring 61B1 at one end in the bent region according to the second embodiment cut in the X direction.

As shown in FIGS. 11 and 12, in the display panel 2 according to the present embodiment, the first flattening layer 24 (first resin layer) and the second flattening layer 26 (second resin layer) in the bent region BA. In the plan view, the surface of the second flattening layer 26 (second resin layer) to the first flattening layer 24 (first resin) is outside the relay wirings W3B1 and W3B2 at both ends of the plurality of relay wirings W. A plurality of slits SL having a depth leading to the layer) are formed.

As a result, when the display panel 2 is cut to a desired size in the step of individualizing, the first flattening layer 24 and the second flattening layer in the bent region BA are formed from the ends EB1 and EB2 in the bent region BA. 26 Even if the crack CR enters in the direction toward the inside of each, it is possible to suppress the crack CR from entering the inside more than the plurality of slits SL. As a result, it is possible to prevent the plurality of relay wirings W3 from being disconnected due to the crack CR.

Further, in the present embodiment, it is preferable that at least one of the plurality of slits SL penetrates the first flattening layer 24 in the Y direction. In other words, the plurality of slits SL are formed so as to extend along the Y direction (that is, along the ends EB1 and EB2), and at least one of the plurality of slits SLs has a length in the Y direction. , It is preferable that the length of the first flattening layer 24 in the bent region BA is the same as the length in the Y direction. According to this, at least one of the plurality of slits SLs prevents the crack CR from entering the inside of the first flattening layer 24 in the bent region BA from the ends EB1 and EB2 of the first flattening layer 24 in the bent region BA. This can be suppressed more reliably. Therefore, it is possible to more reliably suppress the disconnection of the plurality of relay wirings W3 due to the crack CR.

It is preferable that all of the plurality of slits SL penetrate the first flattening layer 24 in the bent region BA in the Y direction.

Further, in the present embodiment, at least one of the plurality of slits SL has a depth that penetrates the second flattening layer 26 (second resin layer) and the first flattening layer 24 (first resin layer). It is preferable to have. In other words, in the bent region BA, it is preferable that at least one bottom surface SLb of the plurality of slits SL is the surface of the second base material resin layer 13. As a result, in the bent region BA, crack CR is generated from the ends EB1 and EB2 of the second flattening layer 26 and the first flattening layer 24 to the inside of the second flattening layer 26 and the first flattening layer 24, respectively. Entering can be more reliably suppressed by at least one of the plurality of slits SL. Therefore, it is possible to more reliably suppress the disconnection of the plurality of relay wirings W3 due to the crack CR.

Further, it is preferable that at least one of the plurality of slits SL has a depth that penetrates the resin layer 25B in addition to the second flattening layer 26 and the first flattening layer 24. As a result, it is possible to more reliably suppress the crack CR that has entered from the end portions EB1 and EB2 from entering further inward, and to prevent the plurality of relay wirings W3 from being disconnected.

It is preferable that all of the plurality of slits SL have a depth that penetrates the first flattening layer 24 and the packed bed 65.

FIG. 13 is a plan view showing a schematic configuration in the vicinity of both ends EB1 and EB2 of the bent region BA of the display panel 2 according to the modified example of the second embodiment. FIG. 14 is a cross-sectional view of the bent region BA according to the modified example of the second embodiment. FIG. 15 is a cross-sectional view of a bent region BA according to another modification of the second embodiment. 14 and 15 show a cross section of the D1-D1 line in FIG.

As shown in FIGS. 13 to 15, the film thickness of the second flattening film 24 provided in the bent region BA may be as thin as possible.

In the example shown in FIG. 14, the film thickness of the second flattening film 24 in the bent region BA is substantially the same as the film thickness of the second flattening film 24 provided on the base coat layer 14 in the vicinity of the bent region BA. ing.

In the example shown in FIG. 15, the second flattening film 24 in the bent region BA is provided so as to cover the end portion of the base coat layer 14 in the bent region BA. The second flattening film 24 is not formed in the central portion of the bent region BA, and the relay wiring W3 is provided on the surface of the second base material resin layer 13.

As shown in FIGS. 13 to 15, the film thickness of the resin layer (for example, the second flattening layer 26) in the bent region BA is made as thin as possible to form the bent region BA when the bent region BA is bent. It is possible to suppress an increase in the load applied to each layer. As a result, the bending region BA can be easily bent.

Further, each element appearing in the above-described embodiment or modification may be appropriately combined as long as there is no contradiction.

1 Display device, 2 Display panel, 3 Base material, 4 TFT layer, 5 Light emitting element, 6 Sealing layer, 7 1st film, 10 2nd film, 11 1st base material resin layer, 12 Buffer layer, 13 2nd Base resin layer, 14 base coat layer (second insulating layer), 20 semiconductor layer, 21 gate insulating layer (second insulating layer), 22 first inorganic insulating layer (first insulating layer, second insulating layer), 23rd 2 Inorganic insulating layer (1st insulating layer, 2nd insulating layer), 24 1st flattening layer (1st insulating layer, 1st resin layer), 25 banks, 25B resin layer, 26 2nd flattening layer (2nd) Resin layer), 60 terminals, 61 lead-out wiring, 65 filled layer (first resin layer), BA bent area, CH1 first contact hole, CH2 second contact hole, CR crack, DA display area,
DE drain electrode, EB1 to EB4 end, GE gate electrode, GW gate wiring, HA to HE opening, M4 intermediate electrode, NA frame area, SE source electrode, SL slit, SP sub pixel, TA terminal area, W1 1st Lead-out wiring, W2 second pull-out wiring, W3 relay wiring

Claims (12)

1. It is provided with an image display area, a terminal area provided with a plurality of terminals, and a folding area that is a region between the display area and the terminal area and is bendable.
   The bent area is
   The first resin layer and
   A plurality of relay wirings provided on the first resin layer and provided between the display area and the terminal area, and
   It has a second resin layer that covers the plurality of relay wirings and is provided on the first resin layer.
   In the bent region, the first resin layer and the second resin layer have the first resin layer from the surface of the second resin layer to the outside of the relay wirings at both ends of the plurality of relay wirings in a plan view. A display device in which a plurality of slits having a depth leading to are formed.
2. Assuming that the direction from the display area to the terminal area is the first direction,
   The display device according to claim 1, wherein at least one of the plurality of slits penetrates the first resin layer in the first direction.
3. The display device according to claim 1 or 2, wherein at least one of the plurality of slits is a depth that penetrates the second resin layer and the first resin layer.
4. The display device according to any one of claims 1 to 3, wherein both ends of the bent region outside the relay wiring at both ends overlap with the slits at both ends of the plurality of slits.
5. Claims 1 to 4 of the first resin layer in the bent region, wherein the thickness of the first resin layer outside the relay wirings at both ends of the plurality of relay wirings is thinner than the thickness of the region surrounded by the relay wirings at both ends. The display device according to any one of the above items.
6. Claims 1 to 5 of the second resin layer in the bent region, wherein the thickness of the second resin layer outside the relay wirings at both ends of the plurality of relay wirings is thinner than the thickness of the region surrounded by the relay wirings at both ends. The display device according to any one of the above items.
7. A plurality of first lead-out wires extending from the display area toward the bent area, and
   A plurality of second lead-out wirings extending from each of the plurality of terminals in the direction of the bending region, and
   The plurality of first lead-out wirings and the first insulating layer covering the plurality of second lead-out wirings are provided.
   Each of the multiple relay wirings is
   One end is electrically connected to each of the plurality of first lead-out wires through the plurality of first contact holes formed in the first insulating layer.
   13. The display device described.
8. A second insulating layer provided under the first lead-out wiring and the plurality of second lead-out wirings is further provided.
   The display device according to claim 7, wherein in the bent region, the second insulating layer has an opening extending in a direction intersecting with the plurality of relay wirings.
9. The display area comprises a plurality of thin film transistors including a gate electrode and a source electrode and a drain electrode which are layers different from the gate electrode.
   The plurality of first lead-out wirings and the plurality of second lead-out wirings are provided in the same layer as the gate electrode.
   The display device according to claim 7 or 8, wherein the plurality of relay wirings are provided in the same layer as the source electrode and the drain electrode.
10. The display area is
    A plurality of thin film transistors including a gate electrode and a source electrode and a drain electrode which are layers different from the gate electrode,
    A first flattening layer that covers the plurality of thin film transistors and contains a resin material,
    An intermediate electrode provided in an island shape on the first flattening layer and electrically connected to the drain electrode through a contact hole formed in the first flattening layer.
    A second flattening layer that covers the intermediate electrode and is provided on the first flattening layer and contains a resin material.
    An anode or cathode provided in an island shape on the second flattening layer is provided.
    The plurality of first lead-out wirings and the plurality of second lead-out wirings are provided in the same layer as the source electrode and the drain electrode.
    The display device according to claim 7 or 8, wherein the plurality of relay wirings are provided in the same layer as the intermediate electrode.
11. A method of manufacturing a display device including an image display area, a terminal area provided with a plurality of terminals, and a folding area that is a region between the display area and the terminal area and is bendable.
    The step of forming the bent region is included, and the step of forming the bent region is
    The process of forming the first resin layer and
    A step of forming a plurality of relay wirings between the display area and the terminal area on the first resin layer,
    A step of covering the plurality of relay wirings and forming a second resin layer on the first resin layer, and a step of forming the second resin layer.
    The depth from the surface of the second resin layer to the first resin layer is provided to the first resin layer and the second resin layer so as to be outside the relay wirings at both ends of the plurality of relay wirings in a plan view. A method of manufacturing a display device, which comprises a step of forming a plurality of slits having the same.
12. After forming the plurality of slits, the first resin layer and the second resin layer are cut so as to include the outer edges of the plurality of slits, and the display area, the bent area, and the terminal area are formed. And the process of individualizing the display panel with
    The method for manufacturing a display device according to claim 11, further comprising a step of bending the bent region in the display panel after the individual pieces are separated.

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