WO2022001722A1 - Procédé et dispositif d'implémentation pour le calcul d'une fonction sinus ou cosinus - Google Patents

Procédé et dispositif d'implémentation pour le calcul d'une fonction sinus ou cosinus Download PDF

Info

Publication number
WO2022001722A1
WO2022001722A1 PCT/CN2021/101216 CN2021101216W WO2022001722A1 WO 2022001722 A1 WO2022001722 A1 WO 2022001722A1 CN 2021101216 W CN2021101216 W CN 2021101216W WO 2022001722 A1 WO2022001722 A1 WO 2022001722A1
Authority
WO
WIPO (PCT)
Prior art keywords
result
sine
constant
mapped
range
Prior art date
Application number
PCT/CN2021/101216
Other languages
English (en)
Chinese (zh)
Inventor
万江华
龙科莅
陈虎
Original Assignee
湖南毂梁微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 湖南毂梁微电子有限公司 filed Critical 湖南毂梁微电子有限公司
Publication of WO2022001722A1 publication Critical patent/WO2022001722A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/548—Trigonometric functions; Co-ordinate transformations

Definitions

  • the present invention mainly relates to the technical field, and particularly relates to an implementation method and apparatus for calculating a sine or cosine function.
  • Sine function and cosine function are important components in scientific technology and engineering applications. Compared with basic elementary functions, it has the characteristics of relatively complex implementation, large calculation delay, and many implementation methods. However, to obtain high-precision single-precision floating-point output results that meet the IEEE-754 standard, the cost is relatively higher.
  • the main implementation methods include: coordinate rotation method (CORDIC: Cordinate Rotation Digital Computer), look-up table method and polynomial approximation method.
  • the estimation point is generally set in advance to predict and estimate the result. The closer the distance between the input value and the estimated point is, the closer the estimated result of the estimated point is to the ideal accurate result, and the more accurate the result can be obtained with fewer iterations.
  • the resulting estimates are typically stored in the corresponding circuit or device in the form of a coefficient table.
  • the present invention provides a simple principle, high precision, little hardware resource consumption, low calculation delay, and relatively low storage space occupied by coefficients. Smaller implementation method and apparatus for calculating sine or cosine functions.
  • an implementation method for calculating a sine or cosine function the steps of which include: Step S1: map the input number to the range of [0, TT/4], and Obtain the function type of the internal operation and the sign of the result; Step S2: Obtain the constant result and the nearest estimated point according to the number mapped to the range of [0, TT/4] in Step S1; Step S3: According to the function of the internal operation Type and the nearest estimated point to obtain the estimated value of the corresponding sine or cosine function, that is, the coefficients required for the polynomial calculation; Step S4: Obtain the number mapped to the range of [0, TT/4] in step S1 to the nearest estimated point Step S5: Use the estimated value and the distance from the number mapped to the range of [0,TT/4] to the nearest estimated point to complete the polynomial operation; Step S6: Perform the calculation on the number mapped to the range of [0,TT/4] And the
  • Step S201 According to the partial digits of the number that have been mapped to [0, TT/4], obtain the nearest estimated point
  • Step S202 According to the mapped To the number of [0,TT/4], obtain the constant result: If the number after mapping is equal to several specific constants, the number position used to identify the valid constant result is set to 1, indicating that there is a valid constant result output; valid constant result
  • the existence of is mainly used to eliminate the sudden change of coefficient value in the very narrow range of number domain in the middle of two adjacent estimated points.
  • step S3 the coefficient search is completed using the partial digits of the nearest estimated point and the function type identifier of the internal operation obtained in the step S1 as an index.
  • step S4 add the number mapped to the range of [0,7r/4] and the nearest estimated point to obtain the result; map the number mapped to [0,TT/4] in step S1 4] and the nearest estimated point are added to obtain the distance between the two; the two data order codes in step S4 are consistent, and there is no need to perform order matching, directly add the mantissa, and then according to the leading 0 of the mantissa The number of adjustment order code.
  • step S5 a polynomial operation is completed according to the input variables and the correlation coefficient, wherein the polynomial form is as follows:
  • Y C 0 + (Ci + C 2 x D) x D (2) where 0 ) , 6, and C 2 represent coefficients, and D is the number obtained in step S4 and mapped to the range of [0,?r/4] The distance value to the nearest estimated point; where D can be positive or negative, determined by the relative position of the two numbers on the number axis for calculating the value of D; Coefficients C Q , C 1; C 2 can be the same or only have a sign bit Different or differ only by a constant multiple, which is calculated by shifting.
  • the steps of step S6 include: Step S601: if the input of the constant result is detected, select the constant result as the selected number; that is: if the valid identifier of the constant result is 1, then the constant result is the selected number; Step S602: Otherwise, when the number mapped to the range of [0,TT/4] in step S1 is less than or equal to the set threshold and the function type of the internal operation is a sine function, select the input mapping [0,TT] The number within the range of /4] is the selected number; Step S603: Otherwise, the result of the polynomial calculation is selected as the selected number; Step S604: Use the sign of the result obtained in Step S1 to give the correct sign bit to the selected number; Step S605: Rounds and normalizes the selected number to obtain a single-precision floating-point output that conforms to the IEEE-754 standard.
  • the present invention further provides an apparatus for calculating a sine or cosine function, which includes: a preprocessing module, including a compression mapping circuit unit for mapping input numbers to [0, ?r/4], an addition unit, a translation unit a code unit, a constant selection circuit; a coefficient look-up table, using a non-volatile storage device, for storing the estimated value corresponding to the estimated point, that is, the coefficient value used for the polynomial calculation; an operation module, including two multiply-add operation units and a related left shift unit, used to complete polynomial operations; a result selection module, including an addition unit, a constant result valid flag detection unit, and a basic selection circuit; when the constant result is valid flag When the bit detection unit detects that the valid flag bit is 1, it
  • the preprocessing module in the preprocessing module, two constant multiplication units are used to assist in completing the compression mapping of the input number to [0, TT/4]; the addition unit is used to complete the output value after compression mapping The calculation of the distance to the nearest estimated point; the decoding unit is a two-level decoder, which is used to complete the decoding of the order code of the output value of the compression mapping and the partial digits of the mantissa to the coefficient index value, and obtain the nearest estimate. Point; the constant selection circuit includes a multiplexer for selecting the constant result for output according to the value after the compression mapping is completed.
  • the implementation method and device for calculating a sine or cosine function of the present invention map data to [0, TT/4] for operation, and map the data in the range of [0, TT/4] close to 0
  • the method in which the number of sine function is directly output as the result without calculation during the internal sine function operation, and the multiplexing of the coefficients during the polynomial operation of the internal sine function and cosine function at the same estimation point, so that the result can be guaranteed. Under the premise of accuracy, the size of the coefficient table space is effectively reduced.
  • the implementation method and device for calculating the sine or cosine function of the present invention through flexible setting of the distance between adjacent estimated points, and mapping to the number close to 0 in the range of [0, TT/4]
  • the precision of the output result can reach the ideal precision of the single-precision floating-point number of the IEEE-754 standard (that is, the maximum The error is less than or equal to the size of 1 unit represented by the last digit of the single-precision floating-point mantissa).
  • the implementation method and device for calculating a sine or cosine function of the present invention fine-tune the bit width of the input and output data of the multiplication and addition unit in the operation module, fine-tune the bit width of some coefficients, and fine-tune the bit width of the input and output data.
  • the number equal to some constants is directly assigned to the constant result, so as to ensure that the monotonicity of the output result is consistent with the original function without affecting the accuracy of the output result.
  • the implementation method and device for calculating a sine or cosine function of the present invention on the premise of ensuring the accuracy of the result, includes 1 compression mapping operation, 1 secondary decoding operation, and 1 coefficient search operation on the critical path , 2 multiplication operations operation, 2 addition operations, 1 result selection operation, and 1 normalization processing operation, which meet the application requirements of low latency.
  • FIG. 1 is a schematic flow chart of the method of the present invention.
  • FIG. 2 is a schematic diagram of the structure principle of the device of the present invention in a specific application example.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be emphasized that the calculation of the sine or cosine function discussed in the present invention is based on the content of the computer or the processing end of the chip, that is, how to realize the calculation of high-precision sine or cosine function by means of hardware technology, and can also ensure the performance of the hardware. The optimization, the reduction of the hardware overhead, the improvement of the accuracy under the condition of the hardware platform.
  • Step S1 Map the input number to the range of [0, TT/4], and obtain the function of the internal operation Type and sign of the result
  • Step S2 Obtain the constant result and the nearest estimated point according to the number mapped to [0, TT/4] in Step S1
  • Step S3 According to the function type of the internal operation and the nearest estimation Obtain the estimated value of the corresponding sine or cosine function, that is, the coefficients required for the polynomial calculation
  • Step S4 Obtain the distance from the number mapped to the range of [0, TT/4] in step S1 to the nearest estimated point
  • Step S5 Use the estimated value and the distance from the number mapped to the range [0,TT/4] to the nearest estimated point to complete the polynomial operation
  • Step S6 For the number mapped to the range [0,TT/4] and the constant result and polynomial The result of the operation is selected, the selected data is normalized and
  • step S2 The number is further mapped into the range of [0,7r/4], and the function type identifier of the internal operation is obtained, with 0 for sine operation and 1 for cosine operation.
  • step S2 the specific implementation steps of step S2 are: Step S201: Acquire the nearest estimated point according to the partial digits of the number that have been mapped to [0, TT/4]; Step S202: According to the number that has been mapped to [0, TT/4] 0,TT/4], and obtain the constant result: If the mapped number is equal to several specific constants, the number position used to identify the valid constant result is set to 1, indicating that there is a valid constant result output; the existence of valid constant result , which is mainly used to eliminate the fluctuation of the result value due to the sudden change of the coefficient value in the extremely narrow number domain range in the middle of the two adjacent estimated points; for the result mapped to the range of [0, TT/4] in step S201 , if it is exactly equal to TT/4, the constant result is given
  • the distance between two adjacent estimated points has a minimum value, that is, the number of estimated values within a limited range is limited, that is, the size of the corresponding coefficient table is limited;
  • the step S3 includes: using the partial digits of the nearest estimated point and the function type identifier of the internal operation obtained in the step S1 as an index to complete the search of the coefficient. Among them, this embodiment further defines the coefficient:
  • the coefficient stored in the coefficient table is the function value of the sine or cosine function corresponding to the estimated point or a constant multiple of the corresponding function value;
  • the coefficients in the coefficient table can be reused as needed to further reduce Coefficient table; that is, some coefficients can be used for the operation of the internal sine function and the operation of the internal cosine function.
  • the step S4 is specifically as follows: performing an addition operation on the number mapped to the range of [0, TT/4] and the nearest estimated point to obtain the result. Add the number mapped to [0, TT/4] in step S1 and the nearest estimated point to obtain the distance between the two.
  • step S4 The two data order codes in step S4 are consistent, and no order matching is required, the mantissa is directly added, and then the order code can be adjusted according to the number of leading 0s of the mantissa.
  • step S5 is specifically: completing the polynomial operation according to the input variable and the correlation coefficient. Among them, the polynomial form is as follows:
  • D is the mapping obtained in step S4 to the range of [0,?r/4] Count the distance value to the nearest estimated point.
  • D can be a positive number or a negative number, which is determined by the relative positions of the two numbers on the number axis for calculating the D value.
  • the series can be the same or only have the difference of the sign bit or only differ by a constant multiple, and the constant multiple can be calculated by shifting.
  • the coefficient The same function operation can be reused.
  • the coefficient used for the sine operation can be used as a coefficient to participate in the operation when the cosine operation is performed, and the difference between the two may only be one sign bit or a constant multiple, and the constant multiple can be completed by shifting.
  • the difference between the coefficients 0 ) and ⁇ : 2 is only a constant multiple, and the operation of this constant multiple can be completed by the operation of shift and addition.
  • the polynomial operation shown in the above formula (1) is further explained as follows: Since the positive and negative signs of the coefficients in the polynomial operation may appear alternately, resulting in the instability of the result value, it is necessary to achieve the required accuracy on the premise of partial multiplication and addition. The result accuracy is adjusted.
  • one input bit width of multiplying unit #2 is adjusted to be the same as one input bit width of multiplying unit #1, and another input bit width of multiplying unit #2 is adjusted to be higher than that of multiplying unit #1.
  • One input bit width is increased by 12 bits.
  • the corresponding input and output signal bit width of the adder and the corresponding output signal bit width of the multiplier #1 are adjusted.
  • the specific steps of the step S6 include: Step S601: if the input of the constant result is detected, select the constant result as the selected number; that is: if the constant result If the valid identifier is 1, the constant result is the selected number; Step S602: Otherwise, when the number mapped to the range of [0, TT/4] in step S1 is less than or equal to the set threshold and the function type of the internal operation is sine When using the function, select the number within the range of the input mapping [0, TT/4] as the selected number; Step S603: Otherwise, select the result of the polynomial calculation as the selected number; Step S604: Use the sign of the result obtained in Step S1 to select the number The number is assigned the correct sign bit; Step S605: Rounding and normalizing the selected number to obtain a single-precision floating-point number output conforming to the IEEE-754 standard.
  • this step uses the method of rounding to an even number to perform a rounding operation on the mantissa of the result; when there is a carry of the highest digit, add 1 to the exponent.
  • some of the steps in the method of the present invention can be executed in parallel or in an exchange order as required, for example, step (4) can be executed in parallel with steps (2) (3) or be executed before step (2). . As shown in FIG.
  • the present invention further provides an apparatus for calculating a sine or cosine function, which includes: a preprocessing module, including completing the mapping of input numbers to [0, ?r/ 4] compression mapping circuit unit, an addition unit, a decoding unit, a constant selection circuit.
  • the coefficient look-up table adopts a non-volatile storage device and is used to store the estimated value corresponding to the estimated point, that is, the coefficient value used for the polynomial calculation.
  • the operation module includes two multiply-add operation units and a related left shift unit for completing polynomial operations. That is, it includes multiplying unit #1, multiplying unit #2, and adding unit #1 and adding unit #2.
  • the result selection module includes an addition unit, a constant result valid flag detection unit, and a basic selection circuit.
  • the normalization processing module includes a decoding unit and a left shift unit. Rounding processing module, including an adder, three comparison units.
  • the output of the preprocessing module in the device of the present invention includes: the coefficient index value, the distance from the output value after the compression mapping to the nearest estimated point, the output value after the compression mapping is completed, the positive value of the result The negative sign, the corresponding constant value obtained from the output value after the compression mapping is completed, and the function type identifier of the internal operation.
  • the input of the preprocessing module includes: the function type identifier of the sine or cosine function to be calculated and the single-precision floating point number conforming to the IEEE-754 standard.
  • two constant multiplication units are used to assist in completing the compression mapping of the input number to [0, TT/4].
  • the addition unit is used to complete the calculation of the distance from the compressed mapped output value to the nearest estimated point.
  • the decoding unit is a two-level decoder, which is used for decoding the exponent of the output value of the compression mapping and the partial digits of the mantissa to the coefficient index value, and obtains the nearest estimated point.
  • the constant selection circuit includes a multiplexer for selecting a constant according to the value after the compression mapping is completed output the result.
  • the coefficient look-up table is a non-volatile storage device for storing estimated values corresponding to the estimated points, that is, coefficient values used for polynomial calculation.
  • the size of the table space required for the coefficient lookup table is not greater than 256 X 64 bits.
  • the operation module includes two multiply-add operation units for completing polynomial operations.
  • the polynomial form is as follows:
  • the operation module on the premise of ensuring the accuracy of the result, needs to adjust the bit width of the output signal of the multiplier #2, for example, to make the bit width of one of the input signals of the multiplication unit #2 and the input bit of the multiplication unit #1
  • the width of the other input signal of the multiplier #2 is 12 bits wider than that of the other input signal of the multiplication unit #1.
  • the bit width of the input and output signals of the adder #1 should be adjusted to ensure the accuracy of the result.
  • the fluctuation of the result value caused by the alternating signs of the coefficients during the polynomial operation is eliminated.
  • operations within the parentheses are performed using multiplier #1 and adder #1
  • operations outside the parentheses are performed using multiplier #2 and adder #2.
  • one input bit width of multiplication unit #2 can be adjusted to be the same as one input bit width of multiplication unit #1, and another input bit width of multiplication unit #2 can be adjusted without affecting the accuracy of the result.
  • the result selection module when the constant result valid flag bit detection unit detects that the valid flag bit is 1, it directly selects and outputs the constant result.
  • the addition unit is used to compare the input compression mapping to [0, TT/4] number with the set threshold, when the input compression mapping to [0, TT/4] number is less than the set threshold and When the function type of the internal operation is identified as a sine function, the compression output in the output preprocessing module is mapped to the [0,TT/4] number.
  • the device of the present invention includes 1 compression mapping operation, 1 secondary decoding operation, 1 coefficient search operation, 2 multiplication operations, 2 addition operations, 1 result selection operation, 1 result selection operation on the critical path.
  • a normalized processing operation which meets the application requirements of low latency.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

L'invention concerne un procédé et un dispositif d'implémentation pour le calcul d'une fonction sinus ou cosinus. Le procédé comprend les étapes suivantes : étape S1, ramener un nombre d'entrée sur un intervalle [0, π/4], et obtenir un type de fonction d'opération interne et un symbole de signe d'un résultat ; étape S2, obtenir un résultat constant et un point d'estimation le plus proche selon le nombre ramené sur l'intervalle [0, π/4] à l'étape S1 ; étape S3, obtenir une valeur estimée d'une fonction sinus ou cosinus correspondante, c'est-à-dire un coefficient requis pour un calcul polynomial ; étape S4, obtenir une distance du nombre ramené sur l'intervalle [0, π/4] à l'étape S1 au point d'estimation le plus proche ; étape S5, effectuer une opération polynomiale en utilisant la valeur estimée et la distance du nombre ramené sur l'intervalle [0, π/4] au point d'estimation le plus proche ; et étape S6, sélectionner le nombre ramené sur l'intervalle [0, π/4], le résultat constant et un résultat de l'opération polynomiale, effectuer un traitement de normalisation et d'arrondi, puis effectuer une sortie. Le dispositif est utilisé pour implémenter le procédé. Le procédé présente les avantages d'un principe simple, d'une grande précision, d'une faible consommation de ressources matérielles, d'un faible temps de calcul, d'un relativement petit espace de stockage occupé par les coefficients, et analogues.
PCT/CN2021/101216 2020-06-29 2021-06-21 Procédé et dispositif d'implémentation pour le calcul d'une fonction sinus ou cosinus WO2022001722A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010607527.6A CN111831257A (zh) 2020-06-29 2020-06-29 一种用于计算正弦或余弦函数的实现方法及装置
CN202010607527.6 2020-06-29

Publications (1)

Publication Number Publication Date
WO2022001722A1 true WO2022001722A1 (fr) 2022-01-06

Family

ID=72899627

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/101216 WO2022001722A1 (fr) 2020-06-29 2021-06-21 Procédé et dispositif d'implémentation pour le calcul d'une fonction sinus ou cosinus

Country Status (2)

Country Link
CN (1) CN111831257A (fr)
WO (1) WO2022001722A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116720554A (zh) * 2023-08-11 2023-09-08 南京师范大学 一种基于fpga技术的多段线性拟合的神经元电路实现方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111831257A (zh) * 2020-06-29 2020-10-27 湖南毂梁微电子有限公司 一种用于计算正弦或余弦函数的实现方法及装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001209525A (ja) * 2000-01-28 2001-08-03 Matsushita Electric Ind Co Ltd 三角関数生成装置
CN102741706A (zh) * 2009-12-16 2012-10-17 泰勒斯公司 地理参照图像区域的方法
CN104536720A (zh) * 2014-12-22 2015-04-22 浙江中控研究院有限公司 基于fpga的待测角三角函数值的测算方法及系统
US20180217814A1 (en) * 2017-02-02 2018-08-02 Vivante Corporation Systems And Methods For Computing Mathematical Functions
CN111831257A (zh) * 2020-06-29 2020-10-27 湖南毂梁微电子有限公司 一种用于计算正弦或余弦函数的实现方法及装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001209525A (ja) * 2000-01-28 2001-08-03 Matsushita Electric Ind Co Ltd 三角関数生成装置
CN102741706A (zh) * 2009-12-16 2012-10-17 泰勒斯公司 地理参照图像区域的方法
CN104536720A (zh) * 2014-12-22 2015-04-22 浙江中控研究院有限公司 基于fpga的待测角三角函数值的测算方法及系统
US20180217814A1 (en) * 2017-02-02 2018-08-02 Vivante Corporation Systems And Methods For Computing Mathematical Functions
CN111831257A (zh) * 2020-06-29 2020-10-27 湖南毂梁微电子有限公司 一种用于计算正弦或余弦函数的实现方法及装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116720554A (zh) * 2023-08-11 2023-09-08 南京师范大学 一种基于fpga技术的多段线性拟合的神经元电路实现方法
CN116720554B (zh) * 2023-08-11 2023-11-14 南京师范大学 一种基于fpga技术的多段线性拟合的神经元电路实现方法

Also Published As

Publication number Publication date
CN111831257A (zh) 2020-10-27

Similar Documents

Publication Publication Date Title
WO2022001722A1 (fr) Procédé et dispositif d'implémentation pour le calcul d'une fonction sinus ou cosinus
WO2022052625A1 (fr) Convertisseur à virgule fixe et à virgule flottante, processeur, procédé, et support de stockage
US8751555B2 (en) Rounding unit for decimal floating-point division
US20160313976A1 (en) High performance division and root computation unit
JP2557190B2 (ja) 引き数簡約の最適化システム
US8788561B2 (en) Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit
CN107423026B (zh) 一种正余弦函数计算的实现方法及装置
CN108228136B (zh) 基于优化查找表法的对数函数计算的方法及装置
US20090172069A1 (en) Method and apparatus for integer division
US20080281890A1 (en) Fast correctly-rounding floating-point conversion
Murillo et al. A suite of division algorithms for posit arithmetic
CN102566965B (zh) 一种误差平坦的浮点数对数运算装置
CN107015783B (zh) 一种浮点角度压缩实现方法及装置
CN117032625A (zh) 一种低延时的浮点平方根函数硬件实现方法
CN117932200A (zh) 一种浮点数平方根计算方法及浮点数计算模块
CN114201140B (zh) 指数函数处理单元、方法和神经网络芯片
CN114691082A (zh) 乘法器电路、芯片、电子设备及计算机可读存储介质
KR101922462B1 (ko) 데이터 처리장치 및 이진수에 대해 시프트 기능을 수행하는 방법
CN1936830A (zh) 小数取幂的数字实现
CN112416296A (zh) 一种用于计算反正切函数的实现方法及装置
CN112667197A (zh) 一种基于posit浮点数格式的参数化加减法运算电路
US7899859B2 (en) Efficient error-check and exact-check for Newton-Raphson divide and square-root operations
US20040254973A1 (en) Rounding mode insensitive method and apparatus for integer rounding
CN113721885B (zh) 一种基于cordic算法的除法器
JPH086766A (ja) 正弦余弦演算装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21831551

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21831551

Country of ref document: EP

Kind code of ref document: A1