WO2022001069A1 - 防止电池组装带电操作电路 - Google Patents

防止电池组装带电操作电路 Download PDF

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Publication number
WO2022001069A1
WO2022001069A1 PCT/CN2020/141875 CN2020141875W WO2022001069A1 WO 2022001069 A1 WO2022001069 A1 WO 2022001069A1 CN 2020141875 W CN2020141875 W CN 2020141875W WO 2022001069 A1 WO2022001069 A1 WO 2022001069A1
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Prior art keywords
field effect
effect transistor
port
battery
circuit
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PCT/CN2020/141875
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English (en)
French (fr)
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姜波
周培杰
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上海创功通讯技术有限公司
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Publication of WO2022001069A1 publication Critical patent/WO2022001069A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0069—Charging or discharging for charge maintenance, battery initiation or rejuvenation

Definitions

  • the present application relates to the technical field of live assembly of electronic equipment, and in particular, to a live operation circuit for preventing battery assembly.
  • the purpose of the present application is to provide a live operation circuit for preventing battery assembly.
  • the battery needs to be activated logic to be electrically connected to the charging chip, so as to avoid the subsequent assembly being live assembly because the battery is connected to the circuit, that is, it is automatically electrically connected to the charging chip.
  • the motherboard is damaged due to live assembly, which effectively improves the yield and reduces the workload and difficulty of subsequent inspections.
  • the present application discloses a live operation circuit for preventing battery assembly, which includes a charging chip and a control circuit, wherein the charging chip includes a charging port, a power port and an activation port for connecting to an activation device.
  • the port is connected to the positive pole of the battery, the negative pole of the battery is grounded, the control circuit includes a switch circuit and a logic circuit, the switch circuit is connected in series between the positive pole of the battery and the charging port, and the logic circuit includes a logic circuit an input port and a trigger port, the logic input port is connected to the power port, the trigger port is connected to the switch circuit, and when the activation device is connected to the activation port, the activation device provides an activation signal to the a charging chip, the charging chip outputs a control signal to the logic circuit according to the activation signal, and the logic circuit controls the switch circuit to conduct according to the control signal, so that the charging chip can charge the battery ; After the switch circuit is turned on and the activation device is disconnected from the activation port, the charging chip keeps charging the battery.
  • the switch circuit of the present application is connected in series between the positive electrode of the battery and the charging port of the charging chip.
  • the logic circuit controls the on-off of the switch circuit according to whether the activation device is connected to the activation port.
  • the switch circuit conducts It enables the charging chip to charge the battery, and when the switch circuit is turned on and the activation device disconnects the electrical connection with the activation port, the charging chip keeps charging the battery. Only by activating the device can the charging chip charge the battery, avoid the battery being connected to the circuit, that is, it is directly electrically connected to the charging chip, avoid the subsequent assembly being a live assembly due to the direct electrical connection of the battery to the charging chip, and avoid damage to the motherboard due to live assembly.
  • the electrical connection between the battery and the charging chip is activated by means of the activation device, and after the battery and the charging chip are electrically connected, the activation device disconnects the electrical connection with the activation port, and the battery is connected to the charging chip.
  • the charging chip can maintain the electrical connection, so that the activation device does not need to be retained after the electrical connection between the activated battery and the charging chip, which effectively reduces the number of components and the production cost.
  • the switch circuit includes a switch field effect transistor, the switch field effect transistor is an N-channel enhancement type field effect transistor, the source electrode of the switch field effect transistor is connected to the positive electrode of the battery, and the drain electrode is connected to the positive electrode of the battery. connected to the charging port, and the gate is connected to the trigger port.
  • the logic circuit further includes a first comparator, a second comparator and an AND gate unit, the negative input terminal of the first comparator is connected to the positive pole of the battery, and the output terminal is connected to the AND gate
  • the first input terminal of the unit, the negative input terminal of the second comparator is connected to the power supply port, the output terminal is connected to the second input terminal of the AND gate unit, the positive poles of the first comparator and the second comparator are connected
  • the input terminals are respectively connected to a reference level
  • the output terminal of the AND gate unit is connected to the switch circuit, and when the activation device is connected to the activation port, the first comparator and the second comparator output high respectively level to the AND gate unit, and the AND gate unit controls the switch circuit to be turned on.
  • the logic circuit further includes a first field effect transistor, a second field effect transistor, a first resistor and a second resistor
  • the first field effect transistor is an N-channel enhancement type field effect transistor
  • the second field effect transistor is a P-channel enhancement type field effect transistor
  • the source electrode of the first field effect transistor is grounded, and the drain electrode is connected to the drain electrode of the second field effect transistor.
  • the source is connected to the pull-up voltage through the first resistor, and the gates of the first field effect transistor and the second field effect transistor are respectively connected to the output end of the first comparator, and are connected together through the second resistor.
  • Pull-up voltage, the first input terminal of the AND gate unit is connected between the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor.
  • the logic circuit further includes a third field effect transistor, a fourth field effect transistor and a third resistor, the fourth field effect transistor is an N-channel enhancement type field effect transistor, and the third field effect transistor is an N-channel enhancement type field effect transistor.
  • the effect transistor is a P-channel enhancement type field effect transistor, the source electrode of the fourth field effect transistor is grounded, the drain electrode is connected to the drain electrode of the third field effect transistor, and the source electrode of the third field effect transistor passes through the
  • the first resistor is connected to the pull-up voltage
  • the gates of the fourth and third field-effect transistors are respectively connected to the output end of the second comparator, and are jointly connected to the pull-up voltage through the third resistor
  • the second input terminal of the AND gate unit is connected between the drain electrode of the fourth field effect transistor and the drain electrode of the third field effect transistor.
  • the logic circuit further includes a fifth field effect transistor and a sixth field effect transistor
  • the fifth field effect transistor is a P-channel enhancement type field effect transistor
  • the sixth field effect transistor is an N-type field effect transistor channel enhancement type field effect transistor
  • the source electrode of the fifth field effect transistor is connected to the positive electrode of the battery
  • the drain electrode is connected to the drain electrode of the sixth field effect transistor
  • the source electrode of the sixth field effect transistor is grounded
  • the drain electrodes of the fifth field effect transistor and the sixth field effect transistor are connected to form the trigger port
  • the trigger port is connected to the gate of the switch field effect transistor
  • the fifth field effect transistor and the sixth field effect transistor are connected.
  • the gates of the six field effect transistors are connected to each other, and the output end of the AND gate unit is connected to the gates of the fifth field effect transistor and the sixth field effect transistor.
  • the activation port is a USB interface
  • the activation device is a USB plug.
  • the switch circuit further includes a first diode, the anode of the first diode is connected to the charging port, and the cathode is connected to the anode of the battery.
  • the charging chip further includes a second diode, the anode of the second diode is connected to the activation port, and the cathode is connected to the power port.
  • the charging chip further includes a power supply port for external power supply.
  • FIG. 1 is a circuit diagram of a battery assembly prevention live operation circuit of the present application.
  • FIG. 2 is a circuit diagram when the activation device is connected to the activation port of the circuit diagram of the circuit diagram for preventing the battery assembly live operation circuit of the present application.
  • the operation circuit 100 for preventing battery assembly from being electrified in this embodiment includes a charging chip 10 and a control circuit 20 .
  • the activation port 13 and the power supply port 14 for external power supply, the charging port 11 is connected to the positive electrode of the battery 200, and the negative electrode of the battery 200 is grounded to GND.
  • the activation device 300 here is, for example, a USB plug, and correspondingly, the activation port 13 is, for example, a USB interface. The USB plug is inserted into the USB port to complete the activation operation.
  • the control circuit 20 includes a switch circuit 21 and a logic circuit 22 .
  • the switch circuit 21 is connected in series between the positive electrode of the battery 200 and the charging port 11 .
  • the logic circuit 22 includes a logic input port 221 and a trigger port 222 .
  • the logic input port 221 is connected to the power port 12
  • the trigger port 222 is connected to the switch circuit 21 .
  • the activation device 300 When the activation device 300 is connected to the activation port 13, the activation device 300 provides an activation signal to the charging chip, the charging chip 10 outputs a control signal to the logic circuit 22 according to the activation signal, and the logic circuit 22 controls the switch circuit 21 to conduct according to the control signal, For the charging chip 10 to charge the battery 200 ; after the switch circuit 21 is turned on and the activation device 300 is disconnected from the activation port 13 , the charging chip 10 keeps charging the battery 200 .
  • the activation signal here can be an activation voltage or an activation current, and the charging chip 10 generates and outputs a control signal to the logic circuit 22 according to the activation voltage or activation current to control the switch circuit 21 .
  • the switch circuit 21 includes a switch field effect transistor Q0 that is a P-channel enhancement type field effect transistor.
  • the source electrode of the switch field effect transistor Q0 is connected to the positive electrode of the battery 200 , the drain electrode is connected to the charging port 11 , and the gate electrode is connected to the battery 200 .
  • the sending port 222 adopts the switch field effect transistor Q0 as the switch, which has low cost and simple implementation.
  • the switch circuit 21 can also be a software switch or other hardware switch with a trigger port 222 .
  • the live operation circuit 100 for preventing battery assembly has reserved a card position for the battery 200 to access the circuit.
  • the positive electrode of the battery 200 is electrically connected to the charging port 11, and the negative electrode is electrically connected to the ground.
  • the battery 200 can also be connected to the circuit by welding, but directly welding the battery 200 to the circuit is inconvenient for subsequent repair and maintenance of the circuit.
  • the logic circuit 22 of this embodiment further includes a first comparator 223 , a second comparator 224 and an AND gate unit 225 , and the negative input terminal of the first comparator 223 is connected to the positive electrode of the battery 200
  • the output terminal of the first comparator 223 is connected to the first input terminal 2251 of the AND gate unit 225, and the negative input terminal of the second comparator 224 is connected to the power port 12 to detect whether the activation device 300 is connected.
  • Port 13 is activated, the output terminal of the second comparator 224 is connected to the second input terminal 2252 of the AND gate unit 225, the positive input terminals of the first comparator 223 and the second comparator 224 are respectively connected to a reference level vref, and the AND gate unit The output terminal of 225 is connected to the switch circuit 21.
  • the voltage of the negative input terminal of the first comparator 223 is higher than the reference level vref, and the first comparator 223 is inverted to output an inverted signal to the AND gate unit 225;
  • the activation device 300 is connected to the activation port 13
  • the voltage of the negative input terminal of the second comparator 224 is higher than the reference level vref
  • the second comparator 224 inverts and outputs an inversion signal to the AND gate unit 225
  • the AND gate unit 225 is only in the
  • the switch circuit 21 is controlled to be turned on only when the voltage of the negative input terminal of the first comparator 223 and the voltage of the negative input terminal of the second comparator 224 are both higher than the reference level vref. That is to say, the core significance of the circuit structure is that the switch circuit 21 needs to be turned on to satisfy the requirements that the battery 200 is connected to the circuit and the activation device 300 is connected to the activation port 13 .
  • the logic circuit 22 further includes a first field effect transistor Q1, a second field effect transistor Q2, a first resistor R1 and a second resistor R2, and the first field effect transistor Q1 is an N-channel enhancement type field effect transistor,
  • the second field effect transistor Q2 is a P-channel enhancement type field effect transistor, the source electrode of the first field effect transistor Q1 is grounded, the drain electrode is connected to the drain electrode of the second field effect transistor Q2, and the source electrode of the second field effect transistor Q2 passes through
  • the first resistor R1 is connected to the pull-up voltage VCC, the gates of the first field effect transistor Q1 and the second field effect transistor Q2 are respectively connected to the output end of the first comparator 223, and are jointly connected to the pull-up voltage VCC through the second resistor R2,
  • the first input terminal 2251 of the AND gate unit 225 is connected between the drain electrode of the first field effect transistor Q1 and the drain electrode of the second field effect transistor Q2. Under the cooperation of the first field effect transistor Q1 , the second field effect transistor Q2
  • the logic circuit 22 further includes a third field effect transistor Q3, a fourth field effect transistor Q4 and a third resistor R3, the fourth field effect transistor Q4 is an N-channel enhancement type field effect transistor, and the third field effect transistor Q3 is P-channel enhancement type field effect transistor, the source electrode of the fourth field effect transistor Q4 is grounded, the drain electrode is connected to the drain electrode of the third field effect transistor Q3, and the source electrode of the third field effect transistor Q3 is pulled up through the first resistor R1 voltage VCC, the gates of the fourth field effect transistor Q4 and the third field effect transistor Q3 are respectively connected to the output end of the second comparator 224, and are jointly connected to the pull-up voltage VCC through the third resistor R3, and the second gate of the AND gate unit 225
  • the input terminal 2252 is connected between the drain electrode of the fourth field effect transistor Q4 and the drain electrode of the third field effect transistor Q3. Under the cooperation of the third field effect transistor Q3 , the fourth field effect transistor Q4 , the first resistor R1 and the third resistor R3,
  • the logic circuit 22 further includes a fifth field effect transistor Q5 and a sixth field effect transistor Q6, the fifth field effect transistor Q5 is a P-channel enhancement type field effect transistor, and the sixth field effect transistor Q6 is an N-channel The enhancement mode field effect transistor, the source of the fifth field effect transistor Q5 is connected to the positive electrode of the battery 200, the drain electrode is connected to the drain electrode of the sixth field effect transistor Q6, the source electrode of the sixth field effect transistor Q6 is grounded, and the fifth field effect transistor is connected to the ground.
  • the trigger port 222 is connected to the gate of the switch field effect transistor Q0, and the gate of the fifth field effect transistor Q5 and the sixth field effect transistor Q6 are connected , the output terminal of the AND gate unit 225 is connected to the gates of the fifth field effect transistor Q5 and the sixth field effect transistor Q6.
  • the switch circuit 21 further includes a first diode D1 , and the anode of the first diode D1 is connected to the charging port 11 , the negative electrode is connected to the positive electrode of the battery 200 .
  • the charging chip further includes a second diode D2, the anode of the second diode D2 is connected to the activation port 13, and the cathode is connected to the power port 12.
  • the battery 200 is not buckled into the card position.
  • the switch circuit 21 is in a disconnected state and the charging chip 10 is not charged, so as to prevent the battery assembly from being charged and the operation circuit 100 is not charged;
  • the battery 200 is buckled into the card position, and the switch circuit 21 is in a disconnected state at this time and the charging chip 10 is not charged, preventing the battery assembly from being charged with the charged operating circuit 100;
  • the activation device 300 is inserted into the activation port 13. At this time, the switch circuit 21 is in a conducting state and the charging chip 10 is connected to the battery 200 to prevent the battery assembly from electrifying the operation circuit 100;
  • the activation device 300 is pulled out after activating the circuit.
  • the switch circuit 21 is in an on state and the charging chip 10 is connected to the battery 200 to prevent the battery assembly live operation circuit 100 from being charged. Since the operation circuit 100 for preventing the battery assembly from being charged is charged at this time, the charging chip 10 in this state can charge the battery 200 , and the battery 200 can also supply power to an external system through the charging chip 10 . In one example, the battery 200 can pass the charging chip 10
  • the power supply port 14 provides external power to realize the power supply to the external system.
  • control circuit 20 of this embodiment is implemented by a hardware circuit constructed by electronic components, the circuit is simple, the construction cost is low, and it is easy to mass produce.
  • control circuit 20 may be implemented by a control chip, and its activation logic is implemented by programming, which will not be repeated here.
  • the switch circuit 21 of the present application is connected in series between the positive electrode of the battery 200 and the charging port 11 of the charging chip 10, and the logic circuit 22 controls the switching circuit 21 according to whether the activation device 300 is connected to the activation port 13 or not.
  • the switch circuit 21 On and off, when the activation device 300 is connected to the activation port 13, the switch circuit 21 is turned on so that the charging chip 10 can charge the battery 200, and when the switch circuit 21 is turned on and the activation device 300 is disconnected from the activation port 13 When the battery 200 is electrically connected, the charging chip 10 keeps charging the battery 200.
  • the device 300 activates the electrical connection between the battery 200 and the charging chip 10, and after the battery 200 is electrically connected with the charging chip 10, the activation device 300 disconnects the electrical connection with the activation port 13, and the battery 200 and the charging chip 10 can maintain the electrical connection, so that the After the activation battery 200 is electrically connected with the charging chip 10, it is not necessary to retain the activation device 300, which effectively reduces the number of components and production costs.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

本申请公开了一种防止电池组装带电操作电路，其包括充电芯片和控制电路，充电端口接电池的正极，电池的负极接地，开关电路串接于电池的正极和充电端口之间，逻辑输入端口接电源端口，触发端口接开关电路，激活器件接入激活端口时，激活器件提供一激活信号至充电芯片，充电芯片输出一控制信号至逻辑电路，逻辑电路依据控制信号控制开关电路导通，以供充电芯片对电池充电；开关电路导通后且激活器件断开与激活端口的电连接时，充电芯片保持对电池充电。

Description

防止电池组装带电操作电路
相关申请的交叉引用
本申请基于申请号为202010616346.X、申请日为2020年6月30日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请涉及电子设备带电组装技术领域，尤其涉及一种防止电池组装带电操作电路。
背景技术
现有诸如手机、平板电脑和穿戴设备等电子产品一般会内置电池，而电池接入电子产品的系统后，会与充电芯片直接相连，而一旦接入电子产品的系统，整个系统处于带电状态，生产工人在进行电子产品的后续装配流程中即为带电组装，而带电组装容易对系统引入浪涌和/或负压冲击，导致主板损坏，严重者直接导致主板报废。且出现损坏的主板的出厂检测中不容易被发现，大大增加了检测工作量、工作难度及严重影响良品率。
因此，亟需一种防止电池组装带电操作电路来解决上述问题。
发明内容
本申请的目的是提供一种防止电池组装带电操作电路，其电池需要通过激活逻辑才能与充电芯片电连接，避免因电池接入电路即自动与充电芯片电连接而使后续组装为带电组装，避免因带电组装而导致主板损坏，有效提升良品率和降低后续检测工作量、工作难度。
为了实现上述目的，本申请公开了一种防止电池组装带电操作电路，其包 括充电芯片和控制电路，所述充电芯片包括充电端口、电源端口和用于接入激活器件的激活端口，所述充电端口接电池的正极，所述电池的负极接地，所述控制电路包括开关电路和逻辑电路，所述开关电路串接于所述电池的正极和所述充电端口之间，所述逻辑电路包括逻辑输入端口和触发端口，所述逻辑输入端口接所述电源端口，所述触发端口接所述开关电路，所述激活器件接入所述激活端口时，所述激活器件提供一激活信号至所述充电芯片，所述充电芯片依据所述激活信号输出一控制信号至所述逻辑电路，所述逻辑电路依据所述控制信号控制所述开关电路导通，以供所述充电芯片对所述电池充电；所述开关电路导通后且所述激活器件断开与所述激活端口的电连接时，所述充电芯片保持对所述电池充电。
本申请的开关电路串接于电池的正极和充电芯片的充电端口之间，逻辑电路根据激活器件是否接入激活端口以控制开关电路的通断，当激活器件接入激活端口时，开关电路导通以使充电芯片能够对电池进行充电操作，而当开关电路导通后且激活器件断开与激活端口的电连接时，充电芯片保持对电池充电，一方面，由于电池接入电路后需要通过激活器件才能使充电芯片对电池充电，避免电池接入电路即直接与充电芯片电连接，避免因电池直接电连接充电芯片而导致后续组装为带电组装，避免因带电组装而导致主板损坏，有效提升良品率和降低后续检测工作量、工作难度；另一方面，借助激活器件激活电池与充电芯片的电连接，且电池与充电芯片电连接后，激活器件断开与激活端口的电连接，电池与充电芯片能够保持电连接，使得激活电池与充电芯片的电连接后无需保留激活器件，有效降低元器件数量和生产成本。
在一个实施例中，所述开关电路包括开关场效应管，所述开关场效应管为N沟道增强型场效应晶体管，所述开关场效应管的源极接所述电池的正极，漏电极接所述充电端口，栅极接所述触发端口。
在一个实施例中，所述逻辑电路还包括第一比较器、第二比较器和与门单元，所述第一比较器的负极输入端接所述电池的正极，输出端接所述与门单元的第一输入端，所述第二比较器的负极输入端接所述电源端口，输出端接所述与门单元的第二输入端，所述第一比较器和第二比较器的正极输入端分别接一 参考电平，所述与门单元的输出端接所述开关电路，当所述激活器件接入所述激活端口时，所述第一比较器和第二比较器分别输出高电平至所述与门单元，所述与门单元控制所述开关电路导通。
在一个实施例中，所述逻辑电路还包括第一场效应管、第二场效应管、第一电阻和第二电阻，所述第一场效应管为N沟道增强型场效应晶体管，所述第二场效应管为P沟道增强型场效应晶体管，所述第一场效应管的源极接地，漏电极接所述第二场效应管的漏电极，所述第二场效应管的源极通过所述第一电阻接上拉电压，所述第一场效应管和第二场效应管的栅极分别接所述第一比较器的输出端，且共同通过所述第二电阻接上拉电压，所述与门单元的第一输入端接于所述第一场效应管的漏电极和第二场效应管的漏电极之间。
在一个实施例中，所述逻辑电路还包括第三场效应管、第四场效应管和第三电阻，所述第四场效应管为N沟道增强型场效应晶体管，所述第三场效应管为P沟道增强型场效应晶体管，所述第四场效应管的源极接地，漏电极接所述第三场效应管的漏电极，所述第三场效应管的源极通过所述第一电阻接上拉电压，所述第四场效应管和第三场效应管的栅极分别接所述第二比较器的输出端，且共同通过所述第三电阻接上拉电压，所述与门单元的第二输入端接于所述第四场效应管的漏电极和第三场效应管的漏电极之间。
在一个实施例中，所述逻辑电路还包括第五场效应管和第六场效应管，所述第五场效应管为P沟道增强型场效应晶体管，所述第六场效应管为N沟道增强型场效应晶体管，所述第五场效应管的源极接所述电池的正极，漏电极接所述第六场效应管的漏电极，所述第六场效应管的源极接地，所述第五场效应管和第六场效应管的漏电极相接并形成所述触发端口，所述触发端口接所述开关场效应管的栅极,所述第五场效应管和第六场效应管的栅极相接，所述与门单元的输出端接所述第五场效应管和第六场效应管的栅极。
在一个实施例中，所述激活端口为USB接口，所述激活器件为USB插头。
在一个实施例中，所述开关电路还包括第一二极管，所述第一二极管的正极接所述充电端口，负极接所述电池的正极。
在一个实施例中，所述充电芯片还包括第二二极管，所述第二二极管的正 极接所述激活端口，负极接所述电源端口。
在一个实施例中，所述充电芯片还包括用于对外供电的供电端口。
附图说明
图1是本申请的防止电池组装带电操作电路的电路图。
图2是激活器件接入本申请的防止电池组装带电操作电路的电路图的激活端口时的电路图。
具体实施方式
为详细说明本申请的技术内容、构造特征、所实现目的及效果，以下结合实施方式并配合附图详予说明。
请参阅图1和图2所示，本实施例的防止电池组装带电操作电路100包括充电芯片10和控制电路20，充电芯片10包括充电端口11、电源端口12、用于接入激活器件300的激活端口13和用于对外供电的供电端口14，充电端口11接电池200的正极，电池200的负极接地GND，这里的激活器件300例如为USB插头，对应的，激活端口13例如为USB接口，USB插头插入USB接口以完成激活操作。
控制电路20包括开关电路21和逻辑电路22，开关电路21串接于电池200的正极和充电端口11之间。逻辑电路22包括逻辑输入端口221和触发端口222，逻辑输入端口221接电源端口12，触发端口222接开关电路21。激活器件300接入激活端口13时，激活器件300提供一激活信号至充电芯片，充电芯片10依据该激活信号输出一控制信号至逻辑电路22，逻辑电路22依据控制信号控制开关电路21导通，以供充电芯片10对电池200充电；开关电路21导通后且激活器件300断开与激活端口13的电连接时，充电芯片10保持对电池200充电。这里的激活信号可以为一激活电压或一激活电流，充电芯片10依据激活电压或激活电流生成并输出控制信号至逻辑电路22，以实现对开关电路21的控制。
在一个示例中，开关电路21包括类型为P沟道增强型场效应晶体管的开关场效应管Q0，开关场效应管Q0的源极接电池200的正极，漏电极接充电端口11，栅极接触发端口222，采用开关场效应管Q0作为开关，其成本低，实现方式简单。当然，开关电路21还可以为软件开关或其他带有触发端口222的硬件开关。
本实施例中，防止电池组装带电操作电路100预留了供电池200接入电路的卡位，电池200扣入卡位时，电池200的正极即电连接充电端口11，负极即电连接地，以便于快捷组装电池200。当然，电池200还可以通过焊接的方式接入电路，但将电池200直接焊接于电路上，不便于后续对电路的维修、维护。
请参阅图1和图2所示，本实施例的逻辑电路22还包括第一比较器223、第二比较器224和与门单元225，第一比较器223的负极输入端接电池200的正极以检测电池200是否接入电路，第一比较器223的输出端接与门单元225的第一输入端2251，第二比较器224的负极输入端接电源端口12以检测激活器件300是否接入激活端口13，第二比较器224的输出端接与门单元225的第二输入端2252，第一比较器223和第二比较器224的正极输入端分别接一参考电平vref，与门单元225的输出端接开关电路21，电池200接入电路时，第一比较器223的负极输入端的电压高于参考电平vref，第一比较器223翻转而输出一翻转信号至与门单元225；激活器件300接入激活端口13时，第二比较器224的负极输入端的电压高于参考电平vref，第二比较器224翻转而输出一翻转信号至与门单元225，与门单元225仅在第一比较器223的负极输入端的电压和第二比较器224的负极输入端的电压均高于参考电平vref的情况下，才控制开关电路21导通。即该电路结构的核心意义在于，开关电路21导通需要同时满足：电池200接入电路及激活器件300接入激活端口13。
在一个示例中，逻辑电路22还包括第一场效应管Q1、第二场效应管Q2、第一电阻R1和第二电阻R2，第一场效应管Q1为N沟道增强型场效应晶体管，第二场效应管Q2为P沟道增强型场效应晶体管，第一场效应管Q1的源极接地，漏电极接第二场效应管Q2的漏电极，第二场效应管Q2的源极通过第一电阻R1接上拉电压VCC，第一场效应管Q1和第二场效应管Q2的栅极分别接第一 比较器223的输出端，且共同通过第二电阻R2接上拉电压VCC，与门单元225的第一输入端2251接于第一场效应管Q1的漏电极和第二场效应管Q2的漏电极之间。在第一场效应管Q1、第二场效应管Q2、第一电阻R1和第二电阻R2的配合下，第一比较器223的输出信号稳定的输送至与门单元225。
对应地，逻辑电路22还包括第三场效应管Q3、第四场效应管Q4和第三电阻R3，第四场效应管Q4为N沟道增强型场效应晶体管，第三场效应管Q3为P沟道增强型场效应晶体管，第四场效应管Q4的源极接地，漏电极接第三场效应管Q3的漏电极，第三场效应管Q3的源极通过第一电阻R1接上拉电压VCC，第四场效应管Q4和第三场效应管Q3的栅极分别接第二比较器224的输出端，且共同通过第三电阻R3接上拉电压VCC，与门单元225的第二输入端2252接于第四场效应管Q4的漏电极和第三场效应管Q3的漏电极之间。在第三场效应管Q3、第四场效应管Q4、第一电阻R1和第三电阻R3的配合下，第二比较器224的输出信号稳定的输送至与门单元225。
在一个示例中，逻辑电路22还包括第五场效应管Q5和第六场效应管Q6，第五场效应管Q5为P沟道增强型场效应晶体管，第六场效应管Q6为N沟道增强型场效应晶体管，第五场效应管Q5的源极接电池200的正极，漏电极接第六场效应管Q6的漏电极，第六场效应管Q6的源极接地，第五场效应管Q5和第六场效应管Q6的漏电极相接并形成触发端口222，触发端口222接开关场效应管Q0的栅极,第五场效应管Q5和第六场效应管Q6的栅极相接，与门单元225的输出端接第五场效应管Q5和第六场效应管Q6的栅极。
请参阅图1和图2所示，为了避免因电池200反向接入电路而损坏充电芯片10，开关电路21还包括第一二极管D1，第一二极管D1的正极接充电端口11，负极接电池200的正极。充电芯片还包括第二二极管D2，第二二极管D2的正极接激活端口13，负极接电源端口12。
下面对本实施例的防止电池组装带电操作电路100的工作过程进行说明：
1、电池200未扣入卡位，此时开关电路21处于断开状态且充电芯片10不带电，防止电池组装带电操作电路100不带电；
2、电池200扣入卡位，此时开关电路21处于断开状态且充电芯片10不带 电，防止电池组装带电操作电路100不带电；
3、激活器件300插入激活端口13，此时开关电路21处于导通状态且充电芯片10接入电池200，防止电池组装带电操作电路100带电；
4、激活器件300激活电路后再拔出，此时开关电路21处于导通状态且充电芯片10接入电池200，防止电池组装带电操作电路100带电。由于此时的防止电池组装带电操作电路100带电，该状态下的充电芯片10可以对电池200充电，电池200也可以通过充电芯片10对外部系统供电，在一个示例中，电池200通过充电芯片10的供电端口14对外供电，以实现对外部系统的供电。
值得注意的是，本实施例的控制电路20为通过电子元器件搭建的硬件电路实施，其电路简单，搭建成本低，易于批量化生产。当然，在其他实施方式中，控制电路20可以通过控制芯片实现，其激活逻辑通过编程实现，在此不做赘述。
结合图1和图2，本申请的开关电路21串接于电池200的正极和充电芯片10的充电端口11之间，逻辑电路22根据激活器件300是否接入激活端口13以控制开关电路21的通断，当激活器件300接入激活端口13时，开关电路21导通以使充电芯片10能够对电池200进行充电操作，而当开关电路21导通后且激活器件300断开与激活端口13的电连接时，充电芯片10保持对电池200充电，一方面，由于电池200接入电路后需要通过激活器件300才能使充电芯片10对电池200充电，避免电池200接入电路即直接与充电芯片10电连接，避免因电池200直接电连接充电芯片10而导致后续组装为带电组装，避免因带电组装而导致主板损坏，有效提升良品率和降低后续检测工作量、工作难度；另一方面，借助激活器件300激活电池200与充电芯片10的电连接，且电池200与充电芯片10电连接后，激活器件300断开与激活端口13的电连接，电池200与充电芯片10能够保持电连接，使得激活电池200与充电芯片10的电连接后无需保留激活器件300，有效降低元器件数量和生产成本。
以上所揭露的仅为本申请的优选实施例而已，当然不能以此来限定本申请之权利范围，因此依本申请申请专利范围所作的等同变化，仍属本申请所涵盖的范围。

Claims (10)

  1. 一种防止电池组装带电操作电路，包括充电芯片和控制电路，其中，所述充电芯片包括充电端口、电源端口和用于接入激活器件的激活端口，所述充电端口接电池的正极，所述电池的负极接地；所述控制电路包括开关电路和逻辑电路，所述开关电路串接于所述电池的正极和所述充电端口之间，所述逻辑电路包括逻辑输入端口和触发端口，所述逻辑输入端口接所述电源端口，所述触发端口接所述开关电路，所述激活器件接入所述激活端口时，所述激活器件提供一激活信号至所述充电芯片，所述充电芯片输出一控制信号至所述逻辑电路，所述逻辑电路依据所述控制信号控制所述开关电路导通，以供所述充电芯片对所述电池充电；所述开关电路导通后且所述激活器件断开与所述激活端口的电连接时，所述充电芯片保持对所述电池充电。
  2. 如权利要求1所述的防止电池组装带电操作电路，其中，所述开关电路包括开关场效应管，所述开关场效应管为P沟道增强型场效应晶体管，所述开关场效应管的源极接所述电池的正极，漏电极接所述充电端口，栅极接所述触发端口。
  3. 如权利要求2所述的防止电池组装带电操作电路，其中，所述逻辑电路还包括第一比较器、第二比较器和与门单元，所述第一比较器的负极输入端接所述电池的正极，输出端接所述与门单元的第一输入端，所述第二比较器的负极输入端接所述电源端口，输出端接所述与门单元的第二输入端，所述与门单元的输出端接所述开关电路，当所述激活器件接入所述激活端口时，所述第一比较器和第二比较器分别输出高电平至所述与门单元，所述与门单元控制所述开关电路导通。
  4. 如权利要求3所述的防止电池组装带电操作电路，其中，所述逻辑电路还包括第一场效应管、第二场效应管、第一电阻和第二电阻，所述第一场效应管为N沟道增强型场效应晶体管，所述第二场效应管为P沟道增强型场效应晶体管，所述第一场效应管的源极接地，漏电极接所述第二场效应管的漏电极，所述第二场效应管的源极通过所述第一电阻接上拉电压，所述第一场效应管和第二场效应管的栅极分别接所述第一比较器的输出端，且共同通过所述第二电阻接上拉电压，所述与门单元的第一输入端接于所述第一场效应管的漏电极和第二场效应管的漏电极之间。
  5. 如权利要求4所述的防止电池组装带电操作电路，其中，所述逻辑电路还包括第三场效应管、第四场效应管和第三电阻，所述第四场效应管为N沟道增强型场效应晶体管，所述第三场效应管为P沟道增强型场效应晶体管，所述第四场效应管的源极接地，漏电极接所述第三场效应管的漏电极，所述第三场效应管的源极通过所述第一电阻接上拉电压，所述第四场效应管和第三场效应管的栅极分别接所述第二比较器的输出端，且共同通过所述第三电阻接上拉电压，所述与门单元的第二输入端接于所述第四场效应管的漏电极和第三场效应管的漏电极之间。
  6. 如权利要求5所述的防止电池组装带电操作电路，其中，所述逻辑电路还包括第五场效应管和第六场效应管，所述第五场效应管为P沟道增强型场效应晶体管，所述第六场效应管为N沟道增强型场效应晶体管，所述第五场效应管的源极接所述电池的正极，漏电极接所述第六场效应管的漏电极，所述第六场效应管的源极接地，所述第五场效应管和第六场效应管的漏电极相接并形成所述触发端口，所述触发端口接所述开关场效应管的栅极,所述第五场效应管和第六场效应管的栅极相接，所述与门单元的输出端接所述第五场效应管和第六场效应管的栅极。
  7. 如权利要求1所述的防止电池组装带电操作电路，其中，所述激活端口为USB接口，所述激活器件为USB插头。
  8. 如权利要求1所述的防止电池组装带电操作电路，其中，所述开关电路还包括第一二极管，所述第一二极管的正极接所述充电端口，负极接所述电池的正极。
  9. 如权利要求1所述的防止电池组装带电操作电路，其中，所述充电芯片还包括第二二极管，所述第二二极管的正极接所述激活端口，负极接所述电源端口。
  10. 如权利要求1所述的防止电池组装带电操作电路，其中，所述充电芯片还包括用于对外供电的供电端口。
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