WO2022000349A1 - 图像传感器及其制作方法、搭载图像传感器的成像装置 - Google Patents

图像传感器及其制作方法、搭载图像传感器的成像装置 Download PDF

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Publication number
WO2022000349A1
WO2022000349A1 PCT/CN2020/099595 CN2020099595W WO2022000349A1 WO 2022000349 A1 WO2022000349 A1 WO 2022000349A1 CN 2020099595 W CN2020099595 W CN 2020099595W WO 2022000349 A1 WO2022000349 A1 WO 2022000349A1
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trench
image sensor
region
doped region
conductivity type
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PCT/CN2020/099595
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English (en)
French (fr)
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徐泽
肖�琳
周雪梅
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2020/099595 priority Critical patent/WO2022000349A1/zh
Priority to CN202080006505.2A priority patent/CN113169204A/zh
Publication of WO2022000349A1 publication Critical patent/WO2022000349A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Definitions

  • the present application relates to the technical field of image sensors, and in particular, to an image sensor, a manufacturing method thereof, and an imaging device equipped with an image sensor.
  • Image sensors are widely used in consumer electronics, security monitoring, industrial automation, artificial intelligence, Internet of Things and other fields. They are used to collect and organize image data information and provide information sources for subsequent processing and applications.
  • the image sensor can be divided into a photosensitive circuit area and a peripheral reading circuit area according to its functional composition.
  • the function of the photosensitive circuit area is to convert the optical signal into an electrical signal through the photodiode and store it, and then hand it over to the subsequent peripheral readout circuit for conversion into a digital image signal.
  • the lighting conditions in the environment are very complex, some are very dark, some are very bright, that is, in some environments, the contrast between light and dark is very strong, so the image sensor needs to increase the details of the dark area of the image clearly.
  • Exposure time to increase the amount of signal in the dark.
  • the exposure time cannot be changed with the brightness of different spatial areas.
  • the brighter areas in the image will be overexposed, showing a dead white, so the image
  • the dynamic range (DR) of the sensor is insufficient.
  • the present application provides an image sensor, a manufacturing method thereof, and an imaging device equipped with the image sensor.
  • the present application provides an image sensor, the image sensor comprising:
  • the photosensitive region located on the semiconductor substrate, the photosensitive region can generate photo-generated carriers under illumination;
  • the readout circuit is connected to the photosensitive region for reading out the voltage signal generated by the photo-generated carriers;
  • the photosensitive region includes a first doped region of a first conductivity type and a second doped region of a second conductivity type, the first doped region is disposed close to the first surface, the second doped region The doped region is disposed on a side of the first doped region away from the first surface; a trench extending toward the first surface is formed in the second doped region, and a groove wall of the trench is formed A semiconductor layer having a first conductivity type.
  • the present application provides an imaging device equipped with any of the above-mentioned image sensors.
  • the present application provides a method for fabricating an image sensor, the method comprising:
  • a photosensitive region is formed on the semiconductor substrate, the photosensitive region includes a first doped region of a first conductivity type and a second doped region of a second conductivity type, the first doped region is disposed close to the the first surface, the second doped region is disposed on a side of the first doped region away from the first surface;
  • a semiconductor layer having a first conductivity type is formed on the groove wall of the trench.
  • Embodiments of the present application provide an image sensor and a manufacturing method thereof, and an imaging device equipped with the image sensor, which can improve the imaging effect.
  • FIG. 1 is a schematic structural diagram of an image sensor provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of the functional composition of an image sensor in an embodiment
  • FIG. 3 is a schematic diagram of a pixel in an image sensor in an embodiment
  • FIG. 4 is a timing diagram of pixel imaging in an image sensor in one embodiment
  • FIG. 5 is a schematic structural diagram of a groove on an image sensor in an embodiment
  • FIG. 6 is a schematic structural diagram of a groove on an image sensor in another embodiment
  • FIG. 7 is a schematic structural diagram of a groove on an image sensor in yet another embodiment
  • FIG. 8 is a schematic structural diagram of a groove on an image sensor in yet another embodiment
  • FIG. 9 is a schematic flowchart of a manufacturing method of an image sensor provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an imaging device according to an embodiment of the present application.
  • an imaging device 601, an image sensor; 602, a processor; 603, a display screen.
  • FIG. 1 is a schematic structural diagram of an image sensor 100 .
  • the image sensor 100 includes a semiconductor substrate 110 , a photosensitive region 120 and a readout circuit 130 .
  • the image sensor 200 can be divided into a photosensitive circuit area 210 and a peripheral circuit 220 according to functional composition, wherein the photosensitive circuit area 210 may include tens of thousands to hundreds of millions of photosensitive units 211 , such as photosensitive circuits
  • the area 210 may be formed by a large number of photosensitive units 211 in an array formed in a certain manner, that is, a so-called pixel array.
  • the peripheral circuit 220 is responsible for converting the signal induced by the photosensitive unit 211 into a digital signal and reading it out.
  • the photosensitive unit 211 of the image sensor 200 may also be referred to as a pixel.
  • the photosensitive unit 211 includes a photodiode 201 , a transfer transistor (TX) 202 , a floating diffusion (FD) 203 , a reset transistor (RST) 204 , and a source follower transistor (SF) 205 , Row strobe (SEL) 206 .
  • FIG. 4 a typical working sequence of the photosensitive unit 211 is shown in FIG. 4 .
  • the typical working process of the photosensitive unit 211 is as follows:
  • Reset stage the reset transistor 204 is turned on (ie, turned on), the row strobe tube 206 is turned off (ie, turned off), the transfer tube 202 is turned on (ie, turned on) first, and the photo-generated current in the photodiode 201 is emptied then the transfer tube 202 is closed (ie, disconnected);
  • Exposure stage the transfer tube 202 is maintained in an off state (ie, an off state), and the photodiode 201 generates photo-generated carriers under illumination;
  • the row strobe tube 206 is turned on, then the reset tube 204 is turned off, the floating diffusion region 203 is floated to a high potential, and the reference voltage Vref is read at the output end (PXD end) after stabilization (SHR stage)
  • the reference voltage Vref ie, the reference signal
  • the reference voltage Vref can be read by setting the read reference voltage enable signal of the peripheral circuit to a high level; then the transfer tube 202 is turned on, and the photo-generated carriers in the photodiode 201 are injected into the The floating diffusion region 203, the potential of the floating diffusion region 203 becomes lower as the photo-generated carriers enter.
  • the transfer tube 202 is turned off, and the sample and hold signal voltage Vsig (SHS stage) is read at the output end after stabilization. ), for example, the sample-and-hold signal voltage Vsig can be read by setting the read sample-and-hold signal voltage enable signal of the peripheral circuit to a high level.
  • the image sensor 200 may include the peripheral circuit 220 , or may not include the peripheral circuit 220 , for example, functions such as analog-to-digital conversion may be implemented by an additional peripheral circuit.
  • the image sensor 100 includes a semiconductor substrate 110 , a photosensitive region 120 and a readout circuit 130 .
  • the semiconductor substrate 110 has an opposite first surface 111 and a second surface 112, the photosensitive region 120 is located on the semiconductor substrate 110, the photosensitive region 120 generates photo-generated carriers under illumination, and the readout circuit 130 is connected to the photosensitive region 120, And it is used to read out the voltage signal generated by the photogenerated carriers.
  • the photosensitive region 120 may also be referred to as a photodiode.
  • the semiconductor substrate 110 may include at least one of a silicon substrate, a germanium substrate, and a silicon carbide substrate.
  • tens of thousands to hundreds of millions of photosensitive regions 120 are formed on the semiconductor substrate 110 . It is understood that an array of photosensitive regions 120 is formed on the semiconductor substrate 110 .
  • the readout circuit 130 includes a floating diffusion region 131 and a transfer tube 132 .
  • the floating diffusion region 131 is located on the side of the semiconductor substrate 110 close to the first surface 111, and the floating diffusion region 131 is used to receive photo-generated carriers; the transfer tube 132 can be controlled to connect or disconnect the photosensitive region 120 and the floating The diffusion region 131 is placed.
  • the transfer tube 132 is controlled to communicate with the photosensitive region 120 and the floating diffusion region 131 .
  • the control signal line of the transfer tube 132 receives a high level to make the transfer tube 132 conduct, so that the photosensitive region 120 and the floating diffusion region 131 are connected.
  • the floating diffusion region 131 is connected to the reset power supply through the conductive reset tube, and the photosensitive region 120 and the floating diffusion region 131 are reset under the action of the reset power supply, and the photo-generated carriers in the photosensitive region 120 are emptied, and then the transmission tube 132 is turned off;
  • the transfer tube 132 In the exposure stage, the transfer tube 132 is kept in a closed state, and the photosensitive region 120 generates photo-generated carriers under illumination; in the signal readout stage, the transfer tube 132 can be controlled to communicate with the photosensitive region 120 and the floating diffusion region 131, so that the photo-generated carriers in the photosensitive region 120 can be controlled.
  • Carriers are poured into the floating diffusion region 131 , and the potential of the floating diffusion region 131 decreases as the photogenerated carriers enter. After the photogenerated carriers are transmitted, the transfer tube 132 is closed.
  • the readout circuit 130 further includes a voltage output circuit 133 connected to the floating diffusion region 131 for transmitting the voltage signal of the floating diffusion region 131 to peripheral circuits.
  • the voltage output circuit 133 may include a source follower transistor (SF) and a row strobe transistor (SEL). It should be noted that the voltage output signal includes a sample and hold signal and a reference signal. Among them, the sample-and-hold signal is generated by photo-generated carriers.
  • the photosensitive region 120 includes a first doped region 121 of a first conductivity type and a second doped region 122 of a second conductivity type, and the first doped region 121 is disposed close to the first surface 111 .
  • the second doped region 122 is disposed on a side of the first doped region 121 away from the first surface 111 .
  • the first conductivity type may be P type, and the second conductivity type may be N type.
  • the first conductivity type may be N-type, and the second conductivity type may be P-type. The following will describe in detail that the first conductivity type is P-type and the second conductivity type is N-type.
  • the first doped region 121 may be referred to as a PIN
  • the second doped region 122 may be referred to as a PD
  • the photosensitive region 120 includes a p-i-n Photo-Diode (pin-PD).
  • the photosensitive region 120 includes an N-type doped ion implantation layer PD and a P-type doped ion implantation layer PIN.
  • the size of the full-well capacity (FWC) of the photosensitive region 120 essentially depends on the size of the PN junction capacitance between the PIN and the PD, but the area of the photosensitive region 120 is usually limited.
  • the full well capacity of 120 is limited by the junction area. Therefore, when the lighting conditions in the environment are very complex and the contrast between light and dark is very strong, the image sensor 100 needs to increase the exposure time in order to clearly present the details of the image in the dark. signal.
  • the dynamic range (DR) of the image sensor 100 appears to be insufficient.
  • the inventors of the present application have improved the image sensor 100 by increasing the junction capacitance between the second doped region 122 and the surrounding first conductive type semiconductor to increase the full well capacity of the photosensitive region 120 .
  • DR 20 ⁇ log(FWC ⁇ noise)
  • FWC the full well capacity of the photosensitive region 120
  • noise represents the read noise (Read Noise)
  • log() Representing a logarithmic operation
  • a trench 140 extending toward the first surface 111 is formed in the second doped region 122 , and a semiconductor layer 101 of the first conductivity type is formed on the trench wall 141 of the trench 140 .
  • a large-area PN junction interface is formed near the trench 140 , that is, the capacitance between the second doped region 122 and the surrounding first conductive type semiconductor is increased.
  • the second doped region 122 of the second conductivity type and the semiconductor layer 101 of the first conductivity type form a PN junction capacitance, so that the PN junction capacitance of the photosensitive region 120 includes the first doped region 121 and the second doped region
  • the capacitance between 122 and the capacitance between the second doped region 122 and the semiconductor layer 101 can improve the ability of the photosensitive region 120 to store charges, that is, improve the ability of the photosensitive region 120 to store carriers, and increase the maximum ability to store charges , that is, the full well capacity of the photosensitive region 120 is increased, and the full well capacity of the photogenerated carriers is not easily exceeded, which can prevent the photogenerated carriers from overflowing, so that more photogenerated carriers can be retained in the photosensitive region 120, preventing the Image details in bright areas are lost, improving the dynamic range of the image sensor 100 .
  • the trench walls 141 of the trenches 140 extend from the second surface 112 toward the first surface 111 , and the trench walls 141 extend at least partially into the interior of the second doped region 122 .
  • one or more trenches 140 may be etched on the backside of the second doped region 122 , that is, the second surface 112 , such as dry etching or wet etching, and these trenches 140 penetrate into the second doped region 122 internal.
  • the bottom 142 of the trench 140 is located inside the second doped region 122 .
  • the capacitance between the second doped region 122 and the semiconductor layer 101 can be increased.
  • the bottom 142 of the trench 140 may not be located inside the second doped region 122, for example, the bottom 142 of the trench 140 reaches the side of the second doped region 122 close to the second surface 112, or It is achieved to increase the full well capacity of the photosensitive region 120 by configuring the capacitance between the second doped region 122 and the semiconductor layer 101 .
  • trenches 140 have a depth of 0.5 to 5 microns.
  • the depth of the trench 140 can be determined according to the structure of the image sensor 100 , such as the thickness of the photosensitive region 120 , the thickness of the semiconductor substrate 110 , and the parameter requirements of the image sensor 100 , such as full well capacity and dynamic range.
  • the width of the trenches 140 ranges from 0.1 to 0.5 microns.
  • the trench can be determined according to the structure of the image sensor 100 (such as the width of the photosensitive region 120 ), the processing technology of the image sensor 100 (such as the processing accuracy of the etching process, etc.), and the parameter requirements of the image sensor 100 , such as full well capacity, dynamic range, etc.
  • the depth and the like of the grooves 140 determine the width of the grooves 140 . Exemplarily, when the length and number of trenches 140 are constant, the wider the trench 140 is, the larger the area of the semiconductor layer 101 on the trench wall 141 is, and the more the full well capacity of the photosensitive region 120 is improved.
  • the width of the slot 143 of the trench 140 is greater than or equal to the width of the bottom 142 of the trench 140 .
  • the groove wall 141 of the trench 140 may be slope-shaped, which facilitates the formation of the semiconductor layer 101 of the first conductivity type on the groove wall 141 and the groove bottom 142 , and facilitates the etching process of the trench 140 .
  • the width of the notch 143 is 0.5 micrometers, and the width of the groove bottom 142 is 0.2 micrometers; or the width of the notch 143 is 0.4 micrometers, and the width of the groove bottom 142 is 0.1 micrometers; of course, it is not limited thereto.
  • one or more trenches 140 are formed in the second doped region 122 of the photosensitive region 120 . As shown in FIG. 1 , FIG. 5 , and FIG. 6 , a plurality of trenches 140 are formed in the second doped region 122 , as shown in FIG. 7 , and a trench 140 is formed in the second doped region 122 , as shown in FIG. 8 As shown, two trenches 140 are formed in the second doped region 122 .
  • multiple channels 140 may be arranged in parallel.
  • the processing efficiency of the trenches 140 can be improved, for example, multiple parallel-arranged linear trenches 140 can be etched at the same time.
  • At least two grooves 140 are intersected. More trenches 140 may be formed in the photosensitive region 120 to increase the full well capacity of the photosensitive region 120 .
  • the groove 140 includes a straight groove, which can facilitate the processing of the groove 140 .
  • the trench 140 includes a spiral trench, and a longer trench 140 can be formed in the second doped region 122 to improve the full well capacity of the photosensitive region 120 .
  • the trench 140 includes an annular trench, for example, includes one or more annular trenches, and a trench 140 with a longer total length may be formed in the second doped region 122 to improve the photosensitive region 120 full well capacity.
  • the semiconductor layer 101 is a doped layer of the first conductivity type.
  • the semiconductor layer 101 includes a P-type doped semiconductor.
  • the P-type doped semiconductor may form a PN junction capacitor with the N-type second doped region 122 .
  • the semiconductor layer 101 includes an N-type doped semiconductor.
  • the N-type doped semiconductor can form a PN junction capacitor with the P-type second doped region 122 .
  • a doping treatment may be performed on the groove wall 141 of the trench 140 to form a doping layer having the first conductivity type.
  • the trench 140 is first etched from the second surface 112 to the inside of the second doped region 122, and then the trench wall 141 of the trench 140 is doped, such as ion implantation or thermal doping, to form the first conductive type of doped layer.
  • the trench 140 is filled with a negatively charged dielectric material 102 , wherein the dielectric material 102 induces a P-type semiconductor layer 101 on the trench wall 141 of the trench 140 .
  • trenches 140 are first etched from the second surface 112 to the inside of the second doped region 122 , and then the trenches 140 are filled with a negatively charged dielectric material 102 , such as silicon dioxide, aluminum oxide, and silicon dioxide. At least one of hafnium, tantalum oxide, and silicon nitride. It can be understood that the dielectric material 102 is silicon dioxide, aluminum oxide, hafnium dioxide, tantalum oxide, silicon nitride or a multi-layer mixture thereof.
  • the negatively charged dielectric material 102 can induce a high concentration of P-type hole accumulation layers on the surface of the trench 140 in the N-type second doped region 122 , that is, the P-type semiconductor layer 101 and the P-type semiconductor layer 101 A PN junction capacitance can be formed with the N-type second doped region 122 .
  • the dielectric material 102 is the dielectric material 102 whose absorption rate to visible light is less than the first value.
  • the first value may be determined according to the parameter requirements of the image sensor 100, such as the sensitivity to light. In one embodiment, the first value is five percent.
  • the dielectric material 102 needs to have a smaller absorption rate of visible light, and can transmit more visible light to ensure the photosensitive efficiency of the photosensitive region 120;
  • the absorption rate of visible light by the dielectric material 102 may be slightly larger, so as to appropriately reduce the photosensitive efficiency of the photosensitive region 120 and prevent overexposure.
  • a trench is formed in the photosensitive area of the image sensor and a semiconductor layer is formed on the groove wall of the trench, so that a PN junction capacitance is formed between the semiconductor layer and the photosensitive area, so that the photosensitive area can be improved.
  • the ability of the region to store charges, that is, to increase the full well capacity of the photosensitive region, can keep more photo-generated carriers in the photosensitive region and improve the dynamic range of the image sensor.
  • FIG. 9 is a schematic flowchart of a manufacturing method of an image sensor provided by an embodiment of the present application.
  • the manufacturing method includes steps S110 to S150.
  • Step S110 providing a semiconductor substrate, the semiconductor substrate having an opposite first surface and a second surface;
  • Step S120 forming a photosensitive region on the semiconductor substrate, the photosensitive region includes a first doped region of a first conductivity type and a second doped region of a second conductivity type, the first doped region is close to the the first surface is disposed, and the second doping region is disposed on a side of the first doping region away from the first surface;
  • Step S130 forming a readout circuit on the semiconductor substrate, and the readout circuit is connected to the photosensitive region;
  • Step S140 forming a trench extending toward the first surface in the second doped region
  • Step S150 forming a semiconductor layer with a first conductivity type on the groove wall of the trench.
  • the forming a trench extending toward the first surface in the second doped region includes:
  • the trench is formed from the second surface toward the first surface, and the trench walls extend at least partially into the interior of the second doped region.
  • the bottom of the trench is located inside the second doped region.
  • the width of the notch of the groove is greater than or equal to the width of the groove bottom of the groove.
  • the width of the trenches ranges from 0.1 to 0.5 microns.
  • the depth of the trenches is 0.5 to 5 microns.
  • forming a trench in the second doped region extending toward the first surface includes:
  • One or more of the trenches are formed in the second doped region extending toward the first surface.
  • a plurality of the grooves are arranged in parallel or at least two of the grooves are arranged to intersect.
  • the grooves include at least one of linear grooves, spiral grooves, and annular grooves.
  • the first conductivity type is P-type and the second conductivity type is N-type.
  • the forming the semiconductor layer having the first conductivity type on the groove wall of the trench includes:
  • a negatively charged dielectric material is filled in the trench, so that the dielectric material induces a P-type semiconductor layer on the groove wall of the trench.
  • the dielectric material is a dielectric material whose absorbance to visible light is less than a specific value.
  • the trench is filled with at least one of silicon dioxide, aluminum oxide, hafnium dioxide, tantalum oxide, and silicon nitride.
  • the forming a semiconductor layer having the first conductivity type on the trench wall of the trench includes:
  • Doping treatment is performed on the groove wall of the trench to form a doped layer with the first conductivity type.
  • forming a readout circuit on the semiconductor substrate includes:
  • a transfer tube is formed between the photosensitive region and the floating diffusion region, and the transfer tube can controllably connect or disconnect the photosensitive region and the floating diffusion region.
  • a trench is formed in a photosensitive region of the image sensor and a semiconductor layer is formed on the groove wall of the trench, so that a PN junction capacitance is formed between the semiconductor layer and the photosensitive region, thereby
  • the ability to store charges in the photosensitive region can be improved, that is, the full well capacity of the photosensitive region can be increased, more photo-generated carriers can be retained in the photosensitive region, and the dynamic range of the image sensor can be improved.
  • FIG. 10 is a schematic block diagram of an imaging apparatus 600 provided by an embodiment of the present application.
  • This imaging device 600 is equipped with the aforementioned image sensor 601 .
  • the imaging device 600 may further include a processor 602 , where the processor 602 is configured to process the image data output by the image sensor 601 into a captured picture that can be presented on the display screen 603 .
  • the imaging device 600 may further include a display screen 603 , and the processor 602 is configured to process the image data output by the image sensor 601 into a shooting picture that can be presented on the display screen 603 .
  • the imaging device may be a terminal.
  • the terminal may be a terminal device integrated with a camera and a display screen, including but not limited to a smart phone, a tablet, a handheld computer, a camera, and the like.
  • the camera in the terminal can be used to realize the functions of taking pictures and video
  • the display screen can be used to realize the preview function of the shooting picture, that is, by displaying the picture currently collected by the camera in real time for preview, so as to achieve the viewfinder. Effect.

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Abstract

一种图像传感器，包括：半导体衬底，具有第一表面和第二表面；位于半导体衬底上的感光区；读出电路，连接感光区；其中，感光区包括第一掺杂区和第二掺杂区，第一掺杂区靠近第一表面设置，第二掺杂区中形成有朝向第一表面延伸的沟槽，沟槽的槽壁上具有半导体层。能够提高成像效果。还提供了图像传感器的制作方法和成像装置。

Description

图像传感器及其制作方法、搭载图像传感器的成像装置 技术领域
本申请涉及图像传感器技术领域，尤其涉及一种图像传感器及其制作方法、搭载图像传感器的成像装置。
背景技术
图像传感器广泛用于消费电子、安防监控、工业自动化、人工智能、物联网等领域，用于图像数据信息的采集和整理，为后续处理和应用提供信息源。
图像传感器按功能组成可以分为感光电路区和外围读取电路区。其中感光电路区的功能是负责把光信号，通过光电二极管转换成电信号并存储，然后交给后续外围读出电路用于转换成数字图像信号。
在实际应用中，环境中光照条件很复杂，有的很暗，有的很亮，即在某些环境下，明暗对比的十分强烈，因此图像传感器为了清晰的呈现图像暗处的细节，需要增加曝光时间，来增加暗处的信号量。但是，由于图像传感器整体的曝光时间是统一的，无法随不同空间区域的亮度改变曝光时间，当曝光时间较长时，图像中较亮的区域会产生过曝，呈现出一片死白，因此图像传感器的动态范围(Dynamic Range，DR)显得不足。
发明内容
基于此，本申请提供了一种图像传感器及其制作方法、搭载图像传感器的成像装置。
第一方面，本申请提供了一种图像传感器，所述图像传感器包括：
半导体衬底，所述半导体衬底具有相对的第一表面和第二表面；
位于所述半导体衬底上的感光区，所述感光区在光照下能够产生光生载流子；
读出电路，所述读出电路连接至所述感光区，用于读出由所述光生载流子 产生的电压信号；
其中，所述感光区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区，所述第一掺杂区被设置于靠近所述第一表面，所述第二掺杂区被设置于第一掺杂区远离所述第一表面的一侧；所述第二掺杂区中形成有朝向所述第一表面延伸的沟槽，所述沟槽的槽壁上具有第一导电类型的半导体层。
第二方面，本申请提供了一种成像装置，搭载任一上述的图像传感器。
第三方面，本申请提供了一种图像传感器的制作方法，所述方法包括：
提供半导体衬底，所述半导体衬底具有相对的第一表面和第二表面；
在所述半导体衬底上形成感光区，所述感光区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区，所述第一掺杂区被设置于靠近所述第一表面，所述第二掺杂区被设置于第一掺杂区远离所述第一表面的一侧；
在所述半导体衬底上形成读出电路，所述读出电路连接所述感光区；
在所述第二掺杂区中形成朝向所述第一表面延伸的沟槽；
在所述沟槽的槽壁上形成具有第一导电类型的半导体层。
本申请实施例提供了一种图像传感器及其制作方法、搭载图像传感器的成像装置，可提高成像效果。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本申请的公开内容。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例提供的一种图像传感器的结构示意图；
图2是一实施方式中图像传感器功能组成的结构示意图；
图3是一实施方式中图像传感器中像素的原理示意图；
图4是一实施方式中图像传感器中像素成像的时序示意图；
图5是一实施方式中图像传感器上沟槽的结构示意图；
图6是另一实施方式中图像传感器上沟槽的结构示意图；
图7是又一实施方式中图像传感器上沟槽的结构示意图；
图8是又一实施方式中图像传感器上沟槽的结构示意图；
图9是本申请一实施例提供的一种图像传感器的制作方法的流程示意图；
图10是本申请一实施例提供的一种成像装置的结构示意图。
附图标记：100、图像传感器；110、半导体衬底；111、第一表面；112、第二表面；120、感光区；121、第一掺杂区；122、第二掺杂区；130、读出电路；131、浮置扩散区；132、传输管；133、电压输出电路；140、沟槽；141、槽壁；142、槽底；143、槽口；101、半导体层；102、介质材料；
200、图像传感器；210、感光电路区；211、感光单元；201、光电二极管；202、传输管；203、浮置扩散区；204、复位管；205、源跟随管；206、行选通管；220、外围电路；
600、成像装置；601、图像传感器；602、处理器；603、显示屏。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
附图中所示的流程图仅是示例说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解、组合或部分合并，因此实际执行的顺序有可能根据实际情况改变。
下面结合附图，对本申请的一些实施方式作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
如图1所示为一种图像传感器100的结构示意图。图像传感器100包括半导体衬底110、感光区120和读出电路130。
在一些实施方式中，如图2所示，图像传感器200按功能组成可以分为感光电路区210和外围电路220，其中感光电路区210可以包括几万至几亿的感光单元211，例如感光电路区210可以由大量的感光单元211按一定的方式组 成阵列而成，即所谓的像素阵列。外围电路220则负责把感光单元211感生的信号转换成数字信号并读出。
图像传感器200的感光单元211又可称为像素(pixel)。在一些实施方式中，如图3所示，感光单元211包括光电二极管201、传输管(TX)202、浮置扩散区(FD)203、复位管(RST)204、源跟随管(SF)205、行选通管(SEL)206。
在一些实施方式中，感光单元211典型的工作时序如图4所示。
请参阅图3和图4，感光单元211典型工作过程如下：
a.复位阶段：复位管204打开(即，导通),行选通管206关闭(即，断开)，传输管202先打开(即，导通)，清空光电二极管201内的光生载流子，然后传输管202关闭(即，断开)；
b.曝光阶段：传输管202维持关闭状态(即，断开状态)，光电二极管201在光照下产生光生载流子；
c.信号读出阶段：行选通管206打开，然后复位管204关闭，浮置扩散区203被浮置为高电位，稳定后在输出端(PXD端)读取参考电压Vref(SHR阶段)，例如可以通过将外围电路的读参考电压使能信号置为高电平，而读取参考电压Vref(即，参考信号)；接着传输管202打开，光电二极管201内的光生载流子灌入浮置扩散区203，浮置扩散区203电位随着光生载流子进入变低，光生载流子传输完毕后，关闭传输管202，稳定后在输出端读取采样保持信号电压Vsig(SHS阶段)，例如可以通过将将外围电路的读采样保持信号电压使能信号置为高电平，而读取采样保持信号电压Vsig。
之后可以根据参考电压Vref和采样保持信号电压Vsig的差值ΔV＝Vref-Vsig，即为入射光信号引起的电压差，经过后续模拟-数字(AD)转换电路，即可转换成表征图像信息的数字信号。例如由外围电路220进行模拟-数字转换。
在一些实施方式中，图像传感器200可以包括外围电路220，当然也可以不包括外围电路220，例如可以通过额外搭载的外围电路实现模数转换等功能。
如图1所示，图像传感器100包括半导体衬底110、感光区120和读出电路130。
其中，半导体衬底110具有相对的第一表面111和第二表面112，感光区 120位于半导体衬底110上，感光区120在光照下产生光生载流子，读出电路130连接感光区120，且用于读出由光生载流子产生的电压信号。在一些实施方式中，感光区120又可称为光电二极管。
示例性的，半导体衬底110可以包括硅衬底、锗衬底、碳化硅衬底中的至少一种。
示例性的，半导体衬底110上形成几万至几亿的感光区120，可以理解的，在半导体衬底110上形成感光区120阵列。
在一些实施方式中，如图1所示，读出电路130包括浮置扩散区131和传输管132。
其中，浮置扩散区131位于半导体衬底110上靠近第一表面111的一侧，浮置扩散区131用于接收光生载流子；传输管132能够受控连通或断开感光区120和浮置扩散区131。
请参见图1，在复位阶段传输管132受控连通感光区120和浮置扩散区131。例如传输管132的控制信号线接收高电平以使传输管132导通，从而感光区120和浮置扩散区131连通。浮置扩散区131经导通的复位管连接复位电源，感光区120和浮置扩散区131在复位电源的作用下复位，清空感光区120内的光生载流子，然后传输管132关闭；在曝光阶段传输管132维持关闭状态，感光区120在光照下产生光生载流子；在信号读出阶段可以控制传输管132连通感光区120和浮置扩散区131，以使感光区120内的光生载流子灌入浮置扩散区131，浮置扩散区131电位随着光生载流子进入变低，光生载流子传输完毕后，关闭传输管132。
在一些实施方式中，如图1所示，读出电路130还包括电压输出电路133，电压输出电路133连接浮置扩散区131，用于将浮置扩散区131的电压信号传输至外围电路。示例性的，电压输出电路133可以包括源跟随管(SF)和行选通管(SEL)。需要说明的是，电压输出信号包括采样保持信号和参考信号。其中，采样保持信号由光生载流子产生。
如图1和图5所示，感光区120包括第一导电类型的第一掺杂区121和第二导电类型的第二掺杂区122，第一掺杂区121靠近第一表面111设置，第二掺杂区122设于第一掺杂区121远离第一表面111的一侧。
示例性的，第一导电类型可以为P型，则第二导电类型为N型。或者第一 导电类型可以为N型，则第二导电类型为P型。以下将以第一导电类型为P型，第二导电类型为N型进行详细介绍。
示例性的，第一掺杂区121可称为PIN，第二掺杂区122可称为PD。例如，感光区120包括p-i-n光电二极管(p-i-n Photo-Diode，pin-PD)。
示例性的，感光区120包括由N型掺杂的离子注入层PD和由P型掺杂的离子注入层PIN。
可以理解的，感光区120的满阱容量(Full-Well Capacity，FWC)的大小本质上取决于PIN与PD之间的PN结电容的大小，但是感光区120的面积通常是有限的，感光区120的满阱容量受到结面积的限制，因此当环境中光照条件很复杂，明暗对比的十分强烈时，图像传感器100为了清晰的呈现图像暗处的细节，需要增加曝光时间，来增加暗处的信号量。
但是，由于图像传感器100整体的曝光时间是统一的，无法随不同空间区域的亮度改变曝光时间，当曝光时间较长时，图像中较亮的区域会产生过曝，呈现出一片死白，因此图像传感器100的动态范围(Dynamic Range，DR)显得不足。
PIN/PD的结面积越大，PN结电容就越大，则感光区120的满阱容量越大。但是感光区120的面积通常是有限的，感光区120的满阱容量受到结面积的限制。针对该发现，本申请的发明人对图像传感器100进行了改进，通过提高第二掺杂区122与周围第一导电类型半导体之间的结电容以提高感光区120的满阱容量。
根据动态范围计算公式：DR＝20×log(FWC÷noise)，其中DR表示图像传感器100的动态范围，FWC表示感光区120的满阱容量，noise表示读出噪声(Read Noise)，log()表示对数运算，可以理解：通过提高感光区120的满阱容量可以提升图像传感器100的动态范围。
在一些实施方式中，第二掺杂区122中形成有朝向第一表面111延伸的沟槽140，沟槽140的槽壁141上具有第一导电类型的半导体层101。相比与一般光电二极管的PN结电容，在沟槽140附近形成了大面积的PN结界面，即增加了第二掺杂区122与周围第一导电类型半导体之间的电容。
可以理解的，第二导电类型的第二掺杂区122和第一导电类型的半导体层101形成PN结电容，从而感光区120的PN结电容包括第一掺杂区121和第二 掺杂区122之间的电容以及第二掺杂区122和半导体层101之间的电容，可以提升感光区120存储电荷的能力，即提升感光区120存储载流子的能力，增加最大能够存储电荷的能力，即提高了感光区120的满阱容量，光生载流子不容易超出的满阱容量，可以防止光生载流子溢出，从而可以将更多的光生载流子保留在感光区120内，防止亮处的图像细节丢失，提高图像传感器100的动态范围。
在一些实施方式中，沟槽140的槽壁141从第二表面112朝向第一表面111延伸，且槽壁141至少部分延伸到第二掺杂区122的内部。
示例性的，可以在第二掺杂区122的背面，即第二表面112刻蚀，如干刻或湿刻出一条或多条沟槽140，这些沟槽140贯穿进入第二掺杂区122的内部。例如，沟槽140的槽底142位于第二掺杂区122的内部。可以增大第二掺杂区122和半导体层101之间的电容。可以理解的，沟槽140的槽底142也可以不位于第二掺杂区122的内部，例如沟槽140的槽底142到达第二掺杂区122靠近第二表面112的一侧，也可以实现通过构造第二掺杂区122和半导体层101之间的电容提高感光区120的满阱容量。
示例性的，沟槽140的深度为0.5至5微米。可以根据图像传感器100的结构，如感光区120的厚度、半导体衬底110的厚度，以及图像传感器100的参数要求，如满阱容量、动态范围等确定沟槽140的深度。
示例性的，沟槽140的宽度的范围为0.1至0.5微米。可以根据图像传感器100的结构(如感光区120的宽度)、图像传感器100的加工工艺(如刻蚀工艺的加工精度等)以及图像传感器100的参数要求，如满阱容量、动态范围等确定沟槽140的深度等确定沟槽140的宽度。示例性的，沟槽140的长度和数目一定时，沟槽140的宽度越宽，则槽壁141上具有的半导体层101的面积越大，感光区120的满阱容量提升的也越多。
在一些实施方式中，如图1所示，沟槽140的槽口143的宽度大于等于沟槽140的槽底142的宽度。
示例性的，沟槽140的槽壁141可以为斜坡状，便于在槽壁141和槽底142上形成第一导电类型的半导体层101，而且可以便于沟槽140的刻蚀加工。
示例性的，槽口143的宽度为0.5微米，槽底142的宽度为0.2微米；或者槽口143的宽度为0.4微米，槽底142的宽度为0.1微米；当然并不限于此。
在一些实施方式中，感光区120的第二掺杂区122中形成有一道或多道沟槽140。如图1、图5、图6所示，第二掺杂区122中形成有多道沟槽140，如图7所示，第二掺杂区122中形成有一道沟槽140，如图8所示，第二掺杂区122中形成有两道沟槽140。
示例性的，如图1、图5、图6、图8所示，多道沟槽140可以平行排布。例如可以提高沟槽140加工的效率，例如可以同时刻蚀多道平行排布的直线型沟槽140。
示例性的，如图6所示，至少两道沟槽140相交设置。可以在感光区120中形成更多数目的沟槽140，提高感光区120的满阱容量。
示例性的，如图5和图6所示，沟槽140包括直线形沟槽，可以便于沟槽140加工。
示例性的，如图7所示，沟槽140包括螺旋形沟槽，可以第二掺杂区122中形成更大长度的沟槽140，提高感光区120的满阱容量。
示例性的，如图8所示，沟槽140包括环形沟槽，例如包括一个或多个环形沟槽，可以第二掺杂区122中形成总长度更长的沟槽140，提高感光区120的满阱容量。
在一些实施方式中，半导体层101为第一导电类型的掺杂层。例如半导体层101包括P型掺杂的半导体。P型掺杂的半导体可以和N型的第二掺杂区122形成PN结电容。或者，半导体层101包括N型掺杂的半导体。N型掺杂的半导体可以和P型的第二掺杂区122形成PN结电容。
示例性的，可以对沟槽140的槽壁141进行掺杂处理，形成具有第一导电类型的掺杂层。例如，先从第二表面112向第二掺杂区122内部刻蚀出沟槽140，然后对沟槽140的槽壁141进行掺杂处理，如进行离子注入或热掺杂以形成第一导电类型的掺杂层。
在一些实施方式中，沟槽140中填充带负电荷的介质材料102，其中，介质材料102在沟槽140的槽壁141上感生出P型的半导体层101。
示例性的，先从第二表面112向第二掺杂区122内部刻蚀出沟槽140，然后在沟槽140中填充带负电荷的介质材料102，如二氧化硅、氧化铝、二氧化铪、氧化钽、氮化硅中的至少一种。可以理解的，介质材料102为二氧化硅,氧化铝，二氧化铪，氧化钽，氮化硅或其多层混合物。
带负电荷的介质材料102能够在N型第二掺杂区122中的沟槽140的表面感生出高浓度的P型空穴积累层，即P型的半导体层101，P型的半导体层101可以和N型的第二掺杂区122形成PN结电容。
示例性的，介质材料102为对可见光的吸收率小于第一值的介质材料102。具体的，第一值可以根据图像传感器100的参数要求，如对光的敏感度等确定。在一个实施方式中，第一值为百分之五。例如，若期望图像传感器100应用于较暗的环境，则介质材料102为对可见光的吸收率需要更小，可以透过更多的可见光，以保证感光区120的感光效率；若期望图像传感器100应用于较亮的环境，则介质材料102对可见光的吸收率可以稍大，以适当降低感光区120的感光效率，防止产生过曝光。
本申请实施例提供的图像传感器，通过在图像传感器的感光区中形成沟槽并在沟槽的槽壁上形成半导体层，以使半导体层和感光区之间形成PN结电容，从而可以提升感光区存储电荷的能力，即提高感光区的满阱容量，可以将更多的光生载流子保留在感光区内，提高图像传感器的动态范围。
请结合上述实施例参阅图9，图9是本申请实施例提供的图像传感器的制作方法的流程示意图。
如图9所示，所述制作方法包括步骤S110至步骤S150。
步骤S110、提供半导体衬底，所述半导体衬底具有相对的第一表面和第二表面；
步骤S120、在所述半导体衬底上形成感光区，所述感光区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区，所述第一掺杂区靠近所述第一表面设置，所述第二掺杂区设于第一掺杂区远离所述第一表面的一侧；
步骤S130、在所述半导体衬底上形成读出电路，所述读出电路连接所述感光区；
步骤S140、在所述第二掺杂区中形成朝向所述第一表面延伸的沟槽；
步骤S150、在所述沟槽的槽壁上形成具有第一导电类型的半导体层。
在一些实施方式中，所述在所述第二掺杂区中形成朝向所述第一表面延伸的沟槽，包括：
从所述第二表面朝向所述第一表面形成所述沟槽，且所述槽壁至少部分延伸到所述第二掺杂区的内部。
示例性的，所述沟槽的槽底位于所述第二掺杂区的内部。
示例性的，所述沟槽的槽口的宽度大于等于所述沟槽的槽底的宽度。
在一些实施方式中，所述沟槽的宽度的范围为0.1至0.5微米。
在一些实施方式中，所述沟槽的深度为0.5至5微米。
在一些实施方式中，在所述第二掺杂区中形成朝向所述第一表面延伸的沟槽，包括：
在所述第二掺杂区中形成朝向所述第一表面延伸的一道或多道所述沟槽。
示例性的，多道所述沟槽平行排布或至少两道所述沟槽相交设置。
示例性的，所述沟槽包括直线形沟槽、螺旋形沟槽、环形沟槽中的至少一种。
在一些实施方式中，所述第一导电类型为P型，所述第二导电类型为N型。
示例性的，所述在所述沟槽的槽壁上形成具有第一导电类型的半导体层，包括：
在所述沟槽中填充带负电荷的介质材料，以使所述介质材料在所述沟槽的槽壁上感生出P型的半导体层。
示例性的，所述介质材料为对可见光的吸收率小于特定值的介质材料。
示例性的，所述沟槽中填充二氧化硅、氧化铝、二氧化铪、氧化钽、氮化硅中的至少一种。
在一些实施方式中，所述在所述沟槽的槽壁上形成具有第一导电类型的半导体层，包括：
对所述沟槽的槽壁进行掺杂处理，形成具有第一导电类型的掺杂层。
在一些实施方式中，所述在所述半导体衬底上形成读出电路，包括：
在所述半导体衬底上靠近所述第一表面的一侧形成浮置扩散区；
在所述感光区和所述浮置扩散区之间形成传输管，所述传输管能够受控连通或断开所述感光区和所述浮置扩散区。
本申请实施例提供的图像传感器的制作方法，通过在图像传感器的感光区中形成沟槽并在沟槽的槽壁上形成半导体层，以使半导体层和感光区之间形成PN结电容，从而可以提升感光区存储电荷的能力，即提高感光区的满阱容量，可以将更多的光生载流子保留在感光区内，提高图像传感器的动态范围。
请结合上述实施例参阅图10，图10是本申请一实施例提供的成像装置600 的示意性框图。该成像装置600搭载前述的图像传感器601。
在一些实施方式中，图10所示，成像装置600还可以包括处理器602，该处理器602用于将该图像传感器601输出的图像数据处理为可以呈现在显示屏603上的拍摄画面。
在一些实施方式中，图10所示，成像装置600还可以包括显示屏603，处理器602用于将图像传感器601输出的图像数据处理为可以呈现在显示屏603上的拍摄画面。
示例性的，该成像装置可以为终端。该终端可以是集成了摄像头和显示屏的终端设备，包括但不限于智能手机，平板，掌上电脑，照相机等。该终端中的摄像头可以用于实现拍照、摄像功能，而显示屏可以用于实现对拍摄画面的预览功能，即，通过对摄像头当前收入的画面进行实时显示，以供用于预览，从而达到取景器的效果。
本申请实施例提供的成像装置备的具体原理和实现方式均与前述实施例的图像传感器类似，此处不再赘述。
应当理解，在此本申请中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本申请。
还应当理解，在本申请和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (32)

  1. 一种图像传感器，其特征在于，所述图像传感器包括：
    半导体衬底，所述半导体衬底具有相对的第一表面和第二表面；
    位于所述半导体衬底上的感光区，所述感光区在光照下能够产生光生载流子；
    读出电路，所述读出电路连接至所述感光区，用于读出由所述光生载流子产生的电压信号；
    其中，所述感光区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区，所述第一掺杂区被设置于靠近所述第一表面，所述第二掺杂区被设置于第一掺杂区远离所述第一表面的一侧；所述第二掺杂区中形成有朝向所述第一表面延伸的沟槽，所述沟槽的槽壁上具有第一导电类型的半导体层。
  2. 根据权利要求1所述的图像传感器，其特征在于，所述沟槽的槽壁从所述第二表面朝向所述第一表面延伸，且所述槽壁至少部分延伸到所述第二掺杂区的内部。
  3. 根据权利要求1或2所述的图像传感器，其特征在于，所述沟槽的槽底位于所述第二掺杂区的内部。
  4. 根据权利要求1或2所述的图像传感器，其特征在于，所述沟槽的槽口的宽度大于等于所述沟槽的槽底的宽度。
  5. 根据权利要求1-4中任一项所述的图像传感器，其特征在于，所述沟槽的宽度的范围为0.1至0.5微米。
  6. 根据权利要求1-5中任一项所述的图像传感器，其特征在于，所述沟槽的深度为0.5至5微米。
  7. 根据权利要求1-6中任一项所述的图像传感器，其特征在于，所述感光区的第二掺杂区中形成有一道或多道所述沟槽。
  8. 根据权利要求7所述的图像传感器，其特征在于，多道所述沟槽平行排布或至少两道所述沟槽相交设置。
  9. 根据权利要求7所述的图像传感器，其特征在于，所述沟槽包括直线形沟槽、螺旋形沟槽、环形沟槽中的至少一种。
  10. 根据权利要求1-9中任一项所述的图像传感器，其特征在于，所述沟槽的槽壁上具有第一导电类型的半导体层；其中，所述第一导电类型为P型，所述第二导电类型为N型。
  11. 根据权利要求10所述的图像传感器，其特征在于，所述沟槽中填充带负电荷的介质材料，其中，所述介质材料在所述沟槽的槽壁上能够感生出P型的半导体层。
  12. 根据权利要求11所述的图像传感器，其特征在于，所述介质材料为对可见光的吸收率小于第一值的介质材料。
  13. 根据权利要求11所述的图像传感器，其特征在于，所述沟槽中填充二氧化硅、氧化铝、二氧化铪、氧化钽、氮化硅中的至少一种。
  14. 根据权利要求1-9中任一项所述的图像传感器，其特征在于，所述半导体层为第一导电类型的掺杂层。
  15. 根据权利要求1-14中任一项所述的图像传感器，其特征在于，所述读出电路包括：
    浮置扩散区，所述浮置扩散区位于所述半导体衬底上靠近所述第一表面的一侧，所述浮置扩散区用于接收所述光生载流子；
    传输管，能够受控连通或断开所述感光区和所述浮置扩散区。
  16. 根据权利要求15所述的图像传感器，其特征在于，所述读出电路还包括：
    电压输出电路，连接所述浮置扩散区，用于将所述浮置扩散区的电压信号传输至外围电路。
  17. 一种成像装置，其特征在于，搭载如权利要求1-16中任一项所述的图像传感器。
  18. 一种图像传感器的制作方法，其特征在于，所述方法包括：
    提供半导体衬底，所述半导体衬底具有相对的第一表面和第二表面；
    在所述半导体衬底上形成感光区，所述感光区包括第一导电类型的第一掺杂区和第二导电类型的第二掺杂区，所述第一掺杂区被设置于靠近所述第一表面，所述第二掺杂区被设置于第一掺杂区远离所述第一表面的一侧；
    在所述半导体衬底上形成读出电路，所述读出电路连接所述感光区；
    在所述第二掺杂区中形成朝向所述第一表面延伸的沟槽；
    在所述沟槽的槽壁上形成具有第一导电类型的半导体层。
  19. 根据权利要求18所述的方法，其特征在于，所述在所述第二掺杂区中形成朝向所述第一表面延伸的沟槽，包括：
    从所述第二表面朝向所述第一表面形成所述沟槽，且所述槽壁至少部分延伸到所述第二掺杂区的内部。
  20. 根据权利要求18或19所述的方法，其特征在于，所述沟槽的槽底位于所述第二掺杂区的内部。
  21. 根据权利要求18或19所述的方法，其特征在于，所述沟槽的槽口的宽度大于等于所述沟槽的槽底的宽度。
  22. 根据权利要求18-21中任一项所述的方法，其特征在于，所述沟槽的宽度的范围为0.1至0.5微米。
  23. 根据权利要求18-22中任一项所述的方法，其特征在于，所述沟槽的深度为0.5至5微米。
  24. 根据权利要求18-23中任一项所述的方法，其特征在于，在所述第二掺杂区中形成朝向所述第一表面延伸的沟槽，包括：
    在所述第二掺杂区中形成朝向所述第一表面延伸的一道或多道所述沟槽。
  25. 根据权利要求24所述的方法，其特征在于，多道所述沟槽平行排布或至少两道所述沟槽相交设置。
  26. 根据权利要求24所述的方法，其特征在于，所述沟槽包括直线形沟槽、螺旋形沟槽、环形沟槽中的至少一种。
  27. 根据权利要求18-26中任一项所述的方法，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型。
  28. 根据权利要求27所述的方法，其特征在于，所述在所述沟槽的槽壁上形成具有第一导电类型的半导体层，包括：
    在所述沟槽中填充带负电荷的介质材料，以使所述介质材料在所述沟槽的槽壁上感生出P型的半导体层。
  29. 根据权利要求28所述的方法，其特征在于，所述介质材料为对可见光的吸收率小于特定值的介质材料。
  30. 根据权利要求28所述的方法，其特征在于，所述沟槽中填充二氧化硅、氧化铝、二氧化铪、氧化钽、氮化硅中的至少一种。
  31. 根据权利要求18-26中任一项所述的方法，其特征在于，所述在所述沟槽的槽壁上形成具有第一导电类型的半导体层，包括：
    对所述沟槽的槽壁进行掺杂处理，形成具有第一导电类型的掺杂层。
  32. 根据权利要求18-31中任一项所述的方法，其特征在于，所述在所述半导体衬底上形成读出电路，包括：
    在所述半导体衬底上靠近所述第一表面的一侧形成浮置扩散区；
    在所述感光区和所述浮置扩散区之间形成传输管，所述传输管能够受控连通或断开所述感光区和所述浮置扩散区。
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