WO2022000282A1 - 阵列基板及其显示面板和显示装置 - Google Patents

阵列基板及其显示面板和显示装置 Download PDF

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Publication number
WO2022000282A1
WO2022000282A1 PCT/CN2020/099341 CN2020099341W WO2022000282A1 WO 2022000282 A1 WO2022000282 A1 WO 2022000282A1 CN 2020099341 W CN2020099341 W CN 2020099341W WO 2022000282 A1 WO2022000282 A1 WO 2022000282A1
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Prior art keywords
sub
reset
transistor
column
light
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PCT/CN2020/099341
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English (en)
French (fr)
Inventor
杨静
陈祯祐
赵爽
杨中流
陈文波
卢红婷
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20943643.5A priority Critical patent/EP4036903A4/en
Priority to US17/283,174 priority patent/US11893928B2/en
Priority to PCT/CN2020/099341 priority patent/WO2022000282A1/zh
Priority to CN202080001133.4A priority patent/CN114223026B/zh
Publication of WO2022000282A1 publication Critical patent/WO2022000282A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and in particular, to an array substrate, a display panel and a display device thereof.
  • OLED display panels have the advantages of self-luminescence, high efficiency, bright colors, light weight, power saving, rollability, and wide temperature range, and have been gradually applied to large-area displays, lighting, and automotive displays. and other fields.
  • Embodiments of the present disclosure provide array substrates and related display panels and display devices.
  • an array substrate including a substrate.
  • the array substrate further includes a pixel array disposed on the substrate, including a plurality of sub-pixels arranged in multiple rows and multiple columns.
  • Each sub-pixel has a pixel circuit and a data signal input terminal, a scan signal input terminal, and a drive reset control signal input terminal coupled to the pixel circuit.
  • the pixel circuit includes a data writing circuit, a driving circuit and a driving reset circuit.
  • the driving circuit includes a control terminal, a first terminal and a second terminal.
  • the data writing circuit is coupled to the data signal input terminal, the scan signal input terminal and the first terminal of the driving circuit, and is configured to provide the data signal to the first terminal of the driving circuit under the control of the scan signal.
  • the drive circuit is configured to provide drive current to the light emitting device.
  • the drive reset circuit is coupled to the drive reset control signal input end, the control end of the drive circuit and the reset voltage source, and is configured to reset the control end of the drive circuit under the control of the drive reset control signal.
  • the array substrate also includes a plurality of pairs of scanning signal lines. The plurality of pairs of scan signal lines extend in the row direction and are spaced apart from each other in the column direction. Each of the plurality of pairs of scan signal lines includes a first scan signal line and a second scan signal line. The m-th pair of scan signal lines corresponds to the m-th row of sub-pixels, where m is an integer greater than or equal to 1.
  • the first scan signal line of the mth pair of scan signal lines is configured to provide a first scan signal to the scan input terminal of the 2n-1th column of subpixels of the mth row of subpixels, where n is an integer greater than or equal to 1, and the mth pair
  • the second scan signal line of the scan signal lines is configured to provide the second scan signal to the scan signal input terminal of the 2nth column of the mth row of the sub-pixels.
  • the array substrate also includes a plurality of pairs of driving reset control signal lines. The many-to-many pairs of drive reset control signal lines extend in the row direction and are spaced apart from each other in the column direction.
  • Each of the plurality of pairs of drive reset control signal lines includes a first drive reset control signal line and a second drive reset control signal line.
  • the m-th pair of driving reset control signal lines corresponds to the m-th row of sub-pixels.
  • the first drive reset control signal line of the mth pair of drive reset control signal lines is configured to provide the first drive reset control signal to the drive reset control signal input terminal of the 2n-1th column of subpixels in the mth row of subpixels, and the mth drive reset control signal
  • the second drive reset control signal line to the drive reset control signal line is configured to supply the second drive reset control signal to the drive reset control signal input terminal of the 2nth column of subpixels of the mth row of subpixels.
  • the first scan signal line of the mth pair of scan signal lines and the second drive reset control signal line of the mth pair of drive reset control signal lines are the same signal line.
  • the data writing circuit may include a data writing transistor.
  • the drive reset circuit may include a drive reset transistor.
  • the first pole of the data writing transistor can be coupled with the data input terminal, the second pole of the data writing transistor can be coupled with the first terminal of the driving circuit, and the control pole of the data writing transistor can be connected with the scan signal terminal coupled.
  • the first pole of the driving reset transistor can be coupled with the control terminal of the driving circuit, the second pole of the driving reset transistor can be coupled with the reset voltage terminal, and the gate of the driving reset transistor can be coupled with the driving reset control signal input terminal catch.
  • the first scan signal line of the m-th pair of scan signal lines may include the gate of the data writing transistor of the sub-pixel in the 2n-1th column of the sub-pixel in the m-th row and the drive reset transistor of the sub-pixel in the 2n-th column of the sub-pixel in the m-th row. gate.
  • the pixel circuit may further include a compensation circuit, which may be coupled to the second terminal of the driving circuit, the control terminal of the driving circuit, and the scan signal input terminal, and is configured to compensate the driving circuit according to the scan signal. Perform threshold compensation.
  • a compensation circuit which may be coupled to the second terminal of the driving circuit, the control terminal of the driving circuit, and the scan signal input terminal, and is configured to compensate the driving circuit according to the scan signal. Perform threshold compensation.
  • the compensation circuit may include a compensation transistor.
  • the first electrode of the compensation transistor can be coupled with the second end of the driving circuit, the second electrode of the compensation transistor can be coupled with the control end of the driving circuit, and the gate of the compensation transistor can be coupled with the scan signal input end.
  • the first scan signal line of the m-th pair of scan signal lines may further include gates of the compensation transistors of the 2n-1-th column sub-pixels of the m-th row of sub-pixels.
  • the pixel circuit may further include a storage circuit.
  • the storage circuit may be coupled to the first voltage source and the control terminal of the driving circuit, and is configured to store a voltage difference between the first voltage source and the control terminal of the driving circuit.
  • the sub-pixel may further include a light-emitting control signal terminal.
  • the pixel circuit may also include a lighting control circuit.
  • the light-emitting control circuit may be coupled to the light-emitting control signal terminal, the first voltage terminal, the driving circuit and the light-emitting device, and is configured to apply a first voltage from a first voltage source to the driving circuit, and generate a driving current generated by the driving circuit applied to light-emitting devices.
  • the array substrate may further include a plurality of light emission control signal lines.
  • the plurality of light emission control signals extend in the column direction and are spaced apart from each other in the row direction.
  • the m-th light-emitting control signal line is configured to be coupled with the light-emitting control signal terminals of the sub-pixels in the m-th row to provide light-emitting control signals.
  • the sub-pixel may further include a light-emitting reset control signal input terminal.
  • the pixel circuit also includes a light-emitting reset circuit.
  • the light-emitting reset circuit is coupled to the light-emitting reset control signal input terminal, the reset voltage terminal and the light-emitting device, and is configured to reset the light-emitting device under the control of the light-emitting reset control signal.
  • the array substrate may further include multiple pairs of light-emitting reset control signal lines.
  • the plurality of pairs of light-emitting reset control signal lines extend in the row direction and are spaced apart from each other in the column direction.
  • Each of the plurality of pairs of light-emitting reset control signal lines includes a first light-emitting reset control signal line and a second light-emitting reset control signal line.
  • the m-th pair of light-emitting reset control signal lines corresponds to the m-th row of sub-pixels.
  • the first light-emission reset control value signal line of the m-th pair of light-emission reset control signal lines is configured to provide a first light-emission reset control signal to the light-emission reset control signal input terminal of the 2n-1th column of sub-pixels of the m-th row of sub-pixels, and the first light-emission reset control signal
  • the second light-emission reset control signal line of the m pair of light-emission reset control signal lines is configured to provide the second light-emission reset control signal to the light-emission reset control signal input terminal of the 2nth column of subpixels of the mth row of subpixels.
  • the first light-emitting reset control signal line of the m-th pair of light-emitting reset control signal lines and the first driving reset control signal line of the m+1-th pair of driving reset control signal lines may be the same signal line.
  • the second light-emitting reset control signal line of the m-th pair of light-emitting reset control signal lines and the second driving reset control signal line of the m+1-th pair of driving reset control signal lines may be the same signal line.
  • the array substrate may further include data signal lines extending in a column direction.
  • the data signal input terminal of each column of sub-pixels is connected to a corresponding data line to receive the data signal.
  • the array substrate may further include reset power signal lines extending in the column direction and configured to provide reset voltages to corresponding pixel circuits.
  • the compensation circuit may include a compensation transistor.
  • the light emission control circuit may include a first light emission control transistor and a second light emission control transistor.
  • the light emitting reset circuit may include a light emitting reset transistor.
  • the storage circuit may include a capacitor.
  • the first electrode of the driving transistor may be coupled with the first terminal of the driving circuit, the second electrode of the driving transistor may be coupled with the second terminal of the driving circuit, and the gate of the driving transistor may be coupled with the control terminal of the driving circuit catch.
  • the first electrode of the data writing transistor may be coupled with the data signal input terminal, the second electrode of the data writing transistor may be coupled with the first electrode of the driving transistor, and the gate of the data writing transistor may be coupled with the scan signal The input terminal is coupled.
  • the first electrode of the driving reset transistor may be coupled with the gate of the driving transistor, the second electrode of the driving reset transistor may be coupled with the reset voltage terminal, and the gate of the driving reset transistor may be coupled with the driving reset control signal input terminal catch.
  • the first electrode of the compensation transistor may be coupled with the second electrode of the driving transistor, the second electrode of the compensation transistor may be coupled with the gate of the driving transistor, and the gate of the compensation transistor may be coupled with the scan signal input terminal.
  • the first electrode of the first light-emitting control transistor may be coupled to the first voltage terminal, the second electrode of the first light-emitting control transistor may be coupled to the first electrode of the driving transistor, and the gate of the first light-emitting control transistor may be is coupled to the light-emitting control signal input terminal.
  • the first electrode of the second light-emitting control transistor may be coupled to the second electrode of the driving transistor, the second electrode of the second light-emitting control transistor may be coupled to the first electrode of the light-emitting device, and the gate of the second light-emitting control transistor
  • the pole can be coupled with the light-emitting control signal input terminal.
  • the first pole of the light-emitting reset transistor can be coupled to the first pole of the light-emitting device, the second pole of the light-emitting reset transistor can be coupled to the reset voltage terminal, and the gate of the light-emitting reset transistor can be connected to the light-emitting reset control signal input terminal coupled.
  • the first electrode of the capacitor may be coupled to the gate of the driving transistor, and the second electrode of the capacitor may be coupled to the first voltage terminal.
  • the array substrate may further include an active semiconductor layer on the substrate.
  • the active semiconductor layer may include active regions of transistors in the pixel circuit.
  • the active semiconductor layer of the 2n-1-th column of sub-pixels may include a first portion, a second portion and a third portion spaced apart from each other.
  • the first part and the second part are arranged in sequence in the row direction, and the combination of the first part and the second part and the third part are arranged in sequence in the column direction.
  • the first portion may include active regions of the drive reset transistors and the compensation transistors in the 2n-1th column of subpixels.
  • the second portion may include active regions of the data write transistors in the 2n-1 column of sub-pixels.
  • the third portion may include active regions of the drive transistor, the first light emission control transistor, the second light emission control transistor, and the light emission reset transistor in the 2n-1 column of sub-pixels.
  • the active semiconductor layer of the sub-pixel in the 2nth column includes a fourth portion and a fifth portion that are sequentially arranged along the column direction.
  • the fourth portion may include active regions of the drive reset transistor, the data write transistor, the compensation transistor, the drive transistor, the first light emission control transistor and the second light emission control transistor in the 2nth column of subpixels.
  • the fifth portion may include the active region of the light emitting reset transistor in the 2nth column of subpixels.
  • the array substrate may further include a first conductive layer on a side of the active semiconductor layer away from the substrate.
  • the first conductive layer may include a first drive reset control signal line, a first scan signal line, a second scan signal line, a first pole of a capacitor, a light emission control signal line, and a first light emission reset control signal, which are sequentially arranged along the column direction line and a second light-emitting reset control signal line.
  • the first scan signal line can be used as a second drive reset control signal line, and the first electrode of the capacitor can be integrated with the gate of the drive transistor.
  • the portion where the orthographic projection of the first driving reset control signal line on the substrate overlaps with the orthographic projection of the first portion of the active semiconductor layer on the substrate may be in the 2n-1th column of sub-pixels drive the gate of the reset transistor.
  • the overlapping portion of the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the first portion, the second portion, and the fourth portion of the active semiconductor layer on the substrate may be the sub-pixels in the 2n-1th column, respectively.
  • the overlapping portion of the orthographic projection of the second scanning signal line on the substrate and the orthographic projection of the fourth portion of the active semiconductor layer on the substrate may be the gates of the data writing transistor and the compensation transistor in the 2nth column of sub-pixels, respectively pole.
  • the portion where the orthographic projection of the first pole of the capacitor on the substrate in the sub-pixel in the 2n-1th column overlaps with the orthographic projection of the third portion of the active semiconductor layer on the substrate may be the sub-pixel in the 2n-1th column. gate of the drive transistor.
  • the portion where the orthographic projection of the first electrode of the capacitor in the sub-pixel in the 2nth column on the substrate overlaps the orthographic projection of the fourth portion of the active semiconductor layer on the substrate may be the gate of the driving transistor in the sub-pixel in the 2nth column. pole.
  • the part where the orthographic projection of the light-emitting control signal line on the substrate overlaps the orthographic projection of the third part and the fourth part of the active semiconductor layer on the substrate may be the first light-emitting control in the 2n-1th column of sub-pixels, respectively.
  • the portion where the orthographic projection of the first light-emitting reset control signal line on the substrate overlaps with the orthographic projection of the third portion of the active semiconductor layer on the substrate may be the gate of the light-emitting reset transistor in the 2n-1th column of sub-pixels .
  • the portion where the orthographic projection of the second light-emitting reset control signal line on the substrate overlaps the orthographic projection of the fifth portion of the active semiconductor layer on the substrate may be the gate of the light-emitting reset transistor in the 2nth column of subpixels.
  • the array substrate may further include a second conductive layer on a side of the first conductive layer away from the substrate.
  • the second conductive layer may include a second pole of a capacitor arranged in a column direction and a first power signal line serving as a first voltage source.
  • the projections of the second pole of the capacitor and the first pole of the capacitor on the substrate may at least partially overlap.
  • the first power signal line extends in the row direction and may be integrally formed with the second pole of the capacitor.
  • the array substrate may further include a third conductive layer on a side of the second conductive layer away from the substrate.
  • the third conductive layer may include a data signal line, a reset power signal line, a second power signal line serving as a first voltage source, a third power signal line serving as a first voltage source, a first connection portion, a second connection portion, The third connection part, the fourth connection part, the fifth connection part and the sixth connection part.
  • One end of the first connection portion can be coupled to the first electrode of the compensation transistor of the 2n-1 column of sub-pixels, and the other end of the first connection portion can be coupled to the second electrode of the driving transistor of the 2n-1 column of sub-pixels.
  • One end of the second connection portion can be coupled to the first electrode of the driving reset transistor of the sub-pixel in the 2n-1 column, and the other end can be coupled to the gate of the driving transistor of the sub-pixel in the 2n-1 column.
  • One end of the third connection portion can be coupled to the second electrode of the data writing transistor of the 2n-1 column sub-pixel, and the other end can be coupled to the first electrode of the driving transistor of the 2n-1 column sub-pixel.
  • the fourth connection portion can be coupled to the second electrode of the second light-emitting control transistor of the 2n-1th column of sub-pixels.
  • One end of the fifth connection portion can be coupled to the first electrode of the driving reset transistor of the sub-pixel in the 2nth column, and the other end can be coupled to the gate of the driving transistor of the sub-pixel in the 2nth column.
  • One end of the sixth connecting portion can be coupled to the second electrode of the second light-emitting control transistor of the sub-pixel in the 2nth column, and the other end can be coupled to the first electrode of the light-emitting reset transistor of the sub-pixel in the 2nth column.
  • the data signal line may be coupled to the first electrode of the data writing transistor of the 2n-1th column of sub-pixels and the first electrode of the data writing transistor of the 2nth column of sub-pixels.
  • the second power signal line may extend along the column direction and be located in the 2n-1 column of sub-pixels, and may be coupled to the second electrode of the capacitor of the 2n-1 column of sub-pixels and the first electrode of the first light-emitting control transistor.
  • the third power signal line may extend along the column direction and be located in the 2nth column of subpixels, and may be coupled to the second electrode of the capacitor of the 2nth column of subpixels and the first electrode of the first light-emitting control transistor.
  • the second conductive layer may further include a first additional reset power signal line and a second additional reset power signal line extending in the row direction.
  • the first additional reset power signal line and the second additional reset power signal line may be coupled to the reset power signal line.
  • the second pole of the capacitor and the first power signal line may be located between the first additional reset power signal line and the second additional reset power signal line in the column direction.
  • the array substrate may further include a third conductive layer on a side of the second conductive layer away from the substrate.
  • the third conductive layer may include a data signal line, a reset power signal line, a second power signal line serving as a first voltage source, a third power signal line serving as a first voltage source, a first connection portion, a second connection portion, The third connection part, the fourth connection part, the fifth connection part, the sixth connection part, the seventh connection part, the eighth connection part, the ninth connection part and the tenth connection part.
  • One end of the first connecting portion can be coupled to the first electrode of the compensation transistor of the sub-pixel in the 2n-1 column, and the other end can be coupled to the second electrode of the driving transistor of the sub-pixel in the 2n-1 column.
  • One end of the second connecting portion The first electrode of the drive reset transistor of the 2n-1th column of sub-pixels can be coupled, and the other end of the drive reset transistor can be coupled to the gate of the 2n-1th column of sub-pixels.
  • One end of the third connection portion can be coupled to the second electrode of the data writing transistor of the 2n-1 column sub-pixel, and the other end can be coupled to the first electrode of the driving transistor of the 2n-1 column sub-pixel.
  • the fourth connection portion can be coupled to the second electrode of the second light-emitting control transistor of the 2n-1th column of sub-pixels.
  • One end of the fifth connection portion can be coupled to the first electrode of the driving reset transistor of the sub-pixel in the 2nth column, and the other end can be coupled to the gate of the driving transistor of the sub-pixel in the 2nth column.
  • One end of the sixth connecting portion may be coupled to the second electrode of the second light-emitting control transistor of the sub-pixel in the 2nth column, and the other end may be coupled to the first electrode of the light-emitting reset transistor of the sub-pixel in the 2nth column.
  • One end of the seventh connection portion can be coupled to the first additional reset power signal line, and the other end can be coupled to the second pole of the driving reset transistor of the 2n-1th column of sub-pixels.
  • One end of the eighth connection portion can be coupled to the second additional reset power supply signal line, and the other end can be coupled to the second pole of the light-emitting reset transistor of the 2n-1th column of sub-pixels.
  • One end of the ninth connection portion can be coupled to the first additional reset power supply signal line, and the other end can be coupled to the second pole of the driving reset transistor of the 2nth column of sub-pixels.
  • the tenth connection portion can be coupled to the second additional reset power supply signal line, and the other end can be coupled to the second pole of the light-emitting reset transistor of the 2nth column of sub-pixels.
  • the second power signal line may extend along the column direction and be located in the 2n-1 column of sub-pixels, and may be coupled to the second electrode of the capacitor of the 2n-1 column of sub-pixels and the first electrode of the first light-emitting control transistor.
  • the third power signal line may extend along the column direction and be located in the 2nth column of subpixels, and may be coupled to the second electrode of the capacitor of the 2nth column of subpixels and the first electrode of the first light-emitting control transistor.
  • the array substrate may further include a fourth conductive layer on a side of the third conductive layer away from the substrate.
  • the fourth conductive layer may include a fourth power signal line serving as a first voltage source, an eleventh connection portion, and a twelfth connection portion.
  • the orthographic projection of the second power supply signal line on the substrate may at least partially overlap with the orthographic projection of the fourth power supply signal line on the substrate.
  • the orthographic projection of the third power supply signal line on the substrate may at least partially overlap with the orthographic projection of the fourth power supply signal line on the substrate.
  • the fourth power signal line can be coupled to the second power signal line and the third power signal line.
  • the eleventh connection portion may be coupled to the fourth connection portion.
  • the twelfth connection part may be coupled to one end of the sixth connection part.
  • a display panel includes the array substrate according to any one of the first aspects.
  • a display device includes the display panel according to any one of the second aspects.
  • FIG. 1 shows a schematic structural diagram of an array substrate.
  • FIG. 2 shows a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic block diagram of a sub-pixel according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of the pixel circuit of FIG. 3 according to an embodiment of the present disclosure.
  • FIG. 5 illustrates a timing diagram of signals driving the pixel circuit of FIG. 4 according to an embodiment of the present disclosure.
  • FIG. 6 illustrates a timing diagram of signals driving the array substrate of FIG. 2 according to an embodiment of the present disclosure.
  • FIG. 7-13 illustrate schematic plan views of layers in an array substrate according to embodiments of the present disclosure.
  • FIG. 14-15 illustrate schematic plan layouts of stacked active semiconductor layers, first conductive layers, second conductive layers, third conductive layers, and fourth conductive layers.
  • FIG. 16 shows a schematic cross-sectional structure diagram of the array substrate taken along the line A1A1' in FIG. 14 according to an embodiment of the present disclosure.
  • FIG. 17 shows a schematic cross-sectional structure diagram of the array substrate taken along the line A2A2' in FIG. 15 according to an embodiment of the present disclosure.
  • FIG. 18 shows a schematic cross-sectional structure diagram of the array substrate taken along the line B1B1' in FIG. 14 according to an embodiment of the present disclosure.
  • FIG. 19 shows a schematic cross-sectional structure diagram of the array substrate taken along the line C1C1' in FIG. 14 according to an embodiment of the present disclosure.
  • FIG. 20 shows a schematic cross-sectional structure diagram of the array substrate taken along the line C2C2' in FIG. 15 according to an embodiment of the present disclosure.
  • FIG. 21 shows a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 22 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the multiple columns of pixel units in the same row of pixel units will be driven by the scan signal provided by the same scan line.
  • the multiple columns of pixel units in the same row of pixel units have the same opening time.
  • the pixel unit sequentially writes data signals provided by a plurality of different data lines.
  • multiple columns of pixel units in the same row of pixel units have different charging methods, such as charging first and then discharging and discharging while charging, which in turn leads to multiple columns of pixel units in the same row of pixel units.
  • the display brightness is uneven, which affects the display quality.
  • FIG. 1 shows a schematic structural diagram of an array substrate, which can solve the above problems.
  • the array substrate 10 includes a substrate, a plurality of pairs of scanning signal lines S, a plurality of pairs of driving reset control signal lines R and a pixel array disposed on the substrate.
  • the pixel array includes a plurality of sub-pixels P arranged in rows and columns.
  • the sub-pixel P has a pixel circuit and a data signal input terminal Data, a scan signal input terminal Gate and a drive reset control signal input terminal Rst1 coupled to the pixel circuit.
  • Figure 1 it shows a P 2n-1 m-th row in the sub-pixel and the second sub-pixel and P 2n m + P 2n-1 sub-pixels in the row of sub-pixels and sub-pixels P 2n.
  • both m and n are integers greater than or equal to 1.
  • the array substrate 10 includes two pairs of scan signal lines extending in the row direction and spaced apart from each other in the column direction, and a first pair of sub-pixels corresponding to the sub-pixels in the 2n-1th column and the sub-pixels in the 2n+1-th column in the mth row.
  • the scanning signal line SO m , and the second scanning signal line SE m corresponding to the 2n-th column sub-pixel and the 2n+2-th column sub-pixel in the m-th row, and the 2n-1-th column sub-pixel and the 2n-th sub-pixel in the m+1-th row
  • the array substrate includes two pairs of drive reset control signal lines extending in the row direction and spaced apart from each other in the column direction, corresponding to the 2n-1th column subpixels and the 2n+1th column subpixels in the mth row.
  • the first driving reset control signal line RO m , and the second driving reset control signal line RE m corresponding to the 2n-th column sub-pixel and the 2n+2-th column sub-pixel of the m-th row, and the 2n-th column corresponding to the m+1-th row The first drive reset control signal line RO m+1 corresponding to the 1-column sub-pixel and the 2n+1-th column sub-pixel, and the second drive-reset control signal line RO m+1 corresponding to the 2n-th column sub-pixel and the 2n+2-th column sub-pixel in the m+1 th row Signal line RE m+1 .
  • the scan signal input end of the sub-pixels in the 2n-1th column in the m-th row of sub-pixels can be connected to the first scan signal line SO m to receive the first scan signal, and the m-th row of sub-pixels
  • the scan signal input terminal of the sub-pixels in the 2nth column in the 2n-th column can be connected to the second scan signal line SE m to receive the second scan signal, so that the 2n-1th column of sub-pixels in the m-th row of sub-pixels will be driven by the first scan signal.
  • the subpixels in the 2nth column are turned on after being driven by the second scan signal, and the subpixels in the 2n-1th column and the 2nth column subpixels in the mth row of subpixels have the same turn-on time.
  • the sub-pixels in the 2n-1th column and the sub-pixels in the 2n-th column in the m-th row of sub-pixels are charged in the same way, which avoids the problem of uneven display brightness of multiple columns of sub-pixels in the same row of pixel units, and can improve the Display quality.
  • the array substrate further includes reset power signal lines V and data signal lines D extending in the column direction and spaced apart from each other in the row direction.
  • the 2n-1th reset power signal line V 2n-1 corresponds to the 2n-1th column of sub-pixels in each row of sub-pixels, ..., the 2n+2th reset power signal line V 2n+2 corresponds to each row of sub-pixels
  • the 2n+2th column of sub-pixels corresponds to .
  • the 2n-1th data signal line D2n-1 corresponds to the 2n-1th column of subpixels in each row of subpixels
  • the 2n+2th data signal line D2n+2 corresponds to the 2n-1th column of subpixels in each row of subpixels.
  • the 2n+2th column corresponds to sub-pixels.
  • At least some embodiments of the present disclosure provide an array substrate comprising: a plurality of pairs of scan signal lines, a plurality of pairs of scan signal lines configured to extend in a row direction and spaced apart from each other in a column direction, the plurality of pairs of scan signal lines Each pair of the lines includes a first scan signal line and a second scan signal line; a plurality of pairs of drive reset control signal lines configured to extend in the row direction and spaced apart from each other in the column direction, the plurality of pairs of drive reset control signal lines Each of the pairs includes a first drive reset control signal line and a second drive reset control signal line; a plurality of data lines; and a pixel array including a plurality of sub-pixels arranged in a plurality of rows and columns.
  • Each of the plurality of sub-pixels includes a data signal input terminal, a scan signal input terminal, and a driving reset control signal input terminal.
  • a plurality of rows of sub-pixels are in one-to-one correspondence with a plurality of pairs of scanning signal lines, and each column of sub-pixels corresponds to one data line among the plurality of data lines.
  • the scan signal input terminal of the 2n-1th column (ie, odd-numbered column) subpixels in the mth row of subpixels is connected to the first scan signal line in the mth pair of scan signal lines to receive the first scan signal, m and n are integers greater than or equal to 1; the scan signal input terminal of the sub-pixel in the 2nth column (ie, the even column) in the m-th row of sub-pixels is connected to the second scan signal line in the m-th pair of scan signal lines to receive the second scan signal line. scan signal.
  • the drive reset control signal input terminal of the pixel unit in the 2n-1th column of the pixel unit in the mth row is connected to the first scan signal line in the mth pair of scan signal lines to receive the first scan signal as the first drive reset control signal;
  • the drive reset control signal input terminal of the 2nth column sub-pixel in the mth row of pixel units is connected to the second scan signal line in the mth pair of scan signal lines to receive the second scan signal as the second drive reset control signal .
  • the scan signal input terminal of the sub-pixel in the 2n-1th column of the pixel unit in the mth row may be connected to the first scan signal line in the mth pair of scan signal lines to receive the first scan signal line.
  • the scan signal input terminal of the sub-pixel in the 2n-th column in the sub-pixel in the m-th row can be connected to the second scan-signal line in the m-th pair of scan-signal lines to receive the second scan signal, so that the The sub-pixels in the 2n-1th column will be turned on first under the driving of the first scan signal provided by the first scan signal line in the m-th pair of scan signal lines, and the sub-pixels in the 2n-th column will be turned on during the second scan in the m-th pair of scan signal lines.
  • the signal line is turned on after being driven by the second scan signal provided by the signal line, and the subpixels in the 2n-1th column and the subpixels in the 2nth column in the pixel unit of the mth row can be turned on in the same length.
  • the sub-pixels in the 2n-1 column and the sub-pixels in the 2n-th column in the pixel unit of the m-th row are charged in the same way, which avoids the problem of uneven display brightness of the sub-pixels in multiple columns in the same row of sub-pixels, and can improve the Display quality.
  • the first scan signal line of the mth pair of scan signal lines and the second drive reset control signal line of the mth pair of drive reset control signal lines are the same signal line.
  • the scan signal input terminal of the 2n+1th column of subpixels in the mth row of subpixels may be connected to the first scan signal line in the mth pair of scan signal lines, and the 2nth column of subpixels in the mth row of pixel units
  • the input terminal of the drive reset control signal can also be connected to the first scan signal line in the m-th pair of scan signal lines, so that the first scan signal line in the m-th pair of scan signal lines can be provided to the sub-pixels in the m-th row.
  • the first scan signal of the sub-pixels in the 2n-1 column is applied to the sub-pixels in the 2n-th column in the sub-pixels in the m-th row as the first driving reset control signal to reset the sub-pixels in the 2n-th column in the sub-pixels in the m-th row.
  • the number of gate drivers (gate drivers on array, GOA) integrated on the array substrate can be reduced, which is beneficial to the realization of a narrow frame design of a display device using the array substrate.
  • the sub-pixel may further include a reset voltage terminal.
  • the array substrate further includes a plurality of reset power signal lines.
  • the plurality of reset power signal lines extend in the column direction, and are alternately arranged with the data signal lines in the row direction, and the intervals between the adjacent data signal lines and the adjacent reset power signal lines define a column of sub-pixels .
  • the reset power signal line is configured to supply a reset voltage to reset voltage terminals of subpixels in a subpixel column adjacent to the reset power signal line.
  • the n+1th reset power signal line Vn+1 is adjacent to the 2nth column subpixel and the 2n+1th column subpixel, and is configured to provide the reset voltage terminal of the 2nth column subpixel and the 2n+1th column subpixel reset voltage.
  • the data signal line is configured to provide data signals to data signal input terminals of subpixels in a subpixel column adjacent to the data signal line.
  • the n th data signal line Dn is adjacent to the 2n-1 th column sub-pixels and the 2n th column sub-pixels, and is configured to provide data signals to data signal input terminals of the 2n-1 th and 2n th columns of sub-pixels.
  • the n+1th data signal line Dn+1 is adjacent to the 2n+1th column subpixel and the 2n+2th column subpixel, and is configured to input data signals to the 2n+1th column subpixel and the 2n+2th column subpixel provide data signals.
  • the number of arranged data lines integrated on the array substrate can be reduced, thereby improving the PPI.
  • FIG. 2 is a schematic structural diagram of an array substrate according to some embodiments of the disclosure.
  • the array substrate 20 includes a substrate, a plurality of pairs of scan signal lines S, a plurality of pairs of driving reset control signal lines R, a plurality of reset power signal lines V, a plurality of data lines D and pixels disposed on the substrate. array.
  • the substrate may be a glass substrate, a plastic substrate, or the like, which is not limited by the embodiments of the present disclosure.
  • a plurality of pairs of scan signal lines S may be extended in the row direction and spaced apart from each other along the column direction on the substrate, and each pair of the plurality of pairs of scan signal lines S includes a first scan signal line SO and a second scan signal line SE; the plurality of pairs
  • the driving reset control signal lines R may extend in the row direction and be disposed on the substrate spaced apart from each other in the column direction, and the plurality of pairs of driving reset control signal lines R may include a first driving reset control signal line RO and a second driving reset control signal line RE ;
  • a plurality of reset power supply lines V and a plurality of data lines D are alternately arranged on the substrate along the row direction, and the interval between the adjacent data signal lines and the reset power supply signal lines defines a column of sub-pixels;
  • the pixel array includes an arrangement of Multiple sub-pixels P in multiple rows and multiple columns, for example, multiple sub-pixels P are located in the pixel area defined by the intersection of multiple pairs of scan signal lines S, multiple reset power signal lines V
  • the first direction may be perpendicular to the second direction
  • the first direction may be the row direction of the pixel array (eg, the X direction in FIG. 2 )
  • the second direction may be the column direction of the pixel array (eg, the direction of the pixel array in FIG. 2 ) Y direction).
  • multiple rows of pixel units may correspond to multiple pairs of scan signal lines S one-to-one, and each row of pixel units may be connected to its corresponding pair of scan signal lines S.
  • the m-th row of sub-pixels may correspond to the For the m pair of scan signal lines S m
  • the 2n-1 column sub-pixels in the m-th row of sub-pixels may correspond to the first scan signal line SO m in the m-th pair of scan signal lines S m
  • the m-th row of pixel units in the pixel unit The 2n-column sub-pixels may correspond to the second scan signal line SE m of S m in the m-th pair of scan signal lines
  • the scan signal input gate Gate of the 2n-1-th column sub-pixels in the m-th row of pixel units may be connected to the m-th pair of scan signal lines.
  • the first scan signal line SO m in the signal line S m is to receive the first scan signal, and the scan signal input gate Gate of the 2nth column sub-pixel in the mth row of pixel units can be connected to the mth pair of scan signal lines Sm.
  • Two scan signal lines SE m to receive the second scan signal, where m and n are both integers greater than or equal to 1.
  • multiple rows of pixel units may correspond to multiple pairs of driving reset control signal lines R one-to-one.
  • Each row of pixel units may be connected to a corresponding pair of driving reset control signal lines R.
  • the m-th row of sub-pixels may correspond to the m-th pair of driving reset control signal lines R m
  • the 2n-th row of sub-pixels in the m-th row 1 sub-pixels may correspond to the m first driving control of driving the reset line reset signal R & lt m control signal lines RO m
  • 2n sub-pixels of the pixel unit in the m-th row may correspond to the m-th driving the reset control signal line m R & lt second driving the reset control signal line RE m
  • resetting the first drive sub-pixels 2n-1 of the m-th row in the pixel unit Rst1 control signal input terminal may be connected to a first drive driving the first reset control signal m of Rm reset control signal m to the RO receiving
  • driving the reset m-th row in the first sub-pixel sub-pixels 2n input control signal Rst1 may be connected to the m scanning signal lines S of m in the first scanning signal line SO m / RE m to receive the first scan Signal.
  • the first scan signal that the first scan signal line SO m of the m-th pair of scan signal lines Sm supplies to the 2n-th column sub-pixels of the m-th row of sub-pixels may be applied as the first drive reset control signal to
  • the sub-pixels in the 2n-th column in the sub-pixels in the m-th row are used to reset the sub-pixels in the 2n-th column in the sub-pixels in the m-th row.
  • the data signal line D is configured to supply data signals to data signal input terminals of subpixels in a subpixel column adjacent to the data signal line.
  • the sub-pixels in the 2n-1th column and the sub-pixels in the 2n-th column may correspond to the same data line Dn
  • the sub-pixels in the 2n+1-th column and the 2n+2-th column sub-pixels may correspond to the same data line Dn+1, . . . And so on.
  • the data signal input terminal Data of the sub-pixels in the 2n-1 column and the data signal input terminal Data of the sub-pixels in the 2n-th column can be connected to the same data line Dn to receive the data signal.
  • the data signal input terminals Data of the sub-pixels in 2n+2 columns can be connected to the same data line Dn+1 to receive data signals, . . . , and so on.
  • the reset power signal line V is configured to supply a reset voltage to the reset voltage terminals of the subpixels in the subpixel column adjacent to the reset power signal line.
  • the subpixels in the 2nth column and the subpixels in the 2n+1st column may correspond to the same reset power supply signal line Vn +1
  • the subpixels in the 2n+2th column and the 2n+3th column subpixels may correspond to the same A reset power signal line Vn+2,..., and so on.
  • the reset voltage terminal Vint of the sub-pixel in the 2nth column and the reset voltage terminal Vint of the sub-pixel in the 2n+1th column can be connected to the same reset power signal line Vn +1 to receive the reset voltage, and the reset voltage terminal Vint of the sub-pixel in the 2n+2th column
  • the reset voltage terminal Vint of the sub-pixels in the 2n+3th column may be connected to the same reset power signal line Vn +2 to receive the reset voltage, . . . , and so on.
  • the nth reset power signal line Vn is arranged on the left side of the 2n-1th column of sub-pixels and the nth data line Dn is arranged on the right side of the 2n-1th column of sub-pixels, and the nth reset power supply signal
  • a row of sub-pixels is arranged between the line Vn and the n-th data line Dn, and two columns of sub-pixels may be arranged between two adjacent data lines D. Two columns of sub-pixels may be disposed between two adjacent reset power signal lines V.
  • the embodiments of the present disclosure are obviously not limited thereto.
  • the nth reset power signal line Vn may be disposed on the right side of the 2n-1th column of sub-pixels, and the nth data line Dn may be disposed on the left side of the 2n-1th column of sub-pixels.
  • the sub-pixel P further includes a light-emitting reset control signal input terminal Rst2.
  • the array substrate 20 also includes a plurality of pairs of light-emitting reset control signal lines (not shown).
  • a plurality of pairs of light-emitting reset signal lines extend in the row direction and are spaced apart from each other in the column direction.
  • Each of the plurality of pairs of light-emitting reset signal lines includes a first light-emitting reset control signal line and a second light-emitting reset control signal line.
  • the m-th pair of light-emission reset signal lines corresponds to the m-th row of sub-pixels
  • the first light-emission reset signal line of the m-th pair of light-emission reset signal lines is configured to input the light-emission reset signal of the 2n-1th column of sub-pixels of the m-th row of sub-pixels
  • the terminal provides a first light-emitting reset signal.
  • the second light-emission reset signal line of the m-th pair of light-emission reset signal lines is configured to supply the second light-emission reset signal to the light-emission reset signal input terminal of the 2n-th column of sub-pixels of the m-th row of sub-pixels.
  • the first light-emitting reset signal line of the m-th pair of light-emitting reset signal lines and the first driving reset control signal line of the m+1-th pair of driving reset control signal lines are the same signal line.
  • the second light-emitting reset signal line of the m-th pair of light-emitting reset signal lines and the second drive-reset control signal line of the m+1-th pair of drive-reset control signal lines are the same signal line.
  • the light-emitting reset control signal input end of the 2n-1th column of subpixels in the mth row of subpixels is connected to the first scan signal line in the m+1th pair of scan signal lines to receive the m+1th pair of scan signals
  • the first scan signal provided by the first scan signal line in the line is used as the first light-emitting reset control signal to reset the sub-pixels in the 2n-1th column in the sub-pixels in the m-th row.
  • the first scan signal provided by the first scan signal line SO m+1 of the m+1 pair of scan signal lines S m+1 to the 2n-1 column sub-pixels of the m-th row of sub-pixels may be A light emission reset control signal is applied to the 2n-1 column sub-pixels in the m-th row sub-pixels to reset the 2n-1 column sub-pixels in the m-th row sub-pixels.
  • the light-emitting reset control signal input terminal of the 2nth column subpixel in the mth row of subpixels is connected to the second scan signal line of the m+1th pair of scan signal lines to receive the second scan signal line of the m+1th pair of scan signal lines.
  • the second scan signal provided by the scan signal line is used as a second light-emitting reset control signal to reset the sub-pixels in the 2n-th column in the sub-pixels in the m-th row.
  • the second scan signal provided by the second scan signal line SE m+1 of the m+1 pair of scan signal lines S m+1 to the 2n-th column sub-pixels of the m-th row of sub-pixels can be used as light emission
  • the reset control signal is applied to the 2n-th column of sub-pixels in the m-th row of sub-pixels to reset the 2n-th column of sub-pixels in the m-th row of sub-pixels.
  • the reset signal input terminal RST of the 2n-1 column of sub-pixels in the m-th row of sub-pixels can be connected to the first scan signal line SO m- of the m-1 pair of scan signal lines S m-1 1 .
  • the first scan signal provided by the first scan signal line SO m-1 in the m-1 pair of scan signal lines Sm-1 to the sub-pixel in the n-th column of the sub-pixels in the m-1 row can be used as
  • the second reset signal is applied to the sub-pixels of the n-th column in the sub-pixels of the m-th row to reset the sub-pixels of the n-th column of the sub-pixels of the m-th row.
  • the light-emitting reset control signal input terminal Rst2 of the 2n-1th column of subpixels in the mth row of subpixels is connected to the first scan signal in the m+1th pair of scan signal lines S m+1
  • the light-emitting reset control signal input terminal Rst2 of the 2n-th column sub-pixel in the m-th row of sub-pixels is connected to the second scan signal line SE in the m+1-th pair of scan signal lines S m+1 m+1 .
  • the reset manner of the sub-pixels in the 2n-1th column and the sub-pixels in the 2n-th column in the sub-pixels in the m-th row is the same as that of the sub-pixels in the 2n-1th column and the sub-pixels in the 2n-th column in the sub-pixels in the m+1-th row. The way is different.
  • the sub-pixels in the 2n-1-th column are provided to the sub-pixels in the m+1-th row by using
  • the first scan signal of the sub-pixels in the 2n-1th column is reset as a light-emitting reset control signal; in the sub-pixels in the m-th row, the sub-pixels in the 2n-th column use the second
  • the scan signal is reset as a light emission reset control signal.
  • the sub-pixel P further includes a light-emitting control signal input terminal to receive a light-emitting control signal for the sub-pixel.
  • the array substrate 20 provided in this embodiment may further include a plurality of light-emitting control signal lines extending along the column direction and spaced apart from each other on the substrate along the row direction, and the plurality of light-emitting control signal lines and the plurality of rows of sub-pixels are one by one.
  • the light-emitting control signal input end of the sub-pixels in the m-th row is connected to the m-th light-emitting control signal line to receive the light-emitting control signal.
  • each sub-pixel P further includes a light emission control signal input terminal EM.
  • the array substrate 20 further includes a plurality of light-emitting control signal lines E disposed on the substrate, for example, the plurality of light-emitting control signal lines E may be disposed on the substrate along the first direction.
  • the plurality of light-emitting control signal lines E may be in one-to-one correspondence with the plurality of rows of sub-pixels, and each row of sub-pixels may be connected to a corresponding one of the light-emitting control signal lines E.
  • the m-th row of sub-pixels corresponding to the m-th emission control signal line E m, m-th row sub-pixel emitting a control signal input terminal EM may be connected to the m E m emission control signal line to receive a light emission control signal.
  • a m-th emission control signal line in FIG. 2 E m m-th row is disposed on the side of the sub-pixel, but the present embodiment is obviously not limited to this disclosed embodiment.
  • the m E m emission control signal line may be disposed on the lower side of the m-th row of sub-pixels.
  • the sub-pixel P may further include a first voltage terminal VDD.
  • the array substrate may further include a plurality of first voltage signal lines disposed on the substrate.
  • the plurality of first voltage signal lines are in one-to-one correspondence with the plurality of rows of sub-pixels, and the first voltage terminal of the 2n-1th column of sub-pixels in the m-th row of sub-pixels is connected to the 2n-1th first voltage signal line to receive the first voltage signal line.
  • Voltage, ..., the first voltage terminals of the 2n+2th column subpixels in the mth row of subpixels are connected to the 2n+2th first voltage signal line to receive the first voltage.
  • the sub-pixel P includes a pixel circuit 100 and a light-emitting device 200 .
  • the pixel circuit 100 includes a data writing circuit 110 , a driving circuit 120 , a driving reset circuit 130 , a compensation circuit 140 , a lighting control circuit 150 , a lighting reset circuit 160 and a storage circuit 170 .
  • the data writing circuit 110 is coupled to the data signal input terminal, and the first terminal F of the driving circuit 120 is coupled to the scanning signal input terminal Gate.
  • the data writing circuit is configured to write the data signal into the driving circuit 120 under the control of the scan signal.
  • the scan signal here may be the first scan signal or the second scan signal described in the previous embodiments, and the scan signal mentioned in the subsequent embodiments has a similar meaning, so it will not be repeated.
  • the driving circuit 120 includes a control terminal G, a first terminal F and a second terminal S, and is configured to provide a driving circuit to the light emitting device 200 under the control of a control signal from the control terminal G.
  • the driving reset circuit 130 is coupled to the control terminal G, the reset voltage terminal Vint and the driving reset control signal input terminal Rst1 of the driving circuit 120 , and is configured to switch from the reset voltage under the control of the driving reset control signal.
  • the reset voltage received by the terminal Vint is applied to the driving circuit 120 to reset the control terminal G of the driving circuit 120 .
  • the drive reset control signal here may be the first drive reset control signal or the second drive reset control signal described in the previous embodiments, and the drive reset control signal mentioned in the subsequent embodiments has a similar meaning to this. , so it will not be repeated.
  • the compensation circuit 140 is coupled to the control terminal G of the driving circuit 120 , the second terminal S of the driving circuit 120 and the scan signal input terminal Gate, and is configured to perform a first scan from the scan signal input terminal Gate.
  • the threshold value compensation is performed on the driving circuit under the control of the signal or the second scanning signal.
  • the lighting control circuit 150 is coupled to the first terminal F of the driving circuit 120 , the second terminal S of the driving circuit 120 and the lighting control signal input terminal EM, and is configured to convert the lighting control signal under the control of the lighting control signal.
  • the first voltage received from the first voltage terminal VDD is applied to the driving circuit 120 , thereby applying the driving current generated by the driving circuit 120 to the light emitting device 200 .
  • the light-emitting reset circuit 160 is coupled to the light-emitting device 200 , the reset voltage terminal VINT and the light-emitting reset control signal input terminal Rst2 , and is configured to receive from the reset voltage terminal VINT under the control of the light-emitting reset control signal.
  • a reset voltage of . is applied to the light emitting device 200 to reset the light emitting device 200 .
  • the light-emitting reset control signal here may be the first light-emitting reset control signal or the second light-emitting reset control signal described in the previous embodiment, and the light-emitting reset control signal mentioned in the subsequent embodiments has a similar meaning to this. , so it will not be repeated.
  • the storage circuit 170 is coupled to the first voltage terminal VDD and the control terminal G of the driving circuit 120 , and is configured to store the first voltage from the first voltage terminal VDD and the control terminal G of the driving circuit 120 .
  • the light emitting device 200 is coupled to the second voltage source VSS and the second terminal S of the driving circuit 120 , and is configured to emit light under the driving of the driving current generated by the driving circuit 120 .
  • the light emitting device 200 may be a light emitting diode or the like.
  • the light emitting diode may be an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or the like.
  • FIG. 4 is a schematic diagram of the pixel circuit in FIG. 3 .
  • the data writing circuit 110 includes a data writing transistor T1
  • the drive circuit 120 includes a drive transistor T2
  • the drive reset circuit 130 includes a drive reset transistor T3
  • the compensation circuit 140 includes a compensation transistor T4
  • the lighting control circuit 150 includes a first A light-emitting control transistor T5 and a second light-emitting control transistor T6
  • the light-emitting reset circuit 160 includes a light-emitting reset transistor T7
  • the storage circuit 170 includes a capacitor C.
  • the first pole of the driving transistor T2 is coupled to the first terminal F of the driving circuit 120
  • the second pole of the driving transistor T2 is coupled to the second terminal S of the driving circuit 120
  • the gate of the driving transistor T2 is It is coupled to the control terminal G of the driving circuit 120 .
  • the first pole of the data writing transistor T1 is coupled to the data signal input terminal Data to receive the data signal from the data signal line D; the second pole of the data writing transistor T1 is connected to the first pole of the driving transistor T2
  • the gate of the data writing transistor T1 is coupled to the scan signal input terminal Gate to receive the first scan signal or the second scan signal from the scan signal input terminal Gate, and is configured to receive the first scan signal or the second scan signal from the scan signal input terminal Gate.
  • the first scan signal or the second scan signal of provides the data signal from the data signal line D to the first electrode of the driving transistor T2.
  • the first pole of the driving reset transistor T3 is coupled to the gate of the driving transistor T2; the second pole of the driving reset transistor T3 is coupled to the reset voltage terminal VINT to receive the reset voltage from the reset voltage terminal VINT;
  • the gate of the driving reset transistor T3 is coupled to the driving reset control signal input terminal Rst1 to receive the first driving reset control signal or the second driving reset control signal from the driving reset control signal input terminal Rst1, and is configured to The first drive reset control signal or the second drive reset control signal at the control signal input terminal Rst1 supplies a reset voltage to the gate of the drive transistor T2 to reset the gate of the drive transistor T2.
  • the first pole of the compensation transistor T4 is coupled to the second pole of the driving transistor T2; the second pole of the compensation transistor T4 is coupled to the gate of the driving transistor T2; the gate of the compensation transistor T4 is connected to the scan signal
  • the input terminal Gate is coupled to receive the first scan signal or the second scan signal from the scan signal input terminal Gate, and is configured to drive the transistor T2 according to the first scan signal or the second scan signal from the scan signal input terminal Gate threshold to compensate.
  • the first pole of the first light-emitting control transistor T5 is coupled to the first voltage terminal VDD to receive the first voltage from the first voltage terminal VDD; the second pole of the first light-emitting control transistor T5 is connected to the driving transistor The first pole of T2 is coupled; the gate of the first light-emitting control transistor T5 is coupled to the light-emitting control signal input terminal EM to receive the light-emitting control signal from the light-emitting control signal input terminal EM, and is configured to input the light-emitting control signal according to the light-emitting control signal input terminal EM.
  • the terminal EM light emission control signal controls the on-off between the first voltage terminal VDD and the first electrode of the driving transistor T2, thereby controlling whether to supply the first voltage from the first voltage terminal VDD to the first electrode of the driving transistor T2.
  • the first electrode of the second light-emitting control transistor T6 is coupled to the second electrode of the driving transistor T2; the second electrode of the second light-emitting control transistor T6 is coupled to the first electrode of the light-emitting device 200; the gate of the second light-emitting control transistor T6
  • the pole is coupled to the light-emitting control signal input terminal EM to receive the light-emitting control signal from the light-emitting control signal input terminal EM, and is configured to control the second pole of the driving transistor T2 and the light-emitting device according to the light-emitting control signal from the light-emitting control signal input terminal EM
  • the on-off between the first poles of 200 thereby controlling whether the current generated by the driving transistor is supplied to the light-emitting device 200 .
  • the first light emission control transistor T5 and the second light emission control transistor T6 are jointly configured to apply the first voltage to the driving circuit 120 and apply the driving current generated by the driving circuit 120 to the light emitting device 200 .
  • the first pole of the capacitor C is coupled to the gate of the driving transistor T2; the second pole of the capacitor is coupled to the first voltage terminal VDD, and is configured to store the first voltage from the first voltage terminal VDD The voltage difference between the voltage and the voltage of the gate of the drive transistor T2.
  • the reset voltage terminal VINT is input with a low voltage
  • the first voltage terminal VDD is input with a high voltage
  • the second voltage terminal VSS is input with a low voltage
  • the second terminal of the light emitting device 120 is grounded as an example.
  • the high and low here only represent the relative magnitude relationship between the input voltages.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and thin film transistors are used as examples in the embodiments of the present disclosure.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in structure.
  • one pole is directly described as the first pole, and the other pole is the second pole.
  • the transistors used in the embodiments of the present disclosure may all be P-type transistors or N-type transistors, and it is only necessary to refer to the respective poles of the transistors of the selected type with reference to the corresponding transistors in the embodiments of the present disclosure.
  • the poles are connected accordingly, and the corresponding high voltage or low voltage can be provided at the corresponding voltage terminal.
  • N-type transistor its input is the drain and the output is the source, and its control is the gate
  • P-type transistor its input is the source and the output is the drain
  • its control is the gate pole.
  • the level of the control signal at the control terminal is also different.
  • an N-type transistor when the control signal is at a high level, the N-type transistor is in an on state; and when the control signal is at a low level, the N-type transistor is in an off state.
  • a P-type transistor when the control signal is at a low level, the P-type transistor is in an on state; and when the control signal is at a high level, the P-type transistor is in an off state.
  • an oxide semiconductor such as Indium Gallium Zinc Oxide (IGZO)
  • IGZO Indium Gallium Zinc Oxide
  • Crystalline silicon such as hydrogenated amorphous silicon
  • Low temperature polysilicon generally refers to the case where the crystallization temperature of polysilicon obtained by crystallization of amorphous silicon is lower than 600 degrees Celsius.
  • the pixel circuit of the sub-pixel may be a structure including other numbers of transistors in addition to the 7T1C (ie, seven transistors and one capacitor) structure shown in FIG. 4 ,
  • a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure which is not limited in this embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of signals driving the pixel circuit in FIG. 4 .
  • the working process of the pixel circuit 100 includes three stages, namely, a reset stage P1 , a data writing and compensation stage P2 , and a light-emitting stage P3 .
  • the data writing transistor T1, the driving transistor T2, the driving reset transistor T3, the compensation transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the light-emitting reset transistor are all P-type transistors as an example. The operation of the pixel circuit in FIG. 5 will be described.
  • a low-level drive reset control signal RST As shown in FIG. 5 , in the reset phase P1 , a low-level drive reset control signal RST, a high-level scan signal GA, a high-level light-emitting control signal EMS and a low-level data signal DA are input.
  • the gate of the driving reset transistor T3 receives the low-level driving reset control signal RST1, and the driving reset transistor T3 is turned on, thereby applying the reset voltage VINT to the gate of the driving transistor T2 to control the voltage of the driving transistor T2.
  • the gate is reset, so that the driving transistor T2 enters the data writing and compensation phase P2 in an on state.
  • the gate of the light-emitting reset transistor T7 receives the low-level light-emitting reset control signal RST2, and the light-emitting reset transistor T7 is turned on, thereby applying the reset voltage VINT to the anode of the OLED to reset the anode of the OLED, so that the The OLED does not emit light until the light-emitting phase P3.
  • the gate of the data writing transistor T1 receives the high-level scanning signal GA, and the data writing transistor T1 is turned off;
  • the gate of the compensation transistor T4 receives the high-level scanning signal GA, and the compensation transistor T4 receives the high-level scanning signal GA.
  • T4 is turned off;
  • the gate of the first light-emitting control transistor T5 receives the high-level light-emitting control signal EMS, and the first light-emitting control transistor T5 is turned off;
  • the gate of the second light-emitting control transistor T6 receives the high-level light-emitting control signal EM , the second light-emitting control transistor T6 is turned off.
  • a high-level drive reset control signal RST In the data writing and compensation phase P2, a high-level drive reset control signal RST, a low-level scan signal GA, a high-level light-emitting control signal EM and a high-level data signal DA are input.
  • the gate of the data writing transistor T1 receives the low-level scan signal GA, and the data writing transistor T1 is turned on, thereby writing the data signal into the first gate of the first node driving transistor T2 pole (hereinafter referred to as the first node).
  • the gate of the compensation transistor T4 receives the low-level scan signal GA, and the compensation transistor T3 is turned on. Since the data writing transistor T1, the driving transistor T2 and the compensation transistor T4 are all turned on, the data signal DA charges the storage capacitor C through the data writing transistor T1, the driving transistor T2 and the compensation transistor T4.
  • the gate (hereinafter referred to as the second node) is charged, and the voltage of the gate of the drive transistor T2 is gradually increased.
  • Vda represents the voltage of the data signal DA
  • Vth represents the threshold voltage of the driving transistor T2. Since in this embodiment, the driving transistor T2 is described by taking a P-type transistor as an example, the threshold voltage Vth here may be a negative value. .
  • the voltage of the gate of the driving transistor T2 is Vdata+Vth, that is to say, the voltage information of the data signal DA and the threshold voltage Vth is stored in the storage capacitor C for subsequent light emission.
  • the threshold voltage of the driving transistor T2 is compensated.
  • the gate of the drive reset transistor T3 receives a high-level drive reset control signal RST1, and the drive reset transistor T3 is turned off; the gate of the light-emitting reset transistor T7 receives a high-level light-emitting For the reset control signal, the light-emitting reset transistor T7 is turned off; the gate of the first light-emitting control transistor T5 receives a high-level light-emitting control signal EMS, and the first light-emitting control transistor T5 is turned off; the gate of the second light-emitting control transistor T6 receives a high-level light-emitting control signal EMS. When the level of the light-emitting control signal EMS is reached, the second light-emitting control transistor T6 is turned off.
  • a high-level drive reset control signal RST1 a high-level scan signal GA, a low-level light-emitting control signal EM and a low-level data signal DA are input.
  • the gate of the first light-emitting control transistor T5 receives the low-level light-emitting control signal EM, and the first light-emitting control transistor T5 is turned on, thereby applying the first voltage Vdd to the first node.
  • the gate of the second light-emitting control transistor T6 receives the low-level light-emitting control signal EM, and the second light-emitting control transistor T6 is turned on, thereby applying the driving current generated by the driving transistor T2 to the OLED.
  • the gate of the driving reset transistor T3 receives the high-level driving reset control signal RST1, and the driving reset transistor T3 is turned off; the gate of the light-emitting reset transistor T7 receives the high-level light-emitting reset control signal RST2 , the light-emitting reset transistor T7; the gate of the data writing transistor T1 receives the high-level scanning signal GA, and the data writing transistor T1 is turned off; the gate of the compensation transistor T4 receives the high-level scanning signal GA, and the compensation transistor T4 deadline.
  • the anode and cathode of the OLED are respectively connected to the first voltage Vdd (high voltage) and the second voltage Vss (low voltage), so as to emit light under the driving of the driving current generated by the driving transistor T2.
  • the driving current ID for driving the OLED to emit light can be obtained according to the following formula:
  • Vth represents the threshold voltage of the driving transistor Td
  • VGS represents the voltage between the gate and the source of the driving transistor Td
  • K is a constant.
  • K in the above formula can be expressed as:
  • n is the electron mobility of the driving transistor Td
  • Cox is the gate unit capacitance of the driving transistor Td
  • W is the channel width of the driving transistor Td
  • L is the channel length of the driving transistor Td.
  • FIG. 6 is a timing chart of signals for driving the array substrate in FIG. 2 .
  • the working process of the 2n-1 column of sub-pixels in the m-th row of sub-pixels is divided into three stages, namely the first reset stage P1O, the first data writing and compensation stage P2O, and the first light-emitting stage P3O; the working process of the 2nth column subpixels in the mth row subpixels is also divided into three stages, namely the second reset stage P1E, the second data writing and compensation stage P2E and the third light emitting stage P3E.
  • the first reset stage P1O provides a low-level driving reset control signal RST1O to the 2n-1 column sub-pixels in the m-th row of sub-pixels, so as to provide a low-level driving reset control signal RST1O to the 2n-1 th sub-pixels in the m-th row of sub-pixels.
  • Column subpixels are reset.
  • the driving reset control signal RST1 may refer to the driving reset control function of the first scan signal GAO provided by the m-1 th scan signal line SO m-1 in the scan signal line S m-1. Signal.
  • the first data writing and compensation stage P2O provides a low-level scan signal GAO and a high-level data signal DAO to the 2n-1 column sub-pixels in the m-th row of sub-pixels, so as to The 2n-1th column of sub-pixels in the m rows of sub-pixels performs data writing and compensation.
  • the scan signal GAO refers to a first scan signal provided to the first scan signal line SO m of the m-th pair of scan signal lines S m.
  • the data signal DAO refers to a data signal provided by one data line corresponding to the 2n-1 column of sub-pixels.
  • the data signal DAO refers to the data signal provided by the nth data signal line Dn.
  • the first light-emitting stage P3O provides a low-level light-emitting control signal EMS to the sub-pixels in the 2n-1th column of the sub-pixels in the m-th row, so that the sub-pixels in the 2n-1th column of the sub-pixels in the m-th row are pixels are displayed.
  • the light-emitting control signal EMS refers to the light-emitting control signal provided by the m-th light-emitting control signal line Em.
  • a low-level driving reset control signal RST1E is provided to the sub-pixels in the 2n-th column in the sub-pixels in the m-th row to reset the sub-pixels in the 2n-th column in the sub-pixels in the m-th row.
  • the drive reset control signal RST1E refers to the second scan signal provided by the second scan signal line SE m in the m-th pair of scan signal lines SE, that is, the scan signal GAE.
  • a low-level scan signal GAE and a high-level data signal DAE are provided to the 2n-th column sub-pixels in the m-th row of sub-pixels, so as to provide a low-level scan signal GAE and a high-level data signal DAE to the m-th row
  • the subpixels in the 2nth column of the subpixels perform data writing and compensation.
  • the scan signal GAE refers to the second scan signal provided to the second scan signal line SE m in the m-th pair of scan signal lines S m.
  • the data signal DAE refers to a data signal provided by one data line corresponding to the n+1th column of sub-pixels.
  • the data signal DAE refers to the data signal provided by the n+1 th data signal line Dn+1.
  • a low-level light emission control signal EMS is provided to the 2nth column subpixels in the mth row subpixels, so that the 2nth column subpixels in the mth row subpixels display.
  • light emission control signal EMS refers to the m-th light emission control line E m emitting signal to provide a control signal.
  • the scan signal GAO of the sub-pixels in the 2n-1-th column can serve as the reset signal RST1E for the sub-pixels in the 2n-th column.
  • the sub-pixels in the 2n-th column can be reset while data writing and compensation are performed on the 2n-1 column of sub-pixels, that is, the first data writing and compensation stage P2O and the second reset stage P1E can be synchronized in time.
  • the light-emitting control signal EMS of the 2n-1 column sub-pixels and the light-emitting control signal EMS of the 2n-th column sub-pixels are the same light-emitting control signal, that is, the first light-emitting stage P3O It may be synchronized in time with the second lighting stage P3E.
  • the sub-pixels in the 2n-1th column are reset first, and then data writing and compensation are performed on the 2n-1th column sub-pixels at the same time, and the sub-pixels in the 2n-th column are reset. , and then perform data writing and compensation on the sub-pixels in the 2nth column, and finally make the sub-pixels in the 2n-1th column and the sub-pixels in the 2nth column display at the same time.
  • the first reset stage P1O, the first data writing and compensation stage P2O, the first light emitting stage P3O, the second reset stage P1E, the second data writing and compensation stage P2E, and the third light emitting stage P3E are The order in time is: P1O ⁇ P2O&P1E ⁇ P2E ⁇ P3O&P3E.
  • the charging processes of the sub-pixels in the 2n-th column and the sub-pixels in the 2n-th column are performed separately and charged
  • the time duration is the same, and the light-emitting processes (the first light-emitting stage P3O and the third light-emitting stage P3E) of the 2n-1 column sub-pixel and the 2n-th column sub-pixel are synchronized and have the same light-emitting duration, which can make the 2n-
  • the luminous brightness of the sub-pixels in the 1st column and the sub-pixels in the 2nth column is uniform, which improves the display quality.
  • the sub-pixels in the 2n-1th column and the sub-pixels in the 2n-th column in the sub-pixels in the m-th row receive different data signals (the sub-pixels in the 2n-1th column receive the data signal DAO, the sub-pixels in the 2n-th column receive different data signals,
  • the pixel receives the data signal DAE), but due to the charging process of the 2n-2th column subpixel and the 2nth column subpixel in the mth row of subpixels (the first data writing and compensation stage P2O and the second data writing and compensation stage P2E ) are carried out separately, so the technical solution that the sub-pixels in the 2n-1th column and the sub-pixels in the 2nth column share the same data line can be realized.
  • this data signal is in a high level state in both the first data writing and compensation stage P2O and the second data writing and compensation stage P2E. Since in the first data writing and compensation stage P2O, the sub-pixels in the 2n-1 column are in an active state and the sub-pixels in the 2n-th column are in an inactive state (the scan signal GAO is at a low level, and the scan signal GAE is at a high level), and at In the second data writing and compensation stage P2E, the sub-pixels in the 2n-1 column are in an inactive state and the sub-pixels in the 2n-th column are in an active state (the scan signal GAO is at a high level, and the scan signal GAE is at a low level), so the same data is passed through.
  • the line can provide a high-level data signal to the 2n-1 column sub-pixels in the first data writing and compensation stage P2O, and provide a high-level data signal to the 2n-th column sub-pixels in the second data writing and compensation stage P2E .
  • the sub-pixels of other rows in the array substrate provided by the embodiment of the present disclosure is similar to that of the sub-pixels in the m-th row. Therefore, you can refer to the description of the working process of the sub-pixels in the m-th row in conjunction with FIG. 6 . Repeat.
  • FIGS. 7-13 illustrate schematic plan views of layers in an array substrate according to embodiments of the present disclosure.
  • the examples shown in Figures 7-13 take a pixel circuit of four sub-pixels as an example.
  • the sub-pixels in the m-th row and the 2n-1th column and the 2n-th column sub-pixels may be regarded as the smallest repeating unit.
  • FIGS. 7-13 the positions of the respective transistors of the pixel circuits included in the sub-pixels in the m-th row and the 2n-1th column and the 2n-th column sub-pixels are illustrated. It should be understood that the transistors included in the pixel circuits of other sub-pixels have substantially the same positions as the transistors included in the sub-pixels in the m-th row and the 2n-1 column and the 2n-th column sub-pixels.
  • the array substrate includes an active semiconductor layer on a substrate.
  • the active semiconductor layer 310 includes active regions of transistors in the pixel circuit.
  • the active semiconductor layer 310 may be used to fabricate the above-described driving transistor, data writing transistor, compensation transistor, first light-emitting control transistor, second light-emitting control transistor, driving reset transistor, and light-emitting reset transistor active area.
  • the active semiconductor layer 310 includes an active layer pattern and a doping region pattern of each transistor (ie, first and second source/drain regions of the transistor). In the embodiment of the present disclosure, the active layer pattern and the doped region pattern of each transistor are integrally provided.
  • the active semiconductor layer 310 of the 2n ⁇ 1th column of sub-pixels includes a first portion 311 , a second portion 312 and a third portion 313 which are spaced apart from each other.
  • the first part 311 and the second part 312 are sequentially arranged along the row direction Y.
  • the combination of the first part 311 and the second part 312 and the third part 313 are arranged in this order along the column direction X.
  • the first portion 311 includes the active region T7-a of the drive reset transistor T7 and the active region T4-a of the compensation transistor T4 in the 2n-1 column of subpixels.
  • the second portion 312 includes the active region T1-a of the data writing transistor T1 in the 2n-1 column of subpixels.
  • the third part 313 includes the active region T2-a of the driving transistor T2, the active region T5-a of the first light emission control transistor T5, and the active region T6-a of the second light emission control transistor T5 in the 2n-1 column of sub-pixels a and the active region T3-a of the light-emitting reset transistor T3.
  • the active semiconductor layer of the sub-pixel in the 2nth column includes a fourth portion 314 and a fifth portion 315 arranged in sequence along the column direction X.
  • the fourth part 314 includes the active region T7-a of the driving reset transistor T7, the active region T1-a of the data writing transistor T1, the active region T4-a of the compensation transistor T4, and the driving transistor T2 in the 2nth column of sub-pixels
  • the fifth portion 315 includes the active region T3-a of the light emitting reset transistor T3 in the 2nth column of subpixels.
  • the active semiconductor layer for each transistor may include an integrally formed low temperature polysilicon layer.
  • the source region and the drain region of each transistor may be conductive by doping or the like to realize electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes doped region patterns (ie, source region s and drain region) and Active layer pattern.
  • the active layers of different transistors are separated by doping structures.
  • the active semiconductor layer 310 may be formed of amorphous silicon, polysilicon, oxide semiconductor materials, or the like.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the array substrate further includes a first conductive layer on a side of the active semiconductor layer away from the substrate.
  • FIG. 8 shows a schematic plan view of the first conductive layer 320 in the array substrate according to an embodiment of the present disclosure.
  • the first conductive layer 320 includes a first drive reset control signal line RO m , a first scan signal line SO m , a second scan signal line SE m , a first drive reset control signal line RO m , a second scan signal line SE m , and a capacitor C arranged in sequence along the column direction X pole CC1, emission control signal line E m, the first emission control signal line reset RO m + 1 and a second emission control signal line reset SO m + 1 / RE m + 1.
  • the first scan signal line SO m is used as the second drive reset control signal line RE m .
  • the first electrode CC1 of the capacitor C and the gate T2-g of the driving transistor are integrally formed.
  • the orthographic projection of the first driving reset control signal line RO m on the substrate overlaps with the orthographic projection of the first portion 311 of the active semiconductor layer 310 on the substrate
  • the part is the gates T7-g1 and T7-g2 of the drive reset transistor T7 in the 2n-1th column of sub-pixels.
  • the portion where the orthographic projection of the first scanning signal line SO m on the substrate overlaps with the orthographic projection of the first portion 311 , the second portion 312 and the fourth portion 314 of the active semiconductor layer 310 on the substrate is the 2n-th
  • the parts where the orthographic projection of the second scanning signal line SE m on the substrate and the orthographic projection of the fourth portion 314 of the active semiconductor layer 310 on the substrate overlap are the data writing transistors T1 in the 2nth column of sub-pixels, respectively.
  • the part where the orthographic projection of the first pole CC1 of the capacitor C on the substrate and the orthographic projection of the third part 313 of the active semiconductor layer 310 on the substrate in the 2n-1 column of sub-pixels overlap is the 2n-1 column of sub-pixels
  • the part where the orthographic projection of the first pole CC1 of the capacitor C on the substrate and the orthographic projection of the fourth portion 314 of the active semiconductor layer 310 on the substrate in the 2nth column of subpixels overlap is the driving in the 2nth column of subpixels Gate T2-g of transistor T2.
  • Emission control signal line E m is the orthogonal projection on a substrate portion 313 and fourth portion 314 overlap orthogonal projection on the substrate third portion 310 of the first active semiconductor layer are sub-pixels 2n-1 of The gate T5-g of the first light emission control transistor T5 and the gate T6-g of the second light emission control transistor T6 and the gate T5-g and the second light emission control transistor of the first light emission control transistor T5 in the 2nth column sub-pixel Gate T6-g of T6.
  • the portion where the orthographic projection of the first light-emitting reset control signal line RO m+1 on the substrate overlaps the orthographic projection of the third portion 313 of the active semiconductor layer 310 on the substrate is the light emission in the 2n-1th column of sub-pixels
  • the gate T3-g of the reset transistor T3 is reset.
  • the part where the orthographic projection of the second light-emitting reset control signal line SO m+1 /RE m+1 on the substrate overlaps with the orthographic projection of the fifth part 315 of the active semiconductor layer 310 on the substrate is the sub-pixel in the 2nth column
  • the gates T7-g1 and T7-g2 of the reset transistor T7 are driven for the sub-pixels of the m-th row and the 2n-1th column and the 2n-th column of the sub-pixels.
  • the gates T4-g1 and T4-g2 of the compensation transistor T4 and the gate T1-g of the data writing transistor T1 are located on the first side of the gate T2-g of the driving transistor T2.
  • the gate T5-g of the first light emission control transistor T5, the gate T6-g of the second light emission control transistor T6, and the gate T3-g of the light emission reset transistor T3 are located on the second side of the gate T2-g of the driving transistor T2 .
  • first side and the second side of the gate electrode T2-g of the driving transistor T2 are opposite sides in the row direction Y of the gate electrode T2-g of the driving transistor T2.
  • first side of the gate T2-g of the driving transistor T2 may be the upper side of the gate T2-g of the driving transistor T2.
  • the second side of the gate T2-g of the driving transistor T2 may be the lower side of the gate T2-g of the driving transistor T2.
  • the lower side is, for example, the side of the array substrate for binding ICs.
  • the lower side of the gate T2-g of the driving transistor T2 is the side of the gate T2-g of the driving transistor T2 close to the IC (not shown in the figure).
  • the upper side is the opposite side to the lower side, eg, the side away from the IC of the gate T2-g of the driving transistor T2.
  • the gates T7-g1, T7-g2 of the drive reset transistor T7 are located on the upper side of the gates T4-g1, T4-g2 of the compensation transistor T4 and the gate T1-g of the data writing transistor T1.
  • the gate T3-g of the light emission reset transistor T3 is located on the lower side of the gate T5-g of the first light emission control transistor T5 and the gate T6-g of the second light emission control transistor T6.
  • the gates T4-g1, T4-g2, the gate T6-g of the second light emission control transistor T6 and the gate T3-g of the light emission reset transistor T3 are located on the third side of the gate T2-g of the driving transistor T2.
  • the gate T1-g of the data writing transistor T1 and the gate T5-g of the first light emission control transistor T5 are located on the fourth side of the gate T2-g of the driving transistor T2.
  • the third and fourth sides of the gates T7-g1 and T7-g2 of the driving reset transistor T7 are opposite sides in the column direction X of the gate T2-g of the driving transistor T2.
  • the third side of the gate T2-g of the driving transistor T2 may be the left side of the gate T2-g of the driving transistor T2.
  • the fourth side of the gate T2-g of the driving transistor T2 may be the right side of the gate T2-g of the driving transistor T2.
  • the gates T4-g1, T4-g2 of the compensation transistor T4 are located on the left side of the gate T1-g of the data writing transistor T1.
  • the gate T5-g of the first light emission control transistor T5 is located to the right of the gate T6-g of the second light emission control transistor T6.
  • the third and fourth sides of the gate T2-g of the driving transistor T2 are opposite sides in the column direction X of the gate T2-g of the driving transistor T2.
  • the third side of the gate T2-g of the driving transistor T2 may be the left side of the gate T2-g of the driving transistor T2, and the gate T2-g of the driving transistor T2
  • the fourth side of can be the right side of the gate T2-g of the driving transistor T2.
  • the gates T4-g1, T4-g2 of the compensation transistor T4 are located to the right of the gate T1-g of the data writing transistor T1.
  • the gate T5-g of the first light emission control transistor T5 is located to the left of the gate T6-g of the second light emission control transistor T6.
  • the gates of the drive reset transistor T7 and the compensation transistor T4 in the 2n-1 column of sub-pixels are of a double-gate structure; and the drive reset transistor T7 and the compensation transistor T4 in the 2n-th column of sub-pixels have The gate is a double gate electrode.
  • the present disclosure is not limited thereto.
  • the transistor of the present disclosure can also adopt a single-gate structure, and those skilled in the art can choose according to actual needs.
  • the active regions of the respective transistors shown in FIG. 8 correspond to respective regions where the first conductive layer 320 and the active semiconductor layer 310 overlap.
  • the array substrate further includes a second conductive layer on a side of the first conductive layer away from the substrate.
  • FIG. 9 shows a schematic plan view of the second conductive layer 330 in the array substrate according to an embodiment of the present disclosure.
  • the second conductive layer 330 includes the second electrode CC2 of the capacitor disposed along the column direction X and the first power signal line VD m 1 as the first voltage source.
  • the projections of the second pole CC2 of the capacitor C and the first pole CC1 of the capacitor C on the substrate at least partially overlap.
  • the first power supply signal line VD m 1 extends in the row direction Y and is integrally formed with the second pole CC2 of the capacitor C. As shown in FIG. 9 , as shown in FIG. 9 , as shown in FIG. 9 , the first power supply signal line VD m 1 extends in the row direction Y and is integrally formed with the second pole CC2 of the capacitor C. As shown in FIG. 9 , as shown in FIG. 9 , as shown in FIG. 9 , as shown in FIG. 9 , as shown in FIG. 9 , as shown in FIG. 9 , the first power supply signal line VD m 1 extends in the row direction Y and is integrally formed with the second pole CC2 of the capacitor C. As shown in FIG.
  • the array substrate further includes a third conductive layer on a side of the second conductive layer away from the substrate.
  • FIG. 10 shows a schematic plan view of the third conductive layer 340 in the array substrate according to an embodiment of the present disclosure.
  • the third conductive layer 340 includes data signal lines D n and D n+1 , reset power signal lines V n , V n+1 , a second power signal line VD m 2 serving as a first voltage source,
  • the third power supply signal line VD m 3 as the first voltage source, the first connection part 341 , the second connection part 342 , the third connection part 343 , the fourth connection part 344 , the fifth connection part 345 , and the sixth connection part 346 .
  • the first connection part 341 , the second connection part 342 and the third connection part 343 are sequentially arranged along the row direction Y.
  • the fourth connection part 344 is provided on the lower side of the first connection part 341 , the second connection part 342 and the third connection part 343 in the column direction X.
  • the fifth connection part 345 and the sixth connection part 346 are sequentially arranged along the column direction X.
  • the sixth connection portion 346 is located on the lower side of the fifth connection portion 345 .
  • the via holes (not shown) described below are simultaneously penetrating between the active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, and in the second conductive layer 320. Via holes of each insulating layer or dielectric layer between the conductive layer 330 and the third conductive layer 340 .
  • one end 3411 of the first connection part 341 is coupled to the first pole T4 - 1 of the compensation transistor T4 of the 2n-1 column of sub-pixels through a via hole (for example, the first pole corresponds to the first pole of the transistor T4 - 1 ) source/drain regions, the description below is similar).
  • the other end 3412 of the first connection portion 341 is coupled to the second electrode T4-2 of the driving transistor T2 of the 2n-1 column of sub-pixels through a via hole (for example, the second electrode corresponds to the second source/drain region of the transistor, the following description is similar).
  • One end 3421 of the second connection portion 342 is coupled to the first electrode T7-1 of the driving reset transistor T7 and the second electrode T4-2 of the compensation transistor T4 of the 2n-1th column of sub-pixels through a via hole.
  • the other end 3422 of the second connection portion 342 is coupled to the gate T2-g of the driving transistor T2 of the 2n-1th column of sub-pixels and the first electrode CC1 of the capacitor C through a via hole.
  • One end 3431 of the third connection portion 343 is coupled to the second electrode T1-2 of the data writing transistor T1 of the 2n-1th column of sub-pixels through a via hole.
  • the other end 3432 of the third connection portion 343 is coupled to the first electrode T2-1 of the driving transistor T2 of the 2n-1th column of sub-pixels through a via hole.
  • the fourth connection portion 344 is coupled to the second electrode T6-2 of the second light-emitting control transistor T6 and the first electrode T3-1 of the light-emitting reset transistor T3 of the 2n-1th column of sub-pixels through a via hole.
  • One end 3451 of the fifth connection portion 345 is coupled to the first electrode T7-1 of the driving reset transistor T7 and the second electrode T4-2 of the compensation transistor T4 of the 2nth column of sub-pixels through a via hole.
  • the other end 3452 of the fifth connection portion 345 is coupled to the gate T2-g of the driving transistor T2 of the 2nth column of sub-pixels and the first electrode CC1 of the capacitor C through a via hole.
  • One end 3461 of the sixth connection portion 346 is coupled to the second electrode T6 - 2 of the second light-emitting control transistor T6 of the 2nth column of sub-pixels through a via hole.
  • the other end 3462 of the sixth connection portion 346 is coupled to the first electrode T3 - 1 of the light-emitting reset transistor T3 of the 2nth column of sub-pixels through a via hole.
  • the data signal line Dn is coupled to the first electrode T1-1 of the data writing transistor T1 of the 2n-1th column of sub-pixels and the data of the 2n-th column of sub-pixels through via holes Write the first pole T1-1 of the transistor T1.
  • the white box marked on the data signal line D n represents the area corresponding to the via hole.
  • the reset power signal line V n+1 has a first protrusion V n+1 ⁇ 1 and a second protrusion V n+1 ⁇ , which are arranged in the column direction X. 2.
  • the third protrusions Vn +1-3 and the fourth protrusions Vn +1-4 extend from the reset power signal line Vn +1 toward the 2nth column of subpixels.
  • the third protrusions Vn +1-3 and the fourth protrusions Vn +1-4 extend from the reset power supply signal line Vn +1 toward the 2n+1th column of subpixels.
  • the first protrusion V n+1 -1 is located on the upper side of the fifth connection portion 345 .
  • the second protruding portion V n+1 -2 is located on the lower side of the sixth connecting portion 346 .
  • the third protrusions V n+1 -3 are located on the upper side of the first connecting part 341 and on the left side of one end 3421 of the second connecting part 342 .
  • the fourth protrusions Vn +1-4 are located on the lower side of the fourth connection portion. It should be noted that the description of the sub-pixels in the 2n+1th column can also be applied to the description of the sub-pixels in the 2n-1th column.
  • the first protrusion V n+1 -1 is coupled to the first pole T7 - 1 of the driving reset transistor T7 of the 2nth column of sub-pixels through a via hole.
  • the second protrusions Vn +1-2 are coupled to the second poles T3-2 of the light-emitting reset transistors T3 of the 2nth column of sub-pixels through via holes.
  • the third protrusions Vn +1-3 are coupled to the second poles T7-2 of the drive reset transistors T7 of the 2n+1th column of sub-pixels through via holes.
  • the fourth protrusions Vn +1-4 are coupled to the second poles T3-2 of the light-emitting reset transistors T3 of the 2n+1th column of sub-pixels through via holes.
  • the second power signal line VD m 2 extends along the column direction X and is located in the 2n-1th column of sub-pixels.
  • the second power signal line VD m 2 is located between the first connection part 341 , the second connection part 342 , the third connection part 343 and the fourth connection part 344 and the data line D n .
  • the second power signal line VD m 2 is coupled to the second electrode CC2 of the capacitor C of the 2n-1 column of sub-pixels and the first electrode T5- 1.
  • the white box marked on the second power signal line VD m 2 represents the area corresponding to the via hole.
  • the third power signal line VD m 3 extends along the column direction X and is located in the 2nth column of sub-pixels.
  • the third power signal line VD m 3 is coupled to the second electrode CC2 of the capacitor C of the 2n-th column sub-pixel and the first electrode T5 - 1 of the first light emission control transistor T5 via a via hole.
  • plotted on the third power supply signal line VD m 3 white box represents the area corresponding to the via.
  • the second conductive layer 330 ′ further includes a first additional reset power signal line Va1 and a second additional reset power signal line Va1 extending along the row direction Y
  • the power supply signal line Va2 is reset.
  • the second electrode of the capacitor C and the first power supply signal line CC2 VD m 1 is located in the column direction X of the first additional signal line reset power reset power source Va1 and a second additional signal between line Va2.
  • the first additional reset power supply signal line Va1 is located on the upper side of the second pole CC2 of the capacitor C.
  • the second additional reset power supply signal line Va2 is located on the lower side of the second pole CC2 of the capacitor C.
  • the array substrate further includes a third conductive layer located on a side of the second conductive layer away from the substrate.
  • FIG. 12 shows a schematic plan view of the third conductive layer 340 ′ in the array substrate according to an embodiment of the present disclosure.
  • the third conductive layer 340 ′ includes data signal lines D n , D n+1 , reset power signal lines V n ′, V n+1 ′, and a second power signal line VD serving as a first voltage source m 2, the third power supply signal line VD m 3 as the first voltage source, the first connection part 341, the second connection part 342, the third connection part 343, the fourth connection part 344, the fifth connection part 345, the sixth connection part 345
  • the seventh connection part 347 is located on the upper side of the first connection part 341 , the second connection part 342 and the third connection part 343 .
  • the eighth connection portion 348 is located on the lower side of the fourth connection portion 344 .
  • the ninth connection part 349 is located on the upper side of the fifth connection part 345 .
  • the tenth connection part 3410 is located on the left side of the sixth connection part 346 .
  • between the active semiconductor layer 310 and the first conductive layer 320 , between the first conductive layer 320 and the second conductive layer 330 ′, and between the second conductive layer 330 ' and the third conductive layer 340' are further provided with an insulating layer/dielectric layer (which will be described in detail later with respect to the cross-sectional view).
  • the via holes (not shown) described below are simultaneously penetrating between the active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330', and in the first conductive layer 320'. Via holes of each insulating layer/dielectric layer between the second conductive layer 330' and the third conductive layer 340'.
  • one end 3471 of the seventh connection part 347 is coupled to the first additional reset power signal line Va1 through a via hole.
  • the other end 3472 of the seventh connection portion 347 is coupled to the second pole T7-2 of the drive reset transistor T7 of the 2n-1th column of sub-pixels through a via hole.
  • One end 3481 of the eighth connection portion 348 is coupled to the second additional reset power signal line Va2 through a via hole.
  • the other end 3481 of the eighth connection portion 348 is coupled to the second electrode T3-2 of the light-emitting reset transistor T3 of the 2n-1th column of sub-pixels through a via hole.
  • One end 3491 of the ninth connection portion 349 is coupled to the first additional reset power signal line Va1 through a via hole.
  • the other end 3492 of the ninth connection portion 349 is coupled to the second pole T7 - 2 of the drive reset transistor T7 of the 2nth column of sub-pixels through a via hole.
  • One end 34101 of the tenth connection portion 3410 is coupled to the second additional reset power signal line Va2 through a via hole.
  • the other end 34102 of the tenth connection portion 3410 is coupled to the second pole T3-2 of the light-emitting reset transistor T3 of the 2nth column of sub-pixels through a via hole.
  • the reset power signal line V n+1 ′ is coupled to the first additional reset power signal line Va1 and the second additional reset power signal line Va2 via vias.
  • the white box marked on the reset power signal line Vn+1' represents the area corresponding to the via hole.
  • the array substrate further includes a fourth conductive layer located on a side of the third conductive layer away from the substrate.
  • FIG. 13 shows a schematic plan view of the fourth conductive layer 350 in the array substrate according to an embodiment of the present disclosure.
  • the fourth conductive layer 350 includes a fourth power signal line VD m 4 as a first voltage source, an eleventh connection portion 351 and a twelfth connection portion 352 .
  • the fourth power supply signal lines VD m 4 are distributed across the column direction X and the row direction Y.
  • a second power supply signal line VD m 2 and the orthogonal projection of the fourth power supply signal line VD m 4 orthogonal projection on a substrate on a substrate at least partially overlap.
  • a third power supply signal line VD m 3 orthogonal projection of the fourth power supply signal line VD m 4 orthogonal projection on a substrate on a substrate at least partially overlap.
  • an insulating layer/dielectric layer (which will be described in detail later with respect to the cross-sectional view) is provided between the third conductive layer 340/340' and the fourth conductive layer 350.
  • vias (not shown) described below are vias in the insulating/dielectric layer between the third conductive layer 340/340' and the fourth conductive layer 350.
  • the fourth power supply signal line VD m 4 via the through-hole coupled to the second power supply signal line VD m 2 and the third power supply signal line VD m 3.
  • indicated on the fourth power supply signal line VD m 4 black blocks represent the area corresponding to the via.
  • the eleventh connection part 351 is coupled to the fourth connection part 344 and the light emitting device (not shown) of the 2n-1th column of sub-pixels via via holes
  • the first electrode of the light-emitting device is coupled to the second electrode T6-2 of the second light-emitting control transistor T6 and the first electrode T3-1 of the light-emitting reset transistor T3 of the 2n-1th column of sub-pixels.
  • the twelfth connection part 352 is coupled to one end 3461 of the sixth connection part 346 and the light emitting device (not shown) of the 2nth column of sub-pixels via a via hole
  • the first pole of the light emitting device is coupled to the second pole T6-2 of the second light emitting control transistor T6 and the first pole T3-1 of the light emitting reset transistor T3 of the 2nth column of sub-pixels.
  • the material of the fourth conductive layer 350 may be the third conductive layer 340/340 'of the second power supply signal line VD m 2 and the material of the third power supply signal line VD m 3 are the same.
  • FIG. 14 and 15 illustrate schematic plan layouts of stacked active semiconductor layers, first conductive layers, second conductive layers, third conductive layers, and fourth conductive layers.
  • the diagram shown in FIG. 14 is based on the structures of FIGS. 9 and 10 .
  • the data signal line Dn is coupled to the first electrode T1-1 of the data writing transistor T1 of the 2n-1th column of sub-pixels through the via 340-1, and is coupled to the 2nth through the via 340-2.
  • the data of the column sub-pixels is written into the first pole T1-1 of the transistor T1.
  • a reset power supply signal line of the first projecting portion V n + V n 1 + 1-1 via the through hole 340-3 is coupled to the first sub-pixels 2n of driving the reset transistor T4-2 T7 of the second electrode.
  • Reset power supply signal line of the second projecting portion V n + V n 1 + 1-2 via the through 340-4 is coupled to the first sub-pixels emitting hole 2n reset transistor T3-2 T3 of the second electrode.
  • Reset power supply signal line of the third projecting portion V n + V n + 1 -3 1 via the through hole 340-5 is coupled to the first sub-pixels 2n + 1 driving the reset transistor of the second electrode T7-2 T7.
  • Reset signal supply line V n + fourth projecting portion V n + 1 -4 1 via the through hole 340-6 is coupled to the first sub-pixels 2n + 1 of light emission of the reset transistor of the second electrode T3-2 T3.
  • vias 340-1, 340-2, 340-3, 340-4, 340-5, and 340-6 shown in 14 are all provided in the insulating layer/dielectric (described later with respect to the cross-sectional view). )middle.
  • a data line is provided between the odd-column sub-pixels (eg, the 2n-1 th column sub-pixels) and the even-column sub-pixels (eg, the 2n-th column sub-pixels) adjacent to each other and by dividing the data signal into The odd-column sub-pixels and the even-column sub-pixels are sequentially written, so that data lines can be shared. Therefore, the number of data lines in the pixel circuit can be reduced, the difficulty of wiring layout can be reduced, and the PPI can be improved.
  • the even-column sub-pixels adjacent to each other for example, the 2nth A reset power supply signal line is shared between sub-pixels in columns) and sub-pixels in odd columns (eg, sub-pixels in the 2n-1th column), thereby further reducing the number of wirings in the pixel circuit and further improving the PPI.
  • the diagram shown in FIG. 15 is based on the structures of FIGS. 11 and 12 .
  • the data signal line Dn is coupled to the first electrode T1-1 of the data writing transistor T1 of the 2n-1 column of sub-pixels through the via hole 340'-1, and is coupled to the data of the 2n-th column of sub-pixels through the via hole 340'-2 Write the first pole T1-1 of the transistor T1.
  • the reset power signal line V n+1 ′ is coupled to the first additional reset power signal line Va1 through the via hole 340 ′-3 , and is further coupled to the 2n+1th column through the first additional reset power signal line Va1 and the seventh connection portion 347
  • the second pole T7-2 of the drive reset transistor T7 in the sub-pixels of (the same applies to the sub-pixels in the 2n-1th column) is driven.
  • the reset power signal line V n+1 ′ is coupled to the second additional reset power signal line Va2 through the via hole 340 ′-4 , and is further coupled to the sub-pixels in the 2nth column through the second additional reset power signal line Va2 and the tenth connection portion 3410
  • the second pole T3-2 of the light-emitting reset transistor T3 is coupled.
  • vias 340'-1, 340'-2, 340'-3 and 340'-4 shown in 15 are all provided in the insulating layer/dielectric layer (described later with respect to the cross-sectional view).
  • a data line is provided between the odd-column sub-pixels (eg, the 2n-1 th column sub-pixels) and the even-column sub-pixels (eg, the 2n-th column sub-pixels) adjacent to each other and by dividing the data signal into The odd-column sub-pixels and the even-column sub-pixels are sequentially written, so that data lines can be shared. Therefore, the number of data lines in the pixel circuit can be reduced, the difficulty of wiring layout can be reduced, and the PPI can be improved.
  • the This implementation shares a reset power signal line between the even-column sub-pixels (eg, the 2n-th column sub-pixels) and the odd-column sub-pixels (eg, the 2n-1-th column sub-pixels) that are adjacent to each other, thereby further reducing the number of wirings in the pixel circuit , and further improve the PPI.
  • even-column sub-pixels eg, the 2n-th column sub-pixels
  • the odd-column sub-pixels eg, the 2n-1-th column sub-pixels
  • the first electrode (ie, the first source/drain region) and the second electrode (ie, the second source/drain region) of the transistor used in the embodiments of the present disclosure may be the same in structure.
  • FIG. 16 shows a schematic cross-sectional structure diagram of the array substrate taken along the line A1A1' in FIG. 14 according to an embodiment of the present disclosure.
  • the array substrate 20 includes: a substrate 300 ; a buffer layer 101 on the substrate 300 ; and an active semiconductor layer 310 on the buffer layer 101 .
  • the cross-sectional view shows the active region T4-a of the compensation transistor T4 and the active region T1-a of the data writing transistor T1 of the sub-pixel in the 2n-1th column included in the active semiconductor layer 310 and the driving of the sub-pixel in the 2n-th column
  • the active region T7-a of the reset transistor T7 is the active region of the reset transistor T7.
  • the array substrate 20 further includes: a first gate insulating layer 102 covering the buffer layer 101 and the active semiconductor layer 310 ; and a first gate insulating layer 102 located away from the liner The first conductive layer 320 on one side of the bottom 300 .
  • the cross section shows the first scan signal line SO m included in the first conductive layer 320 .
  • the first scan signal line SO m is a scan signal line for the 2n-1 column of sub-pixels.
  • the first scan signal line SO m is also a second drive reset control signal line RE m for the sub-pixels in the 2nth column. The following selection is described with the name first scan signal line SO m .
  • the orthographic projection of the first scan signal line SO m on the substrate 300 corresponds to the active region T4 - a of the compensation transistor T4 of the sub-pixel in the 2n-1 column included in the active semiconductor layer 310 and the data write
  • the active region T1-a of the input transistor T1 and the active region T7-a of the drive reset transistor T7 of the 2n-th column of sub-pixels are used as compensation transistors for the 2n-1th column of sub-pixels, respectively, where the orthographic projections of the active region T7-a of the sub-pixel T7-a overlap on the substrate 300.
  • the array substrate 20 further includes: a second gate insulating layer 103 located on the side of the first conductive layer 320 away from the substrate 300 ; the second gate insulating layer 103 The interlayer insulating layer 104 on the side away from the substrate 300 ; and the third conductive layer 340 on the side away from the substrate 300 of the interlayer insulating layer 104 .
  • the cross-sectional view shows the reset power signal lines V n , V n+1 , the second connection part 342 , the second power signal line VD m 2 , the data signal line D n and the third power signal included in the third conductive layer 340 Line VD m 3. As shown in FIG.
  • the data signal line Dn is located between the sub-pixels in the 2n-1th column and the sub-pixels in the 2nth column.
  • Reset signal supply line V n 2n-1 may be located in the first sub-pixels and the second sub-pixels 2n-2.
  • the reset power signal line V n+1 may be located between the sub-pixels in the 2n-th column and the sub-pixels in the 2n+1-th column.
  • the array substrate 20 further includes: a dielectric layer 105 covering the interlayer insulating layer 104 and the third conductive layer 340 ; The fourth conductive layer 350 .
  • the dielectric layer 105 may include a passivation layer and a first planarization layer (not shown in the figure) on the passivation layer.
  • the cross-sectional view shows the fourth power supply signal line VD m 4 included in the fourth conductive layer 350 . As shown in FIG.
  • the orthographic projection of the second power line VD m 2 on the substrate 300 and the orthographic projection of the third power line VD m 3 on the substrate 300 included in the third conductive layer 340 are the same as the fourth conductive layer 350 Orthographic projections of the included fourth power supply signal line VD m 4 on the substrate 300 overlap.
  • the array substrate 20 further includes: a second planarization layer 105 covering the dielectric layer 105 and the fourth conductive layer 350 ; and a second planarization layer 105 located away from the substrate Pixel definition layer 107 on one side of 300 .
  • FIG. 17 shows a schematic cross-sectional structure diagram of the array substrate taken along the line A2A2' in FIG. 15 according to an embodiment of the present disclosure.
  • the cross-sectional view shown in FIG. 17 is similar in structure to that in FIG. 16 , except for the fourth conductive layer 340 ′.
  • the fourth conductive layer 340 ′ includes the reset power signal lines V n ′, V n+1 ′, the second connection part 342 , the second power signal line VD m 2 , the data signal line D n and the
  • a ninth connection portion 349 is also included.
  • the ninth connection portion 349 reference may be made to the above description of FIG. 12 , and details are not repeated here.
  • FIG. 18 shows a schematic cross-sectional structure diagram of the array substrate taken along the line B1B1' in FIG. 14 according to an embodiment of the present disclosure. This figure can also be used as a schematic diagram of the cross-sectional structure of the array substrate taken along the line B2B2' in 15. It should be noted that the cross-sectional view is also applicable to the sub-pixels of the m-th row and the 2n-2th column and the 2n-1th column of the sub-pixels.
  • the array substrate 20/20' includes: a substrate 300; a buffer layer 101 on the substrate 300; and an active semiconductor layer 310 on the buffer layer 101.
  • the cross-sectional view shows the first electrode T1-1 of the data writing transistor T1 of the sub-pixel in the 2n-1 column and the first electrode T1-1 of the data writing transistor T1 of the sub-pixel in the 2n-th column included in the active semiconductor layer 310 .
  • the array substrate 20 / 20 ′ further includes: a first gate insulating layer 102 covering the buffer layer 101 and the active semiconductor layer 310 ; and a first gate insulating layer located on the first gate insulating layer 102 is the first conductive layer 320 on the side away from the substrate 300 .
  • the cross section shows the first scan signal line SO m included in the first conductive layer 320 .
  • the first scan signal line SO m is a scan signal line for the 2n-1 column of sub-pixels.
  • the first scan signal line SO m is also a second drive reset control signal line RE m for the sub-pixels in the 2nth column.
  • the array substrate 20/20' further includes: a second gate insulating layer 103 covering the first gate insulating layer 102 and the first scan signal line SO m; The interlayer insulating layer 104 on the side of the second gate insulating layer 103 away from the substrate 300 ; and the third conductive layer 340 / 340 ′ on the side of the interlayer insulating layer 104 away from the substrate 300 .
  • the cross-sectional view shows the second power signal line VD m 2 , the data signal line D n and the third power signal line VD m 3 included in the third conductive layer 340 / 340 ′. As shown in FIG.
  • the data signal line D n is located between the sub-pixels in the 2n-1th column and the sub-pixels in the 2n-th column.
  • the data signal line Dn passes through the via holes 340-1/340'-1 and the via holes 340-2/340'-2 passing through the first gate insulating layer 102, the second gate insulating layer 103 and the interlayer insulating layer 104 They are respectively connected to the first pole T1-1 of the data writing transistor T1 of the 2n-1 column of sub-pixels and the first pole T1-1 of the data writing transistor T1 of the 2n-th column of sub-pixels, so that the 2n-1 column of sub-pixels and One data signal line D n is shared among the sub-pixels in the 2nth column.
  • the array substrate 20 / 20 ′ further includes: a dielectric layer 105 covering the interlayer insulating layer 104 and the third conductive layer 340 / 340 ′; The fourth conductive layer 350 on the side of the substrate 300 .
  • the dielectric layer 105 may include a passivation layer and a first planarization layer (not shown in the figure) on the passivation layer.
  • the cross-sectional view shows the fourth power supply signal line VD m 4 included in the fourth conductive layer 350 . As shown in FIG.
  • the orthographic projection of the second power line VD m 2 on the substrate 300 and the orthographic projection of the third power line VD m 3 on the substrate 300 included in the third conductive layer 340 / 340 ′ are the same as the fourth power line VD m 2 on the substrate 300
  • a fourth power supply signal line VD m 4 is connected to the third conductive layer 353 through a via dielectric layer 105 and vias 354 are 340/340 'second power supply line VD m 2 and comprising a third power supply line VD m 3.
  • the array substrate 20 / 20 ′ further includes: a second planarization layer 105 covering the dielectric layer 105 and the fourth conductive layer 350 ; The pixel definition layer 107 on the side away from the substrate 300 .
  • FIG. 19 shows a schematic cross-sectional structure diagram of the array substrate taken along the line C1C1' in FIG. 14 according to an embodiment of the present disclosure. It should be noted that the cross-sectional view is for the sub-pixels in the m-th row and the 2n-th column and the 2n+1-th sub-pixels in the array substrate. It should be noted that the cross-sectional view is also applicable to the sub-pixels of the m-th row and the 2n-2th column and the 2n-1th column of the sub-pixels.
  • the array substrate 20 includes: a substrate 300 ; a buffer layer 101 on the substrate 300 ; and an active semiconductor layer 310 on the buffer layer 101 .
  • the cross-sectional view shows the first electrode T7-1 of the drive reset transistor T7 of the 2nth column sub-pixel and the second electrode T3-2 of the light-emitting reset transistor T3 of the 2n+1th column of subpixels included in the active semiconductor layer 310.
  • the array substrate 20 further includes: a first gate insulating layer 102 covering the buffer layer 101 and the active semiconductor layer 310 ; and a first gate insulating layer 102 located away from the liner The first conductive layer 320 on one side of the bottom 300 .
  • the cross section shows the second scan signal line SE m and the light emission control signal line E m included in the first conductive layer 320 .
  • the array substrate 20 further includes: a second gate insulating layer 103 covering the first gate insulating layer 102 and the first conductive layer 320 ; and a second gate insulating layer located on the second gate insulating layer 103 ; The second conductive layer 330 on the side of the layer 103 away from the substrate 300 .
  • the cross section shows the first power supply signal line VD m 1 included in the second conductive layer 330 .
  • the array substrate 20 further includes: an interlayer insulating layer 104 covering the second gate insulating layer 103 and the second conductive layer 330 ; and an interlayer insulating layer 104 located away from the liner
  • the third conductive layer 340 on one side of the bottom 300 .
  • the cross-sectional view shows the reset power signal line V n+1 included in the third conductive layer 340 .
  • Reset signal supply line V n + V n 1 of the fourth projecting portion of + 1-4 via the gate insulating layer 102 through the first, second through-hole between the gate insulating layer 103 and the interlayer insulating layer 104 is connected 340-6 To the second pole T3-2 of the light-emitting reset transistor T3 of the 2n+1th column of sub-pixels.
  • the reset voltage can be supplied to the 2nth column subpixel (or 2n-2th column subpixel) and the 2n+1th column subpixel (or 2n-1th column subpixel) through only one reset power signal line Vn +1.
  • the array substrate 20 further includes: a dielectric layer 105 located on a side of the third conductive layer 340 away from the substrate 300 ; and a dielectric layer 105 located on a side away from the substrate 300 the fourth conductive layer 350 on the side.
  • the dielectric layer 105 may include a passivation layer and a first planarization layer (not shown in the figure) on the passivation layer.
  • the cross-sectional view shows the fourth power supply signal line VD m 4 included in the fourth conductive layer 350 .
  • the array substrate 20 further includes: a second planarization layer 105 covering the dielectric layer 105 and the fourth conductive layer 350 ; and a second planarization layer 105 located away from the substrate Pixel definition layer 107 on one side of 300 .
  • FIG. 20 shows a schematic cross-sectional structure diagram of the array substrate taken along the line C2C2' in FIG. 15 according to an embodiment of the present disclosure. It should be noted that the cross-sectional view is for the sub-pixels in the m-th row and the 2n-th column and the 2n+1-th sub-pixels in the array substrate. It should be noted that the cross-sectional view is also applicable to the sub-pixels of the m-th row and the 2n-2th column and the 2n-1th column of the sub-pixels.
  • the array substrate 20 ′ includes: a substrate 300 ; a buffer layer 101 on the substrate 300 ; and an active semiconductor layer on the buffer layer 101 310.
  • the cross-sectional view shows the first electrode T7-1 and the active region T7-a of the driving reset transistor T7 of the 2nth column of sub-pixels included in the active semiconductor layer 310 and the first electrode T7-a of the light-emitting reset transistor T3 of the 2n+1th column of sub-pixels.
  • the array substrate 20 ′ further includes: a first gate insulating layer 102 covering the buffer layer 101 and the active semiconductor layer 310 ; and a first gate insulating layer 102 located away from the first gate insulating layer 102
  • the first conductive layer 320 on one side of the substrate 300 .
  • the cross section shows a first scanning signal line SO m included in the first conductive layer 320, a first control signal driving the reset line RO m, SE m second scanning signal line and the light emission control signal line E m.
  • the first scan signal line SO m located in the sub-pixel in the 2nth column can be used as the gate T7-g2 of the driving reset transistor T7 of the sub-pixel in the 2nth column.
  • the first scan signal line SO m is also a second drive reset control signal line RE m for the sub-pixels in the 2nth column.
  • the array substrate 20 ′ further includes: a second gate insulating layer 103 covering the first gate insulating layer 102 and the first conductive layer 320 ; and a second gate insulating layer 103 located on the second gate The second conductive layer 330 ′ on the side of the insulating layer 103 away from the substrate 300 .
  • the cross section shows the first power signal line VD m 1 , the first additional reset power signal line Va1 and the second additional reset power signal line Va2 included in the second conductive layer 330 ′.
  • the array substrate 20 ′ further includes: an interlayer insulating layer 104 covering the second gate insulating layer 103 and the second conductive layer 330 ′; and an interlayer insulating layer 104 located on the interlayer insulating layer 104 .
  • the third conductive layer 340 ′ on the side away from the substrate 300 .
  • the cross-sectional view shows the reset power signal line V n+1 ′, the eighth connection part 348 and the ninth connection part 349 included in the third conductive layer 340 ′.
  • One end 3481 of the eighth connection portion 348 is coupled to the second additional reset power signal line Va2 included in the second conductive layer 330 via the via hole 340 ′- 7 in the interlayer insulating layer 104 .
  • the other end 3482 of the eighth connection portion 348 is coupled to the 2n+1th column sub-pixels (or The second pole T3-2 of the light-emitting reset transistor T3 of the 2n-1th column of sub-pixels).
  • One end 3491 of the ninth connection portion 349 is coupled to the first additional reset power signal line Va1 included in the second conductive layer 330 via the via hole 340 ′- 6 in the interlayer insulating layer 104 .
  • the other end 3492 of the ninth connection portion 349 is coupled to the 2nth column sub-pixel (or the 2nth column) via the via hole 340 ′-5 penetrating the first gate insulating layer 102 , the second gate insulating layer 103 and the interlayer insulating layer 104 . -2 columns of sub-pixels) drive the first pole T7-1 of the reset transistor T7.
  • the reset power signal line V n+1 ′ is coupled to the first additional reset power signal line Va1 included in the second conductive layer 330 via the vias 340 ′- 3 in the interlayer insulating layer 104 , and thus coupled via the ninth connection portion 349
  • the first pole T7-1 of the reset transistor T7 is driven by the sub-pixels in the 2nth column (or the subpixels in the 2n-2th column).
  • the reset power signal line V n+1 ′ is also coupled to the second additional reset power signal line Va2 included in the second conductive layer 330 via the via holes 340 ′- 4 in the interlayer insulating layer 104 , and thus coupled via the eighth connection portion 348 Connected to the second pole T3-2 of the light-emitting reset transistor T3 of the 2n+1 column of sub-pixels (or of the 2n-1 column of sub-pixels).
  • the reset voltage to the sub-pixels in the 2nth column (or the sub-pixels in the 2n-2th column) and the sub-pixels in the 2n+1th column (or the sub-pixels in the 2n-1th column) through only one reset power signal line Vn+1'. .
  • the array substrate 20 ′ further includes: a dielectric layer 105 located on a side of the third conductive layer 340 ′ away from the substrate 300 ; and a dielectric layer 105 located away from the substrate
  • the fourth conductive layer 350 on the side of 300 may include a passivation layer and a first planarization layer (not shown in the figure) on the passivation layer.
  • the cross-sectional view shows the fourth power supply signal line VD m 4 included in the fourth conductive layer 350 .
  • the array substrate 20 ′ further includes: a second planarization layer 105 covering the dielectric layer 105 and the fourth conductive layer 350 ; and a spacer away from the second planarization layer 105 The pixel definition layer 107 on one side of the bottom 300 .
  • the substrate 300 may include a flexible substrate.
  • the substrate 300 may include a first polyimide layer, a first silicon oxide layer, a second polyimide layer, and a second silicon dioxide layer that are sequentially stacked.
  • Embodiments of the present disclosure also provide a display panel including the array substrate according to any embodiment of the present disclosure.
  • FIG. 21 shows a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 700 may include the array substrate 20/20' according to any embodiment of the present disclosure.
  • the display panel 700 may further include other components, such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc., for example, these components may use existing conventional components, which will not be described in detail here.
  • the display panel 700 may be a rectangular panel, a circular panel, an oval panel, a polygonal panel, or the like.
  • the display panel 700 can be not only a flat panel, but also a curved panel, or even a spherical panel.
  • the display panel 700 may also have a touch function, that is, the display panel 700 may be a touch display panel.
  • Embodiments of the present disclosure also provide a display device including the display panel according to any embodiment of the present disclosure.
  • FIG. 22 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display device 800 may include the display panel 700 according to any embodiment of the present disclosure.
  • the display device 800 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display panels and display devices provided by the embodiments of the present disclosure have the same or similar beneficial effects as the array substrates provided by the foregoing embodiments of the present disclosure. Since the array substrates have been described in detail in the foregoing embodiments, they will not be repeated here.

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Abstract

阵列基板及相关显示面板和显示装置。阵列基板包括：多对扫描信号线（SO/SE），第m对扫描信号线（SOm/SEm）的第一扫描信号线（SOm）被配置为向第m行子像素的第2n-1列子像素（P2n-1）提供第一扫描信号；多对驱动复位控制信号线（RO/RE），第m对驱动复位控制信号线（ROm/REm）的第二驱动复位控制信号线（REm）被配置为向第m行子像素的第2n列子像素（P2n）提供第二驱动复位控制信号。m和n为大于等于1的整数。第m对扫描信号线（SOm/SEm）的第一扫描信号线（SOm）与第m对驱动复位控制信号线（ROm/REm）的第二驱动复位控制信号线（REm）为同一信号线。

Description

阵列基板及其显示面板和显示装置 技术领域
本公开的实施例涉及显示技术领域，特别地，涉及一种阵列基板及其显示面板和显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode,OLED)显示面板具有自发光、高效率、色彩鲜艳、轻薄省电、可卷曲以及使用温度范围宽等优点，已经逐步应用于大面积显示、照明以及车载显示等领域。
发明内容
本公开的实施例提供了阵列基板及相关的显示面板和显示装置。
根据本公开的第一方面，提供了一种阵列基板，其包括衬底。该阵列基板还包括设置在衬底上的像素阵列，包括排布为多行多列的多个子像素。每个子像素具有像素电路和耦合到像素电路的数据信号输入端、扫描信号输入端、驱动复位控制信号输入端。该像素电路包括数据写入电路、驱动电路和驱动复位电路。该驱动电路包括控制端、第一端和第二端。该数据写入电路耦接数据信号输入端、扫描信号输入端以及驱动电路的第一端，并被配置为在扫描信号的控制下将数据信号提供给驱动电路的第一端。该驱动电路被配置为向发光器件提供驱动电流。该驱动复位电路耦接驱动复位控制信号输入端、驱动电路的控制端和复位电压源，并被配置为在驱动复位控制信号的控制下对驱动电路的控制端进行复位。该阵列基板还包括多对扫描信号线。该多对扫描信号线沿行方向延伸且沿列方向彼此间隔设置。该多对扫描信号线中的每对包括第一扫描信号线和第二扫描信号线。第m对扫描信号线与第m行子像素对应，m为大于等于1的整数。第m对扫描信号线的第一扫描信号线被配置为向第m行子像素的第2n-1列子像素的扫描输入端提供第一扫描信号，n为大于等于1的整数，以及第m对 扫描信号线的第二扫描信号线被配置为向第m行的第2n列子像素述扫描信号输入端提供第二扫描信号。该阵列基板还包括多对驱动复位控制信号线。该多对多对驱动复位控制信号线沿行方向延伸且沿列方向彼此间隔设置。该多对驱动复位控制信号线中的每对包括第一驱动复位控制信号线和第二驱动复位控制信号线。第m对驱动复位控制信号线与第m行子像素对应。第m对驱动复位控制信号线的第一驱动复位控制信号线被配置为向第m行子像素的第2n-1列子像素的驱动复位控制信号输入端提供第一驱动复位控制信号，以及第m对驱动复位控制信号线的第二驱动复位控制信号线被配置为向第m行子像素的第2n列子像素的驱动复位控制信号输入端提供第二驱动复位控制信号。第m对扫描信号线的第一扫描信号线与第m对驱动复位控制信号线的第二驱动复位控制信号线为同一信号线。
在本公开的实施例中，数据写入电路可以包括数据写入晶体管。驱动复位电路可以包括驱动复位晶体管。该数据写入晶体管的第一极可以与数据输入端耦接，该数据写入晶体管的第二极可以与驱动电路的第一端耦接，该数据写入晶体管的控制极可以与扫描信号端耦接。该驱动复位晶体管的第一极可以与驱动电路的控制端耦接，该驱动复位晶体管的第二极可以与复位电压端耦接，该驱动复位晶体管的栅极可以与驱动复位控制信号输入端耦接。第m对扫描信号线的第一扫描信号线可以包括第m行子像素的第2n-1列子像素的数据写入晶体管的栅极以及第m行子像素的第2n列子像素的驱动复位晶体管的栅极。
在本公开的实施例中，像素电路还可以包括补偿电路，其可以耦接驱动电路的第二端、驱动电路的控制端、和扫描信号输入端，并被配置为根据扫描信号，对驱动电路进行阈值补偿。
在本公开的实施例中，该补偿电路可以包括补偿晶体管。该补偿晶体管的第一极可以与驱动电路的第二端耦接，该补偿晶体管的第二极可以与驱动电路的控制端耦接，该补偿晶体管的栅极可以与扫描信号输入端耦接。第m对扫描信号线的第一扫描信号线还可以包括第m行子像素的第2n-1列子像素的补偿晶体管的栅极。
在本公开的实施例中，像素电路还可以包括存储电路。该存储电路可以耦接第一电压源和驱动电路的控制端，被配置为存储第一电压源与驱动电路的控制端之间的电压差。
在本公开的实施例中，子像素还可以包括发光控制信号端。像素电路还可以包括发光控制电路。该发光控制电路可以耦接发光控制信号端、第一电压端、驱动电路和发光器件，被配置为将来自第一电压源的第一电压施加至驱动电路，且将该驱动电路产生的驱动电流施加至发光器件。
在本公开的实施例中，阵列基板还可以包括多个发光控制信号线。该多个发光控制信号沿列方向延伸，且沿行方向彼此间隔。第m条发光控制信号线被配置为与第m行子像素的发光控制信号端耦接以提供发光控制信号。
在本公开的实施例中，子像素还可以包括发光复位控制信号输入端。像素电路还包括发光复位电路。该发光复位电路耦接发光复位控制信号输入端、复位电压端和发光器件，并被配置为在发光复位控制信号的控制下复位发光器件。
在本公开的实施例中，阵列基板还可以包括多对发光复位控制信号线。该多对发光复位控制信号线沿行方向延伸且沿列方向彼此间隔设置。该多对发光复位控制信号线中的每对包括第一发光复位控制信号线和第二发光复位控制信号线。第m对发光复位控制信号线与第m行子像素对应。第m对发光复位控制信号线的第一发光复位控制值信号线被配置为向第m行子像素的第2n-1列子像素的发光复位控制信号输入端提供第一发光复位控制信号，以及第m对发光复位控制信号线的第二发光复位控制信号线被配置为向第m行子像素的第2n列子像素的发光复位控制信号输入端提供第二发光复位控制信号。
在本公开的实施例中，第m对发光复位控制信号线的第一发光复位控制信号线与第m+1对驱动复位控制信号线的第一驱动复位控制信号线可以为同一信号线。第m对发光复位控制信号线的第二发光复位控制信号线与第m+1对驱动复位控制信号线的第二驱动复位控制信号线可以为同一信号 线。
在本公开的实施例中，阵列基板还可以包括沿列方向延伸的数据信号线。每列子像素的数据信号输入端连接到对应的一条数据线以接收数据信号。
在本公开的实施例中，阵列基板还可以包括沿列方向延伸的复位电源信号线，被配置为向对应的像素电路提供复位电压。
在本公开的实施例中，补偿电路可以包括补偿晶体管。发光控制电路可以包括第一发光控制晶体管和第二发光控制晶体管。发光复位电路可以包括发光复位晶体管。存储电路可以包括电容器。该驱动晶体管的第一极可以与驱动电路的第一端耦接，该驱动晶体管的第二极可以与驱动电路的第二端耦接，该驱动晶体管的栅极可以与驱动电路的控制端耦接。该数据写入晶体管的第一极可以与数据信号输入端耦接，该数据写入晶体管的第二极可以与驱动晶体管的第一极耦接，该数据写入晶体管的栅极可以与扫描信号输入端耦接。该驱动复位晶体管的第一极可以与驱动晶体管的栅极耦接，该驱动复位晶体管的第二极可以与复位电压端耦接，该驱动复位晶体管的栅极可以与驱动复位控制信号输入端耦接。该补偿晶体管的第一极可以与驱动晶体管的第二极耦接，该补偿晶体管的第二极可以与驱动晶体管的栅极耦接，该补偿晶体管的栅极可以与扫描信号输入端耦接。该第一发光控制晶体管的第一极可以与第一电压端耦接，该第一发光控制晶体管的第二极可以与驱动晶体管的第一极耦接，该第一发光控制晶体管的栅极可以与发光控制信号输入端耦接。该第二发光控制晶体管的第一极可以与驱动晶体管的第二极耦接，该第二发光控制晶体管的第二极可以与发光器件的第一极耦接，该第二发光控制晶体管的栅极可以与发光控制信号输入端耦接。该发光复位晶体管的第一极可以与发光器件的第一极耦接，该发光复位晶体管的第二极可以与复位电压端耦接，该发光复位晶体管的栅极可以与发光复位控制信号输入端耦接。该电容器的第一极可以与驱动晶体管的栅极耦接，该电容器的第二极可以与第一电压端耦接。
在本公开的实施例中，阵列基板还可以包括位于衬底上的有源半导体 层。该有源半导体层可以包括像素电路中的晶体管的有源区。对于第m行子像素：第2n-1列子像素的有源半导体层可以包括彼此间隔设置的第一部分、第二部分和第三部分。该第一部分和该第二部分沿行方向依次设置，该第一部分和该第二部分的组合和该第三部分与沿列方向依次设置。该第一部分可以包括第2n-1列子像素中的驱动复位晶体管和补偿晶体管的有源区。该第二部分可以包括第2n-1列子像素中的数据写入晶体管的有源区。该第三部分可以包括第2n-1列子像素中的驱动晶体管、第一发光控制晶体管、第二发光控制晶体管和发光复位晶体管的有源区。该第2n列子像素的有源半导体层包括沿列方向依次设置的第四部分和第五部分。该第四部分可以包括第2n列子像素中的驱动复位晶体管、数据写入晶体管、补偿晶体管、驱动晶体管、第一发光控制晶体管和第二发光控制晶体管的有源区。该第五部分可以包括第2n列子像素中的发光复位晶体管的有源区。
在本公开的实施例中，阵列基板还可以包括位于有源半导体层的远离衬底的一侧的第一导电层。该第一导电层可以包括沿列方向依次设置的第一驱动复位控制信号线、第一扫描信号线、第二扫描信号线、电容器的第一极、发光控制信号线、第一发光复位控制信号线和第二发光复位控制信号线。该第一扫描信号线可以用作第二驱动复位控制信号线，该电容器的第一极可以与驱动晶体管的栅极为一体结构。
在本公开的实施例中，第一驱动复位控制信号线的在衬底上的正投影与有源半导体层的第一部分在衬底上的正投影重叠的部分可以为第2n-1列子像素中的驱动复位晶体管的栅极。第一扫描信号线的在衬底上的正投影与有源半导体层的第一部分、第二部分和第四部分在衬底上的正投影重叠的部分可以分别为第2n-1列子像素中的补偿晶体管和数据写入晶体管以及第2n列子像素中的驱动复位晶体管的栅极。第二扫描信号线的在衬底上的正投影与有源半导体层的第四部分在衬底上的正投影重叠的部分可以分别为第2n列子像素中的数据写入晶体管和补偿晶体管的栅极。第2n-1列子像素中的电容器的第一极的在衬底上的正投影与有源半导体层的第三部分在衬底上的正投影重叠的部分可以为第2n-1列子像素中的驱动晶体管的栅 极。第2n列子像素中的电容器的第一极的在衬底上的正投影与有源半导体层的第四部分在衬底上的正投影重叠的部分可以为第2n列子像素中的驱动晶体管的栅极。发光控制信号线的在衬底上的正投影与有源半导体层的第三部分和第四部分在衬底上的正投影重叠的部分可以分别为第2n-1列子像素中的第一发光控制晶体管和第二发光控制晶体管以及第2n列子像素中的第一发光控制晶体管和第二发光控制晶体管的栅极。第一发光复位控制信号线的在衬底上的正投影与有源半导体层的第三部分在衬底上的正投影重叠的部分可以为第2n-1列子像素中的发光复位晶体管的栅极。第二发光复位控制信号线的在衬底上的正投影与有源半导体层的第五部分在衬底上的正投影重叠的部分可以为第2n列子像素中的发光复位晶体管的栅极。
在本公开的实施例中，阵列基板还可以包括位于第一导电层的远离衬底的一侧的第二导电层。该第二导电层可以包括沿列方向设置的电容器的第二极和作为第一电压源的第一电源信号线。该电容器的第二极和该电容器的第一极在衬底上的投影可以至少部分重叠。第一电源信号线沿行方向延伸并可以与电容器的第二极一体形成。
在本公开的实施例中，阵列基板还可以包括位于第二导电层的远离衬底的一侧的第三导电层。该第三导电层可以包括数据信号线、复位电源信号线、作为第一电压源的第二电源信号线、作为第一电压源的第三电源信号线、第一连接部、第二连接部、第三连接部、第四连接部、第五连接部以及第六连接部。该第一连接部的一端可以耦接第2n-1列子像素的补偿晶体管的第一极，另一端可以耦接第2n-1列子像素的驱动晶体管的第二极。该第二连接部的一端可以耦接第2n-1列子像素的驱动复位晶体管的第一极，另一端可以耦接第2n-1列子像素的驱动晶体管的栅极。该第三连接部的一端可以耦接第2n-1列子像素的数据写入晶体管的第二极，另一端可以耦接第2n-1列子像素的驱动晶体管的第一极。该第四连接部可以耦接第2n-1列子像素的第二发光控制晶体管的第二极。该第五连接部的一端可以耦接第2n列子像素的驱动复位晶体管的第一极，另一端可以耦接第2n列子像素的驱动晶体管的栅极。该第六连接部的一端可以耦接第2n列子像素的第 二发光控制晶体管的第二极，另一端可以耦接第2n列子像素的发光复位晶体管的第一极。该数据信号线可以耦接第2n-1列子像素的数据写入晶体管的第一极和该第2n列子像素的数据写入晶体管的第一极。该第二电源信号线可以沿列方向延伸且位于第2n-1列子像素中，并可以耦接第2n-1列子像素的电容器的第二极和第一发光控制晶体管的第一极。该第三电源信号线可以沿列方向延伸且位于第2n列子像素中，并可以耦接第2n列子像素的电容器的第二极和第一发光控制晶体管的第一极。
在本公开的实施例中，第二导电层还可以包括沿行方向延伸的第一附加复位电源信号线和第二附加复位电源信号线。该第一附加复位电源信号线和该第二附加复位电源信号线可以耦接到复位电源信号线。电容器的第二极和第一电源信号线可以沿列方向位于第一附加复位电源信号线与第二附加复位电源信号线之间。
在本公开的实施例中，阵列基板还可以包括位于第二导电层的远离衬底的一侧的第三导电层。该第三导电层可以包括数据信号线、复位电源信号线、作为第一电压源的第二电源信号线、作为第一电压源的第三电源信号线、第一连接部、第二连接部、第三连接部、第四连接部、第五连接部、第六连接部、第七连接部、第八连接部、第九连接部以及第十连接部。该第一连接部的一端可以耦接第2n-1列子像素的补偿晶体管的第一极，另一端可以耦接第2n-1列子像素的驱动晶体管的第二极，该第二连接部的一端可以耦接第2n-1列子像素的驱动复位晶体管的第一极，另一端可以耦接第2n-1列子像素的驱动晶体管的栅极。该第三连接部的一端可以耦接第2n-1列子像素的数据写入晶体管的第二极，另一端可以耦接第2n-1列子像素的驱动晶体管的第一极。该第四连接部可以耦接第2n-1列子像素的第二发光控制晶体管的第二极。该第五连接部的一端可以耦接第2n列子像素的驱动复位晶体管的第一极，另一端可以耦接第2n列子像素的驱动晶体管的栅极。该第六连接部的一端可以耦接第2n列子像素的第二发光控制晶体管的第二极，另一端可以耦接第2n列子像素的发光复位晶体管的第一极。该第七连接部的一端可以耦接第一附加复位电源信号线，另一端可以耦接第2n-1 列子像素的驱动复位晶体管的第二极。该第八连接部的一端可以耦接第二附加复位电源信号线，另一端可以耦接第2n-1列子像素的发光复位晶体管的第二极。该第九连接部的一端可以耦接第一附加复位电源信号线，另一端可以耦接第2n列子像素的驱动复位晶体管的第二极。该第十连接部的一端可以耦接第二附加复位电源信号线，另一端可以耦接第2n列子像素的发光复位晶体管的第二极。该第二电源信号线可以沿列方向延伸且位于第2n-1列子像素中，并可以耦接第2n-1列子像素的电容器的第二极和第一发光控制晶体管的第一极。该第三电源信号线可以沿列方向延伸且位于第2n列子像素中，并可以耦接第2n列子像素的电容器的第二极和第一发光控制晶体管的第一极。
在本公开的实施例中，阵列基板还可以包括位于第三导电层的远离衬底的一侧的第四导电层。该第四导电层可以包括作为第一电压源的第四电源信号线、第十一连接部以及第十二连接部。第二电源信号线在衬底上的正投影可以与第四电源信号线在衬底上的正投影至少部分重叠。第三电源信号线在衬底上的正投影可以与第四电源信号线在衬底上的正投影至少部分重叠。该第四电源信号线可以耦接第二电源信号线和第三电源信号线。该第十一连接部可以耦接第四连接部。该第十二连接部可以耦接第六连接部的一端。
根据本公开的第二方面，提供了一种显示面板。该显示面板包括根据第一方面中的任一项的阵列基板。
根据本公开的第三方面，提供了一种显示装置。该显示装置包括根据第二方面中的任一项的显示面板。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的，并不是所有可能的实施方式，并且不旨在限制本申请的范围，其中：
图1示出了一种阵列基板的结构示意图。
图2示出了根据本公开的实施例的阵列基板的结构示意图。
图3示出了根据本公开的实施例的子像素的示意性框图。
图4示出了根据本公开的实施例的图3中的像素电路的示意图。
图5示出了根据本公开的实施例的驱动图4中的像素电路的信号的时序图。
图6示出了根据本公开的实施例的驱动图2中的阵列基板的信号的时序图。
图7-13示出了根据本公开的实施例的阵列基板中各层的平面示意图。
图14-15示出了堆叠的有源半导体层、第一导电层、第二导电层、第三导电层和第四导电层的平面布局示意图。
图16示出了根据本公开的实施例的沿图14中的线A1A1’截取的阵列基板的横截面结构示意图。
图17示出了根据本公开的实施例的沿图15中的线A2A2’截取的阵列基板的横截面结构示意图。
图18示出了根据本公开的实施例的沿图14中的线B1B1’截取的阵列基板的横截面结构示意图。
图19示出了根据本公开的实施例的沿图14中的线C1C1’截取的阵列基板的横截面结构示意图。
图20示出了根据本公开的实施例的沿图15中的线C2C2’截取的阵列基板的横截面结构示意图。
图21示出了根据本公开的实施例的显示面板的结构示意图。
图22示出了根据本公开的实施例的显示装置的结构示意图。
贯穿这些附图的各个视图，相应的参考编号指示相应的部件或特征。
具体实施方式
首先，需要说明的是，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中另有说明。在本文中使用术语“实例”之处，特别是当其位于一组术语之后时，所述“实例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
另外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
此外，在附图中，为了清楚起见夸大了各层的厚度及区域。应当理解的是，当提到层、区域、或组件在别的部分“上”时，指其直接位于别的部分上，或者也可能有别的组件介于其间。相反，当某个组件被提到“直接”位于别的组件上时，指并无别的组件介于其间。
现将参照附图更全面地描述示例性的实施例。
在通常的阵列基板中，由于同一行像素单元中的多列像素单元连接到同一条扫描信号线，因此同一行像素单元中的多列像素单元会在由同一条扫描线提供的扫描信号的驱动下同时打开，同一行像素单元中的多列像素单元的打开时间一致；此外，由于同一行像素单元中的多列像素单元连接到多条不同的数据线，因此同一行像素单元中的多列像素单元会先后写入由多条不同的数据线提供的数据信号。在这种情况下，就会导致同一行像素单元中的多列像素单元具有不同的充电方式，诸如先充电后放电和边充电边放电，这进而会导致同一行像素单元中的多列像素单元的显示亮度不均匀，影响显示质量。
图1示出了一种阵列基板的结构示意图，该阵列基板能够解决上述问题。如图1所示，该阵列基板10包括衬底以及设置在衬底上的多对扫描信 号线S、多对驱动复位控制信号线R和像素阵列。像素阵列包括排布为多行多列的多个子像素P。如图1所示，子像素P具有像素电路和耦接到该像素电路的数据信号输入端Data、扫描信号输入端Gate和驱动复位控制信号输入端Rst1。在图1中，示出了第m行中的P 2n-1子像素和P 2n子像素以及第m+1行子像素中的P 2n-1子像素和P 2n子像素。在本公开的实施例中，m和n均为大于等于1的整数。
如图1所示，阵列基板10包括沿行方向延伸且沿列方向彼此间隔设置的两对扫描信号线，与第m行的第2n-1列子像素和第2n+1列子像素对应的第一扫描信号线SO m，以及与第m行的第2n列子像素和第2n+2列子像素对应的第二扫描信号线SE m，以及与第m+1行的第2n-1列子像素和第2n+1列子像素对应的第一扫描信号线SO m+1，以及与第m+1行的第2n列子像素和第2n+2列子像素对应的第二扫描信号线SE m+1。
如图1所示，该阵列基板包括沿行方向延伸且沿列方向彼此间隔设置的两对驱动复位控制信号线，与第m行的第2n-1列子像素和第2n+1列子像素对应的第一驱动复位控制信号线RO m，以及与第m行的第2n列子像素和第2n+2列子像素对应的第二驱动复位控制信号线RE m，以及与第m+1行的第2n-1列子像素和第2n+1列子像素对应的第一驱动复位控制信号线RO m+1，以及与第m+1行的第2n列子像素和第2n+2列子像素对应的第二驱动复位控制信号线RE m+1。
在图1所示的阵列基板中，第m行子像素中的第2n-1列子像素的扫描信号输入端可以连接到第一扫描信号线SO m以接收第一扫描信号，第m行子像素中的第2n列子像素的扫描信号输入端可连接到第二扫描信号线SE m以接收第二扫描信号，从而第m行子像素中的第2n-1列子像素会在第一扫描信号的驱动下先打开，第2n列子像素会在第二扫描信号的驱动下后打开，并且可使得第m行子像素中的第2n-1列子像素和第2n列子像素的打开时间长短一致。在这种情况下，第m行子像素中的第2n-1列子像素和第2n列子像素的充电方式相同，避免同一行像素单元中的多列子像素的显示亮度不均匀的问题，进而可以改善显示质量。
然而，对于图1所示的阵列基板，对于每一行子像素，需要提供通常设置在阵列基板边缘处的两个扫描信号生成电路和两个驱动复位控制信号生成电路而非常规情况下的一个扫描信号生成电路和一个驱动复位控制信号生成电路，这会不利地增加显示面板边框的尺寸。
此外，如图1所示，阵列基板还包括沿列方向延伸且沿行方向彼此间隔设置的复位电源信号线V和数据信号线D。第2n-1条复位电源信号线V 2n-1与每行子像素中的第2n-1列子像素对应，……，第2n+2条复位电源信号线V 2n+2与每行子像素中的第2n+2列子像素对应。类似地，第2n-1条数据信号线D2n-1与每行子像素中的第2n-1列子像素对应，……，第2n+2条数据信号线D2n+2与每行子像素中的第2n+2列子像素对应。在这种情况下，由于在阵列基板上每个子像素都具有不被其它子像素所共享的单独复位电源信号线和数据线，因此阵列基板上的布线的数量较多，这导致较低的PPI。
本公开至少一些实施例提供一种阵列基板，该阵列基板包括：多对扫描信号线，多对扫描信号线，其被配置为沿行方向延伸且沿列方向彼此间隔设置，该多对扫描信号线中的每对包括第一扫描信号线和第二扫描信号线；多对驱动复位控制信号线，其被配置为沿行方向延伸且沿列方向彼此间隔设置，该多对驱动复位控制信号线中的每对包括第一驱动复位控制信号线和第二驱动复位控制信号线；多条数据线；以及像素阵列，其包括排布为多行多列的多个子像素。多个子像素中的每个包括数据信号输入端、扫描信号输入端和驱动复位控制信号输入端。多行子像素与多对扫描信号线一一对应，每列子像素对应于多条数据线中的一条数据线。第m行子像素中的第2n-1列(即，奇数列)子像素的扫描信号输入端连接到第m对扫描信号线中的第一扫描信号线以接收第一扫描信号，m和n均为大于等于1的整数；第m行子像素中的第2n列(即，偶数列)子像素的扫描信号输入端连接到第m对扫描信号线中的第二扫描信号线以接收第二扫描信号。第m行像素单元中的第2n-1列像素单元的驱动复位控制信号输入端连接到所述第m对扫描信号线中的第一扫描信号线以接收第一扫描信号作为第一 驱动复位控制信号；第m行像素单元中的第2n列子像素的驱动复位控制信号输入端连接到所述第m对扫描信号线中的第二扫描信号线以接收第二扫描信号作为第二驱动复位控制信号。
在本公开的实施例提供的阵列基板中，第m行像素单元中的第2n-1列子像素的扫描信号输入端可以连接到第m对扫描信号线中的第一扫描信号线以接收第一扫描信号，第m行子像素中的第2n列子像素的扫描信号输入端可以连接到第m对扫描信号线中的第二扫描信号线以接收第二扫描信号，从而第m行像素单元中的第2n-1列子像素会在第m对扫描信号线中的第一扫描信号线提供的第一扫描信号的驱动下先打开，第2n列子像素会在第m对扫描信号线中的第二扫描信号线提供的第二扫描信号的驱动下后打开，并且可使得第m行像素单元中的第2n-1列子像素和第2n列子像素的打开时间长短一致。在这种情况下，第m行像素单元中的第2n-1列子像素和第2n列子像素的充电方式相同，避免同一行子像素中的多列子像素的显示亮度不均匀的问题，进而可以改善显示质量。
在本公开的实施例提供的阵列基板中，第m对扫描信号线的第一扫描信号线与第m对驱动复位控制信号线的第二驱动复位控制信号线为同一信号线。具体地，第m行子像素中的第2n+1列子像素的扫描信号输入端可以连接到第m对扫描信号线中的第一扫描信号线，并且第m行像素单元中的第2n列子像素的驱动复位控制信号输入端也可以连接到第m对扫描信号线中的第一扫描信号线，从而可以将第m对扫描信号线中的第一扫描信号线提供给第m行子像素中的第2n-1列子像素的第一扫描信号作为第一驱动复位控制信号施加到第m行子像素中的第2n列子像素，以对第m行子像素中的第2n列子像素进行复位。在这种情况下，可以减少集成在阵列基板上的栅极驱动器(gate driver on array，GOA)的数量，有利于采用该阵列基板的显示装置实现窄边框设计。
在本公开的实施例中，在本公开的实施例中，子像素还可以包括复位电压端。阵列基板还包括多条复位电源信号线。该多条复位电源信号线沿列方向延伸，并和数据信号线沿行方向彼此交替设置，且彼此邻近的数据 信号线之间和彼此邻近的复位电源信号线之间的间隔均限定一列子像素。复位电源信号线被配置为向与该复位电源信号线邻近的子像素列中的子像素的复位电压端提供复位电压。具体地，第n+1条复位电源信号线Vn+1与第2n列子像素和第2n+1列子像素邻近，并被配置为向第2n列子像素和第2n+1列子像素的复位电压端提供复位电压。数据信号线被配置为向与该数据信号线邻近的子像素列中的子像素的数据信号输入端提供数据信号。具体地，第n条数据信号线Dn与第2n-1列子像素和第2n列子像素邻近，并被配置为向第2n-1列子像素和第2n列子像素的数据信号输入端提供数据信号。第n+1条数据信号线Dn+1与第2n+1列子像素和第2n+2列子像素邻近，并被配置为向第2n+1列子像素和第2n+2列子像素的数据信号输入端提供数据信号。在这种情况下，可以减少集成在阵列基板上的布置的数据线的数量，进而提高PPI。
下面结合附图对本公开实施例提供的阵列基板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体实施例中的不同特征可以相互组合，从而得到新的实施例，这些新的实施例也都属于本公开保护的范围。
图2为本公开的一些实施例的一种阵列基板的结构示意图。
如图2所示，阵列基板20包括衬底以及设置在衬底上的多对扫描信号线S、多对驱动复位控制信号线R、多条复位电源信号线V、多条数据线D和像素阵列。该衬底可以为玻璃基板、塑料基板等，本公开的实施例对此不作限制。多对扫描信号线S可以沿行方向延伸且沿列方向彼此间隔设置在衬底上，多对扫描信号线S中的每对包括第一扫描信号线SO和第二扫描信号线SE；多对驱动复位控制信号线R可以沿行方向延伸且沿列方向彼此间隔设置在衬底上，多对驱动复位控制信号线R可以包括第一驱动复位控制信号线RO和第二驱动复位控制信号线RE；多条复位电源线V和多条数据线D沿行方向彼此交替设置在衬底上，彼此邻近的数据信号线和复位电源信号线之间的间隔限定一列子像素；像素阵列包括排布为多行多列的多个子像素P，例如，多个子像素P位于由多对扫描信号线S和多条复 位电源信号线V及多条数据线D交叉限定出的像素区域中，每个子像素P包括扫描信号输入端Gate、数据信号输入端DA、驱动复位控制信号输入端Rst1和复位电压端VINT，以分别接收用于该像素单元P的扫描信号(例如，第一扫描信号或第二扫描信号)、数据信号、驱动复位控制信号(例如，第一驱动复位控制信号或第二驱动复位控制信号)、复位电压。
例如，第一方向可以与第二方向垂直，第一方向可以是像素阵列的行方向(例如，图2中的X方向)，第二方向可以是像素阵列的列方向(例如，图2中的Y方向)。
如图2所示，多行像素单元可以与多对扫描信号线S一一对应，每行像素单元可以连接到与其对应的一对扫描信号线S，例如，第m行子像素可以对应于第m对扫描信号线S m，第m行子像素中的第2n-1列子像素可以对应于第m对扫描信号线S m中的第一扫描信号线SO m，第m行像素单元中的第2n列子像素可以对应于第m对扫描信号线中S m的第二扫描信号线SE m，第m行像素单元中的第2n-1列子像素的扫描信号输入端Gate可以连接到第m对扫描信号线S m中的第一扫描信号线SO m以接收第一扫描信号，第m行像素单元中的第2n列子像素的扫描信号输入端Gate可以连接到第m对扫描信号线Sm中的第二扫描信号线SE m以接收第二扫描信号，m和n均为大于等于1的整数。
如图2所示，多行像素单元可以与多对驱动复位控制信号线R一一对应。每行像素单元可以连接到与其对应的一对驱动复位控制信号线R，例如，第m行子像素可以对应于第m对驱动复位控制信号线R m，第m行子像素中的第2n-1列子像素可以对应于第m对驱动复位控制信号线R m中的第一驱动复位控制信号线RO m，第m行像素单元中的第2n列子像素可以对应于第m对驱动复位控制信号线R m的第二驱动复位控制信号线RE m，第m行像素单元中的第2n-1列子像素的驱动复位控制信号输入端Rst1可以连接到第m对驱动复位控制信号Rm中的第一驱动复位控制信号RO m以接收第一驱动复位控制信号，第m行像素单元中的第2n列子像素的驱 动复位控制信号输入端Rst1可以连接到第m对驱动复位控制信号R m中的第二驱动复位控制信号RE m以接收第二扫描信号。
如图2所示，第m对扫描信号线S m的第一扫描信号线SO m与第m对驱动复位控制信号线R m的第二驱动复位控制信号线RE m为同一信号线。具体地，第m行子像素中的第2n列子像素的驱动复位控制信号输入端Rst1可以连接到第m对扫描信号线S m中的第一扫描信号线SO m/RE m以接收第一扫描信号。在这种情况下，第m对扫描信号线Sm中的第一扫描信号线SO m提供给第m行子像素中的第2n列子像素的第一扫描信号可以作为第一驱动复位控制信号施加到第m行子像素中的第2n列子像素，以对第m行子像素中的第2n列子像素进行复位。
如图2所示，数据信号线D被配置为向与该数据信号线邻近的子像素列中的子像素的数据信号输入端提供数据信号。具体地，第2n-1列子像素和第2n列子像素可以对应于同一条数据线Dn，第2n+1列子像素和第2n+2列子像素可以对应于同一条数据线Dn+1，……，以此类推。第2n-1列子像素的数据信号输入端Data和第2n列子像素的数据信号输入端Data可以连接到同一条数据线Dn以接收数据信号，第2n+1列子像素的数据信号输入端Data和第2n+2列子像素的数据信号输入端Data可以连接到同一条数据线D n+1以接收数据信号，…….，以此类推。
如图2所示，复位电源信号线V被配置为向与该复位电源信号线邻近的子像素列中的子像素的复位电压端提供复位电压。具体地，第2n列子像素和第2n+1列子像素可以对应于同一条复位电源信号线V n+1，第2n+2列子像素和第2n+3列子像素(未示出)可以对应于同一条复位电源信号线Vn+2，……，以此类推。第2n列子像素的复位电压端Vint和第2n+1列子像素的复位电压端Vint可以连接到同一条复位电源信号线V n+1以接收复位电压，第2n+2列子像素的复位电压端Vint和第2n+3列子像素的复位电压端Vint可以连接到同一条复位电源信号线V n+2以接收复位电压，…….，以此类推。
如图2所示，第n条复位电源信号线Vn设置在第2n-1列子像素的左侧而第n条数据线Dn设置在第2n-1列子像素的右侧，第n条复位电源信号线Vn与第n条数据线Dn之间设置有一列子像素，相邻两条数据线D之间可以设置有两列子像素。相邻两条复位电源信号线V之间可以设置有两列子像素。但是本公开的实施例显然不限于此。例如，第n条复位电源信号线Vn设置在第2n-1列子像素的右侧，而第n条数据线Dn可以设置在第2n-1列子像素的左侧。
在本公开的一些实施例中，子像素P还包括发光复位控制信号输入端Rst2。阵列基板20还包括多对发光复位控制信号线(未示出)。多对发光复位信号线，沿行方向延伸且沿列方向彼此间隔设置。多对发光复位信号线中的每对包括第一发光复位控制信号线和第二发光复位控制信号线。第m对发光复位信号线与第m行子像素对应，第m对发光复位信号线的第一发光复位信号线被配置为向第m行子像素的第2n-1列子像素的发光复位信号输入端提供第一发光复位信号。第m对发光复位信号线的第二发光复位信号线被配置为向第m行子像素的第2n列子像素的发光复位信号输入端提供第二发光复位信号。
在本实施例中，第m对发光复位信号线的第一发光复位信号线与第m+1对驱动复位控制信号线的第一驱动复位控制信号线为同一信号线。第m对发光复位信号线的第二发光复位信号线与第m+1对驱动复位控制信号线的第二驱动复位控制信号线为同一信号线。具体地，第m行子像素中的第2n-1列子像素的发光复位控制信号输入端连接到第m+1对扫描信号线中的第一扫描信号线，以接收第m+1对扫描信号线中的第一扫描信号线提供的第一扫描信号作为第一发光复位控制信号，以对第m行子像素中的第2n-1列子像素进行复位。在这种情况下，第m+1对扫描信号线S m+1中的第一扫描信号线SO m+1提供给第m行子像素中的第2n-1列子像素的第一扫描信号可以作为发光复位控制信号施加到第m行子像素中的第2n-1列子像素，以对第m行子像素中的第2n-1列子像素进行复位。第m行子像素中的第2n列子像素的发光复位控制信号输入端连接到第m+1对扫描信号线中的 第二扫描信号线，以接收第m+1对扫描信号线中的第二扫描信号线提供的第二扫描信号作为第二发光复位控制信号，以对第m行子像素中的第2n列子像素进行复位。在这种情况下，第m+1对扫描信号线S m+1中的第二扫描信号线SE m+1提供给第m行子像素中的第2n列子像素的第二扫描信号可以作为发光复位控制信号施加到第m行子像素中的第2n列子像素，以对第m行子像素中的第2n列子像素进行复位。
如图2所示，第m行子像素中的第2n-1列子像素的复位信号输入端RST可以连接到第m-1对扫描信号线S m-1中的第一扫描信号线SO m-1。在这种情况下，第m-1对扫描信号线Sm-1中的第一扫描信号线SO m-1提供给第m-1行子像素中的第n列子像素的第一扫描信号可以作为第二复位信号施加到第m行子像素中的第n列子像素，以对第m行子像素中的第n列子像素进行复位。
此外，如图2所示，在第m行子像素中的第2n-1列子像素的发光复位控制信号输入端Rst2连接到第m+1对扫描信号线S m+1中的第一扫描信号线SO m+1的情况下，第m行子像素中的第2n列子像素的发光复位控制信号输入端Rst2连接到第m+1对扫描信号线S m+1中的第二扫描信号线SE m+1。在这种情况下，第m行子像素中的第2n-1列子像素和第2n列子像素的复位方式与第m+1行子像素中的第2n-1列子像素和第2n列子像素的复位方式是不同的。具体地，就第m行子像素和第m+1行子像素各自的工作周期而言，在第m行子像素中，第2n-1列子像素是利用提供给第m+1行子像素中第2n-1列子像素的第一扫描信号作为发光复位控制信号进行复位；在第m行子像素中，第2n列子像素是利用提供给第m+1行子像素中第2n列子像素的第二扫描信号作为发光复位控制信号进行复位。
在本公开的一些实施例中，子像素P还包括发光控制信号输入端，以接收用于该子像素的发光控制信号。相应地，该实施例提供的阵列基板20还可以包括沿列方向延伸且沿行方向彼此间隔设置在衬底上的多条发光控制信号线，多条发光控制信号线与多行子像素一一对应，第m行子像素的发光控制信号输入端连接到第m条发光控制信号线以接收发光控制信号。
如图2所示，每个子像素P还包括发光控制信号输入端EM。阵列基板20还包括设置在衬底上的多条发光控制信号线E，例如，多条发光控制信号线E可以沿第一方向设置在衬底上。多条发光控制信号线E可以与多行子像素一一对应，每行子像素可以连接到与其对应的一条发光控制信号线E。例如，第m行子像素对应于第m条发光控制信号线E m，第m行子像素的发光控制信号输入端EM可以连接到第m条发光控制信号线E m以接收发光控制信号。
需要说明的是，尽管在图2示出第m条发光控制信号线E m设置在第m行子像素的上侧，但是本公开的实施例显然不限于此。例如，第m条发光控制信号线E m可以设置在第m行子像素的下侧。
在本公开的一些实施例中，子像素P还可以包括第一电压端VDD。阵列基板还可以包括设置在衬底上的多条第一电压信号线。多条第一电压信号线与多行子像素一一对应，第m行子像素中的第2n-1列子像素的第一电压端连接到第2n-1条第一电压信号线以接收第一电压，……，第m行子像素中的第2n+2列子像素的第一电压端连接到第2n+2条第一电压信号线以接收第一电压。
图3为根据本公开的一些实施例的子像素的示意性框图。如图3所示，子像素P包括像素电路100和发光器件200。像素电路100包括数据写入电路110、驱动电路120、驱动复位电路130、补偿电路140、发光控制电路150、发光复位电路160和存储电路170。
如图3所示，数据写入电路110与数据信号输入端耦接、驱动电路120的第一端F和扫描信号输入端Gate耦接。数据写入电路被配置为在扫描信号的控制下将数据信号写入到驱动电路120中。例如，这里的扫描信号可以是前面的实施例中所述的第一扫描信号或第二扫描信号，后续的实施例中提到的扫描信号具有与此类似的含义，因此将不再赘述。
如图3所示，驱动电路120包括控制端G、第一端F和第二端S，并被配置为在来自控制端G的控制信号的控制下，向发光器件200提供驱动电路。
如图3所示，驱动复位电路130与驱动电路120的控制端G、复位电压端Vint和驱动复位控制信号输入端Rst1耦接，并被配置为在驱动复位控制信号的控制下将从复位电压端Vint接收到的复位电压施加到驱动电路120，以对驱动电路120的控制端G进行复位。例如，这里的驱动复位控制信号可以是前面的实施例中所述的第一驱动复位控制信号或第二驱动复位控制信号，后续的实施例中提到的驱动复位控制信号具有与此类似的含义，因此将不再赘述。
如图3所示，补偿电路140与驱动电路120的控制端G、驱动电路120的第二端S和扫描信号输入端Gate耦接，并被配置为在来自扫描信号输入端Gate的第一扫描信号或第二扫描信号的控制下，对驱动电路进行阈值补偿。
如图3所示，发光控制电路150与驱动电路120的第一端F、驱动电路120的第二端S和发光控制信号输入端EM耦接，并被配置为在发光控制信号的控制下将从第一电压端VDD接收到的第一电压施加至驱动电路120，从而将驱动电路120产生的驱动电流施加至发光器件200。
如图3所示，发光复位电路160与发光器件200、复位电压端VINT和发光复位控制信号输入端Rst2耦接，并被配置为在发光复位控制信号的控制下将从复位电压端VINT接收到的复位电压施加到发光器件200，以对发光器件200进行复位。例如，这里的发光复位控制信号可以是前面的实施例中所述的第一发光复位控制信号或第二发光复位控制信号，后续的实施例中提到的发光复位控制信号具有与此类似的含义，因此将不再赘述。
如图3所示，存储电路170与第一电压端VDD和驱动电路120的控制端G耦接，并被配置为存储来自第一电压端VDD的第一电压与驱动电路120的控制端G的电压之间的电压差。
如图3所示，发光器件200与第二电压源VSS和驱动电路120的第二端S耦接，并且被配置为在驱动电路120产生的驱动电流的驱动下发光。
例如，发光器件200可以为发光二极管等。发光二极管可以为有机发光二极管(OLED)或量子点发光二极管(QLED)等。
图4为图3中的像素电路的示意图。如图4所示，数据写入电路110包括数据写入晶体管T1，驱动电路120包括驱动晶体管T2，驱动复位电路130包括驱动复位晶体管T3，补偿电路140包括补偿晶体管T4，发光控制电路150包括第一发光控制晶体管T5和第二发光控制晶体管T6，发光复位电路160包括发光复位晶体管T7，存储电路170包括电容器C。
如图4所示，驱动晶体管T2的第一极与驱动电路120的第一端F耦接，驱动晶体管T2的第二极与驱动电路120的第二端S耦接，驱动晶体管T2的栅极与驱动电路120的控制端G耦接。
如图4所示，数据写入晶体管T1的第一极与数据信号输入端Data耦接，以从数据信号线D接收数据信号；数据写入晶体管T1的第二极与驱动晶体管T2的第一极耦接；数据写入晶体管T1的栅极与扫描信号输入端Gate耦接，以从扫描信号输入端Gate接收第一扫描信号或第二扫描信号，并被配置为根据来自扫描信号输入端Gate的第一扫描信号或第二扫描信号，将来自数据信号线D的数据信号提供给驱动晶体管T2的第一极。
如图4所示，驱动复位晶体管T3的第一极与驱动晶体管T2的栅极耦接；驱动复位晶体管T3的第二极与复位电压端VINT耦接，以从复位电压端VINT接收复位电压；驱动复位晶体管T3的栅极与驱动复位控制信号输入端Rst1耦接，以从驱动复位控制信号输入端Rst1接收第一驱动复位控制信号或第二驱动复位控制信，并被配置为根据来自驱动复位控制信号输入端Rst1的第一驱动复位控制信号或第二驱动复位控制信号，将复位电压提供给驱动晶体管T2的栅极，以对驱动晶体管T2的栅极进行复位。
如图4所示，补偿晶体管T4的第一极与驱动晶体管T2的第二极耦接；补偿晶体管T4的第二极与驱动晶体管T2的栅极耦接；补偿晶体管T4的栅极与扫描信号输入端Gate耦接，以从扫描信号输入端Gate接收第一扫描信号或第二扫描信号，并被配置为根据来自扫描信号输入端Gate的第一扫描信号或第二扫描信号，对驱动晶体管T2的阈值进行补偿。
如图4所示，第一发光控制晶体管T5的第一极与第一电压端VDD耦接，以从第一电压端VDD接收第一电压；第一发光控制晶体管T5的第二 极与驱动晶体管T2的第一极耦接；第一发光控制晶体管T5的栅极与发光控制信号输入端EM耦接，以从发光控制信号输入端EM接收发光控制信号，并被配置为根据来自发光控制信号输入端EM发光控制信号控制第一电压端VDD与驱动晶体管T2的第一极之间的通断，从而控制是否将来自第一电压端VDD的第一电压提供给驱动晶体管T2的第一极。
第二发光控制晶体管T6的第一极与驱动晶体管T2的第二极耦接；第二发光控制晶体管T6的第二极与发光器件200的第一极耦接；第二发光控制晶体管T6的栅极与发光控制信号输入端EM耦接，以从发光控制信号输入端EM接收发光控制信号，并被配置为根据来自发光控制信号输入端EM发光控制信号控制驱动晶体管T2的第二极与发光器件200的第一极之间的通断，从而控制是否驱动晶体管产生的电流提供给发光器件200。
在发光控制信号的控制下，第一发光控制晶体管T5和第二发光控制晶体管T6共同被配置为将第一电压施加至驱动电路120，并将驱动电路120产生的驱动电流施加至发光器件200。
如图4所示，电容器C的第一极与驱动晶体管T2的栅极耦接；电容器的第二极与第一电压端VDD耦接，并被配置为存储来自第一电压端VDD的第一电压和驱动晶体管T2的栅极的电压之间的电压差。
需要说明的是，本公开实施例均是以复位电压端VINT输入低电压，第一电压端VDD输入高电压，第二电压端VSS输入低电压，或将发光器件120的第二端接地为例进行的说明，并且这里的高、低仅表示输入的电压之间的相对大小关系。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，需要说明的是，本公开的实施例中采用的晶体管均可以为P型晶体管或N型晶体管，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。例如，对于N型晶体管，其输入端为漏极而输出端为源极，其控制端为栅极；对于P型晶体管，其输入端为源极而输出端为漏极，其控制端为栅极。对于不同类型的晶体管，其控制端的控制信号的电平也不相同。例如，对于N型晶体管，在控制信号为高电平时，该N型晶体管处于导通状态；而在控制信号为低电平时，N型晶体管处于截止状态。对于P型晶体管时，在控制信号为低电平时，该P型晶体管处于导通状态；而在控制信号为高电平时，P型晶体管处于截止状态。当采用N型晶体管时，可以采用氧化物半导体，例如氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)，作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。低温多晶硅通常指由非晶硅结晶得到多晶硅的结晶温度低于600摄氏度的情形。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图4所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图5为驱动图4中的像素电路的信号的时序图。如图5所示，像素电路100的工作过程包括三个阶段，分别为复位阶段P1、数据写入和补偿阶段P2以及发光阶段P3。
下面以数据写入晶体管T1、驱动晶体管T2、驱动复位晶体管T3、补偿晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和发光复位晶体管均采用P型晶体管为例，结合图4对图5中的像素电路的工作过程进行说明。
如图5所示，在复位阶段P1，输入低电平的驱动复位控制信号RST，高电平的扫描信号GA、高电平的发光控制信号EMS和低电平的数据信号DA。
在复位阶段P1，驱动复位晶体管T3的栅极接收到低电平的驱动复位控制信号RST1，驱动复位晶体管T3导通，从而将复位电压VINT施加至驱动晶体管T2的栅极以对驱动晶体管T2的栅极进行复位，以使得驱动晶体管T2以导通状态进入数据写入与补偿阶段P2。
在复位阶段P1，发光复位晶体管T7的栅极接收低电平的发光复位控制信号RST2，发光复位晶体管T7导通，从而将复位电压VINT施加至OLED的阳极以对OLED的阳极进行复位，以使得OLED在发光阶段P3之前不发光。
此外，在复位阶段P1，数据写入晶体管T1的栅极接收到高点平的扫描信号GA，数据写入晶体管T1截止；补偿晶体管T4的栅极接收到高电平的扫描信号GA，补偿晶体管T4截止；第一发光控制晶体管T5的栅极接收到高电平的发光控制信号EMS，第一发光控制晶体管T5截止；第二发光控制晶体管T6的栅极接收到高电平的发光控制信号EM，第二发光控制晶体管T6截止。
在数据写入与补偿阶段P2，输入高电平的驱动复位控制信号RST，低电平的扫描信号GA、高电平的发光控制信号EM和高电平的数据信号DA。
在数据写入与补偿阶段P2，数据写入晶体管T1的栅极接收到低电平的扫描信号GA，数据写入晶体管T1导通，从而将数据信号写入第一节点驱动晶体管T2的第一极(以下称为第一节点)。补偿晶体管T4的栅极接收到低电平的扫描信号GA，补偿晶体管T3导通。由于数据写入晶体管T1、驱动晶体管T2和补偿晶体管T4均导通，所以数据信号DA经过数据写入晶体管T1、驱动晶体管T2和补偿晶体管T4对存储电容C进行充电，也就是对驱动晶体管T2的栅极(以下称为第二节点)进行充电，驱动晶体管T2的栅极的电压逐渐升高。
容易理解，在数据写入与补偿阶段P2，由于数据写入晶体管T1导通，第一节点的电压保持为Vda。同时，根据驱动晶体管T2自身的特性，当第二节点的电压升高至Vda+Vth时，驱动晶体管T2截止，充电过程结束。这里，Vda表示数据信号DA的电压，Vth表示驱动晶体管T2的阈值电压，由于在本实施例中，驱动晶体管T2是以P型晶体管为例进行说明的，所以此处阈值电压Vth可以是负值。
经过数据写入和补偿阶段P2后，驱动晶体管T2的栅极的电压为Vdata+Vth，也就是说数据信号DA和阈值电压Vth的电压信息被存储在存储电容C中，以用于后续在发光阶段P3时，对驱动晶体管T2的阈值电压进行补偿。
此外，在数据写入与补偿阶段P2，驱动复位晶体管T3的栅极接收到高电平的驱动复位控制信号RST1，驱动复位晶体管T3截止；发光复位晶体管T7的栅极接收到高电平的发光复位控制信号，发光复位晶体管T7截止；第一发光控制晶体管T5的栅极接收到高电平的发光控制信号EMS，第一发光控制晶体管T5截止；第二发光控制晶体管T6的栅极接收到高电平的发光控制信号EMS，第二发光控制晶体管T6截止。
在发光阶段P3，输入高电平的驱动复位控制信号RST1，高电平的扫描信号GA、低电平的发光控制信号EM和低电平的数据信号DA。
在发光阶段P3，第一发光控制晶体管T5的栅极接收到低电平的发光控制信号EM，第一发光控制晶体管T5导通，从而将第一电压Vdd施加至第一节点。第二发光控制晶体管T6的栅极接收到低电平的发光控制信号EM，第二发光控制晶体管T6导通，从而将驱动晶体管T2产生的驱动电流施加至OLED。
此外，在发光阶段P3，驱动复位晶体管T3的栅极接收到高电平的驱动复位控制信号RST1，驱动复位晶体管T3截止；发光复位晶体管T7的栅极接收到高电平的发光复位控制信号RST2，发光复位晶体管T7；数据写入晶体管T1的栅极接收到高点平的扫描信号GA，数据写入晶体管T1 截止；补偿晶体管T4的栅极接收到高电平的扫描信号GA，补偿晶体管T4截止。
容易理解，在发光阶段P3，由于第一发光控制晶体管T5导通，第一节点的电压为Vdd，而第二节点的电压为Vdata+Vth，所以驱动晶体管T2也导通。
在发光阶段P3，OLED的阳极和阴极分别接入了第一电压Vdd(高电压)和第二电压Vss(低电压)，从而在驱动晶体管T2产生的驱动电流的驱动下发光。
基于驱动晶体管T2的饱和电流公式，驱动OLED发光的驱动电流ID可以根据下式得出：
ID＝K(VGS-Vth)2
＝K[(Vda+Vth-Vdd)-Vth]2
＝K(Vda-Vdd)2
在上述公式中，Vth表示驱动晶体管Td的阈值电压，VGS表示驱动晶体管Td的栅极和源极之间的电压，K为常数。从上式可以看出，流经OLED的驱动电流ID不再与驱动晶体管T2的阈值电压Vth有关，而只与数据信号DA的电压Vda有关，由此可以实现对驱动晶体管T2的阈值电压Vth的补偿，解决了驱动晶体管Td由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流ID的影响，从而可以改善显示效果。
例如，上述公式中K可以表示为：
K＝0.5nCox(W/L)，
其中，n为驱动晶体管Td的电子迁移率，Cox为驱动晶体管Td的栅极单位电容量，W为驱动晶体管Td的沟道宽，L为驱动晶体管Td的沟道长。
图6为驱动图2中的阵列基板的信号的时序图。
下面参考图6，对本公开的实施例提供的阵列基板中的第m行子像素的工作过程进行说明。
如图6所示，第m行子像素中的第2n-1列子像素的工作过程分为三个阶段，分别是第一复位阶段P1O、第一数据写入与补偿阶段P2O和第一发光阶段P3O；第m行子像素中的第2n列子像素的工作过程也分为三个阶段，分别是第二复位阶段P1E、第二数据写入与补偿阶段P2E和第三发光阶段P3E。
如图6所示，在第一复位阶段P1O向第m行子像素中的第2n-1列子像素提供低电平的驱动复位控制信号RST1O，以对第m行子像素中的第2n-1列子像素进行复位。
在本公开的实施例中，驱动复位控制信号RST1可以指第m-1对扫描信号线S m-1中的第一扫描信号线SO m-1提供的第一扫描信号GAO充当的驱动复位控制信号。
如图6所示，在第一数据写入与补偿阶段P2O向第m行子像素中的第2n-1列子像素提供低电平的扫描信号GAO和高电平的数据信号DAO，以对第m行子像素中的第2n-1列子像素进行数据写入和补偿。
例如，扫描信号GAO指的是第m对扫描信号线S m中的第一扫描信号线SO m提供的第一扫描信号。
例如，数据信号DAO指的是与第2n-1列子像素对应的一条数据线提供的数据信号。例如，相邻两列像素子像素共用一条数据线的情况下，数据信号DAO指第n条数据信号线Dn提供的数据信号。
如图6所示，在第一发光阶段P3O向第m行子像素中的第2n-1列子像素提供低电平的发光控制信号EMS，以使第m行子像素中的第2n-1列子像素进行显示。
例如，发光控制信号EMS指的是第m条发光控制信号线Em提供的发光控制信号。
如图6所示，在第二复位阶段P1E向第m行子像素中的第2n列子像素提供低电平的驱动复位控制信号RST1E，以对第m行子像素中的第2n列子像素进行复位。
例如，驱动复位控制信号RST1E指的是第m对扫描信号线SE中的第二扫描信号线SE m提供的第二扫描信号，也就是扫描信号GAE。
如图6所示，在第二数据写入与补偿阶段P2E向第m行子像素中的第2n列子像素提供低电平的扫描信号GAE和高电平的数据信号DAE，以对第m行子像素中的第2n列子像素进行数据写入和补偿。
例如，扫描信号GAE指的是第m对扫描信号线S m中的第二扫描信号线SE m提供的第二扫描信号。
例如，数据信号DAE指的是与第n+1列子像素对应的一条数据线提供的数据信号。例如，相邻两列像素子像素共用一条数据线的情况下，数据信号DAE指第n+1条数据信号线Dn+1提供的数据信号。
如图6所示，在第二发光阶段P3E向第m行子像素中的第2n列子像素提供低电平的发光控制信号EMS，以使第m行子像素中的第2n列子像素进行显示。
例如，发光控制信号EMS指的是第m条发光控制信号线E m提供的发光控制信号。
参考图6可知，在第m行子像素中，第2n-1列子像素的扫描信号GAO可以充当第2n列子像素的复位信号RST1E。在这种情况下，在对第2n-1列子像素进行数据写入与补偿的同时，可以对第2n列子像素进行复位，也就是说，第一数据写入与补偿阶段P2O与第二复位阶段P1E在时间上可以是同步的。
参考图6可知，在第m行子像素中，第2n-1列子像素的发光控制信号EMS与第2n列子像素的发光控制信号EMS是同一个发光控制信号，也就是说，第一发光阶段P3O与第二发光阶段P3E在时间上可以是同步的。
此外，参考图6可知，在第m行子像素中，是先对第2n-1列子像素进行复位，然后同时对第2n-1列子像素进行数据写入与补偿并对第2n列子像素进行复位，然后在对第2n列子像素进行数据写入与补偿，最后同时使第2n-1列子像素和第2n列子像素进行显示。在这种情况下，第一复位阶段P1O、第一数据写入与补偿阶段P2O、第一发光阶段P3O、第二复位阶 段P1E、第二数据写入与补偿阶段P2E和第三发光阶段P3E在时间上的顺序为：P1O→P2O&P1E→P2E→P3O&P3E。由此可知，在第m行子像素中，第2n-列子像素和第2n列子像素的充电过程(第一数据写入与补偿阶段P2O和第二数据写入与补偿阶段P2E)分开进行且充电时长相同，并且第2n-1列子像素和第2n列子像素的发光过程(第一发光阶段P3O和第三发光阶段P3E)同步且发光时长相同，这可以使得第m行子像素中的第2n-1列子像素和第2n列子像素的发光亮度均匀，改善显示质量。
需要说明的是，尽管在图6中示出第m行子像素中的第2n-1列子像素和第2n列子像素接收不同的数据信号(第2n-1列子像素接收数据信号DAO，第2n列子像素接收数据信号DAE)，但是由于第m行子像素中的第2n-2列子像素和第2n列子像素的充电过程(第一数据写入与补偿阶段P2O和第二数据写入与补偿阶段P2E)是分开进行的，所以第2n-1列子像素和第2n列子像素公用同一条数据线的技术方案得以实现。具体地，这个数据信号在第一数据写入与补偿阶段P2O和第二数据写入与补偿阶段P2E均处于高电平状态。由于在第一数据写入与补偿阶段P2O时第2n-1列子像素处于工作状态而第2n列子像素处于不工作状态(扫描信号GAO处于低电平，扫描信号GAE处于高电平)，且在第二数据写入与补偿阶段P2E第2n-1列子像素处于不工作状态而第2n列子像素处于工作状态(扫描信号GAO处于高电平，扫描信号GAE处于低电平)，所以通过同一条数据线可以在第一数据写入与补偿阶段P2O向第2n-1列子像素提供高电平的数据信号，并且在第二数据写入与补偿阶段P2E向第2n列子像素提供高电平的数据信号。需要说明的是，尽管仅结合图6对本公开的实施例提供的阵列基板中的第m行子像素的工作过程进行了说明，但是本公开的实施例提供的阵列基板中的其他行的子像素(例如，第m-1行子像素)的工作过程与第m行子像素的工作过程是类似的，因此可以参考上面结合图6对第m行子像素的工作过程所做的描述，这里不再赘述。
图7-13示出了根据本公开的实施例的阵列基板中各层的平面示意图。图7-13所示的示例以四个子像素的像素电路为例。在本公开的实施例中， 第m行第2n-1列子像素和第2n列子像素可被视为最小重复单元。在图7-13中，对第m行第2n-1列子像素和第2n列子像素包括的像素电路的各晶体管的位置进行示意。应理解，其他子像素的像素电路包括的晶体管与第m行第2n-1列子像素和第2n列子像素包括的晶体管的位置大致相同。
下面结合附图7-13描述像素电路中的各个电路在衬底上的位置关系。
需要说明的是，以下内容均为针对所述第m行子像素描述，并且针对可被视为最小重复单元的第2n-1列子像素和第2n列子像素的描述的。需要说明的是，在以下平面布局图中，各个层的平面布局被放大，以更清楚地示出各个层的各个部分。本领域的技术人员将理解，图7-13中的比例为绘制比例，以便于更清楚地表示各部分的位置，其不可视为部件的真实比例。本领域技术人员可基于实际需求来选择各部件的尺寸，本公开对此不作具体限定。
在本公开的实施例中，阵列基板包括位于衬底上的有源半导体层。
图7示出了根据本公开的实施例的阵列基板中的有源半导体层310的平面示意图。有源半导体层包括像素电路中的晶体管的有源区。在本公开的示例性实施例中，有源半导体层310可用于制作上述的驱动晶体管、数据写入晶体管、补偿晶体管、第一发光控制晶体管、第二发光控制晶体管、驱动复位晶体管和发光复位晶体管的有源区。在本公开的示例性实施例中，有源半导体层310包括各晶体管的有源层图案和掺杂区图案(即，晶体管的第一源/漏区和第二源/漏区)。在本公开的实施例中，各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，在图7中，白色圆圈被示出为以便更清楚地标示有源半导体层310中的用于各个晶体管源/漏区的区域。
如图7所示，第2n-1列子像素的有源半导体层310包括彼此间隔设置的第一部分311、第二部分312和第三部分313。第一部分311和第二部分312沿行方向Y依次设置。第一部分311和第二部分312的组合和第三部分313与沿列方向X依次设置。第一部分311包括第2n-1列子像素中的驱动复位晶体管T7的有源区T7-a和补偿晶体管T4的有源区T4-a。第二部 分312包括第2n-1列子像素中的数据写入晶体管T1的有源区T1-a。第三部分313包括第2n-1列子像素中的驱动晶体管T2的有源区T2-a、第一发光控制晶体管T5的有源区T5-a、第二发光控制晶体管T5的有源区T6-a和发光复位晶体管T3的有源区T3-a。
如图7所示，第2n列子像素的有源半导体层包括沿列方向X依次设置的第四部分314和第五部分315。第四部分314包括第2n列子像素中的驱动复位晶体管T7的有源区T7-a、数据写入晶体管T1的有源区T1-a、补偿晶体管T4的有源区T4-a、驱动晶体管T2的有源区T2-a、第一发光控制晶体管T5的有源区T5-a和第二发光控制晶体管T6的有源区T6-a。第五部分315包括第2n列子像素中的发光复位晶体管T3的有源区T3-a。
在本公开的示例性实施例中，用于各晶体管的有源半导体层可以包括一体形成的低温多晶硅层。各晶体管的源极区域和漏极区域可以通过掺杂等进行导体化以实现各结构的电连接。也就是，每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即，源极区域s和漏极区域)和有源层图案。不同晶体管的有源层之间由掺杂结构隔开。
作为示例，有源半导体层310可以由非晶硅、多晶硅、氧化物半导体材料等形成。作为另一示例，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
在本公开的实施例中，阵列基板还包括位于有源半导体层的远离衬底的一侧的第一导电层。
图8示出了根据本公开的实施例的阵列基板中的第一导电层320的平面示意图。如图8所示，第一导电层320包括沿列方向X依次设置的第一驱动复位控制信号线RO m、第一扫描信号线SO m、第二扫描信号线SE m、电容器C的第一极CC1、发光控制信号线E m、第一发光复位控制信号线RO m+1和第二发光复位控制信号线SO m+1/RE m+1。在本公开的示例性实施例中，第一扫描信号线SO m用作第二驱动复位控制信号线RE m。电容器C的第一极CC1与驱动晶体管的栅极T2-g为一体结构。
在本公开的实施例中，参考图7和图8，第一驱动复位控制信号线RO m的在衬底上的正投影与有源半导体层310的第一部分311在衬底上的正投影重叠的部分为第2n-1列子像素中的驱动复位晶体管T7的栅极T7-g1、T7-g2。第一扫描信号线SO m的在衬底上的正投影与有源半导体层310的第一部分311、第二部分312和第四部分314在衬底上的正投影重叠的部分分别为第2n-1列子像素中的补偿晶体管T4的栅极T4-g1、T4-g2和数据写入晶体管T1的栅极T1-g以及第2n列子像素中的驱动复位晶体管T7的栅极T7-g1、T7-g2。第二扫描信号线SE m的在衬底上的正投影与有源半导体层310的第四部分314在衬底上的正投影重叠的部分分别为第2n列子像素中的数据写入晶体管T1的栅极T1-g和补偿晶体管T4的栅极T4-g1、T4-g2。第2n-1列子像素中的电容器C的第一极CC1的在衬底上的正投影与有源半导体层310的第三部分313在衬底上的正投影重叠的部分为第2n-1列子像素中的驱动晶体管T2的栅极T2-g。第2n列子像素中的电容器C的第一极CC1的在衬底上的正投影与有源半导体层310的第四部分314在衬底上的正投影重叠的部分为第2n列子像素中的驱动晶体管T2的栅极T2-g。发光控制信号线E m的在衬底上的正投影与有源半导体层310的第三部分313和第四部分314在衬底上的正投影重叠的部分分别为第2n-1列子像素中的第一发光控制晶体管T5的栅极T5-g和第二发光控制晶体管T6的栅极T6-g以及第2n列子像素中的第一发光控制晶体管T5的栅极T5-g和第二发光控制晶体管T6的栅极T6-g。第一发光复位控制信号线RO m+1的在衬底上的正投影与有源半导体层310的第三部分313在衬底上的正投影重叠的部分为第2n-1列子像素中的发光复位晶体管T3的栅极T3-g。第二发光复位控制信号线SO m+1/RE m+1的在衬底上的正投影与有源半导体层310的第五部分315在衬底上的正投影重叠的部分为第2n列子像素中的发光复位晶体管T3的栅极T3-g。
在本公开的实施例中，如图8所示，在行方向Y上，对于第m行第2n-1列子像素和第2n列子像素，驱动复位晶体管T7的栅极T7-g1、T7-g2、补偿晶体管T4的栅极T4-g1、T4-g2和数据写入晶体管T1的栅极T1-g位 于驱动晶体管T2的栅极T2-g的第一侧。第一发光控制晶体管T5的栅极T5-g、第二发光控制晶体管T6的栅极T6-g和发光复位晶体管T3的栅极T3-g位于驱动晶体管T2的栅极T2-g的第二侧。
需要说明的是，驱动晶体管T2的栅极T2-g的第一侧和第二侧为驱动晶体管T2的栅极T2-g的在行方向Y上的相对两侧。例如，如图8所示，在XY面内，驱动晶体管T2的栅极T2-g的第一侧可以为驱动晶体管T2的栅极T2-g的上侧。驱动晶体管T2的栅极T2-g的第二侧可以为驱动晶体管T2的栅极T2-g的下侧。在本公开的描述中，所述下侧例如为阵列基板的用于绑定IC的一侧。例如，驱动晶体管T2的栅极T2-g的下侧为驱动晶体管T2的栅极T2-g的靠近IC(图中未示出)的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管T2的栅极T2-g的远离IC的一侧。
更具体地，驱动复位晶体管T7的栅极T7-g1、T7-g2位于补偿晶体管T4的栅极T4-g1、T4-g2和数据写入晶体管T1的栅极T1-g的上侧。发光复位晶体管T3的栅极T3-g位于第一发光控制晶体管T5的栅极T5-g和第二发光控制晶体管T6的栅极T6-g的下侧。
在本公开的实施例中，在列方向X上，对于第m行第2n-1列子像素，如图8所示，驱动复位晶体管T7的栅极T7-g1、T7-g2、补偿晶体管T4的栅极T4-g1、T4-g2、第二发光控制晶体管T6的栅极T6-g和发光复位晶体管T3的栅极T3-g位于驱动晶体管T2的栅极T2-g的第三侧。数据写入晶体管T1的栅极T1-g和第一发光控制晶体管T5的栅极T5-g位于驱动晶体管T2的栅极T2-g的第四侧。
需要说明的是，驱动复位晶体管T7的栅极T7-g1、T7-g2的第三侧和第四侧为驱动晶体管T2的栅极T2-g的在列方向X上的相对两侧。例如，如图8所示，在XY面内，驱动晶体管T2的栅极T2-g的第三侧可以为驱动晶体管T2的栅极T2-g的左侧。驱动晶体管T2的栅极T2-g的第四侧可以为驱动晶体管T2的栅极T2-g的右侧。
更具体地，补偿晶体管T4的栅极T4-g1、T4-g2位于数据写入晶体管T1的栅极T1-g的左侧。第一发光控制晶体管T5的栅极T5-g位于第二发 光控制晶体管T6的栅极T6-g的右侧。
在本公开的实施例中，在列方向X上，对于第m行第2n列子像素，如图8所示，数据写入晶体管T1的栅极T1-g和第一发光控制晶体管T5的栅极T5-g位于驱动晶体管T2的栅极T2-g的第三侧。驱动复位晶体管T7的栅极T7-g1、T7-g2、补偿晶体管T4的栅极T4-g1、T4-g2、第二发光控制晶体管T6的栅极T6-g和发光复位晶体管T3的栅极T3-g位于驱动晶体管T2的栅极T2-g的第四侧。
类似地，驱动晶体管T2的栅极T2-g的第三侧和第四侧为驱动晶体管T2的栅极T2-g的在列方向X上的相对两侧。例如，如图8所示，在XY面内，驱动晶体管T2的栅极T2-g的第三侧可以为驱动晶体管T2的栅极T2-g的左侧，驱动晶体管T2的栅极T2-g的第四侧可以为驱动晶体管T2的栅极T2-g的右侧。
更具体地，补偿晶体管T4的栅极T4-g1、T4-g2位于数据写入晶体管T1的栅极T1-g的右侧。第一发光控制晶体管T5的栅极T5-g位于第二发光控制晶体管T6的栅极T6-g的左侧。
需要说明的是，在附图中，第2n-1列子像素中的驱动复位晶体管T7和补偿晶体管T4的栅极为双栅极结构；以及第2n列子像素中的驱动复位晶体管T7和补偿晶体管T4的栅极为双栅极电极。尽管在附图中示出为双栅极电极结构，但是本公开并不限于此。本公开的晶体管也可以采用单栅极结构，本领域的技术人员可以根据实际需要进行选择。
应注意，图8示出的各晶体管的有源区对应于第一导电层320与有源半导体层310交叠的各个区域。
在本公开的实施例中，阵列基板还包括位于第一导电层的远离衬底的一侧的第二导电层。
图9示出了根据本公开的实施例的阵列基板中的第二导电层330的平面示意图。如图9所示，第二导电层330包括沿列方向X设置的电容器的第二极CC2和作为第一电压源的第一电源信号线VD m1。
在本公开的实施例中，参考图8和图9，电容器C的第二极CC2和电 容器C的第一极CC1在衬底上的投影至少部分重叠。
在本公开的示例性实施例中，如图9所示，第一电源信号线VD m1沿行方向Y延伸并与电容器C的第二极CC2一体形成。
在本公开的实施例中，阵列基板还包括位于第二导电层的远离衬底的一侧的第三导电层。
图10示出了根据本公开的实施例的阵列基板中的第三导电层340的平面示意图。如图10所示，第三导电层340包括数据信号线D n和D n+1、复位电源信号线V n、V n+1、作为第一电压源的第二电源信号线VD m2、作为第一电压源的第三电源信号线VD m3、第一连接部341、第二连接部342、第三连接部343、第四连接部344、第五连接部345以及第六连接部346。
在本公开的实施例中，第一连接部341、第二连接部342和第三连接部343沿行方向Y依次设置。第四连接部344沿列方向X设置在第一连接部341、第二连接部342和第三连接部343的下侧。在本公开的实施例中，第五连接部345和第六连接部346沿列方向X依次设置。第六连接部346位于第五连接部345的下侧。
需要说明的是，在图10中，白色圆圈被示出为以便更清楚地标示第三导电层中的各连接部的两端的区域。
需要说明的是，在本公开的实施例中，在有源半导体层310与第一导电层320之间、在第一导电层320与第二导电层330之间以及在第二导电层330与第三导电层340之间还分别设置有绝缘层或介质层(其在稍后关于截面图进行具体描述)。
应注意，以下描述的过孔(未示出)为同时贯穿有源半导体层310与第一导电层320之间的、在第一导电层320与第二导电层330之间的以及在第二导电层330与第三导电层340之间的各绝缘层或介质层的过孔。
参考图7和图10，第一连接部341的一端3411经由过孔耦接第2n-1列子像素的补偿晶体管T4的第一极T4-1(例如，该第一极对应于晶体管的第一源/漏区，以下描述与之类似)。第一连接部341的另一端3412经由过孔耦接第2n-1列子像素的驱动晶体管T2的第二极T4-2(例如，该第二 极对应于晶体管的第二源/漏区，以下描述与之类似)。
第二连接部342的一端3421经由过孔耦接第2n-1列子像素的驱动复位晶体管T7的第一极T7-1和补偿晶体管T4的第二极T4-2。第二连接部342的另一端3422经由过孔耦接第2n-1列子像素的驱动晶体管T2的栅极T2-g和电容器C的第一极CC1。
第三连接部343的一端3431经由过孔耦接第2n-1列子像素的数据写入晶体管T1的第二极T1-2。第三连接部343的另一端3432经由过孔耦接第2n-1列子像素的驱动晶体管T2的第一极T2-1。
第四连接部344经由过孔耦接第2n-1列子像素的第二发光控制晶体管T6的第二极T6-2和发光复位晶体管T3的第一极T3-1。
第五连接部345的一端3451经由过孔耦接第2n列子像素的驱动复位晶体管T7的第一极T7-1和补偿晶体管T4的第二极T4-2。第五连接部345的另一端3452经由过孔耦接第2n列子像素的驱动晶体管T2的栅极T2-g和电容器C的第一极CC1。
第六连接部346的一端3461经由过孔耦接第2n列子像素的第二发光控制晶体管T6的第二极T6-2。第六连接部346的另一端3462经由过孔耦接第2n列子像素的发光复位晶体管T3的第一极T3-1。
在本公开的实施例中，如图10所示，数据信号线D n经由过孔耦接第2n-1列子像素的数据写入晶体管T1的第一极T1-1和第2n列子像素的数据写入晶体管T1的第一极T1-1。需要说明的是，在图10中，标示在数据信号线D n上的白色方框表示的是与过孔对应的区域。
在本公开的实施例中，如图10所示，复位电源信号线V n+1具有在列方向X上设置的第一突出部V n+1-1、第二突出部V n+1-2、第三突出部V n+1-3和第四突出部V n+1-4。第一突出部V n+1-1和第二突出部V n+1-2从复位电源信号线V n+1朝向第2n列子像素延伸。第三突出部V n+1-3和第四突出部V n+1-4从复位电源信号线V n+1朝向第2n+1列子像素延伸。第一突出部V n+1-1位于第五连接部345的上侧。第二突出部V n+1-2位于第六连接部346的下侧。第三突出部V n+1-3位于第一连接部341的上侧且位于第二连接部342 的一端3421的左侧。第四突出部V n+1-4位于第四连接部的下侧。需要说明的是，对于第2n+1列子像素的描述同样可应用于第2n-1列子像素的描述。
在本公开的实施例中，参考图7和图10，第一突出部V n+1-1经由过孔耦接第2n列子像素的驱动复位晶体管T7的第一极T7-1。第二突出部V n+1-2经由过孔耦接第2n列子像素的发光复位晶体管T3的第二极T3-2。第三突出部V n+1-3经由过孔耦接第2n+1列子像素的驱动复位晶体管T7的第二极T7-2。第四突出部V n+1-4经由过孔耦接第2n+1列子像素的发光复位晶体管T3的第二极T3-2。
在本公开的实施例中，如图10所示，第二电源信号线VD m2沿列方向X延伸且位于第2n-1列子像素中。第二电源信号线VD m2位于第一连接部341、第二连接部342、第三连接部343和第四连接部344与数据线D n之间。
参考图7、图9和图10，第二电源信号线VD m2经由过孔耦接第2n-1列子像素的电容器C的第二极CC2和第一发光控制晶体管T5的第一极T5-1。在图10中，标示在第二电源信号线VD m2上的白色方框表示的是与过孔对应的区域。
在本公开的实施例中，如图10所示，第三电源信号线VD m3沿列方向X延伸且位于第2n列子像素中。第三电源信号线VD m3位于第五连接部345和第六连接部346与复位电源信号线V n+1之间。
参考图7、图9和图10，第三电源信号线VD m3经由过孔耦接第2n列子像素的电容器C的第二极CC2和第一发光控制晶体管T5的第一极T5-1。在图10中，标示在第三电源信号线VD m3上的白色方框表示的是与过孔对应的区域。
在本公开的替代实施例中，在图9的结构的基础上，如图11所示，第二导电层330’还包括沿行方向Y延伸的第一附加复位电源信号线Va1和第二附加复位电源信号线Va2。
在本公开的实施例中，如图11所示，电容器C的第二极CC2和第一电源信号线VD m1沿列方向X位于第一附加复位电源信号线Va1和第二附 加复位电源信号线Va2之间。第一附加复位电源信号线Va1位于电容器C的第二极CC2的上侧。第二附加复位电源信号线Va2位于电容器C的第二极CC2的下侧。
需要说明的是，关于电容器C的第二极CC2和第一电源信号线VD m1的描述与上述关于图9的描述类似，在此不再赘述。
在图11所示的上述实施例的基础上，阵列基板还包括位于第二导电层的远离衬底的一侧的第三导电层。
图12示出了根据本公开的实施例的阵列基板中的第三导电层340’的平面示意图。如图12所示，第三导电层340’包括数据信号线D n、D n+1、复位电源信号线V n’、V n+1’、作为第一电压源的第二电源信号线VD m2、作为第一电压源的第三电源信号线VD m3、第一连接部341、第二连接部342、第三连接部343、第四连接部344、第五连接部345、第六连接部346、第七连接部347、第八连接部348、第九连接部349以及第十连接部3410。
需要说明的是，关于数据信号线D n、D n+1、第二电源信号线VD m2、第三电源信号线VD m3、第一连接部341、第二连接部342、第三连接部343、第四连接部344、第五连接部345、第六连接部346的描述与上述关于图10的描述类似，在此不再赘述。
在本公开的实施例中，第七连接部347位于第一连接部341、第二连接部342和第三连接部343的上侧。第八连接部348位于第四连接部344的下侧。第九连接部349位于第五连接部345的上侧。第十连接部3410位于第六连接部346的左侧。
需要说明的是，在图12中，白色圆圈被示出为以便更清楚地标示第三导电层中的各连接部的两端的区域。
需要说明的是，在本公开的实施例中，在有源半导体层310与第一导电层320之间、在第一导电层320与第二导电层330’之间以及在第二导电层330’与第三导电层340’之间还分别设置有绝缘层/介质层(其在稍后关于截面图进行具体描述)。
应注意，以下描述的过孔(未示出)为同时贯穿有源半导体层310与 第一导电层320之间的、在第一导电层320与第二导电层330’之间的以及在第二导电层330’与第三导电层340’之间的各绝缘层/介质层的过孔。
参考图7和图12，第七连接部347的一端3471经由过孔耦接第一附加复位电源信号线Va1。第七连接部347的另一端3472经由过孔耦接第2n-1列子像素的驱动复位晶体管T7的第二极T7-2。
第八连接部348的一端3481经由过孔耦接第二附加复位电源信号线Va2。第八连接部348的另一端3481经由过孔耦接第2n-1列子像素的发光复位晶体管T3的第二极T3-2。
第九连接部349的一端3491经由过孔耦接第一附加复位电源信号线Va1。第九连接部349的另一端3492经由过孔耦接第2n列子像素的驱动复位晶体管T7的第二极T7-2。
第十连接部3410的一端34101经由过孔耦接第二附加复位电源信号线Va2。第十连接部3410的另一端34102经由过孔耦接第2n列子像素的发光复位晶体管T3的第二极T3-2。
在本公开的实施例中，参考图11和图12，复位电源信号线V n+1’经由过孔耦接第一附加复位电源信号线Va1和第二附加复位电源信号线Va2。在图12中，标示在复位电源信号线Vn+1’上的白色方框表示的是与过孔对应的区域。
在图10或图12的基础上，在本公开的实施例中，阵列基板还包括位于第三导电层的远离衬底的一侧的第四导电层。
图13示出了根据本公开的实施例的阵列基板中的第四导电层350的平面示意图。如图13所示，第四导电层350包括作为第一电压源的第四电源信号线VD m4、第十一连接部351以及第十二连接部352。在本公开的示例性实施例中，第四电源信号线VD m4沿列方向X和行方向Y交叉分布。
参考图10或图12和图13，第二电源信号线VD m2在衬底上的正投影与第四电源信号线VD m4在衬底上的正投影至少部分重叠。第三电源信号线VD m3在衬底上的正投影与第四电源信号线VD m4在衬底上的正投影至少部分重叠。
需要说明的是，在本公开的实施例中，在第三导电层340/340’与第四导电层350之间设置有绝缘层/介质层(其在稍后关于截面图进行具体描述)。
应注意，以下描述的过孔(未示出)为位于第三导电层340/340’与第四导电层350之间的有绝缘层/介质层中的过孔。
在本公开的实施例中，第四电源信号线VD m4经由过孔耦接第二电源信号线VD m2和第三电源信号线VD m3。在图13中，标示在第四电源信号线VD m4上的黑色方框表示的是与过孔对应的区域。
在本公开的实施例中，参考图10或图12和图13，第十一连接部351经由过孔耦接第四连接部344和第2n-1列子像素的发光器件(未示出)的第一极，从而使发光器件的第一极耦接第2n-1列子像素的第二发光控制晶体管T6的第二极T6-2和发光复位晶体管T3的第一极T3-1。
在本公开的实施例中，参考图10或图12和图13，第十二连接部352经由过孔耦接第六连接部346的一端3461和第2n列子像素的发光器件(未示出)的第一极，从而使发光器件的第一极耦接第2n列子像素的第二发光控制晶体管T6的第二极T6-2和发光复位晶体管T3的第一极T3-1。
在本公开的示例性实施例中，第四导电层350的材料可以与第三导电层340/340’中的第二电源信号线VD m2和第三电源信号线VD m3的材料相同。
图14和图15示出了堆叠的有源半导体层、第一导电层、第二导电层、第三导电层和第四导电层的平面布局示意图。
图14示出的图基于图9和图10的结构。如图14所示，数据信号线D n经由过孔340-1耦接第2n-1列子像素的数据写入晶体管T1的第一极T1-1，且经由过孔340-2耦接第2n列子像素的数据写入晶体管T1的第一极T1-1。
继续参考图14，复位电源信号线V n+1的第一突出部V n+1-1经由过孔340-3耦接第2n列子像素的驱动复位晶体管T7的第二极T4-2。复位电源信号线V n+1的第二突出部V n+1-2经由过孔340-4耦接第2n列子像素的发光复位晶体管T3的第二极T3-2。复位电源信号线V n+1的第三突出部V n+1-3 经由过孔340-5耦接第2n+1列子像素的驱动复位晶体管T7的第二极T7-2。复位电源信号线V n+1的第四突出部V n+1-4经由过孔340-6耦接第2n+1列子像素的发光复位晶体管T3的第二极T3-2。
需要说明的是，在14中所示的过孔340-1、340-2、340-3、340-4、340-5和340-6均设置在绝缘层/介质(稍后关于截面图描述)中。
在本公开的实施例中，在彼此相邻的奇列子像素(例如，第2n-1列子像素)与偶列子像素(例如，第2n列子像素)之间设置一条数据线并且通过将数据信号分时序写入奇列子像素和偶列子像素，从而可实现数据线的共用。由此，可减少像素电路中数据线的数量、降低布线布局的难度，进而能够实现PPI的提高。
此外，在本公开的实施例中，通过在复位电源信号线上设置四个突出部，进而经由各个突出部耦接相应的晶体管，由此实现在彼此相邻的偶列子像素(例如，第2n列子像素)与奇列子像素(例如，第2n-1列子像素)之间共用一条复位电源信号线，从而进一步减少像素电路中的布线数量，进而进一步实现PPI的提高。
图15示出的图基于图11和图12的结构。数据信号线D n经由过孔340’-1耦接第2n-1列子像素的数据写入晶体管T1的第一极T1-1，且经由过孔340’-2耦接第2n列子像素的数据写入晶体管T1的第一极T1-1。
复位电源信号线V n+1’经由过孔340’-3耦接第一附加复位电源信号线Va1，进而经由第一附加复位电源信号线Va1、第七连接部347耦接第2n+1列的子像素(对第2n-1列子像素同样适用)中的驱动复位晶体管T7的第二极T7-2。
复位电源信号线V n+1’经由过孔340’-4耦接第二附加复位电源信号线Va2，进而经由第二附加复位电源信号线Va2、第十连接部3410耦接第2n列子像素中的发光复位晶体管T3的第二极T3-2耦接。
需要说明的是，在15中所示的过孔340’-1、340’-2、340’-3和340’-4均设置在绝缘层/介质层(稍后关于截面图描述)中。
在本公开的实施例中，在彼此相邻的奇列子像素(例如，第2n-1列子 像素)与偶列子像素(例如，第2n列子像素)之间设置一条数据线并且通过将数据信号分时序写入奇列子像素和偶列子像素，从而可实现数据线的共用。由此，可减少像素电路中数据线的数量、降低布线布局的难度，进而能够实现PPI的提高。
此外，在本公开的实施例中，通过在复位电源信号线的两端设置两条附加复位电源信号线，由此经由两条附加复位电源信号线和相应的连接部耦接相应的晶体管，由此实现在彼此相邻的偶列子像素(例如，第2n列子像素)与奇列子像素(例如，第2n-1列子像素)之间共用一条复位电源信号线，从而进一步减少像素电路中的布线数量，进而进一步实现PPI的提高。
需要说明的是，本公开实施例中采用的晶体管的第一极(即，第一源/漏区)和第二极(即，第二源/漏区)在结构上可以是相同的。
图16示出了根据本公开的实施例的沿图14中的线A1A1’截取的阵列基板的横截面结构示意图。
如图16所示并且参考图7至图10和图13，阵列基板20包括：衬底300；位于衬底300上的缓冲层101；以及位于缓冲层101上的有源半导体层310。该截面图示出了有源半导体层310包括的第2n-1列子像素的补偿晶体管T4的有源区T4-a和数据写入晶体管T1的有源区T1-a以及第2n列子像素的驱动复位晶体管T7的有源区T7-a。
在本公开的实施例中，如图16所示，阵列基板20还包括：覆盖缓冲层101和有源半导体层310的第一栅极绝缘层102；以及位于第一栅极绝缘层102远离衬底300一侧的第一导电层320。该截面示出了第一导电层320包括的第一扫描信号线SO m。如上文所述，该第一扫描信号线SO m为用于第2n-1列子像素的扫描信号线。同时，该第一扫描信号线SO m也是用于第2n列子像素的第二驱动复位控制信号线RE m。以下选择用名称第一扫描信号线SO m来进行描述。如图16所示，第一扫描信号线SO m的在衬底300上的正投影与有源半导体层310包括的第2n-1列子像素的补偿晶体管T4的有源区T4-a和数据写入晶体管T1的有源区T1-a以及第2n列子像素 的驱动复位晶体管T7的有源区T7-a在衬底300上的正投影重叠的部分分别用作第2n-1列子像素的补偿晶体管T4的栅极T4-g2和数据写入晶体管T1的栅极T1-g以及第2n列子像素的驱动复位晶体管T7的栅极T7-g1、T7-g2。
在本公开的实施例中，如图16所示，阵列基板20还包括：位于第一导电层320的远离衬底300一侧的第二栅极绝缘层103；位于第二栅极绝缘层103远离衬底300一侧的层间绝缘层104；以及位于层间绝缘层104远离衬底300一侧的第三导电层340。该截面图示出了第三导电层340包括的复位电源信号线V n、V n+1、第二连接部342、第二电源信号线VD m2、数据信号线D n和第三电源信号线VD m3。如图16所示，数据信号线D n位于第2n-1列子像素与第2n列子像素之间。复位电源信号线V n可位于第2n-1列子像素与第2n-2列子像素。复位电源信号线V n+1可位于第2n列子像素与第2n+1列子像素之间。
在本公开的实施例中，如图16所示，阵列基板20还包括：覆盖层间绝缘层104和第三导电层340的介质层105；以及位于介质层105的远离衬底300一侧的第四导电层350。在本公开的示例性实施例中，介质层105可包括钝化层和位于钝化层上的第一平坦化层(图中未示出)。该截面图示出了第四导电层350包括的第四电源信号线VD m4。如图16所示，第三导电层340包括的第二电源线VD m2在衬底300上的正投影和第三电源线VD m3在衬底300上的正投影与第四导电层350包括的第四电源信号线VD m4在衬底300上的正投影重叠。
在本公开的实施例中，如图16所示，阵列基板20还包括：覆盖介质层105和第四导电层350的第二平坦化层105；以及位于第二平坦化层105的远离衬底300的一侧的像素定义层107。
图17示出了根据本公开的实施例的沿图15中的线A2A2’截取的阵列基板的横截面结构示意图。
图17示出的截面图结构与图16类似，除了第四导电层340’之外。如图17所示，第四导电层340’除了包括复位电源信号线V n’、V n+1’、第二连 接部342、第二电源信号线VD m2、数据信号线D n和第三电源信号线VD m3之外，还包括第九连接部349。关于第九连接部349的描述可参考上述关于图12的描述，在此不再赘述。
此外，关于图17的阵列基板20’中其他部件的描述可参考上述关于图16的阵列基板20的描述，在此不再赘述。
图18示出了根据本公开的实施例的沿图14中的线B1B1’截取的阵列基板的横截面结构示意图。该图同时也可作为沿15中的线B2B2’截取的阵列基板的横截面结构示意图。应注意，该截面图同样可适用于第m行第2n-2列子像素和第2n-1列子像素。
如图18所示并且参考图7至图13，阵列基板20/20’包括：衬底300；位于衬底300上的缓冲层101；以及位于缓冲层101上的有源半导体层310。该截面图示出了有源半导体层310包括的第2n-1列子像素的数据写入晶体管T1的第一极T1-1和第2n列子像素的数据写入晶体管T1的第一极T1-1。
在本公开的实施例中，如图18所示，阵列基板20/20’还包括：覆盖缓冲层101和有源半导体层310的第一栅极绝缘层102；以及位于第一栅极绝缘层102远离衬底300一侧的第一导电层320。该截面示出了第一导电层320包括的第一扫描信号线SO m。如上文所述，该第一扫描信号线SO m为用于第2n-1列子像素的扫描信号线。同时，该第一扫描信号线SO m也是用于第2n列子像素的第二驱动复位控制信号线RE m。
在本公开的实施例中，如图18所示，阵列基板20/20’还包括：覆盖第一栅极绝缘层102和第一扫描信号线SO m的第二栅极绝缘层103；位于第二栅极绝缘层103远离衬底300一侧的层间绝缘层104；以及位于层间绝缘层104远离衬底300一侧的第三导电层340/340’。该截面图示出了第三导电层340/340’包括的第二电源信号线VD m2、数据信号线D n和第三电源信号线VD m3。如图18所示，数据信号线D n位于第2n-1列子像素与第2n列子像素之间。数据信号线D n经由贯穿第一栅极绝缘层102、第二栅极绝缘层103和层间绝缘层104的过孔340-1/340’-1和过孔340-2/340’-2分别连接到第2n-1列子像素的数据写入晶体管T1的第一极T1-1和第2n列子像 素的数据写入晶体管T1的第一极T1-1，从而使第2n-1列子像素和第2n列子像素之间共用一条数据信号线D n。
在本公开的实施例中，如图18所示，阵列基板20/20’还包括：覆盖层间绝缘层104和第三导电层340/340’的介质层105；以及位于介质层105的远离衬底300一侧的第四导电层350。在本公开的示例性实施例中，介质层105可包括钝化层和位于钝化层上的第一平坦化层(图中未示出)。该截面图示出了第四导电层350包括的第四电源信号线VD m4。如图18所示，第三导电层340/340’包括的第二电源线VD m2在衬底300上的正投影和第三电源线VD m3在衬底300上的正投影与第四导电层350包括的第四电源信号线VD m4在衬底300上的正投影重叠。第四电源信号线VD m4经由介质层105的过孔353和过孔354分别连接到第三导电层340/340’包括的第二电源线VD m2和第三电源线VD m3。
在本公开的实施例中，如图18所示，阵列基板20/20’还包括：覆盖介质层105和第四导电层350的第二平坦化层105；以及位于第二平坦化层105的远离衬底300的一侧的像素定义层107。
图19示出了根据本公开的实施例的沿图14中的线C1C1’截取的阵列基板的横截面结构示意图。需要说明的是，该截面图针对阵列基板的第m行第2n列子像素和第2n+1列子像素。应注意，该截面图同样可适用于第m行第2n-2列子像素和第2n-1列子像素。
如图19所示并且参考图7至图10和图13，阵列基板20包括：衬底300；位于衬底300上的缓冲层101；以及位于缓冲层101上的有源半导体层310。该截面图示出了有源半导体层310包括的第2n列子像素的驱动复位晶体管T7的第一极T7-1和第2n+1列子像素的发光复位晶体管T3的第二极T3-2。
在本公开的实施例中，如图19所示，阵列基板20还包括：覆盖缓冲层101和有源半导体层310的第一栅极绝缘层102；以及位于第一栅极绝缘层102远离衬底300一侧的第一导电层320。该截面示出了第一导电层320包括的第二扫描信号线SE m和发光控制信号线E m。
在本公开的实施例中，如图19所示，阵列基板20还包括：覆盖第一栅极绝缘层102和第一导电层320的第二栅极绝缘层103；以及位于第二栅极绝缘层103的远离衬底300一侧的第二导电层330。该截面示出了第二导电层330包括的第一电源信号线VD m1。
在本公开的实施例中，如图19所示，阵列基板20还包括：覆盖第二栅极绝缘层103和第二导电层330的层间绝缘层104；以及位于层间绝缘层104远离衬底300一侧的第三导电层340。该截面图示出了第三导电层340包括的复位电源信号线V n+1。复位电源信号线V n+1的第一突出部V n+1-1经由贯穿第一栅极绝缘层102、第二栅极绝缘层103和层间绝缘层104中的过孔340-3连接到第2n列子像素的驱动复位晶体管T7的第一极T7-1。复位电源信号线V n+1的第四突出部V n+1-4经由贯穿第一栅极绝缘层102、第二栅极绝缘层103和层间绝缘层104中的过孔340-6连接到第2n+1列子像素的发光复位晶体管T3的第二极T3-2。由此，可以实现仅通过一条复位电源信号线V n+1向第2n列子像素(或者第2n-2列子像素)和第2n+1列子像素(或者第2n-1列子像素)提供复位电压。
在本公开的实施例中，如图19所示，阵列基板20还包括：位于第三导电层340的远离衬底300的一侧的介质层105；以及位于介质层105的远离衬底300一侧的第四导电层350。在本公开的示例性实施例中，介质层105可包括钝化层和位于钝化层上的第一平坦化层(图中未示出)。该截面图示出了第四导电层350包括的第四电源信号线VD m4。
在本公开的实施例中，如图19所示，阵列基板20还包括：覆盖介质层105和第四导电层350的第二平坦化层105；以及位于第二平坦化层105的远离衬底300的一侧的像素定义层107。
图20示出了根据本公开的实施例的沿图15中的线C2C2’截取的阵列基板的横截面结构示意图。需要说明的是，该截面图针对阵列基板的第m行第2n列子像素和第2n+1列子像素。应注意，该截面图同样可适用于第m行第2n-2列子像素和第2n-1列子像素。
如图20所示并且参考图7至图8和图11至图13，阵列基板20’包括： 衬底300；位于衬底300上的缓冲层101；以及位于缓冲层101上的有源半导体层310。该截面图示出了有源半导体层310包括的第2n列子像素的驱动复位晶体管T7的第一极T7-1和有源区T7-a和第2n+1列子像素的发光复位晶体管T3的第一极T3-1和第二极T3-2。
在本公开的实施例中，如图20所示，阵列基板20’还包括：覆盖缓冲层101和有源半导体层310的第一栅极绝缘层102；以及位于第一栅极绝缘层102远离衬底300一侧的第一导电层320。该截面示出了第一导电层320包括的第一扫描信号线SO m、第一驱动复位控制信号线RO m、第二扫描信号线SE m和发光控制信号线E m。位于第2n列子像素中的第一扫描信号线SO m可作为第2n列子像素的驱动复位晶体管T7的栅极T7-g2。同时，该第一扫描信号线SO m也是用于第2n列子像素的第二驱动复位控制信号线RE m。
在本公开的实施例中，如图20所示，阵列基板20’还包括：覆盖第一栅极绝缘层102和第一导电层320的第二栅极绝缘层103；以及位于第二栅极绝缘层103的远离衬底300一侧的第二导电层330’。该截面示出了第二导电层330’包括的第一电源信号线VD m1、第一附加复位电源信号线Va1和第二附加复位电源信号线Va2。
在本公开的实施例中，如图20所示，阵列基板20’还包括：覆盖第二栅极绝缘层103和第二导电层330’的层间绝缘层104；以及位于层间绝缘层104远离衬底300一侧的第三导电层340’。该截面图示出了第三导电层340’包括的复位电源信号线V n+1’、第八连接部348和第九连接部349。第八连接部348的一端3481经由层间绝缘层104中的过孔340’-7耦接第二导电层330包括的第二附加复位电源信号线Va2。第八连接部348的另一端3482经由贯穿第一栅极绝缘层102、第二栅极绝缘层103和层间绝缘层104中的过孔340’-8耦接第2n+1列子像素(或者第2n-1列子像素)的发光复位晶体管T3的第二极T3-2。第九连接部349的一端3491经由层间绝缘层104中的过孔340’-6耦接第二导电层330包括的第一附加复位电源信号线Va1。第九连接部349的另一端3492经由贯穿第一栅极绝缘层102、 第二栅极绝缘层103和层间绝缘层104中的过孔340’-5耦接第2n列子像素(或者第2n-2列子像素)的驱动复位晶体管T7的第一极T7-1。复位电源信号线V n+1’经由层间绝缘层104中的过孔340’-3耦接第二导电层330包括的第一附加复位电源信号线Va1，从而经由第九连接部349耦接第2n列子像素(或者第2n-2列子像素)的驱动复位晶体管T7的第一极T7-1。复位电源信号线V n+1’还经由层间绝缘层104中的过孔340’-4耦接第二导电层330包括的第二附加复位电源信号线Va2，从而经由第八连接部348耦接第2n+1列子像素(或者第2n-1列子像素)的发光复位晶体管T3的第二极T3-2。由此，可以实现仅通过一条复位电源信号线V n+1’向第2n列子像素(或者第2n-2列子像素)和第2n+1列子像素(或者第2n-1列子像素)提供复位电压。
在本公开的实施例中，如图20所示，阵列基板20’还包括：位于第三导电层340’的远离衬底300的一侧的介质层105；以及位于介质层105的远离衬底300一侧的第四导电层350。在本公开的示例性实施例中，介质层105可包括钝化层和位于钝化层上的第一平坦化层(图中未示出)。该截面图示出了第四导电层350包括的第四电源信号线VD m4。
在本公开的实施例中，如图20所示，阵列基板20’还包括：覆盖介质层105和第四导电层350的第二平坦化层105；以及位于第二平坦化层105的远离衬底300的一侧的像素定义层107。
在本公开的示例性实施例中，衬底300可包括柔性衬底。作为示例，衬底300可包括依次层叠的第一聚酰亚胺层、第一氧化硅层、第二聚酰亚胺层和第二氧化硅层。
本公开的实施例还提供一种显示面板，该显示面板包括根据本公开任一实施例所述的阵列基板。
图21示出了根据本公开实施例的显示面板的结构示意图。如图21所示，显示面板700可以包括根据本公开任一实施例所述的阵列基板20/20’。
例如，显示面板700还可以包括其他部件，例如时序控制器、信号解码电路、电压转换电路等，这些部件例如可以采用已有的常规部件，这里不再详述。
例如，显示面板700可以为矩形面板、圆形面板、椭圆形面板或多边形面板等。另外，显示面板700不仅可以为平面面板，也可以为曲面面板，甚至球面面板。例如，显示面板700还可以具备触控功能，即显示面板700可以为触控显示面板。
本公开的实施例还提供一种显示装置，该显示装置包括根据本公开任一实施例所述的显示面板。
图22示出了根据本公开的实施例的显示装置的结构示意图。如图22所示，显示装置800可以包括根据本公开任一实施例所述的显示面板700。
显示装置800可以是于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供的显示面板和显示装置具有与本公开前述实施例提供的阵列基板相同或相似的有益效果，由于阵列基板在前述实施例中已经进行了详细说明，此处不再赘述。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的实施例，但是，在合适的情况下，这些元件和特征是可互换的并且可用在所选择的实施例中，即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请，并且所有这些修改都包含在本申请的范围内。

Claims (23)

  1. 一种阵列基板，包括：
    衬底；
    设置在所述衬底上的像素阵列，包括排布为多行多列的多个子像素，其中，每个所述子像素具有像素电路和耦合到所述像素电路的数据信号输入端、扫描信号输入端、驱动复位控制信号输入端，所述像素电路包括数据写入电路、驱动电路和驱动复位电路，所述驱动电路包括控制端、第一端和第二端，所述数据写入电路耦接所述数据信号输入端、所述扫描信号输入端以及所述驱动电路的第一端，并被配置为在扫描信号的控制下将数据信号提供给所述驱动电路的所述第一端，所述驱动电路被配置为向发光器件提供驱动电流，所述驱动复位电路耦接所述驱动复位控制信号输入端、所述驱动电路的所述控制端和所述复位电压端，并被配置为在所述驱动复位控制信号的控制下对所述驱动电路的所述控制端进行复位；
    多对扫描信号线，沿所述行方向延伸且沿所述列方向彼此间隔设置，其中所述多对扫描信号线中的每对包括第一扫描信号线和第二扫描信号线，第m对扫描信号线与第m行子像素对应，m为大于等于1的整数，以及，其中，所述第m对扫描信号线的所述第一扫描信号线被配置为向所述第m行子像素的第2n-1列子像素的所述扫描信号输入端提供第一扫描信号，n为大于等于1的整数，以及所述第m对扫描信号线的所述第二扫描信号线被配置为向所述第m行的第2n列子像素的所述扫描信号输入端提供第二扫描信号；以及
    多对驱动复位控制信号线，沿所述行方向延伸且沿所述列方向彼此间隔设置，其中，所述多对驱动复位控制信号线中的每对包括第一驱动复位控制信号线和第二驱动复位控制信号线，第m对驱动复位控制信号线与第m行子像素对应，
    其中，所述第m对驱动复位控制信号线的所述第一驱动复位控制信号线被配置为向所述第m行子像素的第2n-1列子像素的所述驱动复位控制信号输入端提供第一驱动复位控制信号，以及所述第m对驱动复位控制信号 线的所述第二驱动复位控制信号线被配置为向所述第m行子像素的第2n列子像素的所述驱动复位控制信号输入端提供第二驱动复位控制信号，
    所述第m对扫描信号线的所述第一扫描信号线与所述第m对驱动复位控制信号线的所述第二驱动复位控制信号线为同一信号线。
  2. 根据权利要求1所述的阵列基板，其中，所述数据写入电路包括数据写入晶体管，所述驱动复位电路包括驱动复位晶体管，
    其中，所述数据写入晶体管的第一极与所述数据信号输入端耦接，所述数据写入晶体管的第二极与所述驱动电路的第一端耦接，所述数据写入晶体管的栅极与所述扫描信号端耦接，其中
    所述驱动复位晶体管的第一极与所述驱动电路的控制端耦接，所述驱动复位晶体管的第二极与复位电压端耦接，所述驱动复位晶体管的栅极与所述驱动复位控制信号输入端耦接，
    其中，所述第m对扫描信号线的所述第一扫描信号线包括所述第m行子像素的所述第2n-1列子像素的所述数据写入晶体管的栅极以及所述第m行子像素的所述第2n列子像素的所述驱动复位晶体管的栅极。
  3. 根据权利要求2所述的阵列基板，其中，所述像素电路还包括补偿电路，其耦接所述驱动电路的第二端、所述驱动电路的控制端、和所述扫描信号输入端，并被配置为根据所述扫描信号，对所述驱动电路进行阈值补偿。
  4. 根据权利要求3所述的阵列基板，其中，所述补偿电路包括补偿晶体管，所述补偿晶体管的第一极与所述驱动电路的第二端耦接，所述补偿晶体管的第二极与所述驱动电路的控制端耦接，所述补偿晶体管的栅极与所述扫描信号输入端耦接，以及
    其中，所述第m对扫描信号线的所述第一扫描信号线还包括所述第m行子像素的所述第2n-1列子像素的所述补偿晶体管的栅极。
  5. 根据权利要求4所述的阵列基板，其中，所述像素电路还包括存储电路，所述存储电路耦接第一电压源和所述驱动电路的控制端，被配置为存储所述第一电压源与所述驱动电路的控制端之间的电压差。
  6. 根据权利要求5所述的阵列基板，其中，所述子像素还包括发光控制信号端，所述像素电路还包括发光控制电路,
    其中，所述发光控制电路耦接所述发光控制信号端、所述第一电压端、所述驱动电路和所述发光器件，被配置为将来自所述第一电压源的第一电压施加至所述驱动电路，且将所述驱动电路产生的驱动电流施加至所述发光器件。
  7. 根据权利要求6所述的阵列基板，其中，还包括多个发光控制信号线，其沿列方向延伸，且沿所述行方向彼此间隔，
    其中，第m条发光控制信号线被配置为与第m行子像素的所述发光控制信号端耦接以提供所述发光控制信号。
  8. 根据权利要求7所述的阵列基板，其中，所述子像素还包括发光复位控制信号输入端，所述像素电路还包括发光复位电路，所述发光复位电路耦接所述发光复位控制信号输入端、所述复位电压端和所述发光器件，并被配置为在所述发光复位控制信号的控制下复位所述发光器件。
  9. 根据权利要求8所述的阵列基板，其中，还包括多对发光复位控制信号线，沿所述行方向延伸且沿所述列方向彼此间隔设置，其中所述多对发光复位控制信号线中的每对包括第一发光复位控制信号线和第二发光复位控制信号线，第m对发光复位控制信号线与第m行子像素对应，
    其中，所述第m对发光复位控制信号线的所述第一发光复位控制值信号线被配置为向所述第m行子像素的第2n-1列子像素的所述发光复位控制信号输入端提供第一发光复位控制信号，以及所述第m对发光复位控制信号线的所述第二发光复位控制信号线被配置为向所述第m行子像素的第2n列子像素的所述发光复位控制信号输入端提供第二发光复位控制信号。
  10. 根据权利要求9所述的阵列基板，其中，所述第m对发光复位控制信号线的所述第一发光复位控制信号线与第m+1对驱动复位控制信号线的所述第一驱动复位控制信号线为同一信号线，以及所述第m对发光复位控制信号线的所述第二发光复位控制信号线与第m+1对驱动复位控制信号线的所述第二驱动复位控制信号线为同一信号线。
  11. 根据权利要求10所述的阵列基板，还包括沿列方向延伸的数据信号线，所述每列子像素的数据信号输入端连接到对应的一条数据线以接收数据信号。
  12. 根据权利要求11所述的阵列基板，还包括沿列方向延伸的复位电源信号线，被配置为向对应的像素电路提供复位电压。
  13. 根据权利要求12所述的阵列基板，其中，所述补偿电路包括补偿晶体管，所述发光控制电路包括第一发光控制晶体管和第二发光控制晶体管，所述发光复位电路包括发光复位晶体管，所述存储电路包括电容器，
    其中，所述驱动晶体管的第一极与所述驱动电路的第一端耦接，所述驱动晶体管的第二极与所述驱动电路的第二端耦接，所述驱动晶体管的栅极与所述驱动电路的控制端耦接，
    所述数据写入晶体管的第一极与所述数据信号输入端耦接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极耦接，所述数据写入晶体管的栅极与所述扫描信号输入端耦接，
    所述驱动复位晶体管的第一极与所述驱动晶体管的栅极耦接，所述驱动复位晶体管的第二极与所述复位电压端耦接，所述驱动复位晶体管的栅极与所述驱动复位控制信号输入端耦接，
    所述补偿晶体管的第一极与所述驱动晶体管的第二极耦接，所述补偿晶体管的第二极与所述驱动晶体管的栅极耦接，所述补偿晶体管的栅极与所述扫描信号输入端耦接，
    所述第一发光控制晶体管的第一极与所述第一电压端耦接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极耦接，所述第一发光控制晶体管的栅极与所述发光控制信号输入端耦接，
    所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极耦接，所述第二发光控制晶体管的第二极与所述发光器件的第一极耦接，所述第二发光控制晶体管的栅极与所述发光控制信号输入端耦接，
    所述发光复位晶体管的第一极与所述发光器件的第一极耦接，所述发光复位晶体管的第二极与所述复位电压端耦接，所述发光复位晶体管的栅 极与所述发光复位控制信号输入端耦接，以及
    所述电容器的第一极与所述驱动晶体管的栅极耦接，所述电容器的第二极与所述第一电压端耦接。
  14. 根据权利要求13所述的阵列基板，还包括位于所述衬底上的有源半导体层，所述有源半导体层包括所述像素电路中的晶体管的有源区，其中，对于所述第m行子像素：
    所述第2n-1列子像素的所述有源半导体层包括彼此间隔设置的第一部分、第二部分和第三部分，其中，所述第一部分和所述第二部分沿行方向依次设置，所述第一部分和第二部分的组合和所述第三部分与沿列方向依次设置，
    其中，所述第一部分包括所述第2n-1列子像素中的驱动复位晶体管和补偿晶体管的有源区，
    所述第二部分包括所述第2n-1列子像素中的数据写入晶体管的有源区，以及
    所述第三部分包括所述第2n-1列子像素中的驱动晶体管、第一发光控制晶体管、第二发光控制晶体管和发光复位晶体管的有源区，
    所述第2n列子像素的所述有源半导体层包括沿列方向依次设置的第四部分和第五部分，
    其中，所述第四部分包括所述第2n列子像素中的驱动复位晶体管、数据写入晶体管、补偿晶体管、驱动晶体管、第一发光控制晶体管和第二发光控制晶体管的有源区，以及
    所述第五部分包括所述第2n列子像素中的发光复位晶体管的有源区。
  15. 根据权利要求14所述的阵列基板，还包括位于所述有源半导体层的远离所述衬底的一侧的第一导电层，所述第一导电层包括沿列方向依次设置的所述第一驱动复位控制信号线、所述第一扫描信号线、所述第二扫描信号线、所述电容器的第一极、所述发光控制信号线、所述第一发光复位控制信号线和所述第二发光复位控制信号线，其中，所述第一扫描信号线用作所述第二驱动复位控制信号线，所述电容器的所述第一极与所述驱 动晶体管的所述栅极为一体结构。
  16. 根据权利要求15所述的阵列基板，其中，所述第一驱动复位控制信号线的在所述衬底上的正投影与所述有源半导体层的所述第一部分在所述衬底上的正投影重叠的部分为所述第2n-1列子像素中的驱动复位晶体管的栅极，
    所述第一扫描信号线的在所述衬底上的正投影与所述有源半导体层的所述第一部分、所述第二部分和所述第四部分在所述衬底上的正投影重叠的部分分别为所述第2n-1列子像素中的补偿晶体管和数据写入晶体管以及所述第2n列子像素中的驱动复位晶体管的栅极，
    所述第二扫描信号线在所述衬底上的正投影与所述有源半导体层的所述第四部分在所述衬底上的正投影重叠的部分分别为所述第2n列子像素中的数据写入晶体管和补偿晶体管的栅极，
    所述第2n-1列子像素中的电容器的所述第一极的在所述衬底上的正投影与所述有源半导体层的所述第三部分在所述衬底上的正投影重叠的部分为所述第2n-1列子像素中的驱动晶体管的栅极，
    所述第2n列子像素中的电容器的所述第一极的在所述衬底上的正投影与所述有源半导体层的所述第四部分在所述衬底上的正投影重叠的部分为所述第2n列子像素中的驱动晶体管的栅极，
    所述发光控制信号线的在所述衬底上的正投影与所述有源半导体层的所述第三部分和所述第四部分在所述衬底上的正投影重叠的部分分别为所述第2n-1列子像素中的第一发光控制晶体管和第二发光控制晶体管以及所述第2n列子像素中的第一发光控制晶体管和第二发光控制晶体管的栅极，
    所述第一发光复位控制信号线的在所述衬底上的正投影与所述有源半导体层的所述第三部分在所述衬底上的正投影重叠的部分为所述第2n-1列子像素中的发光复位晶体管的栅极，以及
    所述第二发光复位控制信号线的在所述衬底上的正投影与所述有源半导体层的所述第五部分在所述衬底上的正投影重叠的部分为所述第2n列子像素中的发光复位晶体管的栅极。
  17. 根据权利要求16所述的阵列基板，还包括位于所述第一导电层的远离所述衬底的一侧的第二导电层，所述第二导电层包括沿列方向设置的所述电容器的第二极和作为第一电压源的第一电源信号线，
    其中，所述电容器的第二极和所述电容器的第一极在所述衬底上的投影至少部分重叠，以及所述第一电源信号线沿行方向延伸并与所述电容器的第二极一体形成。
  18. 根据权利要求17所述的阵列基板，还包括位于所述第二导电层的远离所述衬底的一侧的第三导电层，所述第三导电层包括所述数据信号线、所述复位电源信号线、作为所述第一电压源的第二电源信号线、作为所述第一电压源的第三电源信号线、第一连接部、第二连接部、第三连接部、第四连接部、第五连接部以及第六连接部，
    其中，所述第一连接部的一端耦接所述第2n-1列子像素的补偿晶体管的第一极，另一端耦接所述第2n-1列子像素的驱动晶体管的第二极，
    所述第二连接部的一端耦接所述第2n-1列子像素的驱动复位晶体管的第一极，另一端耦接所述第2n-1列子像素的驱动晶体管的栅极，
    所述第三连接部的一端耦接所述第2n-1列子像素的数据写入晶体管的第二极，另一端耦接所述第2n-1列子像素的驱动晶体管的第一极，
    所述第四连接部耦接所述第2n-1列子像素的第二发光控制晶体管的第二极，
    所述第五连接部的一端耦接所述第2n列子像素的驱动复位晶体管的第一极，另一端耦接所述第2n列子像素的驱动晶体管的栅极，
    所述第六连接部的一端耦接所述第2n列子像素的第二发光控制晶体管的第二极，另一端耦接所述第2n列子像素的发光复位晶体管的第一极，
    所述数据信号线耦接所述第2n-1列子像素的数据写入晶体管的第一极和所述第2n列子像素的数据写入晶体管的第一极，
    所述第二电源信号线沿列方向延伸且位于所述第2n-1列子像素中，并耦接所述第2n-1列子像素的所述电容器的第二极和所述第一发光控制晶体管的第一极，以及
    所述第三电源信号线沿列方向延伸且位于所述第2n列子像素中，并耦接所述第2n列子像素的所述电容器的第二极和所述第一发光控制晶体管的第一极。
  19. 根据权利要求17所述的阵列基板，其中，所述第二导电层还包括沿行方向延伸的第一附加复位电源信号线和第二附加复位电源信号线，所述第一附加复位电源信号线和所述第二附加复位电源信号线耦接到所述复位电源信号线，
    其中，所述电容器的第二极和所述第一电源信号线沿列方向位于所述第一附加复位电源信号线与所述第二附加复位电源信号线之间。
  20. 根据权利要求19所述的阵列基板，还包括位于所述第二导电层的远离所述衬底的一侧的第三导电层，所述第三导电层包括所述数据信号线、所述复位电源信号线、作为所述第一电压源的第二电源信号线、作为所述第一电压源的第三电源信号线、第一连接部、第二连接部、第三连接部、第四连接部、第五连接部、第六连接部、第七连接部、第八连接部、第九连接部以及第十连接部，
    其中，所述第一连接部的一端耦接所述第2n-1列子像素的补偿晶体管的第一极，另一端耦接所述第2n-1列子像素的驱动晶体管的第二极，
    所述第二连接部的一端耦接所述第2n-1列子像素的驱动复位晶体管的第一极，另一端耦接所述第2n-1列子像素的驱动晶体管的栅极，
    所述第三连接部的一端耦接所述第2n-1列子像素的数据写入晶体管的第二极，另一端耦接所述第2n-1列子像素的驱动晶体管的第一极，
    所述第四连接部耦接所述第2n-1列子像素的第二发光控制晶体管的第二极，
    所述第五连接部的一端耦接所述第2n列子像素的驱动复位晶体管的第一极，另一端耦接所述第2n列子像素的驱动晶体管的栅极，
    所述第六连接部的一端耦接所述第2n列子像素的第二发光控制晶体管的第二极，另一端耦接所述第2n列子像素的发光复位晶体管的第一极，
    所述第七连接部的一端耦接所述第一附加复位电源信号线，另一端耦 接所述第2n-1列子像素的驱动复位晶体管的第二极，
    所述第八连接部的一端耦接所述第二附加复位电源信号线，另一端耦接所述第2n-1列子像素的发光复位晶体管的第二极，
    所述第九连接部的一端耦接所述第一附加复位电源信号线，另一端耦接所述第2n列子像素的驱动复位晶体管的第二极，
    所述第十连接部的一端耦接所述第二附加复位电源信号线，另一端耦接所述第2n列子像素的发光复位晶体管的第二极，
    所述第二电源信号线沿列方向延伸且位于所述第2n-1列子像素中，并耦接所述第2n-1列子像素的所述电容器的第二极和所述第一发光控制晶体管的第一极，以及
    所述第三电源信号线沿列方向延伸且位于所述第2n列子像素中，并耦接所述第2n列子像素的所述电容器的第二极和所述第一发光控制晶体管的第一极。
  21. 根据权利要求18或20所述的阵列基板，还包括位于所述第三导电层的远离所述衬底的一侧的第四导电层，所述第四导电层包括作为所述第一电压源的第四电源信号线、第十一连接部以及第十二连接部，
    其中，所述第二电源信号线在所述衬底上的正投影与所述第四电源信号线在所述衬底上的正投影至少部分重叠，所述第三电源信号线在所述衬底上的正投影与所述第四电源信号线在所述衬底上的正投影至少部分重叠，
    所述第四电源信号线耦接所述第二电源信号线和所述第三电源信号线，
    所述第十一连接部耦接所述第四连接部，以及
    所述第十二连接部耦接所述第六连接部的所述一端。
  22. 一种显示面板，其包括根据权利要求1至21中任一项所述的阵列基板。
  23. 一种显示装置，其包括根据权利要求22所述的显示面板。
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