WO2022000244A1

WO2022000244A1 - Imaging unit, imaging system, and mobile platform

Info

Publication number: WO2022000244A1
Application number: PCT/CN2020/099163
Authority: WO
Inventors: 徐泽; 占世武; 肖�琳
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2022-01-06
Also published as: CN112823508A

Abstract

The embodiments of the present application provide an imaging unit, an imaging system and a mobile platform. The imaging unit comprises a photosensitive element, a gain adjustment circuit, and an output circuit. The photosensitive element is used for receiving photons to generate and store electric charges generated by the photons; the gain adjustment circuit is used for generating an imaging signal according to the electric charges; and the output circuit is used for outputting the imaging signal. The gain adjustment circuit is capable of adjusting the gain of the imaging signal in response to an adjustment signal sent by a microcontroller. By means of the adjustment of the gain adjustment circuit, the output circuit can output imaging signals suitable for different imaging environments, guaranteeing the imaging quality of the imaging unit in different imaging environments.

Description

Imaging Units, Imaging Systems and Movable Platforms

technical field

The invention relates to the field of photoelectric imaging, in particular to an imaging unit, an imaging system and a movable platform.

Background technique

There is a need to use shooting equipment for shooting in daily entertainment or industrial fields. For example, when users travel, they can use terminal equipment to shoot; for another example, drones can be used to achieve power inspection and so on.

For the above scenes, the shooting environment is usually more complicated. When the light intensity of the shooting environment is weak, the image captured by the shooting device usually has a low signal-to-noise ratio, so that the image quality is not high. When the ambient light intensity is strong, the image captured by the camera is prone to overexposure. Therefore, in different shooting environments, how to ensure the imaging quality of the shooting device becomes an urgent problem to be solved.

SUMMARY OF THE INVENTION

The present invention provides an imaging unit, an imaging system and a movable platform, which are used to ensure imaging effects in different environments.

A first aspect of the present invention is to provide an imaging unit, which includes: a photosensitive element, a gain adjustment circuit, and an output circuit. A photosensitive element for receiving photons to generate and store electric charges generated by the photons; a gain adjustment circuit, electrically connected to the photosensitive element and the microcontroller, and for generating an imaging signal according to the electric charges and an output circuit electrically connected to the gain adjustment circuit, and the output circuit is used to output the imaging signal; wherein the gain adjustment circuit can adjust the gain adjustment signal in response to an adjustment signal sent by the microcontroller Gain of the imaging signal.

A second aspect of the present invention is to provide an imaging system including: a microcontroller and an imaging unit. The microcontroller is used for generating an adjustment signal according to the imaging environment; the imaging unit includes a photosensitive element, a gain adjustment circuit, and an output circuit. A photosensitive element for receiving photons to generate and store electric charges generated by the photons; a gain adjustment circuit, electrically connected to the photosensitive element and the microcontroller, and for generating an imaging signal according to the electric charges and an output circuit electrically connected to the gain adjustment circuit, and the output circuit is used to output the imaging signal; wherein the gain adjustment circuit can adjust the gain adjustment signal in response to an adjustment signal sent by the microcontroller Gain of the imaging signal.

A third aspect of the present invention is to provide a movable platform comprising:

Airframe, power system, imaging system and control system;

the power system, arranged on the body, is used to provide power for the movable platform;

the imaging system, arranged on the body, is used for shooting during the movement of the movable platform;

The imaging system includes: at least one imaging unit provided in the first aspect;

the control system for controlling the imaging system.

In the imaging unit, imaging system and movable platform provided by the present invention, the gain adjustment circuit in the imaging unit can adjust the gain of the imaging signal of the imaging unit, so that the imaging signal after the gain adjustment is adapted to the imaging environment where the imaging unit is located, so as to ensure imaging Image quality of the unit.

Description of drawings

The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation of the present application. In the attached image:

FIG. 1 is a schematic structural diagram of an imaging unit according to an embodiment of the present invention;

2 is a schematic structural diagram of another imaging unit according to an embodiment of the present invention;

3a is a signal timing diagram of each circuit of the imaging unit provided in the embodiment of the present invention in the first gain mode;

3b is a signal timing diagram of each circuit of the imaging unit provided in the embodiment of the present invention in the second (third) gain mode;

FIG. 4 is a schematic structural diagram of another imaging unit according to an embodiment of the present invention;

FIG. 5a is a schematic circuit diagram of an imaging unit provided by an embodiment of the present invention;

FIG. 5b is a schematic circuit diagram of another imaging unit provided by an embodiment of the present invention;

Fig. 6a is a circuit schematic diagram based on the imaging unit shown in Fig. 5a or Fig. 5b, in the first gain mode, the signal timing diagram of each element in the imaging unit;

Fig. 6b is a circuit schematic diagram based on the imaging unit shown in Fig. 5a or Fig. 5b, in the second gain mode, the signal timing diagram of each element in the imaging unit;

Fig. 6c is a circuit schematic diagram based on the imaging unit shown in Fig. 5a or Fig. 5b, in the third gain mode, the signal timing diagram of each element in the imaging unit;

7a is a signal timing diagram of each element in a signal readout stage of a first gain mode of an imaging unit provided by an embodiment of the present invention;

FIG. 7b is a signal timing diagram of each element in the signal readout stage of the second gain mode of the imaging unit provided by the embodiment of the present invention;

7c is a signal timing diagram of each element in the signal readout stage of the third gain mode of the imaging unit provided by the embodiment of the present invention;

8 is a schematic structural diagram of an imaging system according to an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a movable platform according to an embodiment of the present invention.

detailed description

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention.

According to an embodiment of the present invention, an imaging unit is provided. The imaging unit includes: a photosensitive element, a gain adjustment circuit and an output circuit. A photosensitive element for receiving photons to generate and store electric charges generated by the photons; a gain adjustment circuit, electrically connected to the photosensitive element and the microcontroller, and for generating an imaging signal according to the electric charges and an output circuit electrically connected to the gain adjustment circuit, and the output circuit is used to output the imaging signal; wherein the gain adjustment circuit can adjust the gain adjustment signal in response to an adjustment signal sent by the microcontroller Gain of the imaging signal.

As can be seen from the above description, the gain adjustment circuit can adjust the gain of the imaging signal of the imaging unit based on the amount of electric charge stored in the photosensitive element. The imaging signal after gain adjustment is adapted to the imaging environment where the imaging unit is located, so as to ensure the imaging quality of the imaging unit. After the adjustment of the gain adjustment circuit, the imaging signal output by the output circuit can be adapted to different imaging environments, and the imaging quality of the imaging unit can be guaranteed in different imaging environments.

Based on the above description, an embodiment of the present invention provides an imaging unit, where the imaging unit includes: a photosensitive element, a gain adjustment circuit, and an output circuit.

A photosensitive element for receiving photons to generate and store electric charges generated by the photons; a gain adjustment circuit, electrically connected to the photosensitive element and the microcontroller, and for generating an imaging signal according to the electric charges and an output circuit electrically connected to the gain adjustment circuit, and the output circuit is used to output the imaging signal; wherein the gain adjustment circuit can adjust the gain adjustment signal in response to an adjustment signal sent by the microcontroller Gain of the imaging signal.

Embodiments of the present invention also provide an imaging system. The imaging system includes: a microcontroller and an imaging unit. The microcontroller is used for generating an adjustment signal according to the imaging environment; the imaging unit includes a photosensitive element, a gain adjustment circuit, and an output circuit. A photosensitive element for receiving photons to generate and store electric charges generated by the photons; a gain adjustment circuit, electrically connected to the photosensitive element and the microcontroller, and for generating an imaging signal according to the electric charges and an output circuit electrically connected to the gain adjustment circuit, and the output circuit is used to output the imaging signal; wherein the gain adjustment circuit can adjust the gain adjustment signal in response to an adjustment signal sent by the microcontroller Gain of the imaging signal.

The embodiment of the present invention also provides a movable platform, the platform at least includes: a body, a power system, an imaging system and a control system;

the control system for controlling the imaging system.

Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments may be combined with each other without conflict between the embodiments.

The imaging unit provided by the following embodiments of the present invention may be the smallest unit constituting an imaging system, and the imaging system may specifically be a photographing device.

FIG. 1 is a schematic structural diagram of an imaging unit according to an embodiment of the present invention. As shown in FIG. 1 , the imaging unit may include: a photosensitive element 11 , a gain adjustment circuit 12 and an output circuit 13 .

Among them, the photosensitive element 11 is used to receive photons to generate and store the charges generated by the photons. Specifically, the photosensitive element 11 is used to receive photons to generate and store charges generated by the photons when exposed to an imaging environment.

The gain adjustment circuit 12 is electrically connected to the photosensitive element 11 and the microcontroller, and the gain adjustment circuit 11 is used to generate an imaging signal according to electric charges. Optionally, the output imaging signal may be a voltage signal.

The output circuit 13 is electrically connected to the gain adjustment circuit 12, and the output circuit 13 is used for outputting the imaging signal. Wherein, the gain adjustment circuit 12 can adjust the gain of the imaging signal in response to the adjustment signal sent by the microcontroller.

Wherein, the user may first use a photographing device including an imaging unit to photograph in a current photographing environment (ie, an imaging environment). Next, the user can also judge the imaging quality of the captured image by himself, and further trigger the selection of the imaging mode of the photographing device according to the imaging quality. The photographing device may have different imaging modes, and the imaging modes are in one-to-one correspondence with the gain modes of the gain adjustment circuit 12 . Finally, the photographing device may determine the imaging mode of the photographing device in response to the user's selection operation, that is, determine the gain mode of the gain adjustment circuit 12 .

For example, if the user thinks that the brightness of the image captured by the photographing device is insufficient, indicating that the illumination intensity of the current imaging environment is weak, the user may select the first imaging mode. The first imaging mode corresponds to the first gain mode of the gain adjustment circuit 12, ie, the high gain mode. The imaging signal in this mode has the greatest gain.

If the user thinks that the captured image is overexposed, indicating that the current imaging environment has a strong light intensity, the user may select a third imaging mode. The third imaging mode corresponds to the third gain mode of the gain adjustment circuit 12, that is, the low gain mode. The imaging signal in this mode has minimal gain.

Based on the imaging mode selected by the user, the microcontroller can generate an adjustment signal corresponding to the imaging mode and send it to the gain adjustment circuit 12 every time the imaging unit takes an image. The gain adjustment circuit 12 can adjust the gain of the imaging signal according to the adjustment signal to ensure the imaging quality of the imaging unit.

In addition, the gain adjustment circuit 12 also has a second gain mode, that is, a medium gain mode, which is suitable for an imaging environment with moderate illumination intensity.

However, the present invention is not limited to this. In another embodiment, the imaging system may determine the gain of the imaging signal based on the amount of charge (e.g., negative or electronic) stored in the imaging unit.

In one embodiment, the gain adjustment circuit 12 in the imaging unit may adjust the gain of the imaging signal of the imaging unit based on the amount of charge stored in the photosensitive element 11 . The imaging signal after the gain adjustment is adapted to the imaging environment where the imaging unit is currently located, thereby ensuring the imaging quality of the imaging unit. That is to say, after adjustment by the gain adjustment circuit 12 , the output circuit 13 can output imaging signals suitable for different imaging environments, and the imaging quality of the imaging unit can be guaranteed under different imaging environments.

In terms of timing, each imaging cycle of the imaging unit may include three stages, ie, a reset stage, an exposure stage, and a signal readout stage. Based on the embodiment shown in FIG. 1 , FIG. 2 is a schematic structural diagram of another imaging unit according to an embodiment of the present invention, as shown in FIG. 2 . The following describes the specific working states of each circuit in the imaging unit at different stages of the imaging cycle in turn with reference to FIG. 2 :

Optionally, the imaging unit may further include a reset circuit 14 . One end of the reset circuit 14 is connected to the gain adjustment circuit 12, and the other end is connected to the power supply. The gain adjustment circuit 12 is connected to the microcontroller.

When the imaging unit is in the reset stage, the reset circuit 14 is turned on in response to the reset signal sent by the microcontroller. Meanwhile, when the imaging unit is in the reset stage, the photosensitive element 11 can also be discharged through the conduction of the reset circuit 14 . The electric charge stored in the photosensitive element 11 can be completely emptied after discharge, wherein the emptied electric charge is actually the electric charge remaining in the photosensitive element 11 after the last imaging cycle. Wherein, the emptying process of the electric charge may last for a preset time. At this time, the output circuit 13 is in an off state.

According to the description in the above embodiments, the imaging signal output by the output circuit 13 may be a voltage signal. The voltage value of the voltage signal can be expressed as the ratio of the amount of charge stored in the photosensitive element 11 to the capacitance value of the entire imaging unit, and the voltage value can also indirectly reflect the imaging quality. If the charge clearing is not performed, the charge remaining in the photosensitive element 11 after the previous imaging period will affect the voltage value of the imaging signal in the current imaging period, thereby affecting the imaging quality.

Optionally, the imaging unit may further include a switch circuit 15 . One end of the switch circuit 15 is connected to the photosensitive element 11 , and the other end is connected to the gain adjustment circuit 12 .

When the imaging unit is in the reset stage, the photosensitive element 11 , the reset circuit 14 , the switch circuit 15 and the gain adjustment circuit 12 are all in a conducting state.

After the residual charge in the photosensitive element 11 is emptied, the imaging unit enters the exposure stage. During the exposure phase, the photosensitive element 11 is exposed to the imaging environment, receiving photons to generate and store the charge generated by the photons. At the same time, the switch circuit 15 in the imaging unit is switched from the ON state at the reset stage to the OFF state. That is, the switch circuit 15 is in a conducting state when the photosensitive element 11 is emptied of charges, and switches to an off state after the charges are emptied.

In the exposure phase, the reset circuit 14 is in an on state, and the output circuit 13 is in an off state. The exposure stage lasts for a preset duration.

After the exposure of the photosensitive element 11 is completed, the imaging unit further enters a signal readout stage. In this stage, the output circuit 13 first responds to the strobe signal sent by the microcontroller to turn itself on.

After the output circuit 13 is turned on, the output circuit 13 starts to work: when the imaging unit is in the signal readout stage, the output circuit 13 outputs the reference signal and the sample-and-hold signal at different times successively according to the time sequence. The difference between the sample and hold signal and the reference signal is the gain-adjusted imaging signal output by the output circuit 13 .

In one embodiment, the output circuit 13 may output the reference signal first, and then output the sample and hold signal. The reference signal output by the output circuit 13 first is generated according to the charge stored in the gain adjustment circuit 12 ; the sample-hold signal outputted later is generated according to the charge stored in the photosensitive element 11 after exposure. In another embodiment, the output circuit 13 may also output the sample and hold signal first, and then output the reference signal.

It should be noted that the duration of each stage in the imaging process can be preset. Optionally, the signal readout stage has the longest duration, and the reset stage can be less than or equal to the exposure stage.

In this embodiment, on the basis of the embodiment shown in FIG. 1 , the imaging unit further includes a reset circuit 14 and a switch circuit 15 . Based on this structure, on the one hand, when the imaging unit is in the reset stage, the residual charge in the photosensitive element 11 can be emptied, so that it will not affect the imaging. On the other hand, the gain adjustment circuit 12 can adjust the gain of the imaging signal to ensure that the imaging unit can output suitable imaging signals under different imaging environments to ensure imaging quality.

In the embodiment shown in FIG. 2 , the working states of various circuits in the imaging unit at different stages of the imaging process have been described in detail. In practical applications, the working state of each circuit at different stages can be controlled by a microcontroller. Therefore, based on Fig. 2, the working states of each circuit at different stages can be described from the perspective of the timing control of the microcontroller.

The following content involves different signals sent by the microcontroller at different times, and the relationship between the times and the signals can be understood in conjunction with FIGS. 3 a to 3 b . For the three gain modes provided by the gain adjustment circuit 12, Fig. 3a is a signal timing diagram of each circuit in the imaging unit when the gain adjustment circuit 12 is in the first gain mode. FIG. 3b is a signal timing diagram of each circuit in the imaging unit when the gain adjustment circuit 12 is in the second gain mode or the third gain mode.

Specifically, the microcontroller first sends a reset signal at the first time T1, and the reset circuit 14 turns itself on in response to the reset signal. At this time, the imaging unit is also in the reset stage.

When the imaging unit is in the reset stage, the microcontroller may also send an enable signal at the second time T2, and the switch circuit 15 turns itself on in response to the enable signal. At this time, both the switch circuit 15 and the reset circuit 14 are in a conducting state, and the conduction of the two can cause the photosensitive element 11 to be discharged.

Also in the reset phase, after a preset time period, the microcontroller can send a disable signal again at the third time T3, and the switch circuit 15 disconnects itself in response to the disable signal. At this time, the photosensitive element 11 completes the discharge.

The first time T1 is prior to the second time T2, and the second time T2 is prior to the third time T3. The time interval between the second time T2 and the third time T3 is the discharge duration of the photosensitive element 11 . During the discharge time period, the residual charge inside the photosensitive element 11 is emptied by turning on and then turning off the switch circuit 15 first.

After the photosensitive element 11 is discharged, the microcontroller may further control the photosensitive element 11 to be exposed to the imaging environment from the third time T3 to the fourth time T4, so that the photosensitive element 11 receives photons in the imaging environment, generates and Stores the charge produced by photons. The third time T3 precedes the fourth time T4, that is, the imaging unit is in the exposure stage between the third time T3 and the fourth time T4. In the exposure stage, the reset circuit 14 is in an on state, and both the output circuit 13 and the switch circuit 15 are in an off state.

After the exposure of the photosensitive element 11 is completed, the microcontroller may send an adjustment signal at the fourth time T4 , and the adjustment signal corresponds to the current gain mode of the gain adjustment circuit 12 . The gain adjustment circuit 12 turns itself on in response to the adjustment signal. At this time, the imaging unit is also in the signal readout stage.

The adjustment signal may be specifically determined according to the amount of electric charge stored in the photosensitive element and the imaging mode corresponding to the imaging environment in which the imaging unit is located. In different gain modes, the gain adjustment circuit 12 responds to different adjustment signals.

The microcontroller may also send a strobe signal to turn on the output circuit 13 when the imaging unit is in the signal readout phase.

The imaging unit receives the enable signal of the reference signal at the fifth time T5, and at this time, the turned-on output circuit 13 outputs the reference signal of the imaging unit in response to the enable signal.

The microcontroller can also send an enable signal at the sixth time point T6, and the switch circuit 15 in the imaging unit turns on itself in response to this signal. Due to the conduction of the switch circuit 15 , the charge (eg, negative charge or electronic charge) stored by the photosensitive element 11 after the exposure phase can be transferred to the gain adjustment circuit 12 through the switch circuit 15 .

The microcontroller can send a disable signal at the seventh time T7, and the switch circuit 15 in the imaging unit turns itself off in response to this signal. At the seventh time point T7 , it can be considered that the charges in the photosensitive element 11 have all been transferred to the gain adjustment circuit 12 . Next, the imaging unit may also receive the enable signal of the sample and hold signal at the eighth time point T8, and the turned-on output circuit 13 outputs the sample and hold signal of the imaging unit in response to the enable signal. After that, the output circuit 13 completes the output of the sample-and-hold signal. The difference between the sample and hold signal output by the output circuit 13 and the reference signal is the gain-adjusted imaging signal output by the output circuit 13 .

Among them, the fifth time T5 to the eighth time T8 are arranged in sequence as follows: the fifth time T5, the sixth time T6, the seventh time T7, and the eighth time T8.

In this embodiment, the reset circuit 14 is turned on at the first time T1, and the imaging unit is in the reset stage at this time. At the same time, in this reset stage, the switch circuit 15 is turned on at the second time T2 and turned off at the third time T3. By turning on the switch circuit 15 first and then turning it off, the residual charge in the photosensitive element 11 can be emptied, so that the Avoid it affecting image quality. Next, between the third time point T3 and the fourth time point T4, the imaging unit is in an exposure phase, and the photosensitive element 11 re-stores charges in this phase. Then, at the fourth time T4, the imaging unit enters a signal readout phase. In this stage, the output circuit 13 is turned on, and outputs the reference signal at the fifth time T5. As the photosensitive element 11 starts to transfer charges to the gain adjustment circuit 12 at the sixth time T6, the output circuit 13 outputs the adopting hold signal at the eighth time T8. Finally, the difference between the hold signal and the reference signal is used as the imaging signal output by the output circuit 13 , and the imaging signal corresponds to the current imaging environment and can ensure the imaging quality.

Based on the imaging unit shown in FIGS. 1 to 2 , as shown in FIG. 4 , optionally, the imaging unit may further include: a conversion circuit 16 connected to the output circuit 13 .

The gain-adjusted imaging signal output by the output circuit 13 is usually an analog signal. At this time, the conversion circuit 16 can be further used to convert the imaging signal output by the output circuit 13 into a digital signal, and finally output the digital signal.

The above embodiments describe the specific working process of the imaging unit in the form of circuit modules. The specific structure of each circuit module can also be described below.

Optionally, based on the imaging unit shown in FIG. 1 or FIG. 2 , the gain adjustment circuit 12 may specifically include: a first field effect transistor Q1 , a second field effect transistor Q2 , a third field effect transistor Q3 , and a fourth field effect transistor Q3 . The effect transistor Q4, the first capacitor C1 and the second capacitor C2.

The first end of the first capacitor C1 is connected to the switch circuit 15 and the source s of the first field effect transistor Q1 at the same time, and the second end of the first capacitor C1 is grounded. The drain d of the first field effect transistor Q1 is connected to the first end of the second capacitor C2, and the gate g of the first field effect transistor Q1 is used for receiving the first control signal sent by the microcontroller.

The first end of the second capacitor C2 is connected to the reset circuit 14, and the second end of the second capacitor C2 is grounded.

The source s of the second field effect transistor Q2 is connected to the output circuit 13, the drain d of the second field effect transistor Q2 is connected to the source s of the third field effect transistor Q3, and the gate g of the second field effect transistor Q2 is for receiving the second control signal sent by the microcontroller. The adjustment signal sent by the microcontroller may include a first control signal and a second control signal. The first control signal and the second control signal here are used to control the switching states of the first field effect transistor Q1 and the second field effect transistor Q2, so that the gain adjustment circuit 12 can adjust the gain of the imaging signal.

The gate g of the third field effect transistor Q3 is connected to the first end of the second capacitor C2, and the drain d of the third field effect transistor Q3 is connected to the power supply VDD.

The gate g of the fourth field effect transistor Q4 is connected to the first end of the first capacitor C1, the source s of the fourth field effect transistor Q4 is connected to the source s of the second field effect transistor Q2, and the fourth field effect transistor Q4 The drain d is connected to the power supply VDD.

Optionally, the photosensitive element 11 in the imaging unit may specifically include: a photodiode D. The switch circuit 15 specifically includes: a fifth field effect transistor Q5.

The source s of the fifth field effect transistor Q5 is connected to the cathode K of the photodiode D, the anode A of the photodiode D is grounded, the drain d of the fifth field effect transistor Q5 is connected to the first end of the first capacitor C1, the fifth The gate g of the field effect transistor Q5 receives the control signal sent by the microcontroller. The control signal here is used to control the switching state of the fifth field effect transistor Q5.

The reset circuit 14 specifically includes: a sixth field effect transistor Q6.

The source s of the sixth field effect transistor Q6 is connected to the first end of the second capacitor C2, the drain d of the sixth field effect transistor Q6 is connected to the power supply VDD, and the gate g of the sixth field effect transistor Q6 is used for receiving Reset signal sent by microcontroller.

The output circuit 13 specifically includes: a seventh field effect transistor Q7.

The source s of the seventh field effect transistor Q7 is connected to the source s of the fourth field effect transistor Q4, and the gate g of the seventh field effect transistor Q7 is used to receive the strobe signal sent by the microcontroller; the seventh field effect transistor The drain d of Q7 is used to output the imaging signal.

It should be noted that, for the first capacitor C1 and the second capacitor C2 in the gain adjustment circuit 12, an optional way can be understood as an actual capacitor element. At this time, the circuit principle corresponding to the imaging unit The graph may be as shown in Figure 5a.

Alternatively, the two capacitances may also be parasitic capacitances in the imaging unit. At this time, the circuit schematic diagram corresponding to the imaging unit may be as shown in FIG. 5b. Specifically, the first capacitor C1 may be the parasitic capacitance of the first field effect transistor Q1 , the fourth field effect transistor Q4 and the switch circuit 15 (ie, the fifth field effect transistor Q5 ). The second capacitor C2 may be the parasitic capacitance of the first field effect transistor Q1, the third field effect transistor Q3 and the reset circuit 14 (ie, the sixth field effect transistor Q6).

Based on the imaging unit with the above structure, the respective timing signal diagrams of each element in the imaging unit under three gain modes may be shown in FIGS. 6 a to 6 c .

According to the above embodiment, the gain adjustment circuit 12 has three gain modes, based on the imaging unit shown in FIG. 5a or 5b:

In one case, the illumination intensity of the imaging environment is weak. In this case, after the user selects the imaging mode of the photographing device, the gain adjustment circuit 12 can work in the first gain mode. In this mode, when the imaging unit is in the reset stage, the first field effect transistor Q1, the sixth field effect transistor Q6 are in a saturated working state, the second field effect transistor Q2, the third field effect transistor Q3, and the fourth field effect transistor Q4. and the seventh field effect transistor Q7 is in an off state. At the same time, the fifth field effect transistor Q5 is in a saturated working state first, and is in an off state after the residual charge in the photodiode D is emptied. Following the description in the embodiment shown in FIG. 6a, the fifth field effect transistor Q5 is turned on at the second time T2 and turned off at the third time T3.

When the imaging unit is in the exposure phase, the fifth field effect transistor Q5 continues to be in the off state, and the states of the remaining elements in the imaging unit are the same as those in the reset phase. The photodiode D receives photons during the exposure phase (ie, within the third time T3 to the fourth time T4 ) to generate and store charges generated by the photons.

When the imaging unit is in the signal readout stage, the seventh field effect transistor Q7 is in a saturated working state, and the first field effect transistor Q1 and the second field effect transistor Q2 are in an off state. When the imaging unit receives the enable signal of the reference signal, the first capacitor C1 is at the first high potential, and the seventh field effect transistor Q7 outputs the reference signal. At this time, the third field effect transistor Q3, the fourth field effect transistor Q4 and the sixth field effect transistor Q6 are all in a saturated working state.

Then, the fifth field effect transistor Q5 is first in a saturated working state (ie, a conducting state), so as to fill (eg, transfer) the charges (eg, negative charges or electronic charges) stored in the photodiode D into (eg, transfer to) the first capacitor C1 . After the charge transfer is completed, the first capacitor C1 is at the second high potential. Wherein, the first high potential is higher than the second high potential. At this time, the fifth field effect transistor Q5 is in an off state. When the imaging unit receives the enable signal of the sample and hold signal, the first capacitor C1 continues to maintain the second high potential, and the seventh field effect transistor Q7 outputs the sample and hold signal. Following the description in the embodiment shown in FIG. 6 a , the fifth field effect transistor Q5 is in a conducting state from the sixth time point T6 to the seventh time point T7 .

In the signal readout stage in this mode, the first field effect transistor Q1 and the second field effect transistor Q2 are in an off state, and the third field effect transistor Q3 and the fourth field effect transistor Q4 are in a saturated working state, which makes the entire The imaging unit has the smallest capacitance value, that is, the capacitance value of the first capacitor C1. Therefore, for the fixed amount of charges stored in the photodiode D, in the first gain mode, the adjusted imaging signal finally output by the imaging unit has the largest voltage value, that is, the first gain mode has the largest amplification factor for the imaging signal , So in the imaging environment with weak light intensity, improving the brightness of the image is to ensure the imaging quality.

In another case, the illumination intensity of the imaging environment is moderate, and in this case, the gain adjustment circuit 12 can work in the second gain mode. In this mode, when the imaging unit is in the reset stage, the first field effect transistor Q1, the second field effect transistor Q2 and the sixth field effect transistor Q6 are all in a saturated working state. The fifth field effect transistor Q5 is in a saturated working state first, and is in an off state after the residual charge in the photodiode D is cleared. Following the description in the embodiment shown in FIG. 6 b , the fifth field effect transistor Q5 is turned on at the second time T2 and turned off at the third time T3 . Meanwhile, at the third moment, the third field effect transistor Q3, the fourth field effect transistor Q4, and the seventh field effect transistor Q7 are turned off.

When the imaging unit is in the exposure stage, the photodiode D can also store charges, and in this stage, the first field effect transistor Q1, the second field effect transistor Q2 and the sixth field effect transistor Q6 continue to be in a saturated working state, and the remaining field effect transistors Tube is off.

When the imaging unit is in the signal readout stage, the seventh field effect transistor Q7 is in a saturated working state, and the sixth field effect transistor Q6 is turned off. Since the first field effect transistor Q1 and the second field effect transistor Q2 are in a saturated working state, the first capacitor C1 and the second capacitor C2 are at the third high potential, and the seventh field effect transistor Q7 outputs a reference signal. When the seventh field effect transistor Q7 outputs the reference signal, the third field effect transistor Q3 and the fourth field effect transistor Q4 are also in a saturated working state.

The fifth field effect transistor Q5 is first in a saturated working state (ie, a conducting state), and charges (eg, negative charges or electronic charges) stored in the photodiode D into (eg, transfers to) the first capacitor C1. After the charge transfer is completed, the first capacitor C1 and the second capacitor C2 are in the fourth high potential, and the fifth field effect transistor Q5 is in the off state. Wherein, the third high potential is higher than the fourth high potential. When the imaging unit receives the enable signal of the sample and hold signal, the first capacitor C1 and the second capacitor C2 continue to maintain the fourth high potential, and the seventh field effect transistor Q7 outputs the sample and hold signal. Following the description in the embodiment shown in FIG. 6 b , the fifth field effect transistor Q5 is in a conducting state from the sixth time point T6 to the seventh time point T7 .

In the signal readout stage in this mode, the first FET Q1 and the second FET Q2 are in a saturated working state, and the third FET Q3 and the fourth FET Q4 are also in a saturated working state. , the capacitance value of the entire imaging unit is the sum of the respective capacitance values of the first capacitor C1 and the second capacitor C2. Therefore, for the fixed amount of charges stored in the photodiode D, in the second gain mode, the gain adjustment circuit 12 amplifies the imaging signal moderately, which is smaller than that in the first gain mode.

It should be noted that, in the signal readout stage in this mode, the third field effect transistor Q3 and the fourth field effect transistor Q4 have the same potential, and the two can be equivalent to one field effect transistor, and the equivalent field effect The width of the tube is the sum of the respective widths of the third field effect transistor Q3 and the fourth field effect transistor Q4. The larger the width of the FET, the smaller the noise of the imaging signal, thereby ensuring the imaging quality.

In another case, when the illumination intensity of the imaging environment is strong, at this time, the gain adjustment circuit 12 can work in the third gain mode. In this mode, when the imaging unit is in the reset stage, the first field effect transistor Q1 and the sixth field effect transistor Q6 are in a saturated working state. The second field effect transistor Q2, the third field effect transistor Q3, the fourth field effect transistor Q4, and the seventh field effect transistor Q7 are turned off. At the same time, the fifth field effect transistor Q5 is in a saturated working state first, and is in an off state after the residual charge in the photodiode D is emptied. Following the description in the embodiment shown in FIG. 6c, the fifth field effect transistor Q5 is turned on at the second time T2 and turned off at the third time T3.

When the imaging unit is in the exposure stage, the photodiode D can also store charges, and the first field effect transistor Q1 and the sixth field effect transistor Q6 continue to be in a saturated working state, and the remaining field effect transistors are in an off state.

The imaging unit is in the signal readout stage, the seventh field effect transistor Q7 is in a saturated working state, and the sixth field effect transistor Q6 is in an off state. The first field effect transistor Q1 is in a saturated working state, the second field effect transistor Q2 is in an off state, the first capacitor C1 and the second capacitor C2 are at the fifth high potential, and the seventh field effect transistor Q7 outputs a reference signal. At the same time, the third field effect transistor Q3 is in a linear operating state (in the linear operating state, the third field effect transistor Q3 has a large capacitance value), and the fourth field effect transistor Q4 is in a saturated operating state. It should be noted that, in the linear working state, the state of the third field effect transistor Q3 is equivalent to a metal oxide semiconductor capacitor (MOS cap). The capacitance value of this capacitor is much larger than the capacitance value of the third field effect transistor Q3 in the source follower state.

The fifth field effect transistor Q5 is in a saturated working state (ie, conducting state) first, and charges (eg, negative charges or electronic charges) stored in the photodiode D into (eg, transfers to) the first capacitor C1 . After the charge transfer is completed, the first capacitor C1 and the second capacitor C2 are at the sixth high potential. Among them, the fifth high potential is higher than the sixth high potential. After the charge transfer is completed, the fifth field effect transistor Q5 is in an off state. When the imaging unit receives the enable signal of the sample and hold signal, the first capacitor C1 and the second capacitor C2 continue to maintain the sixth high potential, and the seventh field effect transistor Q7 outputs the sample and hold signal. Following the description in the embodiment shown in FIG. 6 c , the fifth field effect transistor Q5 is in a conducting state from the sixth time point T6 to the seventh time point T7 .

In the signal readout stage in this mode, the first field effect transistor Q1 and the fourth field effect transistor Q4 are in a saturated operating state, the second field effect transistor Q2 is in an off state, and the third field effect transistor Q3 is in a linear operating state. , which makes the entire imaging unit have the largest capacitance value, that is, the sum of the capacitance value of the first capacitor C1 , the capacitance value of the second capacitor C2 and the capacitance value corresponding to the third field effect transistor Q3 . Therefore, for the fixed amount of charges stored in the photodiode D, in the third gain mode, the gain adjustment circuit 12 has the smallest amplification factor for the imaging signal, which is smaller than that in the second gain mode.

The working states of each element in the imaging unit at different stages in the imaging process have been described in the above embodiments. In order to better illustrate the signal readout stage with the most complicated work, the specific working process of the signal readout stage is divided into several sub-stages in terms of timing. A detailed description will be given below.

The gain adjustment circuit 12 works in the first gain mode:

When the imaging unit is in the first sub-stage of the signal readout stage, the output circuit 13 is turned off from being turned off (the seventh field effect transistor Q7 is in a saturated working state), and the switch circuit 15 (the fifth field effect transistor Q5) is turned off. On, the first field effect transistor Q1 is turned from on to off, and the first capacitor C1 is at a first high potential. In this sub-phase, the imaging unit may receive the enable signal of the reference signal, and the output circuit 13 starts to output the reference signal in response to the enable signal.

When the imaging unit is in the second sub-stage of the signal readout stage, the switch circuit 13 is turned on, and the charge stored in the photosensitive element 11 is poured into the first capacitor C1 through the switch circuit 15, so that the first capacitor C1 is changed from the first high potential becomes the second highest potential. Wherein, the first high potential is higher than the second high potential.

When the imaging unit is in the third sub-phase of the signal readout phase, the switch circuit 15 is turned off. In this sub-stage, the first capacitor C1 maintains the second high potential, and the imaging unit can also receive the enable signal of the sample and hold signal. When the imaging unit receives the enable signal of the sample and hold signal, the first capacitor C1 is at the second high potential, and at this time, the output circuit 13 outputs the sample and hold signal in response to the enable signal of the sample and hold signal.

In this mode, the relationship between the enable signal of the reference signal, the reference signal, the enable signal of the sample and hold signal, and the sample and hold signal are described as follows:

Alternatively, the enable signal may be triggered by a rising edge, that is, when the enable signal of the reference signal is on a rising edge, the output circuit 13 starts to output the reference signal, and the reference signal may continue to be output within a preset time period. It can be understood with reference to FIG. 7a that the output of the reference signal may continue until the end of the first stage, or until the time when the enable signal of the sample and hold signal changes from a low level to a rising edge.

When the enable signal of the sample and hold signal is on the rising edge, the output circuit 13 starts to output the sample and hold signal, and completes the output of the sample and hold signal within a preset time period, and the output of the sample and hold signal can continue until the third step in FIG. 7a. Phase ends.

Alternatively, the enable signal may be triggered by a falling edge. At this time, the output circuit 13 outputs the reference signal when the enable signal of the reference signal is at the falling edge, and outputs the sample and hold signal when the enable signal of the sample and hold signal is at the falling edge. The output durations of the reference signal and the sample-and-hold signal can be the same as the above-mentioned alternatives.

In another optional manner, the enable signal may be triggered by a high level, that is, when the enable signal of the reference signal is at a high level, the output circuit 13 starts to output the reference signal, and completes the reference signal within a preset time period. output.

When the enable signal of the sample and hold signal is at a high level, the output circuit 13 starts to output the sample and hold signal, and completes the output of the sample and hold signal within a preset time period.

In another optional way, the enable signal can be triggered by a low level, and at this time, the output circuit 13 outputs the reference signal when the enable signal of the reference signal is at the falling edge; when the enable signal of the sample and hold signal is at the falling edge. The sample and hold signal is output at the edge. It should be noted that the signal timing diagram corresponding to the above-mentioned active-low mode is not shown.

The above-mentioned methods are essentially to trigger the reference signal and the sample-hold signal to start outputting according to different states of the enable signal, which can be used according to actual design requirements. However, the above-mentioned enable signal does not control the output end time of the reference signal and the sample and hold signal, and the output duration of the reference signal and the sample and hold signal can be preset.

In addition, in the first sub-stage, the second sub-stage and the third sub-stage, the reset circuit 14 is turned on (the sixth field effect transistor Q6 is in a saturated working state), and the second field effect transistor Q2 is turned off.

The above content can be understood in conjunction with FIG. 7a, which is the signal readout stage cut out from FIG. 6a.

The gain adjustment circuit 12 operates in the second gain mode:

The imaging unit is in the first sub-stage of the signal readout stage, the output circuit 13 is turned on (the seventh field effect transistor Q7 is in a saturated working state), the switch circuit 15 is turned off (the fifth field effect transistor Q5 is turned off), and the first capacitor C1 and the second capacitor C2 is at the third high potential.

The imaging unit is in the second sub-phase of the signal readout phase, the imaging unit can receive the enable signal of the reference signal, and the output circuit 13 outputs the reference signal in response to the enable signal.

The imaging unit is in the third sub-stage of the signal readout stage, the switch circuit 15 is turned on, and the charge stored in the photosensitive element 11 is poured into the first capacitor C1 and the second capacitor C2 through the switch circuit 15, so that the first capacitor C1 and the second capacitor C2 The capacitors C2 all change from the third high potential to the fourth high potential.

The imaging unit is in the fourth stage of the signal readout stage, and the switch circuit 15 is turned off. And in this sub-stage, the imaging unit may also receive the enable signal of the sample-and-hold signal. Both the first capacitor C1 and the second capacitor C2 maintain the fourth high potential. At this time, the output circuit 13 outputs the sample and hold signal in response to the enable signal of the aforesaid sample and hold signal.

In this mode, the relationship between the enable signal of the reference signal, the reference signal, the enable signal of the sample-and-hold signal, and the sample-and-hold signal can be explained as follows:

Alternatively, the enable signal may be triggered by a rising edge, that is, when the enable signal of the reference signal is on a rising edge, the output circuit 13 starts to output the reference signal, and the reference signal may continue to be output within a preset time period. It can be understood with reference to FIG. 7b that the output of the reference signal may continue until the end of the second stage, or until the time when the enable signal of the sample and hold signal changes from a low level to a rising edge.

When the enable signal of the sample and hold signal is on the rising edge, the output circuit 13 starts to output the sample and hold signal, and completes the output of the sample and hold signal within a preset time period, and the output of the sample and hold signal can continue until the fourth step in FIG. 7b. Phase ends.

In addition, in the first sub-stage, the second sub-stage, the third sub-stage and the fourth sub-stage, the first field effect transistor Q1 and the second field effect transistor Q2 are both turned on; in the first sub-stage, the reset circuit 14 (the sixth field effect transistor Q6 ) changes from on to off; when in the second sub-stage, the third sub-stage and the fourth sub-stage, the reset circuit 14 is turned off.

The above content can be understood in conjunction with FIG. 7b, which is the signal readout stage cut out from FIG. 6b.

The gain adjustment circuit 12 operates in the third gain mode:

The imaging unit is in the first sub-stage of the signal readout stage, the output circuit 13 is turned on (the seventh field effect transistor Q7 is in a saturated working state), the switch circuit 15 is turned off (the fifth field effect transistor Q5 is turned off), and the first field effect transistor is turned off. The transistor Q1 is turned on, and the first capacitor C1 and the second capacitor C2 are at the fifth high potential.

The imaging unit is in the second sub-stage of the signal readout stage, the imaging unit receives the enable signal of the reference signal, and the output circuit 13 outputs the reference signal in response to the enable signal.

The imaging unit is in the third sub-stage of the signal readout stage, the switch circuit 15 is turned on, the charges stored in the photosensitive element 11 are all poured into the first capacitor C1 through the switch circuit 15, and the first capacitor C1 and the second capacitor C2 are both stored by the first capacitor C1. The fifth high potential becomes the sixth high potential.

The imaging unit is in the fourth sub-phase of the signal readout phase, and the switch circuit 15 is turned off. And in this sub-stage, the imaging unit may also receive the enable signal of the sample-and-hold signal. Both the first capacitor C1 and the second capacitor C2 maintain the sixth high potential, so that the output circuit 13 outputs the sample and hold signal.

In this mode, the relationship between the enable signal of the reference signal, the reference signal, the enable signal of the sample-hold signal and the sample-and-hold signal has the same understanding as the above-mentioned second gain mode. For details, please refer to the above description. It is understood with reference to FIG. 7c, and details are not repeated here.

In addition, in the first sub-stage, the second sub-stage, the third sub-stage and the fourth sub-stage, the first field effect transistor Q1 is turned on, and the second field effect transistor Q2 is turned off; in the first sub-stage, the reset circuit 14 (ie, the sixth field effect transistor Q6 ) changes from on to off; and when in the second sub-stage, the third sub-stage and the fourth sub-stage, the reset circuit 14 is turned off.

The above content can be understood in conjunction with FIG. 7c, which is the signal readout stage cut out from FIG. 6c.

The above contents shown in FIGS. 7 a to 7 c can also be understood in conjunction with the relevant descriptions in the embodiments shown in FIGS. 1 to 6 c .

FIG. 8 is a schematic structural diagram of an imaging system according to an embodiment of the present invention. As shown in FIG. 8 , the imaging system includes an imaging unit 21 and a microcontroller 22 . The number of imaging units 21 is at least one. The microcontroller 22 is used for generating an adjustment signal according to the imaging environment.

The imaging unit 21 includes: a photosensitive element 31 , a gain adjustment circuit 32 , and an output circuit 33 .

Photosensitive element 31 for receiving photons to generate and store charges generated by the photons. The gain adjustment circuit 32 is electrically connected to the photosensitive element 31 and the microcontroller 22, and the gain adjustment circuit 32 is used for generating an imaging signal according to the electric charge.

The output circuit 33 is electrically connected to the gain adjustment circuit 32, and the output circuit 33 is used for outputting the imaging signal.

Wherein, the gain adjustment circuit 32 can adjust the gain of the imaging signal in response to the adjustment signal sent by the microcontroller 22 .

Optionally, the imaging unit 21 further includes a reset circuit 34

One end of the reset circuit 34 is connected to the gain adjustment circuit 32 , the other end of the reset circuit 34 is connected to a power supply, and the gain adjustment circuit 32 is connected to the microcontroller 22 .

Wherein, when the imaging unit 21 is in the reset stage, the reset circuit 34 responds to the reset signal sent by the microcontroller 22, and the reset circuit 23 is turned on.

When the imaging unit 21 is in the reset stage, the branch from the photosensitive element 31 to the reset circuit 34 is turned on, and the photosensitive element 31 is discharged through the reset circuit 34 .

Optionally, the imaging unit 21 further includes a switch circuit 35 .

One end of the switch circuit 35 is connected to the photosensitive element 31 , and the other end of the switch circuit 35 is connected to the gain adjustment circuit 32 .

The branch from the photosensitive element 31 to the reset circuit 34 includes the reset circuit 34 , the switch circuit 35 and the gain adjustment circuit 32 .

Optionally, the imaging unit 21 further includes a switch circuit 35 ; and one end of the switch circuit 35 is connected to the photosensitive element 31 .

Wherein, when the imaging unit 21 is in the exposure stage, the switch circuit 35 is turned off, and the photosensitive element 31 receives photons to generate and store the charges generated by the photons.

Optionally, when the imaging unit 21 is in the signal readout stage, the output circuit 33 responds to the strobe signal sent by the microcontroller 22 to turn on the output circuit 33 .

Optionally, when the imaging unit 21 is in the signal readout stage, the output circuit 22 sequentially outputs the reference signal and the sample-and-hold signal at different times according to the time sequence.

The imaging signal is the difference between the sample and hold signal and the reference signal, the sample and hold signal is generated based on the charge stored in the photosensitive element 31 , and the reference signal is based on the gain adjustment circuit 32 stored charge.

Optionally, the imaging unit 21 further includes a switch circuit 35 ; one end of the switch circuit 35 is connected to the photosensitive element 31 , and the other end of the switch circuit 35 is connected to the gain adjustment circuit 32 .

The gain adjustment circuit 32 includes: a first field effect transistor Q1, a second field effect transistor Q2, a third field effect transistor Q3, a fourth field effect transistor Q4, a first capacitor C1 and a second capacitor C2.

The first end of the first capacitor C1 is connected to the switch circuit 35 and the source s of the first field effect transistor Q1 at the same time, and the second end of the first capacitor C1 is grounded.

The drain d of the first field effect transistor Q1 is connected to the first end of the second capacitor C2, and the gate g of the first field effect transistor Q1 is used to receive the first signal sent by the microcontroller 22. Control signal; the first end of the second capacitor C2 is connected to the reset circuit 34, and the second end of the second capacitor C2 is grounded.

The source s of the second field effect transistor Q2 is connected to the output circuit 31, the drain d of the second field effect transistor Q2 is connected to the source s of the third field effect transistor Q3, and the The gate g of the second field effect transistor Q2 is used for receiving the second control signal sent by the microcontroller 22 .

The gate s of the third field effect transistor Q3 is connected to the first end of the second capacitor C2, and the drain d of the third field effect transistor Q3 is connected to the power supply VDD.

The gate g of the fourth field effect transistor Q4 is connected to the first end of the first capacitor C1, and the source s of the fourth field effect transistor Q4 and the source s of the second field effect transistor Q2 connected, the drain d of the fourth field effect transistor Q4 is connected to the power supply VDD.

Optionally, the gain mode of the gain adjustment circuit 32 corresponds to an adjustment signal sent by the microcontroller 22, the microcontroller 22 generates the adjustment signal according to the imaging environment, and the adjustment signal includes the a first control signal and the second control signal.

Optionally, if the gain adjustment circuit 32 works in the first gain mode,

Then when the imaging unit 21 is in the first sub-stage of the signal readout stage, the output circuit 31 is turned on, the switch circuit 35 is turned off, the first field effect transistor Q1 is turned off, and the first capacitor C1 is at the first high level, so that the output circuit 33 outputs the reference signal.

When the imaging unit 21 is in the second sub-stage of the signal readout stage, the switch circuit 35 is turned on, and the charges stored in the photosensitive element 31 are poured into the first capacitor C1 through the switch circuit 35 , So that the first capacitor C1 changes from the first potential to the second high potential.

When the imaging unit 21 is in the third sub-phase of the signal readout phase, the switch circuit 35 is turned off. In this sub-phase, the imaging unit may also receive an enable signal for the sample-and-hold signal. When the imaging unit receives the enable signal of the sample and hold signal, the first capacitor C1 is at the second high potential, so that the output circuit 33 outputs the sample and hold signal.

Wherein, in the first sub-stage, the second sub-stage and the third sub-stage, the reset circuit 34 is turned on, and the second field effect transistor Q2 is turned off.

Optionally, if the gain adjustment circuit 32 works in the second gain mode,

Then the imaging unit 21 is in the first sub-phase of the signal readout phase, the output circuit 33 is turned on, the switch circuit 35 is turned off, and the first capacitor C1 and the second capacitor C2 are at the third high potential.

The imaging unit 21 is in the second sub-phase of the signal readout phase, and the output circuit 33 outputs a reference signal.

The imaging unit 21 is in the third sub-stage of the signal readout stage, the switch circuit 35 is turned on, and the charge 31 stored in the photosensitive element is poured into the first capacitor C1 and the first capacitor C1 through the switch circuit 35 . The second capacitor C2, the first capacitor C1 and the second capacitor C2 all change from the third high potential to the fourth high potential.

The imaging unit 21 is in the fourth stage of the signal readout stage, and the switch circuit 35 is turned off. And in this sub-stage, the imaging unit may also receive the enable signal of the sample-and-hold signal. Both the first capacitor C1 and the second capacitor C2 maintain the fourth high potential, so that the output circuit 33 outputs a sample and hold signal.

Wherein, in the first sub-stage, the second sub-stage, the third sub-stage and the fourth sub-stage, the first field effect transistor Q1 and the second field effect transistor Q2 are both turn on; when in the first sub-stage, the reset circuit 34 is turned off from on; in the second sub-stage, the third sub-stage and the fourth sub-stage, the The reset circuit 34 is turned off.

Optionally, if the gain adjustment circuit 32 works in the third gain mode,

Then the imaging unit 21 is in the first sub-stage of the signal readout stage, the output circuit 33 is turned on, the switch circuit 35 is turned off, the first field effect transistor Q1 is turned on, and the first capacitor C1 at the fifth highest potential.

The imaging unit 21 is in the third sub-stage of the signal readout stage, the switch circuit 35 is turned on, the charge stored in the photosensitive element 31 is poured into the first capacitor C1 through the switch circuit, and the Both the first capacitor C1 and the second capacitor C2 change from the fifth high potential to the sixth high potential.

The imaging unit 21 is in the fourth sub-phase of the signal readout phase, and the switch circuit 35 is turned off. And in this sub-stage, the imaging unit may also receive the enable signal of the sample-and-hold signal. Both the first capacitor C1 and the second capacitor C2 maintain the sixth high potential, so that the output circuit 33 outputs a sample and hold signal.

Wherein, in the first sub-stage, the second sub-stage, the third sub-stage and the fourth sub-stage, the first field effect transistor Q1 is turned on and the second field effect transistor Q2 is turned off; in the first sub-stage, the reset circuit 34 is turned off from on; and in the second sub-stage, the third sub-stage and the fourth sub-stage, all The reset circuit 34 is turned off.

Optionally, the first capacitor C1 is the parasitic capacitance of the first field effect transistor Q1 , the fourth field effect transistor Q4 and the switch circuit 35 .

Optionally, the second capacitor C2 is the parasitic capacitance of the first field effect transistor Q1 , the third field effect transistor Q3 and the reset circuit 34 .

Optionally, the photosensitive element 31 includes: a photodiode D, and the switch circuit 35 includes: a fifth field effect transistor Q5.

The source s of the fifth field effect transistor Q5 is connected to the cathode K of the photodiode D, the anode A of the photodiode D is grounded, and the drain d of the fifth field effect transistor Q5 is connected to the first The first end of the capacitor C1 is connected, and the gate g of the fifth field effect transistor Q5 receives the control signal sent by the microcontroller 22 .

Optionally, the reset circuit 34 includes: a sixth field effect transistor Q6.

The source s of the sixth field effect transistor Q6 is connected to the first end of the second capacitor C2, the drain d of the sixth field effect transistor Q6 is connected to the power supply VDD, and the sixth field effect transistor Q6 is connected to the power supply VDD. The gate g of the effect transistor Q6 is used for receiving the reset signal sent by the microcontroller 22 .

Optionally, the output circuit 33 includes: a seventh field effect transistor Q7.

The source s of the seventh field effect transistor Q7 is connected to the source s of the fourth field effect transistor Q4, and the gate g of the seventh field effect transistor Q7 is used to receive the data sent by the microcontroller 22. gate signal; the drain d of the seventh field effect transistor Q7 is used to output the imaging signal.

For the specific working process and composition of the drive system in the movable platform shown in FIG. 8, reference may be made to the embodiments shown in FIG. 1 to FIG. 7c. The parts not described in detail in this embodiment are:

Reference may be made to the related descriptions of the embodiments shown in FIG. 1 to FIG. 7c. For the execution process and technical effects of the technical solution, refer to the descriptions in the embodiments shown in FIG. 1 to FIG. 7 c , which will not be repeated here.

FIG. 9 is a schematic structural diagram of a movable platform according to an embodiment of the present invention. Referring to FIG. 9, an embodiment of the present invention provides a movable platform, and the movable platform is at least one of the following: an unmanned aerial vehicle, an unmanned ship, an unmanned vehicle, a movable intelligent robot, etc.; Specifically, the movable platform includes: a body 41 , a power system 42 , an imaging system 43 and a control system 44 .

The power system 42 is arranged on the body 41 to provide power for the movable platform.

The imaging system 43 is arranged on the body 41 and is used for photographing during the movement of the movable platform.

The imaging system 43 includes: at least one imaging unit as shown in FIG. 1 to FIG. 7c.

The control system 44 includes a processor and memory for controlling the imaging system 43 .

For the specific working process and composition of the imaging system in the movable platform shown in FIG. 9, reference may be made to the embodiments shown in FIG. 1 to FIG. 7c. The parts not described in detail in this embodiment are:

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. Scope.

Claims

An imaging unit, characterized in that the imaging unit comprises:

a photosensitive element for receiving photons to generate and store charges generated by said photons;

a gain adjustment circuit electrically connected to the photosensitive element and the microcontroller, and the gain adjustment circuit is configured to generate an imaging signal according to the electric charge; and

an output circuit, electrically connected to the gain adjustment circuit, and used for outputting the imaging signal;

Wherein, the gain adjustment circuit can adjust the gain of the imaging signal in response to the adjustment signal sent by the microcontroller.
The imaging unit according to claim 1, wherein the imaging unit further comprises a reset circuit;

One end of the reset circuit is connected to the gain adjustment circuit, the other end of the reset circuit is connected to a power supply, and the gain adjustment circuit is connected to the microcontroller;

Wherein, when the imaging unit is in the reset stage, the reset circuit is turned on in response to a reset signal sent by the microcontroller; and

When the imaging unit is in the reset stage, the branch from the photosensitive element to the reset circuit is turned on, and the photosensitive element is discharged through the reset circuit.
The imaging unit according to claim 2, wherein the imaging unit further comprises a switch circuit;

One end of the switch circuit is connected to the photosensitive element, and the other end of the switch circuit is connected to the gain adjustment circuit;

Wherein, the branch from the photosensitive element to the reset circuit includes the reset circuit, the switch circuit and the gain adjustment circuit.
The imaging unit according to claim 1, wherein the imaging unit further comprises a switch circuit; and one end of the switch circuit is connected to the photosensitive element;

Wherein, when the imaging unit is in the exposure stage, the switch circuit is turned off, and the photosensitive element receives photons to generate and store charges generated by the photons.
The imaging unit according to claim 1, wherein when the imaging unit is in a signal readout stage, the output circuit responds to a strobe signal sent by the microcontroller, so that the output circuit is turned on .
The imaging unit according to claim 1, wherein when the imaging unit is in the signal readout stage, the output circuit sequentially outputs the reference signal and the sample-hold signal at different times according to the time sequence;

The imaging signal is the difference between the sample-and-hold signal and the reference signal, the sample-and-hold signal is generated based on the charges stored in the photosensitive element, and the reference signal is based on the stored charge in the gain adjustment circuit generated by the charge.
The imaging unit according to claim 1, wherein the imaging unit further comprises: a reset circuit;

One end of the reset circuit is connected to the gain adjustment circuit, and the other end of the reset circuit is connected to the power supply;

Wherein, in response to the reset signal sent by the microcontroller at the first moment, the reset circuit is turned on, so that the imaging unit is in the reset stage.
The imaging unit according to claim 7, wherein the imaging unit further comprises: a switch circuit;

One end of the switch circuit is connected to the photosensitive element, and the other end of the switch circuit is connected to the gain adjustment circuit;

Wherein, when the imaging unit is in the reset stage, in response to the enable signal sent by the microcontroller at the second moment, the switch circuit is turned on; the photosensitive element passes through the switch circuit and the reset circuit. is discharged by being turned on; and

When the imaging unit is in the reset stage, in response to the disable signal sent by the microcontroller at the third moment, the switch circuit is disconnected, and the photosensitive element is discharged;

Wherein, the first moment is prior to the second moment, and the second moment is prior to the third moment.
9. The imaging unit according to claim 8, wherein from the third time to the fourth time, the photosensitive element receives photons in the imaging environment to generate and store charges generated by the photons, the The third time instant precedes the fourth time instant, and the imaging unit is in the exposure phase.
The imaging unit according to claim 9, wherein the gain adjustment circuit is turned on in response to an adjustment signal sent by the microcontroller at the fourth moment, and the imaging unit is in Signal readout stage;

The adjustment signal is determined according to the amount of charge stored in the photosensitive element and the imaging mode corresponding to the imaging environment in which the imaging unit is located, so that the gain adjustment circuit corresponds to adjustment signals of different gain modes.
The imaging unit of claim 10, wherein the imaging unit is in a signal readout stage;

The output circuit outputs the reference signal in response to the enable signal of the reference signal received by the imaging unit at a fifth time;

In response to the enable signal sent by the microcontroller at the sixth moment, the switch circuit is turned on, so that the charge stored in the photosensitive element is transmitted to the gain adjustment circuit through the switch circuit, and the fourth moment prior to said sixth moment;

In response to the disable signal sent by the microcontroller at the seventh moment, the switch circuit is turned off, and the sixth moment is prior to the seventh moment;

In response to the enable signal of the sample and hold signal received by the imaging unit at the eighth moment, the output circuit outputs the sample and hold signal;

The imaging signal is the difference between the sample-and-hold signal and the reference signal.
The imaging unit according to claim 1, characterized in that, the imaging unit further comprises: a conversion circuit connected to the output circuit for performing analog-to-digital conversion on the imaging signal.
The imaging unit according to claim 1, wherein the imaging unit further comprises a switch circuit; one end of the switch circuit is connected to the photosensitive element, and the other end of the switch circuit is connected to the gain adjustment circuit ;

The gain adjustment circuit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first capacitor and a second capacitor;

Wherein, the first end of the first capacitor is connected to the switch circuit and the source of the first field effect transistor at the same time, and the second end of the first capacitor is grounded;

The drain of the first field effect transistor is connected to the first end of the second capacitor, and the gate of the first field effect transistor is used to receive the first control signal sent by the microcontroller; The first end of the second capacitor is connected to the reset circuit, and the second end of the second capacitor is grounded;

The source electrode of the second field effect transistor is connected to the output circuit, the drain electrode of the second field effect transistor is connected to the source electrode of the third field effect transistor, and the gate electrode of the second field effect transistor is connected for receiving the second control signal sent by the microcontroller;

The gate of the third field effect transistor is connected to the first end of the second capacitor, and the drain of the third field effect transistor is connected to the power supply;

The gate of the fourth field effect transistor is connected to the first end of the first capacitor, the source of the fourth field effect transistor is connected to the source of the second field effect transistor, and the fourth field effect transistor is connected to the source of the second field effect transistor. The drain of the effect transistor is connected to the power supply.
The imaging unit according to claim 13, wherein the gain mode of the gain adjustment circuit corresponds to an adjustment signal sent by the microcontroller, and the adjustment signal includes the first control signal and the second control signal. control signal.
The imaging unit according to claim 14, wherein, if the gain adjustment circuit works in the first gain mode,

Then when the imaging unit is in the first sub-stage of the signal readout stage, the output circuit is turned on, the switch circuit is turned off, the first field effect transistor is turned off, and the first capacitor is at the first high level. potential, so that the output circuit outputs a reference signal;

When the imaging unit is in the second sub-stage of the signal readout stage, the switch circuit is turned on, and the charges stored in the photosensitive element are poured into the first capacitor through the switch circuit, so that the first capacitor is A capacitor changes from the first high potential to the second high potential;

When the imaging unit is in the third sub-phase of the signal readout phase, the switch circuit is turned off, and the first capacitor maintains the second high potential, so that the output circuit outputs a sample-and-hold signal; and

Wherein, in the first sub-stage, the second sub-stage and the third sub-stage, the reset circuit is turned on, and the second field effect transistor is turned off.
The imaging unit according to claim 14, wherein if the gain adjustment circuit operates in the second gain mode,

then the imaging unit is in the first sub-stage of the signal readout stage, the output circuit is turned on, the switch circuit is turned off, and the first capacitor and the second capacitor are at a third high potential;

the imaging unit is in the second sub-phase of the signal readout phase, and the output circuit outputs a reference signal;

The imaging unit is in the third sub-stage of the signal readout stage, the switch circuit is turned on, and the charges stored in the photosensitive element are poured into the first capacitor and the second capacitor through the switch circuit, so Both the first capacitor and the second capacitor are changed from the third high potential to the fourth high potential;

The imaging unit is in the fourth stage of the signal readout stage, the switch circuit is turned off, and both the first capacitor and the second capacitor maintain the fourth high potential, so that the output circuit outputs a sample hold signal; and

Wherein, in the first sub-stage, the second sub-stage, the third sub-stage and the fourth sub-stage, the first field effect transistor and the second field effect transistor are both turned on ; When in the first sub-stage, the reset circuit is turned off from being turned on; in the second sub-stage, the third sub-stage and the fourth sub-stage, the reset circuit is turned off open.
The imaging unit according to claim 14, wherein, if the gain adjustment circuit works in the third gain mode,

Then the imaging unit is in the first sub-stage of the signal readout stage, the output circuit is turned on, the switch circuit is turned off, the first field effect transistor is turned on, the first capacitor and the second The capacitor is at the fifth highest potential;

the imaging unit is in the second sub-phase of the signal readout phase, and the output circuit outputs a reference signal;

The imaging unit is in the third sub-stage of the signal readout stage, the switch circuit is turned on, the charges stored in the photosensitive element are all poured into the first capacitor through the switch circuit, and the first capacitor and The second capacitors are changed from the fifth high potential to the sixth high potential;

The imaging unit is in the fourth sub-phase of the signal readout phase, the switch circuit is turned off, and both the first capacitor and the second capacitor maintain the sixth high potential, so that the output circuit outputs the sample hold the signal; and

Wherein, in the first sub-stage, the second sub-stage, the third sub-stage and the fourth sub-stage, the first field effect transistor is turned on and the second field effect transistor is turned off ; When in the first sub-phase, the reset circuit changes from on to off; and when in the second sub-phase, the third sub-phase and the fourth sub-phase, the reset circuit disconnect.
The imaging unit according to claim 13, wherein the first capacitor is a parasitic capacitor of the first field effect transistor, the fourth field effect transistor and the switching circuit.
The imaging unit according to claim 13, wherein the second capacitance is a parasitic capacitance of the first field effect transistor, the third field effect transistor and the reset circuit.
The imaging unit according to claim 13, wherein the photosensitive element comprises: a photodiode, and the switch circuit comprises: a fifth field effect transistor;

The source of the fifth field effect transistor is connected to the cathode of the photodiode, the anode of the photodiode is grounded, and the drain of the fifth field effect transistor is connected to the first end of the first capacitor, so The gate of the fifth field effect transistor receives the control signal sent by the microcontroller.
The imaging unit according to claim 13, wherein the reset circuit comprises: a sixth field effect transistor;

The source of the sixth field effect transistor is connected to the first end of the second capacitor, the drain of the sixth field effect transistor is connected to the power supply, and the gate of the sixth field effect transistor is for receiving the reset signal sent by the microcontroller.
The imaging unit according to claim 13, wherein the output circuit comprises: a seventh field effect transistor;

The source electrode of the seventh field effect transistor is connected to the source electrode of the fourth field effect transistor, and the gate electrode of the seventh field effect transistor is used to receive the gating signal sent by the microcontroller; The drains of the seven field effect transistors are used to output the imaging signal.
The imaging unit according to claim 22, wherein the gain adjustment circuit operates in a first gain mode;

The imaging unit is in the signal readout stage, the first field effect transistor and the second field effect transistor are turned off, the third field effect transistor, the fourth field effect transistor and the sixth field effect transistor , the seventh field effect transistor is in a saturated working state.
The imaging unit according to claim 22, wherein the gain adjustment circuit operates in the second gain mode;

The imaging unit is in the signal readout stage, and the first field effect transistor, the second field effect transistor, the third field effect transistor, the fourth field effect transistor and the seventh field effect transistor are all in saturation operation state; the sixth field effect transistor is turned off.
The imaging unit according to claim 22, wherein the gain adjustment circuit operates in a third gain mode;

The imaging unit is in a signal readout stage, the first field effect transistor, the fourth field effect transistor and the seventh field effect transistor are in a saturated working state, and the second field effect transistor and the sixth field effect transistor are in a saturated working state. The field effect transistor is disconnected, and the third field effect transistor is in a linear working state.
The imaging unit according to any one of claims 23 to 25, wherein the gain adjustment circuit operates in a first gain mode or a third gain mode;

The imaging unit is in the reset stage, the first field effect transistor and the sixth field effect transistor are in a saturated working state, the second field effect transistor, the third field effect transistor, and the fourth field effect transistor tube, the seventh field effect tube is turned off.
The imaging unit according to any one of claims 23 to 25, wherein the gain adjustment circuit operates in the second gain mode;

The imaging unit is in the reset stage, the first field effect transistor, the second field effect transistor, and the sixth field effect transistor are in a saturated working state, and the third field effect transistor and the fourth field effect transistor are in a saturated working state. tube, the seventh field effect tube is turned off.
The imaging unit according to any one of claims 15 to 17 or 23 to 25, wherein the respective gains corresponding to the first gain mode, the second gain mode and the third gain mode are sequentially decreased small.
An imaging system, characterized in that the system comprises:

a microcontroller for generating an adjustment signal according to the imaging environment;

Imaging unit, including:

a photosensitive element for receiving photons to generate and store charges generated by said photons;

a gain adjustment circuit electrically connected to the photosensitive element and the microcontroller, and the gain adjustment circuit is configured to generate an imaging signal according to the electric charge; and

an output circuit, electrically connected to the gain adjustment circuit, and used for outputting the imaging signal;

Wherein, the gain adjustment circuit can adjust the gain of the imaging signal in response to the adjustment signal sent by the microcontroller.
The imaging system of claim 29, wherein the imaging unit further comprises a reset circuit;

One end of the reset circuit is connected to the gain adjustment circuit, the other end of the reset circuit is connected to a power supply, and the gain adjustment circuit is connected to the microcontroller;

Wherein, when the imaging unit is in the reset stage, the reset circuit is turned on in response to a reset signal sent by the microcontroller; and

When the imaging unit is in the reset stage, the branch from the photosensitive element to the reset circuit is turned on, and the photosensitive element is discharged through the reset circuit.
The imaging system of claim 30, wherein the imaging unit further comprises a switch circuit;

One end of the switch circuit is connected to the photosensitive element, and the other end of the switch circuit is connected to the gain adjustment circuit;

Wherein, the branch from the photosensitive element to the reset circuit includes the reset circuit, the switch circuit and the gain adjustment circuit.
The imaging system according to claim 29, wherein the imaging unit further comprises a switch circuit; and one end of the switch circuit is connected to the photosensitive element;

Wherein, when the imaging unit is in the exposure stage, the switch circuit is turned off, and the photosensitive element receives photons to generate and store charges generated by the photons.
The imaging system according to claim 29, wherein when the imaging unit is in the signal readout stage, the output circuit responds to a strobe signal sent by the microcontroller, so that the output circuit is turned on .
The imaging system according to claim 29, wherein when the imaging unit is in the signal readout stage, the output circuit sequentially outputs the reference signal and the sample-and-hold signal at different times according to time series;

The imaging signal is the difference between the sample-and-hold signal and the reference signal, the sample-and-hold signal is generated based on the charges stored in the photosensitive element, and the reference signal is based on the stored charge in the gain adjustment circuit generated by the charge.
The imaging system according to claim 29, wherein the imaging unit further comprises a switch circuit; one end of the switch circuit is connected to the photosensitive element, and the other end of the switch circuit is connected to the gain adjustment circuit ;

The gain adjustment circuit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first capacitor and a second capacitor;

Wherein, the first end of the first capacitor is connected to the switch circuit and the source of the first field effect transistor at the same time, and the second end of the first capacitor is grounded;

The drain of the first field effect transistor is connected to the first end of the second capacitor, and the gate of the first field effect transistor is used to receive the first control signal sent by the microcontroller; The first end of the second capacitor is connected to the reset circuit, and the second end of the second capacitor is grounded;

The source electrode of the second field effect transistor is connected to the output circuit, the drain electrode of the second field effect transistor is connected to the source electrode of the third field effect transistor, and the gate electrode of the second field effect transistor is connected for receiving the second control signal sent by the microcontroller;

The gate of the third field effect transistor is connected to the first end of the second capacitor, and the drain of the third field effect transistor is connected to the power supply.

The gate of the fourth field effect transistor is connected to the first end of the first capacitor, the source of the fourth field effect transistor is connected to the source of the second field effect transistor, and the fourth field effect transistor is connected to the source of the second field effect transistor. The drain of the effect transistor is connected to the power supply.
The imaging system of claim 35, wherein the gain mode of the gain adjustment circuit corresponds to an adjustment signal sent by the microcontroller, the adjustment signal comprising the first control signal and the second control signal control signal.
The imaging system according to claim 36, wherein, if the gain adjustment circuit operates in the first gain mode,

Then when the imaging unit is in the first sub-stage of the signal readout stage, the output circuit is turned on, the switch circuit is turned off, the first field effect transistor is turned off, and the first capacitor is at the first high level. potential, so that the output circuit outputs a reference signal;

When the imaging unit is in the second sub-stage of the signal readout stage, the switch circuit is turned on, and the charges stored in the photosensitive element are poured into the first capacitor through the switch circuit, so that the first capacitor is A capacitor changes from the first high potential to the second high potential;

When the imaging unit is in the third sub-phase of the signal readout phase, the switch circuit is turned off, and the first capacitor maintains the second high potential, so that the output circuit outputs a sample-and-hold signal; and

Wherein, in the first sub-stage, the second sub-stage and the third sub-stage, the reset circuit is turned on, and the second field effect transistor is turned off.
The imaging system according to claim 36, wherein if the gain adjustment circuit operates in the second gain mode,

then the imaging unit is in the first sub-stage of the signal readout stage, the output circuit is turned on, the switch circuit is turned off, and the first capacitor and the second capacitor are at a third high potential;

the imaging unit is in a second sub-phase of the signal readout phase, the output circuit outputs a reference signal;

The imaging unit is in the third sub-stage of the signal readout stage, the switch circuit is turned on, and the charges stored in the photosensitive element are poured into the first capacitor and the second capacitor through the switch circuit, so Both the first capacitor and the second capacitor are changed from the third high potential to the fourth high potential;

The imaging unit is in the fourth stage of the signal readout stage, the switch circuit is turned off, and both the first capacitor and the second capacitor maintain the fourth high potential, so that the output circuit outputs a sample hold signal; and

Wherein, in the first sub-stage, the second sub-stage, the third sub-stage and the fourth sub-stage, the first field effect transistor and the second field effect transistor are both turned on ; When in the first sub-stage, the reset circuit is turned off from being turned on; in the second sub-stage, the third sub-stage and the fourth sub-stage, the reset circuit is turned off open.
The imaging system according to claim 36, wherein if the gain adjustment circuit operates in the third gain mode,

Then the imaging unit is in the first sub-stage of the signal readout stage, the output circuit is turned on, the switch circuit is turned off, the first field effect transistor is turned on, the first capacitor and the second The capacitor is at the fifth highest potential;

the imaging unit is in the second sub-phase of the signal readout phase, and the output circuit outputs a reference signal;

The imaging unit is in the third sub-stage of the signal readout stage, the switch circuit is turned on, the charges stored in the photosensitive element are all poured into the first capacitor through the switch circuit, and the first capacitor and The second capacitors are changed from the fifth high potential to the sixth high potential;

The imaging unit is in the fourth sub-phase of the signal readout phase, the switch circuit is turned off, and both the first capacitor and the second capacitor maintain the sixth high potential, so that the output circuit outputs the sample hold the signal; and

Wherein, in the first sub-stage, the second sub-stage, the third sub-stage and the fourth sub-stage, the first field effect transistor is turned on and the second field effect transistor is turned off ; When in the first sub-phase, the reset circuit changes from on to off; and when in the second sub-phase, the third sub-phase and the fourth sub-phase, the reset circuit disconnect.
The imaging system according to claim 35, wherein the first capacitance is a parasitic capacitance of the first field effect transistor, the fourth field effect transistor and the switching circuit.
The imaging system according to claim 35, wherein the second capacitance is a parasitic capacitance of the first field effect transistor, the third field effect transistor and the reset circuit.
The imaging system according to claim 35, wherein the photosensitive element comprises: a photodiode, and the switch circuit comprises: a fifth field effect transistor;

The source of the fifth field effect transistor is connected to the cathode of the photodiode, the anode of the photodiode is grounded, and the drain of the fifth field effect transistor is connected to the first end of the first capacitor, so The gate of the fifth field effect transistor receives the control signal sent by the microcontroller.
The imaging system according to claim 35, wherein the reset circuit comprises: a sixth field effect transistor;

The source of the sixth field effect transistor is connected to the first end of the second capacitor, the drain of the sixth field effect transistor is connected to the power supply, and the gate of the sixth field effect transistor is for receiving the reset signal sent by the microcontroller.
The imaging system according to claim 35, wherein the output circuit comprises: a seventh field effect transistor;

The source of the seventh field effect transistor is connected to the source of the fourth field effect transistor, and the gate of the seventh field effect transistor is used to receive the gating signal sent by the microcontroller; The drains of the seven field effect transistors are used to output the imaging signal.
A movable platform, characterized in that it at least includes: a body, a power system, an imaging system and a control system;

the power system, arranged on the body, is used to provide power for the movable platform;

the imaging system, arranged on the body, is used for shooting during the movement of the movable platform;

The imaging system comprises: at least one imaging unit as claimed in any one of claims 1 to 28;

the control system for controlling the imaging system.