WO2016147238A1

WO2016147238A1 - Ad converter, image sensor, and image pickup device

Info

Publication number: WO2016147238A1
Application number: PCT/JP2015/006092
Authority: WO
Inventors: 徳永　祐介
Original assignee: パナソニックＩｐマネジメント株式会社
Priority date: 2015-03-19
Filing date: 2015-12-08
Publication date: 2016-09-22
Also published as: JP2018078350A

Abstract

An AD converter (20A) is provided with: a first amplifying circuit (21) to which an analog signal Vin is inputted; a second amplifying circuit (22) to which a reference signal Vref is inputted; a switched capacitor circuit (23) that has a first switch (231) to which an output signal of the first amplifying circuit (21) is connected, a second switch (232) to which an output signal of the second amplifying circuit (22) is connected, and a capacitor (233); a precharge circuit (24) connected between a reference voltage GND and an interconnection point of the first switch (231), the second switch (232), and the capacitor (233); and an AD conversion circuit (25) connected to the capacitor (233).

Description

AD converter, image sensor, and imaging apparatus

The present disclosure relates to an AD converter, and more particularly to an AD converter mounted on an image sensor.

In recent years, analog-digital conversion circuits (hereinafter referred to as AD converters or ADCs) of various circuit formats have been proposed in the field of image sensors. In particular, Non-Patent Document 1 discloses that a highly accurate and low power consumption image sensor can be realized by using a ΔΣ AD converter for an image sensor.

The AD converter according to the present disclosure includes a first amplifier circuit to which an analog signal is input, a second amplifier circuit to which a reference signal is input, and a first switch to which an output signal of the first amplifier circuit is connected. A switched capacitor circuit having a capacitor and a second switch to which the output signal of the second amplifier circuit is connected, and between the interconnection point of the first switch, the second switch, and the capacitor and the reference voltage A precharge circuit connected to the capacitor; and an AD converter circuit connected to the capacitor.

This configuration provides an AD converter that can suppress the occurrence of streaking.

FIG. 1 is a schematic diagram illustrating an example of the appearance of an image sensor. FIG. 2 is a block diagram showing a functional configuration of the image sensor of FIG. FIG. 3 is a schematic diagram illustrating a reference voltage between the pixel unit and the ADC. FIG. 4A is a schematic diagram for explaining input voltage dependency of current consumption in an ADC. FIG. 4B is a schematic diagram for explaining the potential of GND2. FIG. 4C is a schematic diagram for explaining the relationship between the lightness of light and the digital value output from the ADC. FIG. 5 is a schematic diagram showing the configuration of the column ADC. FIG. 6A is a schematic diagram showing an image in which white strip-like streaking has occurred. FIG. 6B is a schematic diagram illustrating an image in which black strip-like streaking has occurred. FIG. 7 is a circuit diagram of a switched capacitor integrator. FIG. 8 is a block diagram illustrating a schematic configuration of the AD converter according to the first embodiment. FIG. 9 is a circuit diagram illustrating an example of an amplifier circuit in the AD converter according to the first embodiment. FIG. 10 is a circuit diagram showing another example of the amplifier circuit in the AD converter according to the first embodiment. FIG. 11 is a time chart for explaining the operation of the AD converter according to the first embodiment. FIG. 12 is a block diagram illustrating a schematic configuration of the AD converter according to the second embodiment. FIG. 13 is a time chart for explaining the operation of the AD converter according to the second embodiment. FIG. 14 is an external view of a digital camera according to the third embodiment.

(Knowledge that became the basis of the present invention)
Depending on the performance of the image sensor, a phenomenon called streaking may occur in an image taken using the image sensor. Streaking is a phenomenon in which, for example, when a bright point light source or the like is photographed in the dark, white straight lines rise to the left and right of the point light source on the photographed image. In addition, streaking is, for example, when a strong light source such as the sun is photographed during the day, and on the photographed image, areas with band-like color changes appear on the left and right of the sun, or the areas on the left and right of the sun are black. It is a phenomenon that sinks.

First, the configuration and operation of the image sensor will be described with specific examples.

FIG. 1 is a schematic diagram showing an example of the appearance of an image sensor.

FIG. 2 is a block diagram showing a functional configuration of the image sensor of FIG.

1 and 2 includes a pixel unit (pixel array) 102, a row selector 103, a column ADC 104, and a parallel / serial conversion unit 105. In FIG. 1, it is assumed that the parallel / serial conversion unit 105 is provided in the peripheral circuit 106.

Hereinafter, the operation of the image sensor shown in FIGS. 1 and 2 will be described in a simplified manner.

First, light is input to a plurality of photoelectric conversion elements (for example, photodiodes) arranged in a matrix in the pixel portion 102, and a corresponding voltage is output to the row selector 103.

Next, the row selector 103 outputs an output voltage corresponding to one pixel row of the pixel unit 102 to the column ADC 104. The column ADC 104 is composed of a plurality of ADCs, converts the output voltage from analog to digital, and outputs digital data. The output digital data is converted by the parallel / serial conversion unit 105 and output to the outside of the image sensor 101.

FIG. 3 is a schematic diagram showing a reference voltage between the pixel unit 102 and the ADC 107. In FIG. 3, the row selector 103 is omitted.

As shown in FIG. 3, each of the pixel unit 102 and the ADC 107 has independent impedances R1 and R2 in the path to the common GND. That is, the pixel unit 102 outputs a voltage based on GND1, and the ADC 107 receives a voltage (input voltage Vin) based on GND2. Therefore, when the consumption current of the ADC 107 (current flowing through R2 in FIG. 3) has a dependency on the input voltage Vin, an error occurs in the output of the ADC according to the input voltage Vin. In this specification, the dependency of the consumption current on the input voltage Vin means that there is some correlation between the magnitude of the input voltage and the magnitude of the consumption current.

FIG. 4A is a schematic diagram for explaining the input voltage dependence of current consumption in the ADC. FIG. 4B is a schematic diagram for explaining the potential of GND2. FIG. 4C is a schematic diagram for explaining the relationship between the lightness of light and the digital value output from the ADC. In FIG. 4C, the dotted line a indicates the ideal characteristic of the input voltage Vin, and the solid line b indicates the actual characteristic of the input voltage Vin.

FIG. 4A shows the dependence of the consumption current flowing into the common GND on the input voltage Vin. At this time, the potential of GND2 has characteristics as shown in FIG. 4B due to the impedance R2. That is, as shown in FIG. 4C, Vin (actual characteristic b) is lower than an ideal Vin (ideal characteristic a) based on the common GND.

Here, generally, the voltage output from the photoelectric conversion element is inversely proportional to the lightness of the light input to the photoelectric conversion element. Therefore, the light input to the pixel portion 102 and the digital value output from the ADC 107 have characteristics as shown in C of FIG. That is, the difference between the actual characteristic and the ideal characteristic increases as the lightness of the light input to the pixel unit 102 is lower (darker).

Next, streaking will be explained.

FIG. 5 is a schematic diagram showing the configuration of the column ADC.

FIG. 6A is a schematic diagram showing an image in which white strip-like streaking has occurred. FIG. 6B is a schematic diagram illustrating an image in which black strip-like streaking has occurred.

As shown in FIG. 5, the column ADC 104 has a configuration in which a large number of ADCs 107 are connected in parallel, and the plurality of ADCs 107 configuring the column ADC 104 have a common impedance R <b> 2 on the path to the common GND.

When the image sensor 101 is used to photograph an object having a uniform brightness as a whole but only a specific area, the current consumption flowing from the ADC 107 of the pixel corresponding to the specific area to R2 increases. For this reason, the potential of GND2 rises. As a result, the input voltage Vin of the other ADCs 107 connected in parallel is reduced by the increase in the potential of GND2, and a digital value offset in a direction brighter than the actual is output from these other ADCs 107. . That is, because of some low-luminance pixels, the digital values of other pixels in the same row change.

Therefore, an image 110 in which white strip-like streaking has occurred as shown in FIG. 6A is obtained.

Alternatively, when the image sensor 101 is used to photograph an object having a uniform brightness but only a specific area as a whole, the current consumption flowing from the ADC 107 of the pixel for the specific area into R2 decreases. For this reason, the electric potential of GND2 falls. As a result, the input voltage Vin of the other ADCs 107 connected in parallel increases as the potential of the GND2 decreases, and a digital value offset in a darker direction than the actual is output from these other ADCs 107. . That is, because of some high-luminance pixels, the digital values of other pixels in the same row change.

Therefore, an image 111 in which black strip-like streaking occurs as shown in FIG. 6B is obtained.

In order to reduce such streaking, how to reduce (or equalize) the dependency of the consumption current of the ADC 107 on the input voltage Vin becomes an issue.

The dependency of the consumption current on the input voltage Vin in the ADC 107 is due to the switched capacitor technology generally used in the ADC 107.

There are various types of ADCs, such as cyclic ADCs, SAR ADCs, and ΔΣ modulation ADCs, but the basic element circuit is a switched capacitor circuit.

FIG. 7 is a circuit diagram of a switched capacitor integrator, which is an example of a switched capacitor circuit.

Hereinafter, a case where charging and discharging are performed in the sampling capacitor 121 in the circuit shown in FIG. 7 will be described.

One terminal of the sampling capacitor 121 is virtually grounded by the operational amplifier 123. For this reason, the charge / discharge amount in the sampling capacitor 121 is determined by the potential of the other terminal of the sampling capacitor 121, that is, the voltage input to the input terminal 129.

Now, assume that the capacitance of the sampling capacitor 121 is Cs [F], and a voltage of Vin [V] is applied to the input terminal 129. Here, if the switch 124 is short-circuited and the switch 125 is open, the other terminal of the sampling capacitor 121 is set to a voltage of Vin [V]. Therefore, the sampling capacitor 121 is charged with a charge of Cs · Vin [C].

Next, when the switch 124 is opened and the switch 125 is short-circuited, the other terminal of the sampling capacitor 121 is set to GND. For this reason, the charge of Cs · Vin [C] charged in the sampling capacitor 121 is discharged via GND.

As described above, in an AD converter using a switched capacitor circuit as a basic element circuit, it is an essential problem that the consumption current has input dependency.

Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed explanation than necessary may be omitted. For example, detailed descriptions of already well-known matters and repeated descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.

The accompanying drawings and the following description are provided for those skilled in the art to fully understand the present disclosure, and are not intended to limit the claimed subject matter.

(Embodiment 1)
The first embodiment will be described below with reference to FIGS.

[1-1. Constitution]
FIG. 8 is a block diagram illustrating a schematic configuration of the AD converter according to the first embodiment. As shown in FIG. 8, the AD converter 20A includes an amplifier circuit 21, an amplifier circuit 22, a switched capacitor circuit 23, a precharge circuit 24, and an AD converter circuit 25.

The input voltage Vin is input to the amplifier circuit 21. Vin is an analog signal to be subjected to analog-digital conversion by the AD converter 20A. For example, Vin is given from the pixel portion 102 of the image sensor 101 as shown in FIG.

The reference voltage Vref is input to the amplifier circuit 22. Vref is a reference signal serving as a reference for analog-digital conversion by the AD converter 20A. That is, the AD converter 20A performs analog-digital conversion on the differential voltage between Vin and Vref. Vref may be higher or lower than Vin. When Vref is higher than Vin, the input polarity of the AD converter 20A is inverted, and when Vref is lower than Vin, the input polarity of the AD converter 20A is not inverted and remains as it is.

FIG. 9 is a circuit diagram showing an example of the

amplifier circuits

21 and 22. As shown in FIG. 9, the

amplifier circuits

21 and 22 can be configured using a constant current source 26 and a source follower 27 including an NMOS transistor. The constant current source 26 is connected between the output terminals of the

amplifier circuits

21 and 22 and a reference voltage (here, GND). In the

amplifier circuits

21 and 22, a signal is input to the input terminal IN connected to the gate of the source follower 27 (NMOS transistor), and a signal is output from the output terminal OUT connected to the source.

The gains of the

amplifier circuits

21 and 22 shown in FIG. 9 are almost 1 times, and the output voltage of the

amplifier circuits

21 and 22 is a voltage obtained by dropping the gate-source voltage of the source follower 27 from the input voltage. Further, the current flowing into the GND is maintained at a constant value regardless of the input / output voltage.

FIG. 10 is a circuit diagram showing another example of the

amplifier circuits

21 and 22. As shown in FIG. 10, the

amplifier circuits

21 and 22 can be configured using a constant current source 26 and a voltage follower 28 including an operational amplifier. The inverting input terminal IN− and the output terminal OUT of the voltage follower 28 (operational amplifier) are connected to each other. The constant current source 26 is connected as a tail current source of the voltage follower 28 between the output terminals OUT of the

amplifier circuits

21 and 22 and the reference voltage (GND in this case). In the

amplifier circuits

21 and 22, a signal is input to the non-inverting input terminal IN + of the voltage follower 28 (operational amplifier), and a signal is output from the output terminal OUT.

The gains of the

amplifier circuits

21 and 22 shown in FIG. 10 are almost 1 times, and the output voltages of the

amplifier circuits

21 and 22 are almost equal to the input voltage. Further, the current flowing into the GND is maintained at a constant value regardless of the input / output voltage.

Returning to FIG. 8, the switched capacitor circuit 23 includes a switch 231, a switch 232, and a capacitor 233.

The output signal of the amplifier circuit 21 is connected to one end of the switch 231, and the other end of the switch 231 is connected to one end of the capacitor 233. The switch 231 performs a switching operation according to the control signal Φ1, and switches between short circuit and open circuit between the amplifier circuit 21 and the capacitor 233. The control signal Φ1 is output from a controller (not shown).

The output signal of the amplifier circuit 22 is connected to one end of the switch 232, and the other end of the switch 232 is connected to one end of the capacitor 233. The switch 232 performs a switching operation according to the control signal Φ <b> 2 and switches between short circuit and open circuit between the amplifier circuit 22 and the capacitor 233. The control signal Φ2 is output from a controller (not shown).

The capacitor 233 corresponds to the sampling capacitor 121 in FIG.

The precharge circuit 24 is connected between the interconnection point of the switch 231, the switch 232, and the capacitor 233 in the switched capacitor circuit 23 and a reference voltage (GND in this case). For example, the precharge circuit 24 can be configured by a switch 241 having one end connected to the interconnection point and the other end connected to GND. The switch 241 performs a switching operation according to the control signal Φ3, and switches between short-circuiting and opening of the capacitor 233 and GND. The control signal Φ3 is output from a controller (not shown).

The AD conversion circuit 25 is connected to the other end of the capacitor 233. The AD conversion circuit 25 integrates the charging voltage of the capacitor 233, performs analog-digital conversion on the integrated voltage, and outputs a digital value Dout. The AD conversion circuit 25 is a cyclic ADC, a SAR ADC, a ΔΣ modulation ADC, or a composite type thereof.

[1-2. Operation]
The operation of the AD converter 20A configured as described above will be described below. For convenience, the description will be made assuming that Vref is higher than Vin. The

switches

231, 232, and 241 are turned on (short circuit) when Φ1, Φ2, and Φ3 are at the H level, respectively, and are turned off (open) when Φ1, Φ2, and Φ3 are at the L level. Shall be.

It is assumed that the other end of the capacitor 233 is virtually grounded in the AD conversion circuit 25. Further, it is assumed that Vin is output from the amplifier circuit 21 and Vref is output from the amplifier circuit 22.

FIG. 11 is a time chart for explaining the operation of the AD converter 20A according to the present embodiment. Φ1 and Φ2 do not simultaneously become H level, and when one of them is H level, the other is L level. Further, Φ3 becomes H level when both Φ1 and Φ2 are L level.

First, when Φ2 becomes H level, only the switch 232 among the

switches

231, 232, and 241 is turned on, and the output signal (reference voltage Vref) of the amplifier circuit 22 is connected to the capacitor 233. As a result, the charging voltage of the capacitor 233 rises from GND to Vref.

At this time, since the driving capability of the amplifier circuit 22 is sufficiently large with respect to the capacitance of the capacitor 233, the charging voltage of the capacitor 233 immediately rises to Vref. Further, while the switch 232 is in the ON state, the current flowing into the GND is maintained at a constant value by the constant current source 26 in the amplifier circuit 22.

Thereafter, when Φ2 becomes L level, all of the

switches

231, 232, and 241 are turned off, and the charging voltage of the capacitor 233 is maintained at Vref. When Φ3 becomes H level immediately after Φ2 becomes L level, only the switch 241 is turned on among the

switches

231, 232, and 241, and the capacitor 233 is connected to GND.

As a result, the capacitor 233 is immediately discharged and the charging voltage becomes the GND level. That is, the capacitor 233 is precharged to the GND level.

Thereafter, when Φ3 becomes L level, all of the

switches

231, 232, and 241 are turned off, and the charging voltage of the capacitor 233 is maintained at the GND level. When Φ1 becomes H level immediately after Φ3 becomes L level, only the switch 231 among the

switches

231, 232, and 241 is turned on, and the output signal (input voltage Vin) of the amplifier circuit 21 is supplied to the capacitor 233. ) Is connected.

Thereby, the charging voltage of the capacitor 233 rises from GND to Vin. At this time, since the driving capability of the amplifier circuit 21 is sufficiently larger than the capacitance of the capacitor 233, the charging voltage of the capacitor 233 immediately rises to Vin. Further, while the switch 231 is in the ON state, the current flowing into the GND is maintained at a constant value by the constant current source 26 in the amplifier circuit 21.

The AD conversion circuit 25 integrates the input voltage Vin charged in the capacitor 233, converts the integrated voltage from analog to digital, and outputs a digital value Dout.

[1-3. Effect]
As described above, in the present embodiment, the AD converter 20A includes the amplifier circuit 21, the amplifier circuit 22, the switched capacitor circuit 23, the precharge circuit 24, and the AD converter circuit 25.

The analog signal (input voltage Vin) is input to the amplifier circuit 21, the reference signal (reference voltage Vref) is input to the amplifier circuit 22, and the current flowing into the GND in the

amplifier circuits

21 and 22 is constant. The switched capacitor circuit 23 has a capacitor 233 as a sampling capacitor in the AD converter 20A. The

switches

231 and 232 are connected to output signals of the

amplifier circuits

21 and 22, and the capacitor 233 is connected to the AD converter circuit 25. Is done. Precharge circuit 24 precharges capacitor 233 when both

switches

231 and 232 are off.

As a result, when the output signal of the amplifier circuit 21 is connected to the capacitor 233 serving as a sampling capacitor, the current flowing into the GND is always constant regardless of the magnitude of the input voltage Vin, and the input current dependence of the consumption current in the AD converter 20A. Sex is lost.

Further, immediately before the capacitor 233 is connected to the output signal of the

amplifier circuit

21 or 22, the capacitor 233 is precharged to the GND level every time. When the capacitor 233 is connected to the output signal of the

amplifier circuit

21 or 22, the capacitor 233 is charged in the direction of increasing from GND to Vin or Vref by the high-speed pull-up operation of the source follower 27 or the voltage follower 28. The

Thereby, the charging speed of the capacitor 233 is increased, and the input analog signal can be sampled at high speed.

(Embodiment 2)
Hereinafter, the second embodiment will be described with reference to FIGS. 12 and 13.

[2-1. Constitution]
FIG. 12 is a block diagram illustrating a schematic configuration of the AD converter according to the second embodiment. As shown in FIG. 12, the AD converter 20B includes an amplifier circuit 21, an amplifier circuit 22, a switched capacitor circuit 23, a precharge circuit 24, and an AD converter circuit 25. Note that the

amplifier circuits

21 and 22, the switched capacitor circuit 23, and the AD conversion circuit 25 are the same as those in the first embodiment, and thus description thereof is omitted.

The precharge circuit 24 is connected between the interconnection point of the switch 231, the switch 232, and the capacitor 233 in the switched capacitor circuit 23 and a reference voltage (GND in this case). The precharge circuit 24 is configured as a switched capacitor circuit having a switch 241, a switch 242, and a capacitor 243.

One end of the switch 241 is connected to the interconnection point, and the other end of the switch 241 is connected to one end of the capacitor 243. One end of the capacitor 243 is connected to a reference voltage (here, GND). The switch 241 performs a switching operation according to the control signal Φ3, and switches between short-circuit and open-circuit between the capacitor 233 and the capacitor 243. The control signal Φ3 is output from a controller (not shown).

One end of the switch 242 is connected to a reference voltage (here, GND), and the other end of the switch 242 is connected to one end of the capacitor 243. That is, the switch 242 is connected to both ends of the capacitor 243. The switch 242 performs a switching operation according to the control signal Φ4, and switches between short-circuiting and opening-up of both ends of the capacitor 243. The control signal Φ4 is output from a controller (not shown).

[2-2. Operation]
The operation of the AD converter 20B configured as described above will be described below. For convenience, the description will be made assuming that Vref is higher than Vin. Further, it is assumed that the capacitances of the capacitor 233 and the capacitor 243 are equal. The

switches

231, 232, 241, and 242 are turned on (short circuit) when Φ1, Φ2, Φ3, and Φ4 are at the H level, respectively, and when Φ1, Φ2, Φ3, and Φ4 are at the L level. It shall be in the off state (open). Further, it is assumed that the other end of the capacitor 233 is virtually grounded to GND in the AD conversion circuit 25. Further, it is assumed that Vin is output from the amplifier circuit 21 and Vref is output from the amplifier circuit 22.

FIG. 13 is a time chart for explaining the operation of the AD converter 20B according to the present embodiment. Φ1 and Φ2 do not simultaneously become H level, and when one of them is H level, the other is L level. Further, Φ3 and Φ4 are not simultaneously at the H level, and when one of them is at the H level, the other is at the L level. Further, Φ3 and Φ4 logically transition when both Φ1 and Φ2 are at the L level. That is, the

switches

241 and 242 perform a switching operation when both the

switches

231 and 232 are in the off state.

First, when Φ2 becomes H level, the

switches

232 and 242 among the

switches

231, 232, 241, and 242 are turned on, and the output signal (reference voltage Vref) of the amplifier circuit 22 is connected to the capacitor 233. As a result, the charging voltage of the capacitor 233 increases from Vref / 2 to Vref.

At this time, since the driving capability of the amplifier circuit 22 is sufficiently large with respect to the capacitance of the capacitor 233, the charging voltage of the capacitor 233 immediately rises to Vref. Further, while the switch 232 is in the ON state, the current flowing into the GND is maintained at a constant value by the constant current source 26 in the amplifier circuit 22. Further, both ends of the capacitor 243 are connected to a reference voltage (here, GND) and are in a discharged state.

Thereafter, when Φ2 goes to L level and Φ4 goes to L level almost simultaneously, all of the

switches

231, 232, 241, and 242 are turned off, the charging voltage of the capacitor 233 is maintained at Vref, and the charging of the capacitor 243 is performed. The voltage is maintained at zero (discharged state). When Φ3 becomes H level immediately after Φ2 and Φ4 become L level, only the switch 242 among the

switches

231, 232, 241, and 242 is turned on, and the capacitor 233 and the capacitor 243 are connected in series.

As a result, charge redistribution (ecorise) occurs between the capacitor 233 and the capacitor 243, and the capacitances of the

capacitors

233 and 243 are equal to each other, so that the charging voltage of the capacitor 233 rapidly increases to the original half, that is, Vref / 2. Converge to. That is, the capacitor 233 is precharged to the voltage Vref / 2.

Thereafter, when Φ3 becomes L level, all of the

switches

231, 232, 241, 242, and 242 are turned off, and the charging voltage of the capacitor 233 is maintained at Vref / 2. Then, immediately after Φ3 becomes L level, Φ1 becomes H level, and at the same time, Φ4 also becomes H level, and among the

switches

231, 232, 241, and 242, the

switches

231 and 242 are turned on, The output signal (input voltage Vin) of the amplifier circuit 21 is connected to the capacitor 233.

Thereby, the charging voltage of the capacitor 233 increases from Vref / 2 to Vin. At this time, since the driving capability of the amplifier circuit 21 is sufficiently larger than the capacitance of the capacitor 233, the charging voltage of the capacitor 233 immediately rises to Vin. Further, while the switch 231 is in the ON state, the current flowing into the GND is maintained at a constant value by the constant current source 26 in the amplifier circuit 21. The capacitor 243 is discharged with both ends connected to a reference voltage (here, GND).

[2-3. Effect]
As described above, in the present embodiment, the AD converter 20B includes the amplifier circuit 21, the amplifier circuit 22, the switched capacitor circuit 23, the precharge circuit 24, and the AD converter circuit 25. An analog signal (input voltage Vin) is input to the amplifier circuit 21, and a reference signal (reference voltage Vref) is input to the amplifier circuit 22, and the current flowing into the GND in the

amplifier circuits

21 and 22 is constant. The switched capacitor circuit 23 has a capacitor 233 as a sampling capacitor in the AD converter 20B. The

switches

231 and 232 are connected to the output signals of the

amplifier circuits

21 and 22, and the capacitor 233 is connected to the AD converter circuit 25. Is done.

The precharge circuit 24 is configured as a switched capacitor circuit having a switch 241, a switch 242, and a capacitor 243. When one of the

switches

231 and 232 is in an on state, the capacitor 243 is discharged, and which of the

switches

231 and 232 is In the off state, the

switches

241 and 242 perform a switching operation, and charge redistribution occurs between the

capacitors

233 and 243 to precharge the capacitor 233 to a predetermined voltage higher than GND.

As a result, when the output signal of the amplifier circuit 21 is connected to the capacitor 233 serving as the sampling capacitor, the current flowing into the GND is always constant regardless of the magnitude of the input voltage Vin, and the input current dependence of the consumption current in the AD converter 20B. Sex is lost. Further, immediately before the capacitor 233 is connected to the output signal of the

amplifier circuit

21 or 22, the capacitor 233 is precharged to a predetermined voltage higher than the GND level every time.

Here, in order for the constant current source 26 in the

amplifier circuits

21 and 22 to output a constant current, it is necessary to operate a transistor (not shown) constituting the constant current source 26 in a saturation region. In the meantime, a voltage equal to or higher than the voltage obtained by subtracting the threshold voltage from the gate-source voltage must be applied.

In the first embodiment, since the capacitor 233 is precharged to the GND level immediately before the capacitor 233 is connected to the output signal of the

amplifier circuit

21 or 22, the source voltage of a transistor (not shown) constituting the constant current source 26 is instantaneous. Therefore, there is a possibility that the constant current property may be lost due to the GND level and the transistor operating in the non-saturated region.

On the other hand, in the present embodiment, the capacitor 233 is precharged to a predetermined voltage higher than the GND level, so that the unillustrated transistor constituting the constant current source 26 does not operate in the non-saturated region. The constant current property of the constant current source 26 can be maintained.

When the capacitor 233 is connected to the output signal of the

amplifier circuit

21 or 22, the capacitor 233 is charged in the direction of increasing from a predetermined voltage to Vin or Vref by the high-speed pull-up operation of the source follower 27 or the voltage follower 28. Is done. Thereby, the charging speed of the capacitor 233 is increased, and the input analog signal can be sampled at high speed.

Note that the capacitances of the capacitor 233 and the capacitor 243 are not necessarily equal as long as the constant current source 26 does not enter the non-saturation region operation.

(Embodiment 3)
Hereinafter, Embodiment 3 will be described with reference to FIG.

FIG. 14 is an external view of the digital camera 30 according to the fourth embodiment. As shown in FIG. 14, the digital camera 30 includes an interchangeable lens (imaging optical system) 31 and a camera body 32 to which the interchangeable lens 31 can be attached. The interchangeable lens 31 includes a focus lens and a zoom lens (not shown). The camera body 32 includes a release button 33. The camera body 32 incorporates an image sensor 101 (see FIG. 1) including the AD converter 20A according to the first embodiment and the AD converter 20B according to the second embodiment.

Hereinafter, the operation of the digital camera 30 shown in FIG. 14 will be described in a simplified manner.

When the camera body 32 receives a half-press operation by the user of the release button 33, the camera body 32 transmits a control signal to the interchangeable lens 31 so as to perform an autofocus operation. Further, when the camera body 32 receives an operation by the user of the release button 33, the camera body 32 performs a photographing operation of a subject image formed via the interchangeable lens 31.

The interchangeable lens 31 focuses the light from the subject and forms an image on the image sensor 101. The image sensor 101 receives the formed subject image and photoelectrically converts the subject image to generate image data. The image data is processed by a processor (not shown) in the camera body 32.

As described above, according to the present embodiment, the digital camera 30 includes the image sensor 101 including the AD converter 20A according to the first embodiment and the AD converter 20B according to the second embodiment. It is possible to obtain a high-quality captured image in which streaking is suppressed.

(Other embodiments)
As described above, Embodiments 1 to 3 have been described as examples of the technology disclosed in the present application. However, the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed. Moreover, it is also possible to combine each component demonstrated in the said Embodiment 1 thru | or 3 into a new embodiment.

Therefore, other embodiments will be exemplified below.

In the image sensor 101 shown in FIG. 1, the column ADCs 104 are provided on both sides of the pixel unit 102, but the column ADCs 104 may be provided only on one side.

In the AD converter 20B according to the second embodiment, the capacitances of the capacitor 233 and the capacitor 243 are assumed to be equal. In consideration of the characteristics of the transistor, it may be determined as appropriate according to how much the precharge voltage of the capacitor 233 is set.

In the third embodiment, the digital camera 30 is described as an example of an imaging device on which the image sensor 101 is mounted. However, the application range of the image sensor 101 is not limited to the digital camera 30. The image sensor 101 can be mounted on various devices such as a studio camera, a business camera, a digital video camera, a surveillance camera, an in-vehicle camera, a smartphone, and a tablet PC.

As described above, the embodiments have been described as examples of the technology in the present disclosure. For this purpose, the accompanying drawings and detailed description are provided.

Therefore, among the constituent elements described in the accompanying drawings and the detailed description, not only essential constituent elements but also non-essential constituent elements may be included to exemplify the above technique. Therefore, it should not be immediately recognized that these non-essential components are essential as those non-essential components are described in the accompanying drawings and detailed description.

In addition, since the above-described embodiment is for illustrating the technique in the present disclosure, various modifications, replacements, additions, omissions, and the like can be performed within the scope of the claims or an equivalent scope thereof.

This disclosure is applicable to image sensors. Specifically, the present disclosure is applicable to image sensors mounted on studio cameras, business cameras, digital still cameras, movies, mobile phones with camera functions, smartphones, and the like.

20A AD converter

20B AD converter 21 Amplifier circuit (first amplifier circuit)
22 Amplifier circuit (second amplifier circuit)
23 switched capacitor circuit 24 precharge circuit 25 AD converter circuit 26 constant current source 27 source follower 28 voltage follower 30 digital camera (imaging device)
31 Interchangeable lens (shooting optics)
32 Camera body 33 Release button 101 Image sensor 102 Pixel unit (pixel array)
103 row selector 104 column ADC
105 Parallel-serial converter 106 Peripheral circuit 107 ADC
110 image 111 image 121 sampling capacity 123 operational amplifier 124 switch 125 switch 129 input terminal 231 switch (first switch)
232 switch (second switch)
233 capacitor 241 switch (third switch)
242 switch (fourth switch)
243 capacitors

Claims

A first amplifier circuit to which an analog signal is input;
A second amplifier circuit to which a reference signal is input;
A switched capacitor circuit having a first switch to which an output signal of the first amplifier circuit is connected, a second switch to which an output signal of the second amplifier circuit is connected, and a capacitor;
A precharge circuit connected between an interconnection point of the first switch, the second switch, and the capacitor and a reference voltage;
An AD conversion circuit connected to the capacitor;
An AD converter comprising:
The first and second amplifier circuits have constant current sources connected between an output terminal and the reference voltage.
The AD converter according to claim 1.
The precharge circuit includes a switched capacitor circuit having a third switch connected to the interconnection point, a fourth switch connected to the reference voltage, and a capacitor connected to the reference voltage.
The AD converter according to claim 1.
The third and fourth switches perform a switching operation when both the first and second switches are in an off state.
The AD converter according to claim 3.
The first and second amplifier circuits have a source follower,
The AD converter according to claim 1 or 2.
The first and second amplifier circuits have a voltage follower,
The AD converter according to claim 1 or 2.
A pixel array in which a plurality of photoelectric conversion elements are arranged in a matrix;
A column AD converter having a plurality of AD converters according to any one of claims 1 to 6, to which an output voltage corresponding to one row of pixels of the pixel array is input,
An image sensor.
Photographic optics,
The image sensor according to claim 7, which receives a subject image formed by the photographing optical system;
An imaging apparatus comprising: