WO2021256106A1 - Semiconductor device, method for manufacturing semiconductor device, and filling resin - Google Patents

Semiconductor device, method for manufacturing semiconductor device, and filling resin Download PDF

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Publication number
WO2021256106A1
WO2021256106A1 PCT/JP2021/017178 JP2021017178W WO2021256106A1 WO 2021256106 A1 WO2021256106 A1 WO 2021256106A1 JP 2021017178 W JP2021017178 W JP 2021017178W WO 2021256106 A1 WO2021256106 A1 WO 2021256106A1
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WO
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Prior art keywords
substrate
semiconductor device
light emitting
filling resin
solder
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PCT/JP2021/017178
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French (fr)
Japanese (ja)
Inventor
光成 星
英一郎 土橋
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2021256106A1 publication Critical patent/WO2021256106A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/42—Arrays of surface emitting lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Definitions

  • the present disclosure relates to semiconductor devices, methods for manufacturing semiconductor devices, and filling resins.
  • a component portion of the semiconductor device (for example, a light emitting element or a connection portion) is arranged between two substrates, and a filling resin called an underfill material is filled between these substrates.
  • a filling resin called an underfill material is filled between these substrates.
  • connection part is, for example, solder.
  • solder in order to bond the substrates with solder, it is necessary to raise the temperature of the solder to its melting point.
  • the filling resin described above is, for example, a thermosetting resin. In this case, in order to cure the thermosetting resin, it is necessary to heat the thermosetting resin to a high temperature.
  • the semiconductor device when manufacturing the above-mentioned semiconductor device, the semiconductor device may be heated to a high temperature due to the bonding between the substrates and the curing of the filling resin. In this case, if these substrates have different coefficient of linear expansion, a large stress is applied to the above-mentioned light emitting element or the like, which may impair the reliability of the semiconductor device or may cause the semiconductor device to crack and crack. be.
  • the present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and a filling resin capable of suppressing deterioration of the performance of the semiconductor device due to the filling resin.
  • the semiconductor device on the first side surface of the present disclosure includes a first substrate, a second substrate facing the first substrate, and a filling resin provided between the first substrate and the second substrate.
  • the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin satisfy the relationship of 80 ⁇ Tp ⁇ (Tg + 115) /1.5. As a result, for example, it is possible to reduce the stress applied to the constituent portions between these substrates, and it is possible to suppress the deterioration of the performance of the semiconductor device due to the filling resin.
  • the glass transition temperature Tg [° C.] of the filling resin may satisfy the relationship of Tg ⁇ 90. As a result, for example, it is possible to further reduce the stress applied to the constituent portions between these substrates, and it is possible to further suppress the deterioration of the performance of the semiconductor device due to the filling resin.
  • the filling resin may be an acrylic resin. This makes it possible to provide, for example, a filling resin satisfying the relationship of 80 ⁇ Tp ⁇ (Tg + 115) /1.5.
  • the first substrate and the second substrate may have different coefficient of linear expansion.
  • the difference in the coefficient of linear expansion between the first substrate and the second substrate may be 2.0 ⁇ 10 -6 [1 / K] or more.
  • the first substrate may be a semiconductor substrate containing gallium (Ga) and arsenic (As). This makes it possible to suppress the deterioration of the performance of the light emitting device due to the filling resin, for example, when the light emitting device is manufactured using the GaAs substrate.
  • Ga gallium
  • As arsenic
  • the second substrate may be a semiconductor substrate containing silicon (Si).
  • Si silicon
  • the second substrate may be a semiconductor substrate containing silicon (Si).
  • the semiconductor device on the first side surface further includes a plurality of protrusions protruding from the first surface of the first substrate, and the second substrate faces the first surface of the first substrate. You may be doing it. As a result, for example, by using the above-mentioned filling resin, it is possible to reduce the stress applied to the protruding portion.
  • the protruding portion may include a light emitting element that emits light from the first surface to the second surface of the first substrate.
  • a light emitting element that emits light from the first surface to the second surface of the first substrate.
  • the protruding portion may include a connecting portion that electrically connects the first substrate side and the second substrate side. This makes it possible, for example, to protect the connection portion with a suitable filling resin as described above.
  • connection portion may include solder or bumps. This makes it possible to protect the connection portion with the above-mentioned suitable filling resin, for example, when the substrates are solder-connected or bump-connected.
  • the semiconductor device on the first side surface may further include a plurality of lenses provided as a part of the first substrate on the second surface of the first substrate.
  • a plurality of lenses provided as a part of the first substrate on the second surface of the first substrate.
  • the first substrate and the second substrate are arranged so as to face each other, and a filling resin is formed between the first substrate and the second substrate.
  • the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin satisfy the relationship of 80 ⁇ Tp ⁇ (Tg + 115) /1.5. As a result, for example, it is possible to reduce the stress applied to the constituent portions between these substrates, and it is possible to suppress the deterioration of the performance of the semiconductor device due to the filling resin.
  • the glass transition temperature Tg [° C.] of the filling resin may satisfy the relationship of Tg ⁇ 90. As a result, for example, it is possible to further reduce the stress applied to the constituent portions between these substrates, and it is possible to further suppress the deterioration of the performance of the semiconductor device due to the filling resin.
  • the method for manufacturing the semiconductor device on the second side surface further includes thermosetting the filling resin between the first substrate and the second substrate, and the filling resin is heated at 170 to 220 ° C. It may be thermoset. This makes it possible to suppress deterioration of the performance of the semiconductor device due to the filling resin, for example, even when the filling resin is heated for thermosetting.
  • the method for manufacturing a semiconductor device on the second side surface further includes forming a plurality of protrusions protruding from the first surface of the first substrate, and the second substrate is the first substrate. It may be arranged so as to face the first surface of the above. As a result, for example, by using the above-mentioned filling resin, it is possible to reduce the stress applied to the protruding portion.
  • the maximum principal stress applied to the protrusion may be 150 MPa or less. This makes it possible to suppress deterioration in the performance of the semiconductor device due to, for example, the stress applied to the protrusion.
  • the protruding portion includes a connecting portion that electrically connects the first substrate side and the second substrate side, and the material of the connecting portion is the material of the first substrate and the second substrate. It may further include electrically connecting the first substrate side and the second substrate side by the connecting portion by supplying the two substrates and melting them by heating. As a result, for example, even when the material of the connecting portion is heated to connect the substrates to each other, it is possible to suppress the deterioration of the performance of the semiconductor device due to the filling resin.
  • the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] satisfy the relationship of 80 ⁇ Tp ⁇ (Tg + 115) /1.5. This makes it possible to suppress deterioration of the performance of the semiconductor device due to the filling resin, for example, when the filling resin is formed between the substrates of the semiconductor device.
  • the glass transition temperature Tg [° C.] satisfies the relationship of Tg ⁇ 90.
  • FIG. 2 It is a block diagram which shows the structure of the distance measuring apparatus of 1st Embodiment. It is sectional drawing which shows the example of the structure of the light emitting device of 1st Embodiment. 2 is a cross-sectional view, a plan view, and a perspective view showing the structure of the light emitting device shown in FIG. 2B. It is sectional drawing (1/2) which shows the manufacturing method of the light emitting device of 1st Embodiment. It is sectional drawing (2/2) which shows the manufacturing method of the light emitting device of 1st Embodiment. It is sectional drawing (1/4) which shows the detail of the manufacturing method of the light emitting device of 1st Embodiment.
  • FIG. 1 is a block diagram showing a configuration of a distance measuring device according to a first embodiment.
  • the distance measuring device of FIG. 1 includes a light emitting device 1, an image pickup device 2, and a control device 3.
  • the distance measuring device of FIG. 1 irradiates the subject with the light emitted from the light emitting device 1.
  • the image pickup apparatus 2 receives the light reflected by the subject and images the subject.
  • the control device 3 measures (calculates) the distance to the subject using the image signal output from the image pickup device 2.
  • the light emitting device 1 functions as a light source for the image pickup device 2 to take an image of a subject.
  • the light emitting device 1 includes a light emitting unit 11, a drive circuit 12, a power supply circuit 13, and a light emitting side optical system 14.
  • the image pickup apparatus 2 includes an image sensor 21, an image processing unit 22, and an image pickup side optical system 23.
  • the control device 3 includes a ranging unit 31.
  • the light emitting unit 11 emits a laser beam for irradiating the subject.
  • the light emitting unit 11 of the present embodiment includes a plurality of light emitting elements arranged in a two-dimensional array, and each light emitting element has a VCSEL (Vertical Cavity Surface Emitting Laser) structure. The light emitted from these light emitting elements irradiates the subject.
  • the light emitting unit 11 of the present embodiment is provided in a chip called an LD (Laser Diode) chip 41.
  • LD Laser Diode
  • the drive circuit 12 is an electric circuit that drives the light emitting unit 11.
  • the power supply circuit 13 is an electric circuit that generates a power supply voltage of the drive circuit 12. In the distance measuring device of FIG. 1, for example, the power supply circuit 13 generates a power supply voltage from the input voltage supplied from the battery in the distance measuring device, and the drive circuit 12 drives the light emitting unit 11 using this power supply voltage. ..
  • the drive circuit 12 of the present embodiment is provided in a substrate called an LDD (Laser Diode Driver) substrate 42.
  • LDD Laser Diode Driver
  • the light emitting side optical system 14 includes various optical elements, and irradiates the subject with light from the light emitting unit 11 via these optical elements.
  • the image pickup side optical system 23 includes various optical elements, and receives light from the subject through these optical elements.
  • the image sensor 21 receives light from the subject via the image pickup side optical system 23, and converts this light into an electric signal by photoelectric conversion.
  • the image sensor 21 is, for example, a CCD (Charge Coupled Device) sensor or a CMOS (Complementary Metal Oxide Semiconductor) sensor.
  • the image sensor 21 of the present embodiment converts the above electronic signal from an analog signal to a digital signal by A / D (Analog to Digital) conversion, and outputs an image signal as a digital signal to the image processing unit 22.
  • the image sensor 21 of the present embodiment outputs a frame synchronization signal to the drive circuit 12, and the drive circuit 12 emits light from the light emitting unit 11 at a timing corresponding to the frame cycle of the image sensor 21 based on the frame synchronization signal.
  • the image processing unit 22 performs various image processing on the image signal output from the image sensor 21.
  • the image processing unit 22 includes, for example, an image processing processor such as a DSP (Digital Signal Processor).
  • DSP Digital Signal Processor
  • the control device 3 controls various operations of the distance measuring device of FIG. 1, for example, controlling the light emitting operation of the light emitting device 1 and the imaging operation of the image pickup device 2.
  • the control device 3 includes, for example, a CPU (Central Processing Unit), a ROM (ReadOnlyMemory), a RAM (RandomAccessMemory), and the like.
  • the distance measuring unit 31 measures the distance to the subject based on the image signal output from the image sensor 21 and subjected to image processing by the image processing unit 22.
  • the distance measuring unit 31 employs, for example, an STL (Structured Light) method or a ToF (Time of Flight) method as the distance measuring method.
  • the distance measuring unit 31 may further measure the distance between the distance measuring device and the subject for each portion of the subject based on the above image signal to specify the three-dimensional shape of the subject.
  • FIG. 2 is a cross-sectional view showing an example of the structure of the light emitting device 1 of the first embodiment.
  • the light emitting device 1 is an example of the semiconductor device of the present disclosure.
  • a in FIG. 2 shows a first example of the structure of the light emitting device 1 of the present embodiment.
  • the light emitting device 1 of this example includes the above-mentioned LD chip 41 and LDD substrate 42, a mounting substrate 43, a heat radiating substrate 44, a correction lens holding portion 45, one or more correction lenses 46, and a wiring 47. ing.
  • a in FIG. 2 shows an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other.
  • the X and Y directions correspond to the horizontal direction (horizontal direction), and the Z direction corresponds to the vertical direction (vertical direction). Further, the + Z direction corresponds to the upward direction, and the ⁇ Z direction corresponds to the downward direction.
  • the ⁇ Z direction may or may not exactly coincide with the direction of gravity.
  • the LD chip 41 is arranged on the mounting board 43 via the heat radiating board 44, and the LDD board 42 is also arranged on the mounting board 43.
  • the mounting board 43 is, for example, a printed circuit board.
  • the image sensor 21 and the image processing unit 22 of FIG. 1 are also arranged on the mounting board 43 of the present embodiment.
  • the heat dissipation substrate 44 is, for example, a ceramic substrate such as an Al 2 O 3 (aluminum oxide) substrate or an AlN (aluminum nitride) substrate.
  • the correction lens holding portion 45 is arranged on the heat radiating substrate 44 so as to surround the LD chip 41, and holds one or more correction lenses 46 above the LD chip 41. These correction lenses 46 are included in the light emitting side optical system 14 (FIG. 1) described above. The light emitted from the light emitting unit 11 (FIG. 1) in the LD chip 41 is corrected by these correction lenses 46 and then irradiated to the subject (FIG. 1). As an example, A in FIG. 2 shows two correction lenses 46 held by the correction lens holding portion 45.
  • the wiring 47 is provided on the front surface, the back surface, the inside, etc. of the mounting board 43, and electrically connects the LD chip 41 and the LDD board 42.
  • the wiring 47 is, for example, a printed wiring provided on the front surface or the back surface of the mounting board 43, or a via wiring penetrating the mounting board 43.
  • the wiring 47 of the present embodiment further passes through the inside or the vicinity of the heat dissipation board 44.
  • the light emitting device 1 of this example has the same components as the light emitting device 1 of the first example, but includes a solder 48 instead of the wiring 47, and further includes an underfill material 49.
  • the solder 48 is an example of the connection portion of the present disclosure, and is an example of the protrusion portion of the present disclosure together with the light emitting element 53, the electrode 54, and the connection pad 62 described later.
  • the underfill material 49 is an example of the filling resin of the present disclosure.
  • the LDD board 42 is arranged on the heat dissipation board 44, and the LD chip 41 is arranged on the LDD board 42.
  • the LD chip 41 is arranged on the LDD substrate 42 in this way, it is possible to reduce the size of the mounting substrate 43 as compared with the case of the first example.
  • the LD chip 41 is arranged on the LDD board 42 via the solder 48, and is electrically connected to the LDD board 42 by the solder 48.
  • the LD chip 41 may be electrically connected to the LDD substrate 42 by a metal bump instead of the solder 48.
  • the underfill material 49 is filled between the LD chip 41 and the LDD substrate 42 so as to surround the solder 48.
  • the underfill material 49 is, for example, a resin injected between the LD chip 41 and the LDD substrate 42.
  • An example of this resin is a thermosetting resin such as an acrylic resin.
  • the light emitting device 1 of the present embodiment will be described as having the structure of the second example shown in B of FIG.
  • the following description is also applicable to the light emitting device 1 having the structure of the first example, except for the description of the structure peculiar to the second example.
  • FIG. 3 is a cross-sectional view, a plan view, and a perspective view showing the structure of the light emitting device 1 shown in FIG. 2B.
  • a in FIG. 3 shows a cross section of the LD chip 41 and the LDD substrate 42 in the light emitting device 1.
  • the LD chip 41 includes a substrate 51, a laminated film 52, a plurality of light emitting elements 53, a plurality of electrodes 54, and an insulating film 55.
  • the LDD substrate 42 includes a substrate 61 and a plurality of connection pads 62.
  • B and C in FIG. 3 are a plan view and a perspective view corresponding to A in FIG.
  • the illustration of the underfill material 49 is omitted.
  • the substrate 51 is a compound semiconductor substrate such as a GaAs (gallium arsenide) substrate.
  • a in FIG. 3 shows the front surface S1 of the substrate 51 facing the ⁇ Z direction and the back surface S2 of the substrate 51 facing the + Z direction.
  • the substrate 51 is an example of the first substrate of the present disclosure.
  • the front surface S1 is an example of the first surface of the present disclosure
  • the back surface S2 is an example of the second surface of the present disclosure.
  • the laminated film 52 includes a plurality of layers laminated on the surface S1 of the substrate 51. Examples of these layers are an n-type semiconductor layer, an active layer, a p-type semiconductor layer, a light reflecting layer, an insulating layer having a light emission window, and the like.
  • the laminated film 52 includes a plurality of mesa portions M protruding in the ⁇ Z direction. A part of these mesas portions M is a plurality of light emitting elements 53.
  • the light emitting element 53 is provided on the surface S1 of the substrate 51 as a part of the laminated film 52, and protrudes in the ⁇ Z direction with respect to the surface S1 of the substrate 51.
  • the light emitting element 53 is an example of the protruding portion of the present disclosure.
  • the light emitting element 53 of the present embodiment has a VCSEL structure and emits light in the + Z direction. As shown in FIG. 3A, the light emitted from the light emitting element 53 passes through the substrate 51 from the front surface S1 to the back surface S2, and is incident on the correction lens 46 (FIG. 2) from the substrate 51.
  • the LD chip 41 of the present embodiment is a back-illuminated type VCSEL chip.
  • the laminated film 52 in each light emitting element 53 is also called a VCSEL active layer.
  • the electrode 54 is formed on the lower surface of the light emitting element 53. Therefore, the light emitting element 53 and the electrode 54 are sequentially provided on the surface S1 of the substrate 51, and project in the ⁇ Z direction with respect to the surface S1 of the substrate 51.
  • the electrode 54 is also an example of the protrusion of the present disclosure.
  • the electrode 54 of this embodiment is an anode electrode.
  • the LD chip 41 of the present embodiment further includes a cathode electrode formed on the lower surface of the mesa portion M other than the light emitting element 53. Each light emitting element 53 emits light by flowing a current between the corresponding anode electrode and the corresponding cathode electrode.
  • the insulating film 55 is formed on the surface S1 of the substrate 51 between the light emitting elements 53 adjacent to each other and the like.
  • the insulating film 55 is formed on, for example, the lower surface of the laminated film 52 or the surface (side surface or lower surface) of the light emitting element 53.
  • the lower surface of the electrode 54 is exposed from the insulating film 55.
  • the insulating film 55 is, for example, a SiN film (silicon nitride film) or a SiO 2 film (silicon oxide film).
  • the LD chip 41 is arranged on the LDD board 42 via the solder 48, and is electrically connected to the LDD board 42 by the solder 48.
  • the connection pad 62 is formed on the substrate 61 included in the LDD substrate 42, and the mesa portion M is arranged on the connection pad 62 via the solder 48.
  • Each mesa portion M is arranged on the solder 48 via the anode electrode (electrode 54) or the cathode electrode.
  • the substrate 61 is arranged in the ⁇ Z direction of the substrate 51 so as to face the surface S1 of the substrate 51.
  • the substrate 61 is made of, for example, a material different from the material of the substrate 51, and has a linear expansion coefficient different from the linear expansion coefficient of the substrate 51.
  • the difference in the coefficient of linear expansion between the substrate 51 and the substrate 61 is, for example, 2.0 ⁇ 10 -6 [1 / K] or more.
  • the substrate 61 is a semiconductor substrate such as a Si (silicon) substrate.
  • the substrate 61 is an example of the second substrate of the present disclosure.
  • the coefficient of linear expansion of the substrate 51 is 5.7 ⁇ 10 -6 [1 / K].
  • the coefficient of linear expansion of the substrate 61 is 3.0 ⁇ 10-6 [1 / K].
  • connection pad 62 is made of a metal such as Cu (copper), Ni (nickel), Al (aluminum), for example.
  • the light emitting element 53, the electrode 54, the solder 48, and the connection pad 62 project in the ⁇ Z direction with respect to the surface S1 of the substrate 51.
  • the solder 48 and the connection pad 62 are also examples of the protrusions of the present disclosure.
  • the LDD board 42 includes a drive circuit 12 that drives the light emitting unit 11 (FIG. 1).
  • FIG. 3A schematically shows a plurality of switch SWs included in the drive circuit 12. Each switch SW is electrically connected to the corresponding light emitting element 53 via the solder 48.
  • the drive circuit 12 of the present embodiment can control (on / off) these switch SWs for each individual switch SW. Therefore, the drive circuit 12 can drive a plurality of light emitting elements 53 for each individual light emitting element 53. This makes it possible to precisely control the light emitted from the light emitting unit 11, for example, by causing only the light emitting element 53 required for distance measurement to emit light.
  • Such individual control of the light emitting element 53 can be realized by arranging the LDD substrate 42 below the LD chip 41 so that each light emitting element 53 can be easily electrically connected to the corresponding switch SW. ing.
  • the solder 48 of the present embodiment electrically connects the LD chip 41 and the LDD board 42 as described above. Specifically, the electric circuit or circuit element on the board 51 side and the electricity on the board 52 side. It is electrically connected to circuits and circuit elements. For example, each of the above-mentioned switch SWs is electrically connected to the corresponding electrode 54 via the solder 48.
  • the underfill material 49 of the present embodiment is filled between the substrate 51 and the substrate 61, and surrounds the components of the light emitting device 1 such as the light emitting element 53, the electrode 54, the solder 48, and the connection pad 62. .. This makes it possible to protect these components from foreign matter and structurally reinforce these components.
  • the underfill material 49 of the present embodiment is filled in the gap between the LD chip 41 and the LDD substrate 42 after the individual LD chips 41 are diced from the wafer including the plurality of LD chips 41. Therefore, the underfill material 49 shown in FIGS. 3A and 3B includes not only the portion filled in the gap but also the portion protruding from the gap.
  • the underfill material 49 of the present embodiment is a thermosetting resin such as an acrylic resin, and has a predetermined glass transition temperature Tg [° C.] and a curing temperature Tp [° C.].
  • Tg [° C.] and Tp [° C.] of the underfill material 49 of the present embodiment satisfy the relationship of the following formula (1), and more preferably further of the following formula (2). Meet the relationship.
  • 4 and 5 are cross-sectional views showing a method of manufacturing the light emitting device 1 of the first embodiment.
  • the board 51 (A in FIG. 4).
  • the front surface S1 of the substrate 51 faces the + Z direction
  • the back surface S2 of the substrate 51 faces the ⁇ Z direction.
  • the laminated film 52 is formed on the surface S1 of the substrate 51, and the laminated film 52 is etched so as to include a plurality of light emitting elements 53 (mesa portions M) (A in FIG. 4). As a result, the light emitting element 53 projecting in the + Z direction with respect to the surface S1 of the substrate 51 is formed.
  • a plurality of electrodes 54 are formed on the upper surface of these light emitting elements 53, and an insulating film 55 is formed on the surface S1 of the substrate 51 (B in FIG. 4).
  • the laminated film 52, the light emitting element 53, and the electrode 54 are covered with the insulating film 55.
  • the insulating film 55 is etched (C in FIG. 4). As a result, the electrode 54 is exposed from the insulating film 55. In this way, the insulating film 55 is formed between the light emitting elements 53 adjacent to each other.
  • the substrate 51 is placed on the upper surface of the substrate 61 (A in FIG. 5).
  • the substrate 51 is arranged on the upper surface of the substrate 61 so that the front surface S1 faces the ⁇ Z direction and the back surface S2 faces the + Z direction.
  • the substrate 61 is arranged under the substrate 51 so as to face the surface S1 of the substrate 51.
  • a in FIG. 5 shows a plurality of connection pads 62 previously formed on the upper surface of the substrate 61.
  • the substrate 51 is arranged on the substrate 61 so that the electrodes 48 are arranged on the connection pad 62 via the solder 48. As a result, the substrate 51 side is electrically connected to the substrate 61 side.
  • the underfill material 49 is injected between the substrate 51 and the substrate 61, and the underfill material 49 is thermoset (B in FIG. 5).
  • the components of the light emitting device 1 such as the light emitting element 53, the electrode 54, the solder 48, and the connection pad 62 are surrounded by the underfill material 49.
  • the light emitting device 1 of the present embodiment is manufactured. Further details of the steps shown in FIGS. 5A and 5B will be described with reference to FIGS. 6 to 9.
  • 6 to 9 are cross-sectional views showing details of the manufacturing method of the light emitting device 1 of the first embodiment.
  • the substrate 51 When electrically connecting the LD chip 41 and the LDD substrate 42, the substrate 51 is first arranged above the substrate 61 (A in FIG. 6). Specifically, each electrode 54 is placed above the corresponding connection pad 62.
  • Reference numeral P1 indicates that the position of the substrate 51 is fixed with respect to the position of the substrate 61.
  • Reference numeral P2 indicates that the substrate 61 is vacuum-sucked.
  • the temperature of the LD chip 41 and the LDD substrate 42 in the step A of FIG. 6 is, for example, 25 ° C.
  • the solder 48 for joining is supplied between the electrode 54 and the connection pad 62, and the solder 48 is heated and melted in a reflow oven or the like (B in FIG. 6).
  • the melting temperature of the solder 48 differs depending on the composition of the solder 48, but the melting temperature of the Sn—Ag—Cu-based solder 48 is about 220 ° C., and the melting temperature of the Sn—Bi-based solder 48 is about 170 ° C. ( Sn stands for tin, Ag stands for silver, and Bi stands for bismuth).
  • the solder 48 and the components in the vicinity thereof are heated to, for example, 220 ° C.
  • the arrow F1 indicates that when the coefficient of thermal expansion of the substrate 61 is larger than the coefficient of thermal expansion of the substrate 51 when the substrate 61 and the substrate 51 thermally expand due to the heating in the step B of FIG. 6, the substrate 61 becomes the substrate 51. On the other hand, it shows that it expands relatively large.
  • the temperature of the solder 48 drops as the substrates 51, 61, etc. are taken out of the reflow furnace (A in FIG. 7). As a result, the solder 48 is solidified, and the electrode 54 and the connection pad 62 are joined by the solder 48. In this way, the LD chip 41 and the LDD substrate 42 are electrically connected. In the step A of FIG. 7, the temperature of the solder 48 and the components in the vicinity thereof returns to, for example, 25 ° C.
  • the arrow F2 shown in FIG. 7B indicates a case where the coefficient of thermal expansion of the substrate 61 is larger than the coefficient of thermal expansion of the substrate 51 when the substrate 61 and the substrate 51 thermally shrink due to a temperature drop of the solder 48 and its components. Shows that the substrate 61 shrinks relatively significantly with respect to the substrate 51.
  • the underfill material 49 is injected between the substrate 51 and the substrate 61 (A in FIG. 8).
  • the underfill material 49 is, for example, a thermosetting resin such as an acrylic resin.
  • the underfill material 49 injected between the substrate 51 and the substrate 61 is heated to heat-cure the underfill material 49 (B in FIG. 8).
  • the underfill material 49 is thermoset at, for example, 170 to 220 ° C.
  • the underfill material 49 and the components in the vicinity thereof are heated to, for example, about 170 ° C.
  • the arrow F3 indicates that when the coefficient of thermal expansion of the substrate 61 is larger than the coefficient of thermal expansion of the substrate 51 when the substrate 61 and the substrate 51 thermally expand due to the heating in the step B of FIG. 8, the substrate 61 becomes the substrate 51. On the other hand, it shows that it expands relatively large.
  • the temperature of the underfill material 49 drops (Fig. 9).
  • the temperature of the underfill material 49 and the components in the vicinity thereof returns to, for example, 25 ° C.
  • the arrow F4 indicates a substrate when the coefficient of thermal expansion of the substrate 61 is larger than the coefficient of thermal expansion of the substrate 51 when the substrate 61 and the substrate 51 thermally shrink due to a temperature drop of the underfill material 49 and its components. It is shown that 61 shrinks relatively large with respect to the substrate 51.
  • the underfill material 49 is formed between the substrate 51 and the substrate 61.
  • the underfill material 49 of the present embodiment may include not only a portion filled in the gap between the substrate 51 and the substrate 61 but also a portion protruding from the gap.
  • FIG. 10 is a graph for explaining the manufacturing method of the light emitting device 1 of the first embodiment.
  • the graph of FIG. 10 shows an example of the time change of the process temperature in the steps A to 9 of FIG.
  • the various manufacturing steps of the light emitting device 1 of the present embodiment are performed at approximately 25 ° C.
  • the solder 48 for joining is heated and melted, and the solder 48 is supplied between the electrode 54 and the connection pad 62 (bonding step). At this time, the solder 48 is heated to its melting point. In the graph of FIG. 10, the melting point of the solder 48 is about 220 ° C.
  • the underfill material 49 injected between the substrate 51 and the substrate 61 is heated to thermally cure the underfill material 49 (UF (underfill) step). At this time, the underfill material 49 is heated to its curing temperature. In the graph of FIG. 10, the curing temperature of the underfill material 49 is about 170 ° C.
  • the light emitting device 1 when the light emitting device 1 of the present embodiment is manufactured, the light emitting device 1 may be heated to a high temperature due to the joining by the solder 48 and the curing of the underfill material 49. In this case, if the substrate 51 and the substrate 61 have different linear expansion coefficients, a large stress is applied to the light emitting element 53 and the like, the reliability of the light emitting device 1 may be impaired, and the light emitting device 1 may be cracked. There is a risk of cracking. This stress is generated, for example, due to the difference in thermal expansion and contraction between the substrate 61 and the substrate 51 shown in FIGS. 6A to 9 (see arrows F1 to F4). This stress may remain on the substrate 61 in the finished product of the light emitting device 1, and the influence on the light emitting device 1 in this case also becomes a problem.
  • the substrate 51 of this embodiment is, for example, a GaAs substrate. This makes it possible to use a GaAs substrate suitable for forming the light emitting element 53 as the substrate 51.
  • the substrate 61 of this embodiment is, for example, a Si substrate. This makes it possible to use a Si substrate that can be prepared at low cost as the substrate 61.
  • the difference in the coefficient of linear expansion between the substrate 51 and the substrate 61 becomes as large as 2.7 ⁇ 10-6 [1 / K]. Therefore, a large stress is likely to be applied to the light emitting element 53 or the like.
  • the light emitting device 1 of the present embodiment is a back-illuminated type
  • the light emitting element 53 is arranged between the substrate 51 and the substrate 61. Therefore, the light emitting element 53 is arranged near the solder 48 and the underfill material 49, and is easily affected by changes in the mechanical characteristics of the solder 48 and the underfill material 49 in the joining process and the UF process. Is located in. This also contributes to the fact that a large stress is likely to be applied to the light emitting element 53. When a large stress is applied to the light emitting element 53, for example, the intensity of the light emitted from the light emitting element 53 may decrease or the deterioration over time may be accelerated.
  • FIG. 11 is a graph showing the properties of the underfill material 49 of the first embodiment.
  • the graph in FIG. 11 shows the temperature dependence of Young's modulus of the underfill material 49.
  • the Young's modulus of the underfill material 49 changes greatly depending on the glass transition temperature Tg of the underfill material 49. Therefore, the glass dislocation temperature Tg of the underfill material 49 is considered to be a parameter that affects the magnitude of the stress applied to the light emitting element 53 and the like.
  • FIG. 12 is a graph showing the properties of the solder 48 in the light emitting device 1 of the first embodiment.
  • the horizontal axis of FIG. 12 shows the distortion of the solder 48 provided between the electrode 54 and the connection pad 62 and surrounded by the underfill material 49.
  • the solder 48 used in FIG. 12 is a Sn—Ag—Cu based alloy and has a melting point of about 220 ° C.
  • the composition ratios of Sn, Ag, and Cu of the solder 48 are 96.5%, 3.0%, and 0.5%, respectively.
  • the vertical axis of FIG. 12 shows the stress applied to the light emitting element 53.
  • FIG. 12 shows the relationship between the strain of the solder 48 and the stress applied to the light emitting element 53 at various temperatures of the underfill material 49. Specifically, the above relationship at 15 ° C., 25 ° C., 100 ° C., 175 ° C., 230 ° C., and 300 ° C. is shown. It should be noted that since the melting point of the solder 48 is about 220 ° C., the curve at 230 ° C. and the curve at 300 ° C. are almost the same.
  • the stress applied to the light emitting element 53 changes depending on the temperature of the underfill material 49. Therefore, in order to reduce the stress applied to the light emitting element 53, it is desirable to pay attention to the temperature of the underfill material 49.
  • FIG. 13 is another graph showing the properties of the underfill material 49 of the first embodiment.
  • FIG. 13A shows the result of calculating the stress (maximum principal stress) applied to the light emitting element 53 after the joining process and the UF process are completed by computer simulation.
  • the melting point of the solder 48 in this case is 220 ° C.
  • FIG. 13A shows changes in stress when the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the underfill material 49 are set to various temperatures. From this result, it can be seen that the stress can be reduced by setting the glass dislocation temperature Tg [° C.] and the curing temperature Tp [° C.] to predetermined temperatures.
  • the stress applied to the light emitting element 53 be as low as possible.
  • the maximum principal stress applied to the light emitting element 53 after the joining step or the UF step is completed is 150 MPa or less. This makes it possible to suppress deterioration in the performance of the light emitting device 1 due to the stress applied to the light emitting element 53.
  • a in FIG. 13 shows a region R in which the stress applied to the light emitting element 53 is low.
  • the region R is sandwiched between the straight line L1 and the straight line L2.
  • This equation corresponds to the above equation (1).
  • the stress applied to the light emitting element 53 is reduced by using the underfill material 49 having the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] satisfying the relationship of the formula (1). Is possible. It should be noted that in the region R of A shown in FIG. 13, the maximum principal stress is approximately 150 MPa or less.
  • FIG. 13 also shows the result of calculating the stress (maximum principal stress) applied to the light emitting element 53 after the joining process and the UF process are completed by computer simulation.
  • the melting point of the solder 48 in this case is 170 ° C.
  • FIG. 13 also shows the region R sandwiched between the straight line L1 and the straight line L2.
  • the distribution of the maximum principal stress in the region R shown in FIG. 13B is slightly different from the distribution of the maximum principal stress in the region R shown in FIG. 13A.
  • the maximum principal stress applied to the light emitting element 53 is low not only in the region R shown in FIG. 13A but also in the region R shown in FIG. 13B. From this, it can be seen that the underfill material 49 satisfying the relationship of the formula (1) is useful not only when the melting point of the solder 48 is 220 ° C. but also when the melting point of the solder 48 is 170 ° C.
  • the melting point of the solder 48 used in the light emitting device 1 of the present embodiment is often about 170 ° C to 220 ° C.
  • the underfill material 49 satisfying the relationship of the formula (1) is useful when solder 48 having various melting points is used, for example, from 170 ° C. to It turns out to be beneficial when using a solder 48 having a melting point of 220 ° C. Therefore, according to the present embodiment, by using the underfill material 49 satisfying the relationship of the formula (1), it is possible to reduce the stress applied to the light emitting element 53 when various types of solder 48 are used. It will be possible.
  • the stress applied to the light emitting element 53 may remain in the finished product of the light emitting device 1. In this case, such stress may accelerate the aged deterioration of the light emitting element 53.
  • the underfill material 49 satisfying the relationship of the formula (1) it is possible to reduce the stress remaining in the finished product of the light emitting device 1.
  • the maximum principal stress applied to the light emitting element 53 in the finished product of the light emitting device 1 can be set to 150 MPa or less. This makes it possible to suppress aged deterioration of the light emitting element 53 due to stress.
  • FIG. 14 is another graph showing the properties of the underfill material 49 of the first embodiment.
  • a of FIG. 14 shows a simulation result when a solder 48 having a melting point of 220 ° C. is used, similarly to A of FIG. A in FIG. 14 shows a region R1 and a region R2 obtained by dividing the region R.
  • the region R1 is located above the straight line L3, and the region R2 is located below the straight line L3.
  • the underfill material 49 having a glass transition temperature Tg [° C.] and a curing temperature Tp [° C.] satisfying the relationship of the formulas (1) and (2), the light emitting element 53 can be used. It is possible to further reduce the applied stress.
  • B in FIG. 14 shows the simulation result when solder 48 having a melting point of 170 ° C. is used, similarly to B in FIG. B in FIG. 14 also shows a region R1 and a region R2 obtained by dividing the region R.
  • the maximum principal stress applied to the light emitting element 53 is low not only in the region R1 shown in FIG. 14A but also in the region R1 shown in FIG. 14B. From this, the underfill material 49 satisfying the relationship of the formulas (1) and (2) is useful not only when the melting point of the solder 48 is 220 ° C. but also when the melting point of the solder 48 is 170 ° C. I understand.
  • the underfill material 49 satisfying the relationship of the equation (1) and the equation (2) the stress applied to the light emitting element 53 when various types of solder 48 are used. Can be further reduced. Further, according to the present embodiment, by using the underfill material 49 satisfying the relationship of the formula (1) and the formula (2), it is possible to further reduce the stress remaining in the finished product of the light emitting device 1. It becomes.
  • the underfill material 49 of the present embodiment is a thermosetting resin such as an acrylic resin.
  • the underfill material 49 satisfying the relationship of the formula (1) can be realized, for example, by adjusting the components and additives of the acrylic resin.
  • the underfill material 49 satisfying the relationship of the formula (1) and the formula (2) can be realized by adjusting, for example, the components and additives of the acrylic resin.
  • By adjusting the components and additives of the acrylic resin it is possible to adjust the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the underfill material 49.
  • FIG. 15 is a cross-sectional view showing the structure of the light emitting device 1 of the modified example of the first embodiment.
  • the light emitting device 1 of this modification includes a plurality of lenses 56 in addition to the same components as the light emitting device 1 of the first embodiment.
  • the LD chip 41 is provided with a plurality of light emitting elements 53 on the front surface S1 of the substrate 51, and these lenses 56 are provided on the back surface S2 of the substrate 51.
  • the lens 56 of this modification has a one-to-one correspondence with the light emitting element 53, and each of the lenses 56 is arranged in the + Z direction of one light emitting element 53.
  • the lens 56 of this modification is provided on the back surface S2 of the substrate 51 as a part of the substrate 51.
  • the lens 56 of this modification is a concave lens, and is formed as a part of the substrate 51 by etching the back surface S2 of the substrate 51 into a concave shape.
  • the lens 56 of this modification may be a lens other than a concave lens (for example, a convex lens).
  • the light emitted from the plurality of light emitting elements 53 is transmitted from the front surface S1 to the back surface S2 in the substrate 51 and is incident on the plurality of lenses 56. As shown in FIG. 15, the light emitted from each light emitting element 53 is incident on one corresponding lens 56. As a result, the light emitted from each light emitting element 53 can be formed into a suitable shape by the corresponding lens 56.
  • the light that has passed through the lens 56 of this modification passes through the correction lens 46 (FIG. 2) and is applied to the subject (FIG. 1).
  • the light emitting device 1 of this modification can be manufactured by, for example, the methods shown in FIGS. 4 and 5.
  • the lens 56 is formed on the substrate 51 after the step shown in FIG. 5B.
  • the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the underfill material 49 of the present embodiment satisfy the relationship of 80 ⁇ Tp ⁇ (Tg + 115) /1.5. Therefore, according to the present embodiment, it is possible to reduce the stress applied to the constituent portion (for example, the light emitting element 53) of the light emitting device 1 provided between the substrate 51 and the substrate 56, which is caused by the underfill material 49. It is possible to suppress the deterioration of the performance of the light emitting device 1.
  • the glass transition temperature Tg [° C.] of the underfill material 49 of the present embodiment further satisfies the relationship of Tg ⁇ 90. This makes it possible to further suppress the deterioration of the performance of the light emitting device 1 due to the underfill material 49.
  • the light emitting device 1 of the present embodiment is used as a light source of the distance measuring device, it may be used in other embodiments.
  • the light emitting device 1 of the present embodiment may be used as a light source for an optical device such as a printer, or may be used as a lighting device.
  • the underfill material 49 of the present embodiment may be used for a semiconductor device other than the light emitting device 1 or a component portion of the semiconductor device other than the light emitting device 53.
  • the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin are 80 ⁇ Tp ⁇ (Tg + 115) /1.5 A semiconductor device that satisfies the relationship.
  • the glass transition temperature Tg [° C.] of the filling resin is Tg ⁇ 90
  • the semiconductor device according to (1) which satisfies the above relationship.
  • the semiconductor device wherein the first substrate is a semiconductor substrate containing gallium (Ga) and arsenic (As).
  • a plurality of protrusions protruding from the first surface of the first substrate are further provided.
  • connection portion includes solder or bumps.
  • the semiconductor device according to (8) further comprising a plurality of lenses provided as a part of the first substrate on the second surface of the first substrate.
  • the first substrate and the second substrate are arranged so as to face each other.
  • a filling resin is formed between the first substrate and the second substrate. Including that The glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin are 80 ⁇ Tp ⁇ (Tg + 115) /1.5 A method for manufacturing a semiconductor device that satisfies the above relationship.
  • the glass transition temperature Tg [° C.] of the filling resin is Tg ⁇ 90
  • thermosetting the filling resin between the first substrate and the second substrate Further comprising thermosetting the filling resin between the first substrate and the second substrate.
  • the protrusion includes a connection portion that electrically connects the first substrate side and the second substrate side.
  • connection portion By supplying the material of the connection portion between the first substrate and the second substrate and melting it by heating, the first substrate side and the second substrate side are electrically connected by the connection portion.
  • the glass transition temperature Tg [° C] and the curing temperature Tp [° C] are 80 ⁇ Tp ⁇ (Tg + 115) /1.5 Filling resin that satisfies the relationship.
  • the glass transition temperature Tg [° C.] is Tg ⁇ 90

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Abstract

[Problem] To provide a semiconductor device capable of suppressing reduction in performance of the semiconductor device caused by a filling resin. [Solution] A semiconductor device according to the present disclosure is provided with: a first substrate; a second substrate electrically connected to the first substrate; and a filling resin provided between the first and second substrates. The glass transition temperature Tg[°C] and the curing temperature Tp[°C] of the filling resin satisfies the relationship of 80≤Tp≤(Tg+115)/1.5.

Description

半導体装置、半導体装置の製造方法、および充填樹脂Semiconductor devices, semiconductor device manufacturing methods, and filling resins
　本開示は、半導体装置、半導体装置の製造方法、および充填樹脂に関する。 The present disclosure relates to semiconductor devices, methods for manufacturing semiconductor devices, and filling resins.
　発光装置などの半導体装置を製造する際、半導体装置の構成部分（例えば、発光素子や接続部）を２枚の基板間に配置し、これらの基板間にアンダーフィル材と呼ばれる充填樹脂を充填することが考えられる。これにより、この構成部分を異物から保護することや、この構成部分を構造的に補強することが可能となる。 When manufacturing a semiconductor device such as a light emitting device, a component portion of the semiconductor device (for example, a light emitting element or a connection portion) is arranged between two substrates, and a filling resin called an underfill material is filled between these substrates. Can be considered. This makes it possible to protect this component from foreign matter and to structurally reinforce this component.
特開２０１１－１９９０９７号公報Japanese Unexamined Patent Publication No. 2011-199097 特開２００１－３１３３１４号公報Japanese Unexamined Patent Publication No. 2001-313314
　上記の接続部は、例えば半田である。この場合、基板同士を半田で接合するために、半田の温度をその融点まで上昇させる必要がある。また、上記の充填樹脂は、例えば熱硬化樹脂である。この場合、熱硬化樹脂を硬化させるために、熱硬化樹脂を高温に加熱する必要がある。 The above connection part is, for example, solder. In this case, in order to bond the substrates with solder, it is necessary to raise the temperature of the solder to its melting point. Further, the filling resin described above is, for example, a thermosetting resin. In this case, in order to cure the thermosetting resin, it is necessary to heat the thermosetting resin to a high temperature.
　このように、上記の半導体装置を製造する際には、基板同士の接合や充填樹脂の硬化のために、半導体装置が高温に加熱される場合がある。この場合、これらの基板が異なる線膨張係数を有していると、上記の発光素子などに大きな応力が掛かり、半導体装置の信頼性が損なわれるおそれや、半導体装置にクラックが入って割れるおそれがある。 As described above, when manufacturing the above-mentioned semiconductor device, the semiconductor device may be heated to a high temperature due to the bonding between the substrates and the curing of the filling resin. In this case, if these substrates have different coefficient of linear expansion, a large stress is applied to the above-mentioned light emitting element or the like, which may impair the reliability of the semiconductor device or may cause the semiconductor device to crack and crack. be.
　これらの問題を解決するために、充填樹脂の粘度に着目することや、基板の線膨張係数に着目することが知られているが、より効果的な指標が求められている。 In order to solve these problems, it is known to pay attention to the viscosity of the filling resin and the coefficient of linear expansion of the substrate, but a more effective index is required.
　そこで、本開示は、充填樹脂に起因する半導体装置の性能の低下を抑制することが可能な半導体装置、半導体装置の製造方法、および充填樹脂を提供する。 Therefore, the present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and a filling resin capable of suppressing deterioration of the performance of the semiconductor device due to the filling resin.
　本開示の第１の側面の半導体装置は、第１基板と、前記第１基板に対向している第２基板と、前記第１基板と前記第２基板との間に設けられた充填樹脂とを備え、前記充填樹脂のガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］は、８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５の関係を満たす。これにより例えば、これらの基板間の構成部分に掛かる応力を低減することが可能となり、充填樹脂に起因する半導体装置の性能の低下を抑制することが可能となる。 The semiconductor device on the first side surface of the present disclosure includes a first substrate, a second substrate facing the first substrate, and a filling resin provided between the first substrate and the second substrate. The glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin satisfy the relationship of 80 ≦ Tp ≦ (Tg + 115) /1.5. As a result, for example, it is possible to reduce the stress applied to the constituent portions between these substrates, and it is possible to suppress the deterioration of the performance of the semiconductor device due to the filling resin.
　また、この第１の側面において、前記充填樹脂の前記ガラス転移温度Ｔｇ［℃］は、Ｔｇ≧９０の関係を満たしていてもよい。これにより例えば、これらの基板間の構成部分に掛かる応力をさらに低減することが可能となり、充填樹脂に起因する半導体装置の性能の低下をさらに抑制することが可能となる。 Further, in this first aspect, the glass transition temperature Tg [° C.] of the filling resin may satisfy the relationship of Tg ≧ 90. As a result, for example, it is possible to further reduce the stress applied to the constituent portions between these substrates, and it is possible to further suppress the deterioration of the performance of the semiconductor device due to the filling resin.
　また、この第１の側面において、前記充填樹脂は、アクリル系樹脂でもよい。これにより例えば、８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５の関係を満たす充填樹脂を提供することが可能となる。 Further, in this first aspect, the filling resin may be an acrylic resin. This makes it possible to provide, for example, a filling resin satisfying the relationship of 80 ≦ Tp ≦ (Tg + 115) /1.5.
　また、この第１の側面において、前記第１基板と前記第２基板は、異なる線膨張係数を有していてもよい。これにより例えば、上記の充填樹脂を使用することで、これらの基板の線膨張係数の差に起因する半導体装置の性能の低下を抑制することが可能となる。 Further, in this first aspect, the first substrate and the second substrate may have different coefficient of linear expansion. Thereby, for example, by using the above-mentioned filling resin, it is possible to suppress the deterioration of the performance of the semiconductor device due to the difference in the linear expansion coefficients of these substrates.
　また、この第１の側面において、前記第１基板と前記第２基板の前記線膨張係数の差は、２．０×１０－６［１／Ｋ］以上でもよい。これにより例えば、上記の充填樹脂を使用することで、これらの基板の線膨張係数の差が大きい場合でも半導体装置の性能の低下を抑制することが可能となる。 Further, on this first aspect, the difference in the coefficient of linear expansion between the first substrate and the second substrate may be 2.0 × 10 -6 [1 / K] or more. Thereby, for example, by using the above-mentioned filling resin, it is possible to suppress the deterioration of the performance of the semiconductor device even when the difference in the linear expansion coefficients of these substrates is large.
　また、この第１の側面において、前記第１基板は、ガリウム（Ｇａ）およびヒ素（Ａｓ）を含む半導体基板でもよい。これにより例えば、ＧａＡｓ基板を用いて発光装置を製造する場合に、充填樹脂に起因する発光装置の性能の低下を抑制することが可能となる。 Further, in this first aspect, the first substrate may be a semiconductor substrate containing gallium (Ga) and arsenic (As). This makes it possible to suppress the deterioration of the performance of the light emitting device due to the filling resin, for example, when the light emitting device is manufactured using the GaAs substrate.
　また、この第１の側面において、前記第２基板は、シリコン（Ｓｉ）を含む半導体基板でもよい。これにより例えば、これにより例えば、Ｓｉ基板とＳｉ基板以外の基板（例えばＧａＡｓ基板）とを用いて発光装置を製造する際に、充填樹脂に起因する発光装置の性能の低下を抑制することが可能となる。 Further, in the first aspect, the second substrate may be a semiconductor substrate containing silicon (Si). Thereby, for example, when manufacturing a light emitting device using a Si substrate and a substrate other than the Si substrate (for example, a GaAs substrate), it is possible to suppress deterioration of the performance of the light emitting device due to the filling resin. Will be.
　また、この第１の側面の半導体装置は、前記第１基板の第１面に対して突出した複数の突出部をさらに備え、前記第２基板は、前記第１基板の前記第１面に対向していてもよい。これにより例えば、上記の充填樹脂を使用することで、突出部に掛かる応力を低減することが可能となる。 Further, the semiconductor device on the first side surface further includes a plurality of protrusions protruding from the first surface of the first substrate, and the second substrate faces the first surface of the first substrate. You may be doing it. As a result, for example, by using the above-mentioned filling resin, it is possible to reduce the stress applied to the protruding portion.
　また、この第１の側面において、前記突出部は、前記第１基板の前記第１面から第２面に光を出射する発光素子を含んでいてもよい。これにより例えば、発光素子に掛かる応力を低減することが可能となり、発光素子の性能の低下を抑制することが可能となる。 Further, on the first side surface, the protruding portion may include a light emitting element that emits light from the first surface to the second surface of the first substrate. As a result, for example, it is possible to reduce the stress applied to the light emitting element, and it is possible to suppress the deterioration of the performance of the light emitting element.
　また、この第１の側面において、前記突出部は、前記第１基板側と前記第２基板側とを電気的に接続する接続部を含んでいてもよい。これにより例えば、上記のような好適な充填樹脂で接続部を保護することが可能となる。 Further, on the first side surface, the protruding portion may include a connecting portion that electrically connects the first substrate side and the second substrate side. This makes it possible, for example, to protect the connection portion with a suitable filling resin as described above.
　また、この第１の側面において、前記接続部は、半田またはバンプを含んでいてもよい。これにより例えば、基板同士を半田接続またはバンプ接続する場合に、上記のような好適な充填樹脂で接続部を保護することが可能となる。 Further, in this first aspect, the connection portion may include solder or bumps. This makes it possible to protect the connection portion with the above-mentioned suitable filling resin, for example, when the substrates are solder-connected or bump-connected.
　また、この第１の側面の半導体装置は、前記第１基板の第２面に、前記第１基板の一部として設けられた複数のレンズをさらに備えていてもよい。これにより例えば、第１基板がレンズ用の基板である場合にも、突出部に掛かる応力を低減することが可能となる。 Further, the semiconductor device on the first side surface may further include a plurality of lenses provided as a part of the first substrate on the second surface of the first substrate. As a result, for example, even when the first substrate is a substrate for a lens, it is possible to reduce the stress applied to the protruding portion.
　本開示の第２の側面の半導体装置の製造方法は、第１基板と第２基板とを互いに対向するように配置し、前記第１基板と前記第２基板との間に充填樹脂を形成することを含み、前記充填樹脂のガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］は、８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５の関係を満たす。これにより例えば、これらの基板間の構成部分に掛かる応力を低減することが可能となり、充填樹脂に起因する半導体装置の性能の低下を抑制することが可能となる。 In the method for manufacturing a semiconductor device on the second side of the present disclosure, the first substrate and the second substrate are arranged so as to face each other, and a filling resin is formed between the first substrate and the second substrate. The glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin satisfy the relationship of 80 ≦ Tp ≦ (Tg + 115) /1.5. As a result, for example, it is possible to reduce the stress applied to the constituent portions between these substrates, and it is possible to suppress the deterioration of the performance of the semiconductor device due to the filling resin.
　また、この第２の側面において、前記充填樹脂の前記ガラス転移温度Ｔｇ［℃］は、Ｔｇ≧９０の関係を満たしてもよい。これにより例えば、これらの基板間の構成部分に掛かる応力をさらに低減することが可能となり、充填樹脂に起因する半導体装置の性能の低下をさらに抑制することが可能となる。 Further, in this second aspect, the glass transition temperature Tg [° C.] of the filling resin may satisfy the relationship of Tg ≧ 90. As a result, for example, it is possible to further reduce the stress applied to the constituent portions between these substrates, and it is possible to further suppress the deterioration of the performance of the semiconductor device due to the filling resin.
　また、この第２の側面の半導体装置の製造方法は、前記第１基板と前記第２基板との間の前記充填樹脂を熱硬化させることをさらに含み、前記充填樹脂は、１７０～２２０℃で熱硬化されてもよい。これにより例えば、充填樹脂が熱硬化のために加熱される場合でも、充填樹脂に起因する半導体装置の性能の低下を抑制することが可能となる。 Further, the method for manufacturing the semiconductor device on the second side surface further includes thermosetting the filling resin between the first substrate and the second substrate, and the filling resin is heated at 170 to 220 ° C. It may be thermoset. This makes it possible to suppress deterioration of the performance of the semiconductor device due to the filling resin, for example, even when the filling resin is heated for thermosetting.
　また、この第２の側面の半導体装置の製造方法は、前記第１基板の第１面に対して突出した複数の突出部を形成することをさらに含み、前記第２基板は、前記第１基板の前記第１面に対向するように配置されてもよい。これにより例えば、上記の充填樹脂を使用することで、突出部に掛かる応力を低減することが可能となる。 Further, the method for manufacturing a semiconductor device on the second side surface further includes forming a plurality of protrusions protruding from the first surface of the first substrate, and the second substrate is the first substrate. It may be arranged so as to face the first surface of the above. As a result, for example, by using the above-mentioned filling resin, it is possible to reduce the stress applied to the protruding portion.
　また、この第２の側面の半導体装置の製造方法は、前記突出部に掛かる最大主応力は、１５０ＭＰａ以下でもよい。これにより例えば、突出部に掛かる応力に起因する半導体装置の性能の低下を抑制することが可能となる。 Further, in the method for manufacturing the semiconductor device on the second side surface, the maximum principal stress applied to the protrusion may be 150 MPa or less. This makes it possible to suppress deterioration in the performance of the semiconductor device due to, for example, the stress applied to the protrusion.
　また、この第２の側面において、前記突出部は、前記第１基板側と前記第２基板側とを電気的に接続する接続部を含み、前記接続部の材料を前記第１基板と前記第２基板との間に供給して加熱により溶融させることで、前記第１基板側と前記第２基板側とを前記接続部により電気的に接続することをさらに含んでいてもよい。これにより例えば、基板同士を接続するために接続部の材料が加熱される場合でも、充填樹脂に起因する半導体装置の性能の低下を抑制することが可能となる。 Further, on the second side surface, the protruding portion includes a connecting portion that electrically connects the first substrate side and the second substrate side, and the material of the connecting portion is the material of the first substrate and the second substrate. It may further include electrically connecting the first substrate side and the second substrate side by the connecting portion by supplying the two substrates and melting them by heating. As a result, for example, even when the material of the connecting portion is heated to connect the substrates to each other, it is possible to suppress the deterioration of the performance of the semiconductor device due to the filling resin.
　本開示の第３の側面の充填樹脂は、ガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］が、８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５の関係を満たす。これにより例えば、半導体装置の基板間に充填樹脂を形成する場合に、充填樹脂に起因する半導体装置の性能の低下を抑制することが可能となる。 In the filling resin on the third side surface of the present disclosure, the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] satisfy the relationship of 80 ≦ Tp ≦ (Tg + 115) /1.5. This makes it possible to suppress deterioration of the performance of the semiconductor device due to the filling resin, for example, when the filling resin is formed between the substrates of the semiconductor device.
　また、この第３の側面の充填樹脂は、前記ガラス転移温度Ｔｇ［℃］が、Ｔｇ≧９０の関係を満たす。半導体装置の基板間に充填樹脂を形成する場合に、充填樹脂に起因する半導体装置の性能の低下をさらに抑制することが可能となる。 Further, in the filling resin on the third side surface, the glass transition temperature Tg [° C.] satisfies the relationship of Tg ≧ 90. When the filling resin is formed between the substrates of the semiconductor device, it is possible to further suppress the deterioration of the performance of the semiconductor device due to the filling resin.
第１実施形態の測距装置の構成を示すブロック図である。It is a block diagram which shows the structure of the distance measuring apparatus of 1st Embodiment. 第１実施形態の発光装置の構造の例を示す断面図である。It is sectional drawing which shows the example of the structure of the light emitting device of 1st Embodiment. 図２のＢに示す発光装置の構造を示す断面図、平面図および斜視図である。2 is a cross-sectional view, a plan view, and a perspective view showing the structure of the light emitting device shown in FIG. 2B. 第１実施形態の発光装置の製造方法を示す断面図(1/2)である。It is sectional drawing (1/2) which shows the manufacturing method of the light emitting device of 1st Embodiment. 第１実施形態の発光装置の製造方法を示す断面図(2/2)である。It is sectional drawing (2/2) which shows the manufacturing method of the light emitting device of 1st Embodiment. 第１実施形態の発光装置の製造方法の詳細を示す断面図(1/4)である。It is sectional drawing (1/4) which shows the detail of the manufacturing method of the light emitting device of 1st Embodiment. 第１実施形態の発光装置の製造方法の詳細を示す断面図(2/4)である。It is sectional drawing (2/4) which shows the detail of the manufacturing method of the light emitting device of 1st Embodiment. 第１実施形態の発光装置の製造方法の詳細を示す断面図(3/4)である。It is sectional drawing (3/4) which shows the detail of the manufacturing method of the light emitting device of 1st Embodiment. 第１実施形態の発光装置の製造方法の詳細を示す断面図(4/4)である。It is sectional drawing (4/4) which shows the detail of the manufacturing method of the light emitting device of 1st Embodiment. 第１実施形態の発光装置の製造方法を説明するためのグラフである。It is a graph for demonstrating the manufacturing method of the light emitting device of 1st Embodiment. 第１実施形態のアンダーフィル材の性質を示すグラフである。It is a graph which shows the property of the underfill material of 1st Embodiment. 第１実施形態の発光装置内の半田の性質を示すグラフである。It is a graph which shows the property of the solder in the light emitting device of 1st Embodiment. 第１実施形態のアンダーフィル材の性質を示す別のグラフである。It is another graph which shows the property of the underfill material of 1st Embodiment. 第１実施形態のアンダーフィル材の性質を示す別のグラフである。It is another graph which shows the property of the underfill material of 1st Embodiment. 第１実施形態の変形例の発光装置の構造を示す断面図である。It is sectional drawing which shows the structure of the light emitting device of the modification of 1st Embodiment.
　以下、本開示の実施形態を、図面を参照して説明する。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
　（第１実施形態）
　図１は、第１実施形態の測距装置の構成を示すブロック図である。 (First Embodiment)
FIG. 1 is a block diagram showing a configuration of a distance measuring device according to a first embodiment.
　図１の測距装置は、発光装置１と、撮像装置２と、制御装置３とを備えている。図１の測距装置は、発光装置１から発光された光を被写体に照射する。撮像装置２は、被写体で反射した光を受光して被写体を撮像する。制御装置３は、撮像装置２から出力された画像信号を用いて被写体までの距離を測定（算出）する。発光装置１は、撮像装置２が被写体を撮像するための光源として機能する。 The distance measuring device of FIG. 1 includes a light emitting device 1, an image pickup device 2, and a control device 3. The distance measuring device of FIG. 1 irradiates the subject with the light emitted from the light emitting device 1. The image pickup apparatus 2 receives the light reflected by the subject and images the subject. The control device 3 measures (calculates) the distance to the subject using the image signal output from the image pickup device 2. The light emitting device 1 functions as a light source for the image pickup device 2 to take an image of a subject.
　発光装置１は、発光部１１と、駆動回路１２と、電源回路１３と、発光側光学系１４とを備えている。撮像装置２は、イメージセンサ２１と、画像処理部２２と、撮像側光学系２３とを備えている。制御装置３は、測距部３１を備えている。 The light emitting device 1 includes a light emitting unit 11, a drive circuit 12, a power supply circuit 13, and a light emitting side optical system 14. The image pickup apparatus 2 includes an image sensor 21, an image processing unit 22, and an image pickup side optical system 23. The control device 3 includes a ranging unit 31.
　発光部１１は、被写体に照射するためのレーザー光を発光する。本実施形態の発光部１１は、後述するように、２次元アレイ状に配置された複数の発光素子を備え、各発光素子は、ＶＣＳＥＬ（Vertical Cavity Surface Emitting Laser）構造を有している。これらの発光素子から出射された光が、被写体に照射される。本実施形態の発光部１１は、図１に示すように、ＬＤ（Laser Diode）チップ４１と呼ばれるチップ内に設けられている。 The light emitting unit 11 emits a laser beam for irradiating the subject. As will be described later, the light emitting unit 11 of the present embodiment includes a plurality of light emitting elements arranged in a two-dimensional array, and each light emitting element has a VCSEL (Vertical Cavity Surface Emitting Laser) structure. The light emitted from these light emitting elements irradiates the subject. As shown in FIG. 1, the light emitting unit 11 of the present embodiment is provided in a chip called an LD (Laser Diode) chip 41.
　駆動回路１２は、発光部１１を駆動する電気回路である。電源回路１３は、駆動回路１２の電源電圧を生成する電気回路である。図１の測距装置では例えば、電源回路１３が、測距装置内のバッテリから供給される入力電圧から電源電圧を生成し、駆動回路１２が、この電源電圧を用いて発光部１１を駆動する。本実施形態の駆動回路１２は、図１に示すように、ＬＤＤ（Laser Diode Driver）基板４２と呼ばれる基板内に設けられている。 The drive circuit 12 is an electric circuit that drives the light emitting unit 11. The power supply circuit 13 is an electric circuit that generates a power supply voltage of the drive circuit 12. In the distance measuring device of FIG. 1, for example, the power supply circuit 13 generates a power supply voltage from the input voltage supplied from the battery in the distance measuring device, and the drive circuit 12 drives the light emitting unit 11 using this power supply voltage. .. As shown in FIG. 1, the drive circuit 12 of the present embodiment is provided in a substrate called an LDD (Laser Diode Driver) substrate 42.
　発光側光学系１４は、種々の光学素子を備えており、これらの光学素子を介して発光部１１からの光を被写体に照射する。同様に、撮像側光学系２３は、種々の光学素子を備えており、これらの光学素子を介して被写体からの光を受光する。 The light emitting side optical system 14 includes various optical elements, and irradiates the subject with light from the light emitting unit 11 via these optical elements. Similarly, the image pickup side optical system 23 includes various optical elements, and receives light from the subject through these optical elements.
　イメージセンサ２１は、被写体からの光を撮像側光学系２３を介して受光し、この光を光電変換により電気信号に変換する。イメージセンサ２１は例えば、ＣＣＤ（Charge Coupled Device）センサまたはＣＭＯＳ（Complementary Metal Oxide Semiconductor）センサである。本実施形態のイメージセンサ２１は、上記の電子信号をＡ／Ｄ（Analog to Digital）変換によりアナログ信号からデジタル信号に変換し、デジタル信号としての画像信号を画像処理部２２に出力する。また、本実施形態のイメージセンサ２１は、フレーム同期信号を駆動回路１２に出力し、駆動回路１２は、フレーム同期信号に基づいて、発光部１１をイメージセンサ２１におけるフレーム周期に応じたタイミングで発光させる。 The image sensor 21 receives light from the subject via the image pickup side optical system 23, and converts this light into an electric signal by photoelectric conversion. The image sensor 21 is, for example, a CCD (Charge Coupled Device) sensor or a CMOS (Complementary Metal Oxide Semiconductor) sensor. The image sensor 21 of the present embodiment converts the above electronic signal from an analog signal to a digital signal by A / D (Analog to Digital) conversion, and outputs an image signal as a digital signal to the image processing unit 22. Further, the image sensor 21 of the present embodiment outputs a frame synchronization signal to the drive circuit 12, and the drive circuit 12 emits light from the light emitting unit 11 at a timing corresponding to the frame cycle of the image sensor 21 based on the frame synchronization signal. Let me.
　画像処理部２２は、イメージセンサ２１から出力された画像信号に対し種々の画像処理を施す。画像処理部２２は例えば、ＤＳＰ（Digital Signal Processor）などの画像処理プロセッサを備えている。 The image processing unit 22 performs various image processing on the image signal output from the image sensor 21. The image processing unit 22 includes, for example, an image processing processor such as a DSP (Digital Signal Processor).
　制御装置３は、図１の測距装置の種々の動作を制御し、例えば、発光装置１の発光動作や、撮像装置２の撮像動作を制御する。制御装置３は例えば、ＣＰＵ（Central Processing Unit）、ＲＯＭ（Read Only Memory）、ＲＡＭ（Random Access Memory）などを備えている。 The control device 3 controls various operations of the distance measuring device of FIG. 1, for example, controlling the light emitting operation of the light emitting device 1 and the imaging operation of the image pickup device 2. The control device 3 includes, for example, a CPU (Central Processing Unit), a ROM (ReadOnlyMemory), a RAM (RandomAccessMemory), and the like.
　測距部３１は、イメージセンサ２１から出力されて、画像処理部２２により画像処理を施された画像信号に基づいて、被写体までの距離を測定する。測距部３１は、測距方式として例えば、ＳＴＬ（Structured Light）方式またはＴｏＦ（Time of Flight）方式を採用している。測距部３１はさらに、上記の画像信号に基づいて、測距装置と被写体との距離を被写体の部分ごとに測定して、被写体の３次元形状を特定してもよい。 The distance measuring unit 31 measures the distance to the subject based on the image signal output from the image sensor 21 and subjected to image processing by the image processing unit 22. The distance measuring unit 31 employs, for example, an STL (Structured Light) method or a ToF (Time of Flight) method as the distance measuring method. The distance measuring unit 31 may further measure the distance between the distance measuring device and the subject for each portion of the subject based on the above image signal to specify the three-dimensional shape of the subject.
　図２は、第１実施形態の発光装置１の構造の例を示す断面図である。発光装置１は、本開示の半導体装置の例である。 FIG. 2 is a cross-sectional view showing an example of the structure of the light emitting device 1 of the first embodiment. The light emitting device 1 is an example of the semiconductor device of the present disclosure.
　図２のＡは、本実施形態の発光装置１の構造の第１の例を示している。この例の発光装置１は、上述のＬＤチップ４１およびＬＤＤ基板４２と、実装基板４３と、放熱基板４４と、補正レンズ保持部４５と、１つ以上の補正レンズ４６と、配線４７とを備えている。 A in FIG. 2 shows a first example of the structure of the light emitting device 1 of the present embodiment. The light emitting device 1 of this example includes the above-mentioned LD chip 41 and LDD substrate 42, a mounting substrate 43, a heat radiating substrate 44, a correction lens holding portion 45, one or more correction lenses 46, and a wiring 47. ing.
　図２のＡは、互いに垂直なＸ軸、Ｙ軸、およびＺ軸を示している。Ｘ方向とＹ方向は横方向（水平方向）に相当し、Ｚ方向は縦方向（垂直方向）に相当する。また、＋Ｚ方向は上方向に相当し、－Ｚ方向は下方向に相当する。－Ｚ方向は、厳密に重力方向に一致していてもよいし、厳密には重力方向に一致していなくてもよい。 A in FIG. 2 shows an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other. The X and Y directions correspond to the horizontal direction (horizontal direction), and the Z direction corresponds to the vertical direction (vertical direction). Further, the + Z direction corresponds to the upward direction, and the −Z direction corresponds to the downward direction. The −Z direction may or may not exactly coincide with the direction of gravity.
　ＬＤチップ４１は、放熱基板４４を介して実装基板４３上に配置され、ＬＤＤ基板４２も、実装基板４３上に配置されている。実装基板４３は、例えばプリント基板である。本実施形態の実装基板４３には、図１のイメージセンサ２１や画像処理部２２も配置されている。放熱基板４４は例えば、Ａｌ２Ｏ３（酸化アルミニウム）基板やＡｌＮ（窒化アルミニウム）基板などのセラミック基板である。 The LD chip 41 is arranged on the mounting board 43 via the heat radiating board 44, and the LDD board 42 is also arranged on the mounting board 43. The mounting board 43 is, for example, a printed circuit board. The image sensor 21 and the image processing unit 22 of FIG. 1 are also arranged on the mounting board 43 of the present embodiment. The heat dissipation substrate 44 is, for example, a ceramic substrate such as an Al 2 O 3 (aluminum oxide) substrate or an AlN (aluminum nitride) substrate.
　補正レンズ保持部４５は、ＬＤチップ４１を囲むように放熱基板４４上に配置されており、ＬＤチップ４１の上方に１つ以上の補正レンズ４６を保持している。これらの補正レンズ４６は、上述の発光側光学系１４（図１）に含まれている。ＬＤチップ４１内の発光部１１（図１）から発光された光は、これらの補正レンズ４６により補正された後、被写体（図１）に照射される。図２のＡは、一例として、補正レンズ保持部４５に保持された２つの補正レンズ４６を示している。 The correction lens holding portion 45 is arranged on the heat radiating substrate 44 so as to surround the LD chip 41, and holds one or more correction lenses 46 above the LD chip 41. These correction lenses 46 are included in the light emitting side optical system 14 (FIG. 1) described above. The light emitted from the light emitting unit 11 (FIG. 1) in the LD chip 41 is corrected by these correction lenses 46 and then irradiated to the subject (FIG. 1). As an example, A in FIG. 2 shows two correction lenses 46 held by the correction lens holding portion 45.
　配線４７は、実装基板４３の表面、裏面、内部などに設けられており、ＬＤチップ４１とＬＤＤ基板４２とを電気的に接続している。配線４７は例えば、実装基板４３の表面や裏面に設けられたプリント配線や、実装基板４３を貫通するビア配線である。本実施形態の配線４７はさらに、放熱基板４４の内部または付近を通過している。 The wiring 47 is provided on the front surface, the back surface, the inside, etc. of the mounting board 43, and electrically connects the LD chip 41 and the LDD board 42. The wiring 47 is, for example, a printed wiring provided on the front surface or the back surface of the mounting board 43, or a via wiring penetrating the mounting board 43. The wiring 47 of the present embodiment further passes through the inside or the vicinity of the heat dissipation board 44.
　図２のＢは、本実施形態の発光装置１の構造の第２の例を示している。この例の発光装置１は、第１の例の発光装置１と同じ構成要素を備えているが、配線４７の代わりに半田４８を備え、さらにアンダーフィル材４９を備えている。半田４８は、本開示の接続部の例であり、かつ、後述する発光素子５３、電極５４、および接続パッド６２と共に本開示の突出部の例である。アンダーフィル材４９は、本開示の充填樹脂の例である。 B in FIG. 2 shows a second example of the structure of the light emitting device 1 of the present embodiment. The light emitting device 1 of this example has the same components as the light emitting device 1 of the first example, but includes a solder 48 instead of the wiring 47, and further includes an underfill material 49. The solder 48 is an example of the connection portion of the present disclosure, and is an example of the protrusion portion of the present disclosure together with the light emitting element 53, the electrode 54, and the connection pad 62 described later. The underfill material 49 is an example of the filling resin of the present disclosure.
　図２のＢでは、放熱基板４４上にＬＤＤ基板４２が配置されており、ＬＤＤ基板４２上にＬＤチップ４１が配置されている。このようにＬＤチップ４１をＬＤＤ基板４２上に配置することにより、第１の例の場合に比べて、実装基板４３のサイズを小型化することが可能となる。図２のＢでは、ＬＤチップ４１が、ＬＤＤ基板４２上に半田４８を介して配置されており、半田４８によりＬＤＤ基板４２と電気的に接続されている。ＬＤチップ４１は、半田４８の代わりに金属バンプによりＬＤＤ基板４２と電気的に接続されていてもよい。 In B of FIG. 2, the LDD board 42 is arranged on the heat dissipation board 44, and the LD chip 41 is arranged on the LDD board 42. By arranging the LD chip 41 on the LDD substrate 42 in this way, it is possible to reduce the size of the mounting substrate 43 as compared with the case of the first example. In B of FIG. 2, the LD chip 41 is arranged on the LDD board 42 via the solder 48, and is electrically connected to the LDD board 42 by the solder 48. The LD chip 41 may be electrically connected to the LDD substrate 42 by a metal bump instead of the solder 48.
　アンダーフィル材４９は、ＬＤチップ４１とＬＤＤ基板４２との間に、半田４８を包囲するように充填されている。アンダーフィル材４９は例えば、ＬＤチップ４１とＬＤＤ基板４２との間に注入された樹脂である。この樹脂の例は、アクリル系樹脂などの熱硬化樹脂である。 The underfill material 49 is filled between the LD chip 41 and the LDD substrate 42 so as to surround the solder 48. The underfill material 49 is, for example, a resin injected between the LD chip 41 and the LDD substrate 42. An example of this resin is a thermosetting resin such as an acrylic resin.
　以下、本実施形態の発光装置１について、図２のＢに示す第２の例の構造を有しているとして説明する。ただし、以下の説明は、第２の例に特有の構造についての説明を除き、第１の例の構造を有する発光装置１にも適用可能である。 Hereinafter, the light emitting device 1 of the present embodiment will be described as having the structure of the second example shown in B of FIG. However, the following description is also applicable to the light emitting device 1 having the structure of the first example, except for the description of the structure peculiar to the second example.
　図３は、図２のＢに示す発光装置１の構造を示す断面図、平面図および斜視図である。 FIG. 3 is a cross-sectional view, a plan view, and a perspective view showing the structure of the light emitting device 1 shown in FIG. 2B.
　図３のＡは、発光装置１内のＬＤチップ４１とＬＤＤ基板４２の断面を示している。図３のＡに示すように、ＬＤチップ４１は、基板５１と、積層膜５２と、複数の発光素子５３と、複数の電極５４と、絶縁膜５５とを備えている。また、ＬＤＤ基板４２は、基板６１と、複数の接続パッド６２とを備えている。図３のＢおよびＣは、図３のＡに対応する平面図と斜視図である。なお、図３のＣでは、アンダーフィル材４９の図示が省略されている。以下、図３のＡからＣを参照して、本実施形態の発光装置１の構造を説明する。 A in FIG. 3 shows a cross section of the LD chip 41 and the LDD substrate 42 in the light emitting device 1. As shown in FIG. 3A, the LD chip 41 includes a substrate 51, a laminated film 52, a plurality of light emitting elements 53, a plurality of electrodes 54, and an insulating film 55. Further, the LDD substrate 42 includes a substrate 61 and a plurality of connection pads 62. B and C in FIG. 3 are a plan view and a perspective view corresponding to A in FIG. In addition, in C of FIG. 3, the illustration of the underfill material 49 is omitted. Hereinafter, the structure of the light emitting device 1 of the present embodiment will be described with reference to FIGS. 3A to 3C.
　基板５１は、例えばＧａＡｓ（ガリウムヒ素）基板などの化合物半導体基板である。図３のＡは、－Ｚ方向を向いている基板５１の表面Ｓ１と、＋Ｚ方向を向いている基板５１の裏面Ｓ２とを示している。基板５１は、本開示の第１基板の例である。また、表面Ｓ１は本開示の第１面の例であり、裏面Ｓ２は本開示の第２面の例である。 The substrate 51 is a compound semiconductor substrate such as a GaAs (gallium arsenide) substrate. A in FIG. 3 shows the front surface S1 of the substrate 51 facing the −Z direction and the back surface S2 of the substrate 51 facing the + Z direction. The substrate 51 is an example of the first substrate of the present disclosure. Further, the front surface S1 is an example of the first surface of the present disclosure, and the back surface S2 is an example of the second surface of the present disclosure.
　積層膜５２は、基板５１の表面Ｓ１に積層された複数の層を含んでいる。これらの層の例は、ｎ型半導体層、活性層、ｐ型半導体層、および光反射層や、光の射出窓を有する絶縁層などである。積層膜５２は、－Ｚ方向に突出した複数のメサ部Ｍを含んでいる。これらのメサ部Ｍの一部が、複数の発光素子５３となっている。 The laminated film 52 includes a plurality of layers laminated on the surface S1 of the substrate 51. Examples of these layers are an n-type semiconductor layer, an active layer, a p-type semiconductor layer, a light reflecting layer, an insulating layer having a light emission window, and the like. The laminated film 52 includes a plurality of mesa portions M protruding in the −Z direction. A part of these mesas portions M is a plurality of light emitting elements 53.
　発光素子５３は、積層膜５２の一部として、基板５１の表面Ｓ１に設けられており、基板５１の表面Ｓ１に対して－Ｚ方向に突出している。発光素子５３は、本開示の突出部の例である。本実施形態の発光素子５３は、ＶＣＳＥＬ構造を有しており、光を＋Ｚ方向に出射する。発光素子５３から出射された光は、図３のＡに示すように、基板５１内を表面Ｓ１から裏面Ｓ２へと透過し、基板５１から上述の補正レンズ４６（図２）に入射する。このように、本実施形態のＬＤチップ４１は、裏面照射型のＶＣＳＥＬチップとなっている。各発光素子５３内の積層膜５２は、ＶＣＳＥＬ活性層とも呼ばれる。 The light emitting element 53 is provided on the surface S1 of the substrate 51 as a part of the laminated film 52, and protrudes in the −Z direction with respect to the surface S1 of the substrate 51. The light emitting element 53 is an example of the protruding portion of the present disclosure. The light emitting element 53 of the present embodiment has a VCSEL structure and emits light in the + Z direction. As shown in FIG. 3A, the light emitted from the light emitting element 53 passes through the substrate 51 from the front surface S1 to the back surface S2, and is incident on the correction lens 46 (FIG. 2) from the substrate 51. As described above, the LD chip 41 of the present embodiment is a back-illuminated type VCSEL chip. The laminated film 52 in each light emitting element 53 is also called a VCSEL active layer.
　電極５４は、発光素子５３の下面に形成されている。よって、発光素子５３と電極５４は、基板５１の表面Ｓ１に順に設けられており、基板５１の表面Ｓ１に対して－Ｚ方向に突出している。電極５４も、本開示の突出部の例である。本実施形態の電極５４は、アノード電極である。本実施形態のＬＤチップ４１はさらに、発光素子５３以外のメサ部Ｍの下面に形成されたカソード電極を備えている。各発光素子５３は、対応するアノード電極と対応するカソード電極との間に電流が流れることで光を出射する。 The electrode 54 is formed on the lower surface of the light emitting element 53. Therefore, the light emitting element 53 and the electrode 54 are sequentially provided on the surface S1 of the substrate 51, and project in the −Z direction with respect to the surface S1 of the substrate 51. The electrode 54 is also an example of the protrusion of the present disclosure. The electrode 54 of this embodiment is an anode electrode. The LD chip 41 of the present embodiment further includes a cathode electrode formed on the lower surface of the mesa portion M other than the light emitting element 53. Each light emitting element 53 emits light by flowing a current between the corresponding anode electrode and the corresponding cathode electrode.
　絶縁膜５５は、基板５１の表面Ｓ１にて、互いに隣接する発光素子５３同士の間などに形成されている。絶縁膜５５は例えば、積層膜５２の下面や、発光素子５３の表面（側面や下面）に形成されている。ただし、電極５４の下面は、絶縁膜５５から露出している。絶縁膜５５は、例えばＳｉＮ膜（窒化シリコン膜）またはＳｉＯ２膜（酸化シリコン膜）である。 The insulating film 55 is formed on the surface S1 of the substrate 51 between the light emitting elements 53 adjacent to each other and the like. The insulating film 55 is formed on, for example, the lower surface of the laminated film 52 or the surface (side surface or lower surface) of the light emitting element 53. However, the lower surface of the electrode 54 is exposed from the insulating film 55. The insulating film 55 is, for example, a SiN film (silicon nitride film) or a SiO 2 film (silicon oxide film).
　上述のように、ＬＤチップ４１は、ＬＤＤ基板４２上に半田４８を介して配置されており、半田４８によりＬＤＤ基板４２と電気的に接続されている。具体的には、ＬＤＤ基板４２に含まれる基板６１上に接続パッド６２が形成されており、接続パッド６２上に半田４８を介してメサ部Ｍが配置されている。各メサ部Ｍは、アノード電極（電極５４）またはカソード電極を介して半田４８上に配置されている。 As described above, the LD chip 41 is arranged on the LDD board 42 via the solder 48, and is electrically connected to the LDD board 42 by the solder 48. Specifically, the connection pad 62 is formed on the substrate 61 included in the LDD substrate 42, and the mesa portion M is arranged on the connection pad 62 via the solder 48. Each mesa portion M is arranged on the solder 48 via the anode electrode (electrode 54) or the cathode electrode.
　基板６１は、基板５１の表面Ｓ１に対向するように、基板５１の－Ｚ方向に配置されている。基板６１は例えば、基板５１の材料と異なる材料で形成されており、基板５１の線膨張係数と異なる線膨張係数を有している。基板５１と基板６１との線膨張係数の差は、例えば２．０×１０－６［１／Ｋ］以上である。基板６１は、例えばＳｉ（シリコン）基板などの半導体基板である。基板６１は、本開示の第２基板の例である。なお、基板５１がＧａＡｓ基板の場合、基板５１の線膨張係数は５．７×１０－６［１／Ｋ］である。また、基板６１がＳｉ基板の場合、基板６１の線膨張係数は３．０×１０－６［１／Ｋ］である。 The substrate 61 is arranged in the −Z direction of the substrate 51 so as to face the surface S1 of the substrate 51. The substrate 61 is made of, for example, a material different from the material of the substrate 51, and has a linear expansion coefficient different from the linear expansion coefficient of the substrate 51. The difference in the coefficient of linear expansion between the substrate 51 and the substrate 61 is, for example, 2.0 × 10 -6 [1 / K] or more. The substrate 61 is a semiconductor substrate such as a Si (silicon) substrate. The substrate 61 is an example of the second substrate of the present disclosure. When the substrate 51 is a GaAs substrate, the coefficient of linear expansion of the substrate 51 is 5.7 × 10 -6 [1 / K]. When the substrate 61 is a Si substrate, the coefficient of linear expansion of the substrate 61 is 3.0 × 10-6 [1 / K].
　接続パッド６２は例えば、Ｃｕ（銅）、Ｎｉ（ニッケル）、Ａｌ（アルミニウム）などの金属により形成されている。発光素子５３、電極５４、半田４８、および接続パッド６２は、基板５１の表面Ｓ１に対して－Ｚ方向に突出している。半田４８と接続パッド６２も、本開示の突出部の例である。 The connection pad 62 is made of a metal such as Cu (copper), Ni (nickel), Al (aluminum), for example. The light emitting element 53, the electrode 54, the solder 48, and the connection pad 62 project in the −Z direction with respect to the surface S1 of the substrate 51. The solder 48 and the connection pad 62 are also examples of the protrusions of the present disclosure.
　ＬＤＤ基板４２は、発光部１１を駆動する駆動回路１２を含んでいる（図１）。図３のＡは、駆動回路１２に含まれる複数のスイッチＳＷを模式的に示している。各スイッチＳＷは、半田４８を介して、対応する発光素子５３と電気的に接続されている。本実施形態の駆動回路１２は、これらのスイッチＳＷを個々のスイッチＳＷごとに制御（オン・オフ）することができる。よって、駆動回路１２は、複数の発光素子５３を個々の発光素子５３ごとに駆動させることができる。これにより、例えば測距に必要な発光素子５３のみ発光させるなど、発光部１１から出射される光を精密に制御することが可能となる。このような発光素子５３の個別制御は、ＬＤＤ基板４２をＬＤチップ４１の下方に配置することにより、各発光素子５３を対応するスイッチＳＷと電気的に接続しやすくなったことで実現可能となっている。 The LDD board 42 includes a drive circuit 12 that drives the light emitting unit 11 (FIG. 1). FIG. 3A schematically shows a plurality of switch SWs included in the drive circuit 12. Each switch SW is electrically connected to the corresponding light emitting element 53 via the solder 48. The drive circuit 12 of the present embodiment can control (on / off) these switch SWs for each individual switch SW. Therefore, the drive circuit 12 can drive a plurality of light emitting elements 53 for each individual light emitting element 53. This makes it possible to precisely control the light emitted from the light emitting unit 11, for example, by causing only the light emitting element 53 required for distance measurement to emit light. Such individual control of the light emitting element 53 can be realized by arranging the LDD substrate 42 below the LD chip 41 so that each light emitting element 53 can be easily electrically connected to the corresponding switch SW. ing.
　本実施形態の半田４８は、上述のようにＬＤチップ４１とＬＤＤ基板４２とを電気的に接続しており、具体的には、基板５１側の電気回路や回路素子と、基板５２側の電気回路や回路素子とを電気的に接続している。例えば、上述の各スイッチＳＷが、半田４８を介して、対応する電極５４と電気的に接続されている。 The solder 48 of the present embodiment electrically connects the LD chip 41 and the LDD board 42 as described above. Specifically, the electric circuit or circuit element on the board 51 side and the electricity on the board 52 side. It is electrically connected to circuits and circuit elements. For example, each of the above-mentioned switch SWs is electrically connected to the corresponding electrode 54 via the solder 48.
　本実施形態のアンダーフィル材４９は、基板５１と基板６１との間に充填されており、発光素子５３、電極５４、半田４８、接続パッド６２などの発光装置１の構成要素を包囲している。これにより、これらの構成部分を異物から保護することや、これらの構成部分を構造的に補強することが可能となる。 The underfill material 49 of the present embodiment is filled between the substrate 51 and the substrate 61, and surrounds the components of the light emitting device 1 such as the light emitting element 53, the electrode 54, the solder 48, and the connection pad 62. .. This makes it possible to protect these components from foreign matter and structurally reinforce these components.
　本実施形態のアンダーフィル材４９は、複数のＬＤチップ４１を含むウェハから個々のＬＤチップ４１がダイシングされた後に、ＬＤチップ４１とＬＤＤ基板４２との間の隙間に充填される。そのため、図３のＡおよびＢに示すアンダーフィル材４９は、この隙間に充填された部分だけでなく、この隙間からはみ出た部分も含んでいる。 The underfill material 49 of the present embodiment is filled in the gap between the LD chip 41 and the LDD substrate 42 after the individual LD chips 41 are diced from the wafer including the plurality of LD chips 41. Therefore, the underfill material 49 shown in FIGS. 3A and 3B includes not only the portion filled in the gap but also the portion protruding from the gap.
　本実施形態のアンダーフィル材４９は、アクリル系樹脂などの熱硬化樹脂であり、所定のガラス転位温度Ｔｇ［℃］および硬化温度Ｔｐ［℃］を有している。例えば、本実施形態のアンダーフィル材４９のガラス転位温度Ｔｇ［℃］および硬化温度Ｔｐ［℃］は、以下の式（１）の関係を満たしており、好ましくはさらに以下の式（２）の関係を満たしている。 The underfill material 49 of the present embodiment is a thermosetting resin such as an acrylic resin, and has a predetermined glass transition temperature Tg [° C.] and a curing temperature Tp [° C.]. For example, the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the underfill material 49 of the present embodiment satisfy the relationship of the following formula (1), and more preferably further of the following formula (2). Meet the relationship.
　　８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５　・・・（１）
　　Ｔｇ≧９０　・・・（２）
　これらの式の詳細については、後述することにする。 80 ≦ Tp ≦ (Tg + 115) /1.5 ・ ・ ・ (1)
Tg ≧ 90 ・ ・ ・ (2)
Details of these equations will be described later.
　図４および図５は、第１実施形態の発光装置１の製造方法を示す断面図である。 4 and 5 are cross-sectional views showing a method of manufacturing the light emitting device 1 of the first embodiment.
　まず、基板５１を用意する（図４のＡ）。図４のＡでは、基板５１の表面Ｓ１が＋Ｚ方向を向いており、基板５１の裏面Ｓ２が－Ｚ方向を向いている。次に、基板５１の表面Ｓ１に積層膜５２を形成し、積層膜５２を複数の発光素子５３（メサ部Ｍ）を含むようにエッチング加工する（図４のＡ）。これにより、基板５１の表面Ｓ１に対して＋Ｚ方向に突出した発光素子５３が形成される。 First, prepare the board 51 (A in FIG. 4). In A of FIG. 4, the front surface S1 of the substrate 51 faces the + Z direction, and the back surface S2 of the substrate 51 faces the −Z direction. Next, the laminated film 52 is formed on the surface S1 of the substrate 51, and the laminated film 52 is etched so as to include a plurality of light emitting elements 53 (mesa portions M) (A in FIG. 4). As a result, the light emitting element 53 projecting in the + Z direction with respect to the surface S1 of the substrate 51 is formed.
　次に、これらの発光素子５３の上面に複数の電極５４を形成し、基板５１の表面Ｓ１に絶縁膜５５を形成する（図４のＢ）。これにより、積層膜５２、発光素子５３、および電極５４が、絶縁膜５５により覆われる。 Next, a plurality of electrodes 54 are formed on the upper surface of these light emitting elements 53, and an insulating film 55 is formed on the surface S1 of the substrate 51 (B in FIG. 4). As a result, the laminated film 52, the light emitting element 53, and the electrode 54 are covered with the insulating film 55.
　次に、絶縁膜５５をエッチング加工する（図４のＣ）。これにより、絶縁膜５５から電極５４が露出する。このようにして、互いに隣接する発光素子５３同士の間に、絶縁膜５５が形成される。 Next, the insulating film 55 is etched (C in FIG. 4). As a result, the electrode 54 is exposed from the insulating film 55. In this way, the insulating film 55 is formed between the light emitting elements 53 adjacent to each other.
　次に、基板６１の上面上に基板５１を配置する（図５のＡ）。この際、基板５１は、表面Ｓ１が－Ｚ方向を向き、裏面Ｓ２が＋Ｚ方向を向くように、基板６１の上面上に配置される。これにより、基板６１は、基板５１の表面Ｓ１に対向するように、基板５１下に配置される。図５のＡは、基板６１の上面上にあらかじめ形成された複数の接続パッド６２を示している。基板５１は、接続パッド６２上に半田４８を介して電極４８が配置されるように、基板６１上に配置される。これにより、基板５１側が、基板６１側と電気的に接続される。 Next, the substrate 51 is placed on the upper surface of the substrate 61 (A in FIG. 5). At this time, the substrate 51 is arranged on the upper surface of the substrate 61 so that the front surface S1 faces the −Z direction and the back surface S2 faces the + Z direction. As a result, the substrate 61 is arranged under the substrate 51 so as to face the surface S1 of the substrate 51. A in FIG. 5 shows a plurality of connection pads 62 previously formed on the upper surface of the substrate 61. The substrate 51 is arranged on the substrate 61 so that the electrodes 48 are arranged on the connection pad 62 via the solder 48. As a result, the substrate 51 side is electrically connected to the substrate 61 side.
　次に、基板５１と基板６１との間にアンダーフィル材４９を注入し、このアンダーフィル材４９を熱硬化させる（図５のＢ）。これにより、発光素子５３、電極５４、半田４８、接続パッド６２などの発光装置１の構成要素が、アンダーフィル材４９により包囲される。 Next, the underfill material 49 is injected between the substrate 51 and the substrate 61, and the underfill material 49 is thermoset (B in FIG. 5). As a result, the components of the light emitting device 1 such as the light emitting element 53, the electrode 54, the solder 48, and the connection pad 62 are surrounded by the underfill material 49.
　このようにして、本実施形態の発光装置１が製造される。図５のＡおよびＢに示す工程のさらなる詳細については、図６から図９を参照して説明する。 In this way, the light emitting device 1 of the present embodiment is manufactured. Further details of the steps shown in FIGS. 5A and 5B will be described with reference to FIGS. 6 to 9.
　図６から図９は、第１実施形態の発光装置１の製造方法の詳細を示す断面図である。 6 to 9 are cross-sectional views showing details of the manufacturing method of the light emitting device 1 of the first embodiment.
　ＬＤチップ４１とＬＤＤ基板４２とを電気的に接続する際には、まず基板６１の上方に基板５１を配置する（図６のＡ）。具体的には、各電極５４を、対応する接続パッド６２の上方に配置する。符号Ｐ１は、基板５１の位置が基板６１の位置に対して固定されていることを示している。符号Ｐ２は、基板６１が真空吸着されていることを示している。図６のＡの工程におけるＬＤチップ４１とＬＤＤ基板４２の温度は、例えば２５℃である。 When electrically connecting the LD chip 41 and the LDD substrate 42, the substrate 51 is first arranged above the substrate 61 (A in FIG. 6). Specifically, each electrode 54 is placed above the corresponding connection pad 62. Reference numeral P1 indicates that the position of the substrate 51 is fixed with respect to the position of the substrate 61. Reference numeral P2 indicates that the substrate 61 is vacuum-sucked. The temperature of the LD chip 41 and the LDD substrate 42 in the step A of FIG. 6 is, for example, 25 ° C.
　次に、接合用の半田４８を電極５４と接続パッド６２との間に供給し、この半田４８をリフロー炉などで加熱して溶融させる（図６のＢ）。半田４８の溶融温度は半田４８の組成により異なるが、Ｓｎ－Ａｇ－Ｃｕ系の半田４８の溶融温度は約２２０℃であり、Ｓｎ－Ｂｉ系の半田４８の溶融温度は約１７０℃である（Ｓｎはスズ、Ａｇは銀、Ｂｉはビスマスを表す）。図６のＢの工程では、半田４８やその付近の構成要素が、例えば２２０℃に加熱される。矢印Ｆ１は、図６のＢの工程における加熱により基板６１と基板５１が熱膨張する際に、基板６１の熱膨張係数が基板５１の熱膨張係数より大きい場合には、基板６１が基板５１に対して相対的に大きく膨張することを示している。 Next, the solder 48 for joining is supplied between the electrode 54 and the connection pad 62, and the solder 48 is heated and melted in a reflow oven or the like (B in FIG. 6). The melting temperature of the solder 48 differs depending on the composition of the solder 48, but the melting temperature of the Sn—Ag—Cu-based solder 48 is about 220 ° C., and the melting temperature of the Sn—Bi-based solder 48 is about 170 ° C. ( Sn stands for tin, Ag stands for silver, and Bi stands for bismuth). In the step B of FIG. 6, the solder 48 and the components in the vicinity thereof are heated to, for example, 220 ° C. The arrow F1 indicates that when the coefficient of thermal expansion of the substrate 61 is larger than the coefficient of thermal expansion of the substrate 51 when the substrate 61 and the substrate 51 thermally expand due to the heating in the step B of FIG. 6, the substrate 61 becomes the substrate 51. On the other hand, it shows that it expands relatively large.
　次に、基板５１、６１等がリフロー炉から外に出されることで、半田４８の温度が低下する（図７のＡ）。その結果、半田４８が固化し、電極５４と接続パッド６２が半田４８により接合される。このようにして、ＬＤチップ４１とＬＤＤ基板４２が電気的に接続される。図７のＡの工程では、半田４８やその付近の構成要素の温度が、例えば２５℃に戻る。 Next, the temperature of the solder 48 drops as the substrates 51, 61, etc. are taken out of the reflow furnace (A in FIG. 7). As a result, the solder 48 is solidified, and the electrode 54 and the connection pad 62 are joined by the solder 48. In this way, the LD chip 41 and the LDD substrate 42 are electrically connected. In the step A of FIG. 7, the temperature of the solder 48 and the components in the vicinity thereof returns to, for example, 25 ° C.
　このようにして、ＬＤチップ４１とＬＤＤ基板４２が半田４８により接合される。図７のＢに示す矢印Ｆ２は、半田４８やその付近の構成要素の温度低下により基板６１と基板５１が熱収縮する際に、基板６１の熱膨張係数が基板５１の熱膨張係数より大きい場合には、基板６１が基板５１に対して相対的に大きく収縮することを示している。 In this way, the LD chip 41 and the LDD substrate 42 are joined by the solder 48. The arrow F2 shown in FIG. 7B indicates a case where the coefficient of thermal expansion of the substrate 61 is larger than the coefficient of thermal expansion of the substrate 51 when the substrate 61 and the substrate 51 thermally shrink due to a temperature drop of the solder 48 and its components. Shows that the substrate 61 shrinks relatively significantly with respect to the substrate 51.
　次に、基板６１の真空吸着を解放した後、基板５１と基板６１との間にアンダーフィル材４９を注入する（図８のＡ）。アンダーフィル材４９は例えば、アクリル系樹脂などの熱硬化樹脂である。 Next, after releasing the vacuum suction of the substrate 61, the underfill material 49 is injected between the substrate 51 and the substrate 61 (A in FIG. 8). The underfill material 49 is, for example, a thermosetting resin such as an acrylic resin.
　次に、基板５１と基板６１との間に注入されたアンダーフィル材４９を加熱して、このアンダーフィル材４９を熱硬化させる（図８のＢ）。アンダーフィル材４９は、例えば１７０～２２０℃で熱硬化される。図８のＢの工程では、アンダーフィル材４９やその付近の構成要素が、例えば約１７０℃に加熱される。矢印Ｆ３は、図８のＢの工程における加熱により基板６１と基板５１が熱膨張する際に、基板６１の熱膨張係数が基板５１の熱膨張係数より大きい場合には、基板６１が基板５１に対して相対的に大きく膨張することを示している。 Next, the underfill material 49 injected between the substrate 51 and the substrate 61 is heated to heat-cure the underfill material 49 (B in FIG. 8). The underfill material 49 is thermoset at, for example, 170 to 220 ° C. In the step B of FIG. 8, the underfill material 49 and the components in the vicinity thereof are heated to, for example, about 170 ° C. The arrow F3 indicates that when the coefficient of thermal expansion of the substrate 61 is larger than the coefficient of thermal expansion of the substrate 51 when the substrate 61 and the substrate 51 thermally expand due to the heating in the step B of FIG. 8, the substrate 61 becomes the substrate 51. On the other hand, it shows that it expands relatively large.
　次に、アンダーフィル材４９の温度が低下する（図９）。図９の工程では、アンダーフィル材４９やその付近の構成要素の温度が、例えば２５℃に戻る。矢印Ｆ４は、アンダーフィル材４９やその付近の構成要素の温度低下により基板６１と基板５１が熱収縮する際に、基板６１の熱膨張係数が基板５１の熱膨張係数より大きい場合には、基板６１が基板５１に対して相対的に大きく収縮することを示している。 Next, the temperature of the underfill material 49 drops (Fig. 9). In the step of FIG. 9, the temperature of the underfill material 49 and the components in the vicinity thereof returns to, for example, 25 ° C. The arrow F4 indicates a substrate when the coefficient of thermal expansion of the substrate 61 is larger than the coefficient of thermal expansion of the substrate 51 when the substrate 61 and the substrate 51 thermally shrink due to a temperature drop of the underfill material 49 and its components. It is shown that 61 shrinks relatively large with respect to the substrate 51.
　このようにして、基板５１と基板６１との間にアンダーフィル材４９が形成される。本実施形態のアンダーフィル材４９は、基板５１と基板６１との間の隙間に充填された部分だけでなく、この隙間からはみ出た部分も含んでいてもよい。 In this way, the underfill material 49 is formed between the substrate 51 and the substrate 61. The underfill material 49 of the present embodiment may include not only a portion filled in the gap between the substrate 51 and the substrate 61 but also a portion protruding from the gap.
　図１０は、第１実施形態の発光装置１の製造方法を説明するためのグラフである。 FIG. 10 is a graph for explaining the manufacturing method of the light emitting device 1 of the first embodiment.
　図１０のグラフは、図６のＡから図９の工程におけるプロセス温度の時間変化の例を示している。本実施形態の発光装置１の種々の製造工程は、概ね２５℃で行われる。 The graph of FIG. 10 shows an example of the time change of the process temperature in the steps A to 9 of FIG. The various manufacturing steps of the light emitting device 1 of the present embodiment are performed at approximately 25 ° C.
　ただし、図６のＢの工程では、接合用の半田４８を加熱して溶融させ、電極５４と接続パッド６２との間にこの半田４８を供給する（接合工程）。この際には、半田４８がその融点まで加熱される。図１０のグラフでは、半田４８の融点は約２２０℃である。 However, in the process B of FIG. 6, the solder 48 for joining is heated and melted, and the solder 48 is supplied between the electrode 54 and the connection pad 62 (bonding step). At this time, the solder 48 is heated to its melting point. In the graph of FIG. 10, the melting point of the solder 48 is about 220 ° C.
　また、図８のＢの工程では、基板５１と基板６１との間に注入されたアンダーフィル材４９を加熱して、このアンダーフィル材４９を熱硬化させる（ＵＦ（アンダーフィル）工程）。この際には、アンダーフィル材４９がその硬化温度まで加熱される。図１０のグラフでは、アンダーフィル材４９の硬化温度は約１７０℃である。 Further, in the step B of FIG. 8, the underfill material 49 injected between the substrate 51 and the substrate 61 is heated to thermally cure the underfill material 49 (UF (underfill) step). At this time, the underfill material 49 is heated to its curing temperature. In the graph of FIG. 10, the curing temperature of the underfill material 49 is about 170 ° C.
　このように、本実施形態の発光装置１を製造する際には、半田４８による接合やアンダーフィル材４９の硬化のために、発光装置１が高温に加熱される場合がある。この場合、基板５１と基板６１が異なる線膨張係数を有していると、発光素子５３などに大きな応力が掛かり、発光装置１の信頼性が損なわれるおそれや、発光装置１にクラックが入って割れるおそれがある。この応力は例えば、図６のＡから図９に示す基板６１と基板５１の熱膨張の差や収縮の差に起因して発生する（矢印Ｆ１～Ｆ４を参照）。この応力は、発光装置１の完成品内の基板６１に残存する可能性もあり、この場合の発光装置１への影響も問題となる。 As described above, when the light emitting device 1 of the present embodiment is manufactured, the light emitting device 1 may be heated to a high temperature due to the joining by the solder 48 and the curing of the underfill material 49. In this case, if the substrate 51 and the substrate 61 have different linear expansion coefficients, a large stress is applied to the light emitting element 53 and the like, the reliability of the light emitting device 1 may be impaired, and the light emitting device 1 may be cracked. There is a risk of cracking. This stress is generated, for example, due to the difference in thermal expansion and contraction between the substrate 61 and the substrate 51 shown in FIGS. 6A to 9 (see arrows F1 to F4). This stress may remain on the substrate 61 in the finished product of the light emitting device 1, and the influence on the light emitting device 1 in this case also becomes a problem.
　本実施形態の基板５１は、例えばＧａＡｓ基板である。これにより、発光素子５３を形成するのに適したＧａＡｓ基板を、基板５１として使用することが可能となる。また、本実施形態の基板６１は、例えばＳｉ基板である。これにより、安価に用意できるＳｉ基板を、基板６１として使用することが可能となる。しかしながら、基板５１としてＧａＡｓ基板を使用し、基板６１としてＳｉ基板を使用すると、基板５１と基板６１との線膨張係数の差が、２．７×１０－６［１／Ｋ］と大きくなる。そのため、発光素子５３などに大きな応力が掛かりやすい。 The substrate 51 of this embodiment is, for example, a GaAs substrate. This makes it possible to use a GaAs substrate suitable for forming the light emitting element 53 as the substrate 51. Further, the substrate 61 of this embodiment is, for example, a Si substrate. This makes it possible to use a Si substrate that can be prepared at low cost as the substrate 61. However, when a GaAs substrate is used as the substrate 51 and a Si substrate is used as the substrate 61, the difference in the coefficient of linear expansion between the substrate 51 and the substrate 61 becomes as large as 2.7 × 10-6 [1 / K]. Therefore, a large stress is likely to be applied to the light emitting element 53 or the like.
　また、本実施形態の発光装置１は、裏面照射型であるため、発光素子５３が基板５１と基板６１との間に配置されている。そのため、発光素子５３が、半田４８やアンダーフィル材４９のそばに配置されており、接合工程やＵＦ工程にて半田４８やアンダーフィル材４９の機械的な特性が変わることの影響を受けやすい位置に配置されている。このことも、発光素子５３に大きな応力が掛かりやすい一因となる。発光素子５３に大きな応力が掛かると、例えば発光素子５３から発光される光の強度が低下したり、経年劣化を速めてしまったりするおそれがある。 Further, since the light emitting device 1 of the present embodiment is a back-illuminated type, the light emitting element 53 is arranged between the substrate 51 and the substrate 61. Therefore, the light emitting element 53 is arranged near the solder 48 and the underfill material 49, and is easily affected by changes in the mechanical characteristics of the solder 48 and the underfill material 49 in the joining process and the UF process. Is located in. This also contributes to the fact that a large stress is likely to be applied to the light emitting element 53. When a large stress is applied to the light emitting element 53, for example, the intensity of the light emitted from the light emitting element 53 may decrease or the deterioration over time may be accelerated.
　そこで、本実施形態では、所定のガラス転位温度Ｔｇ［℃］および硬化温度Ｔｐ［℃］を有するアンダーフィル材４９を使用することで、この問題に対処する。このような対処の詳細については、後述することにする。 Therefore, in the present embodiment, this problem is dealt with by using an underfill material 49 having a predetermined glass dislocation temperature Tg [° C.] and curing temperature Tp [° C.]. Details of such measures will be described later.
　図１１は、第１実施形態のアンダーフィル材４９の性質を示すグラフである。 FIG. 11 is a graph showing the properties of the underfill material 49 of the first embodiment.
　図１１のグラフは、アンダーフィル材４９のヤング率の温度依存性を示している。このグラフから分かるように、アンダーフィル材４９のヤング率は、アンダーフィル材４９のガラス転位温度Ｔｇにて大きく変化する。そのため、アンダーフィル材４９のガラス転位温度Ｔｇは、発光素子５３などに掛かる応力の大きさに影響するパラメータであると考えられる。 The graph in FIG. 11 shows the temperature dependence of Young's modulus of the underfill material 49. As can be seen from this graph, the Young's modulus of the underfill material 49 changes greatly depending on the glass transition temperature Tg of the underfill material 49. Therefore, the glass dislocation temperature Tg of the underfill material 49 is considered to be a parameter that affects the magnitude of the stress applied to the light emitting element 53 and the like.
　図１２は、第１実施形態の発光装置１内の半田４８の性質を示すグラフである。 FIG. 12 is a graph showing the properties of the solder 48 in the light emitting device 1 of the first embodiment.
　図１２の横軸は、電極５４と接続パッド６２との間に設けられ、アンダーフィル材４９により包囲された半田４８の歪みを示している。図１２において使用された半田４８は、Ｓｎ－Ａｇ－Ｃｕ系の合金であり、その融点は約２２０℃である。また、この半田４８のＳｎ、Ａｇ、Ｃｕの組成率は、それぞれ９６．５％、３．０％、０．５％である。図１２の縦軸は、発光素子５３に掛かる応力を示している。 The horizontal axis of FIG. 12 shows the distortion of the solder 48 provided between the electrode 54 and the connection pad 62 and surrounded by the underfill material 49. The solder 48 used in FIG. 12 is a Sn—Ag—Cu based alloy and has a melting point of about 220 ° C. The composition ratios of Sn, Ag, and Cu of the solder 48 are 96.5%, 3.0%, and 0.5%, respectively. The vertical axis of FIG. 12 shows the stress applied to the light emitting element 53.
　図１２は、半田４８の歪みと発光素子５３に掛かる応力との関係を、アンダーフィル材４９の様々な温度にて示している。具体的には、１５℃、２５℃、１００℃、１７５℃、２３０℃、３００℃における上記関係を示している。半田４８の融点が約２２０℃であるため、２３０℃の曲線と３００℃の曲線がほぼ同じになっていることに留意されたい。 FIG. 12 shows the relationship between the strain of the solder 48 and the stress applied to the light emitting element 53 at various temperatures of the underfill material 49. Specifically, the above relationship at 15 ° C., 25 ° C., 100 ° C., 175 ° C., 230 ° C., and 300 ° C. is shown. It should be noted that since the melting point of the solder 48 is about 220 ° C., the curve at 230 ° C. and the curve at 300 ° C. are almost the same.
　図１２から分かるように、発光素子５３に掛かる応力は、アンダーフィル材４９の温度に応じて変化する。よって、発光素子５３に掛かる応力を低減するためには、アンダーフィル材４９の温度に着目することが望ましいと考えられる。 As can be seen from FIG. 12, the stress applied to the light emitting element 53 changes depending on the temperature of the underfill material 49. Therefore, in order to reduce the stress applied to the light emitting element 53, it is desirable to pay attention to the temperature of the underfill material 49.
　図１３は、第１実施形態のアンダーフィル材４９の性質を示す別のグラフである。 FIG. 13 is another graph showing the properties of the underfill material 49 of the first embodiment.
　図１３のＡは、接合工程やＵＦ工程が終了した後の発光素子５３に掛かる応力（最大主応力）を、コンピュータシミュレーションにより計算した結果を示している。この場合の半田４８の融点は、２２０℃である。図１３のＡは、アンダーフィル材４９のガラス転位温度Ｔｇ［℃］および硬化温度Ｔｐ［℃］を様々な温度に設定した場合の応力の変化を示している。この結果から、ガラス転位温度Ｔｇ［℃］および硬化温度Ｔｐ［℃］を所定の温度に設定すれば、応力を低減できることが分かる。 FIG. 13A shows the result of calculating the stress (maximum principal stress) applied to the light emitting element 53 after the joining process and the UF process are completed by computer simulation. The melting point of the solder 48 in this case is 220 ° C. FIG. 13A shows changes in stress when the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the underfill material 49 are set to various temperatures. From this result, it can be seen that the stress can be reduced by setting the glass dislocation temperature Tg [° C.] and the curing temperature Tp [° C.] to predetermined temperatures.
　発光素子５３に掛かる応力は、なるべく低いことが望ましい。例えば、接合工程やＵＦ工程が終了した後の発光素子５３に掛かる最大主応力は、１５０ＭＰａ以下とすることが望ましい。これにより、発光素子５３に掛かる応力に起因する発光装置１の性能の低下を抑制することが可能となる。 It is desirable that the stress applied to the light emitting element 53 be as low as possible. For example, it is desirable that the maximum principal stress applied to the light emitting element 53 after the joining step or the UF step is completed is 150 MPa or less. This makes it possible to suppress deterioration in the performance of the light emitting device 1 due to the stress applied to the light emitting element 53.
　図１３のＡは、発光素子５３に掛かる応力が低い領域Ｒを示している。領域Ｒは、直線Ｌ１と直線Ｌ２との間に挟まれている。直線Ｌ１は、Ｔｐ＝８０という式で表される。直線Ｌ２は、Ｔｇ＝１．５×Ｔｐ－１１５という式で表される。よって、領域Ｒは、８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５という式で表される。この式は、上述の式（１）に相当する。本実施形態によれば、式（１）の関係を満たすガラス転位温度Ｔｇ［℃］および硬化温度Ｔｐ［℃］を有するアンダーフィル材４９を使用することで、発光素子５３に掛かる応力を低減することが可能となる。なお、図１３に示すＡの領域Ｒでは、最大主応力が概ね１５０ＭＰａ以下となっていることに留意されたい。 A in FIG. 13 shows a region R in which the stress applied to the light emitting element 53 is low. The region R is sandwiched between the straight line L1 and the straight line L2. The straight line L1 is expressed by the equation Tp = 80. The straight line L2 is expressed by the formula Tg = 1.5 × Tp-115. Therefore, the region R is expressed by the formula 80 ≦ Tp ≦ (Tg + 115) /1.5. This equation corresponds to the above equation (1). According to the present embodiment, the stress applied to the light emitting element 53 is reduced by using the underfill material 49 having the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] satisfying the relationship of the formula (1). Is possible. It should be noted that in the region R of A shown in FIG. 13, the maximum principal stress is approximately 150 MPa or less.
　図１３のＢも、接合工程やＵＦ工程が終了した後の発光素子５３に掛かる応力（最大主応力）を、コンピュータシミュレーションにより計算した結果を示している。ただし、この場合の半田４８の融点は、１７０℃である。 B in FIG. 13 also shows the result of calculating the stress (maximum principal stress) applied to the light emitting element 53 after the joining process and the UF process are completed by computer simulation. However, the melting point of the solder 48 in this case is 170 ° C.
　図１３のＢも、直線Ｌ１と直線Ｌ２との間に挟まれた領域Ｒを示している。図１３のＢに示す領域Ｒ内の最大主応力の分布は、図１３のＡに示す領域Ｒ内の最大主応力の分布と若干異なっている。しかしながら、発光素子５３に掛かる最大主応力は、図１３のＡに示す領域Ｒ内だけでなく、図１３のＢに示す領域Ｒ内でも低くなっている。このことから、式（１）の関係を満たすアンダーフィル材４９は、半田４８の融点が２２０℃の場合だけでなく、半田４８の融点が１７０℃の場合でも有益であることが分かる。 B in FIG. 13 also shows the region R sandwiched between the straight line L1 and the straight line L2. The distribution of the maximum principal stress in the region R shown in FIG. 13B is slightly different from the distribution of the maximum principal stress in the region R shown in FIG. 13A. However, the maximum principal stress applied to the light emitting element 53 is low not only in the region R shown in FIG. 13A but also in the region R shown in FIG. 13B. From this, it can be seen that the underfill material 49 satisfying the relationship of the formula (1) is useful not only when the melting point of the solder 48 is 220 ° C. but also when the melting point of the solder 48 is 170 ° C.
　本実施形態の発光装置１で使用される半田４８の融点は、おおむね１７０℃～２２０℃程度であることが多い。一方、図１３のＡおよびＢに示す結果によれば、式（１）の関係を満たすアンダーフィル材４９は、様々な融点を有する半田４８を使用する場合に有益であり、例えば、１７０℃～２２０℃の融点を有する半田４８を使用する場合に有益であることが分かる。よって、本実施形態によれば、式（１）の関係を満たすアンダーフィル材４９を使用することで、様々な種類の半田４８を使用する場合において、発光素子５３に掛かる応力を低減することが可能となる。 The melting point of the solder 48 used in the light emitting device 1 of the present embodiment is often about 170 ° C to 220 ° C. On the other hand, according to the results shown in A and B of FIG. 13, the underfill material 49 satisfying the relationship of the formula (1) is useful when solder 48 having various melting points is used, for example, from 170 ° C. to It turns out to be beneficial when using a solder 48 having a melting point of 220 ° C. Therefore, according to the present embodiment, by using the underfill material 49 satisfying the relationship of the formula (1), it is possible to reduce the stress applied to the light emitting element 53 when various types of solder 48 are used. It will be possible.
　上述のように、発光素子５３に掛かる応力は、発光装置１の完成品内にも残存している可能性がある。この場合、このような応力が、発光素子５３の経年劣化を速めるおそれがある。本実施形態によれば、式（１）の関係を満たすアンダーフィル材４９を使用することで、発光装置１の完成品内に残存する応力を低減することが可能となる。例えば、発光装置１の完成品内の発光素子５３に掛かる最大主応力を、１５０ＭＰａ以下とすることが可能となる。これにより、応力に起因する発光素子５３の経年劣化を抑制することが可能となる。 As described above, the stress applied to the light emitting element 53 may remain in the finished product of the light emitting device 1. In this case, such stress may accelerate the aged deterioration of the light emitting element 53. According to the present embodiment, by using the underfill material 49 satisfying the relationship of the formula (1), it is possible to reduce the stress remaining in the finished product of the light emitting device 1. For example, the maximum principal stress applied to the light emitting element 53 in the finished product of the light emitting device 1 can be set to 150 MPa or less. This makes it possible to suppress aged deterioration of the light emitting element 53 due to stress.
　図１４は、第１実施形態のアンダーフィル材４９の性質を示す別のグラフである。 FIG. 14 is another graph showing the properties of the underfill material 49 of the first embodiment.
　図１４のＡは、図１３のＡと同様に、融点が２２０℃の半田４８を使用した場合のシミュレーション結果を示している。図１４のＡは、領域Ｒを分割して得られた領域Ｒ１と領域Ｒ２とを示している。 A of FIG. 14 shows a simulation result when a solder 48 having a melting point of 220 ° C. is used, similarly to A of FIG. A in FIG. 14 shows a region R1 and a region R2 obtained by dividing the region R.
　領域Ｒ１は、直線Ｌ３の上方に位置しており、領域Ｒ２は、直線Ｌ３の下方に位置している。この直線Ｌ３は、Ｔｇ＝９０という式で表される。よって、領域Ｒ１は、８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５とＴｇ≧９０という２つの式で表される。これらの式は、上述の式（１）と式（２）とに相当する。本実施形態によれば、式（１）および式（２）の関係を満たすガラス転位温度Ｔｇ［℃］および硬化温度Ｔｐ［℃］を有するアンダーフィル材４９を使用することで、発光素子５３に掛かる応力をさらに低減することが可能となる。 The region R1 is located above the straight line L3, and the region R2 is located below the straight line L3. This straight line L3 is expressed by the equation Tg = 90. Therefore, the region R1 is represented by two equations, 80 ≦ Tp ≦ (Tg + 115) /1.5 and Tg ≧ 90. These equations correspond to the above equations (1) and (2). According to the present embodiment, by using the underfill material 49 having a glass transition temperature Tg [° C.] and a curing temperature Tp [° C.] satisfying the relationship of the formulas (1) and (2), the light emitting element 53 can be used. It is possible to further reduce the applied stress.
　図１４のＢは、図１３のＢと同様に、融点が１７０℃の半田４８を使用した場合のシミュレーション結果を示している。図１４のＢも、領域Ｒを分割して得られた領域Ｒ１と領域Ｒ２とを示している。 B in FIG. 14 shows the simulation result when solder 48 having a melting point of 170 ° C. is used, similarly to B in FIG. B in FIG. 14 also shows a region R1 and a region R2 obtained by dividing the region R.
　発光素子５３に掛かる最大主応力は、図１４のＡに示す領域Ｒ１内だけでなく、図１４のＢに示す領域Ｒ１内でも低くなっている。このことから、式（１）および式（２）の関係を満たすアンダーフィル材４９は、半田４８の融点が２２０℃の場合だけでなく、半田４８の融点が１７０℃の場合でも有益であることが分かる。 The maximum principal stress applied to the light emitting element 53 is low not only in the region R1 shown in FIG. 14A but also in the region R1 shown in FIG. 14B. From this, the underfill material 49 satisfying the relationship of the formulas (1) and (2) is useful not only when the melting point of the solder 48 is 220 ° C. but also when the melting point of the solder 48 is 170 ° C. I understand.
　よって、本実施形態によれば、式（１）および式（２）の関係を満たすアンダーフィル材４９を使用することで、様々な種類の半田４８を使用する場合において、発光素子５３に掛かる応力をさらに低減することが可能となる。また、本実施形態によれば、式（１）および式（２）の関係を満たすアンダーフィル材４９を使用することで、発光装置１の完成品内に残存する応力もさらに低減することが可能となる。 Therefore, according to the present embodiment, by using the underfill material 49 satisfying the relationship of the equation (1) and the equation (2), the stress applied to the light emitting element 53 when various types of solder 48 are used. Can be further reduced. Further, according to the present embodiment, by using the underfill material 49 satisfying the relationship of the formula (1) and the formula (2), it is possible to further reduce the stress remaining in the finished product of the light emitting device 1. It becomes.
　上述のように、本実施形態のアンダーフィル材４９は、例えばアクリル系樹脂などの熱硬化樹脂である。式（１）の関係を満たすアンダーフィル材４９は、例えばアクリル系樹脂の成分や添加物を調整することで実現可能である。同様に、式（１）および式（２）の関係を満たすアンダーフィル材４９は、例えばアクリル系樹脂の成分や添加物を調整することで実現可能である。アクリル系樹脂の成分や添加物を調整することで、アンダーフィル材４９のガラス転位温度Ｔｇ［℃］および硬化温度Ｔｐ［℃］を調整することが可能となる。 As described above, the underfill material 49 of the present embodiment is a thermosetting resin such as an acrylic resin. The underfill material 49 satisfying the relationship of the formula (1) can be realized, for example, by adjusting the components and additives of the acrylic resin. Similarly, the underfill material 49 satisfying the relationship of the formula (1) and the formula (2) can be realized by adjusting, for example, the components and additives of the acrylic resin. By adjusting the components and additives of the acrylic resin, it is possible to adjust the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the underfill material 49.
　図１５は、第１実施形態の変形例の発光装置１の構造を示す断面図である。 FIG. 15 is a cross-sectional view showing the structure of the light emitting device 1 of the modified example of the first embodiment.
　本変形例の発光装置１は、第１実施形態の発光装置１と同様の構成要素に加えて、複数のレンズ５６を備えている。本変形例では、ＬＤチップ４１が、基板５１の表面Ｓ１に複数の発光素子５３を備えると共に、基板５１の裏面Ｓ２にこれらのレンズ５６を備えている。本変形例のレンズ５６は、発光素子５３と１対１で対応しており、レンズ５６の各々が、１つの発光素子５３の＋Ｚ方向に配置されている。 The light emitting device 1 of this modification includes a plurality of lenses 56 in addition to the same components as the light emitting device 1 of the first embodiment. In this modification, the LD chip 41 is provided with a plurality of light emitting elements 53 on the front surface S1 of the substrate 51, and these lenses 56 are provided on the back surface S2 of the substrate 51. The lens 56 of this modification has a one-to-one correspondence with the light emitting element 53, and each of the lenses 56 is arranged in the + Z direction of one light emitting element 53.
　本変形例のレンズ５６は、基板５１の裏面Ｓ２に、基板５１の一部として設けられている。具体的には、本変形例のレンズ５６は、凹レンズであり、基板５１の裏面Ｓ２を凹形状にエッチング加工することで、基板５１の一部として形成されている。なお、本変形例のレンズ５６は、凹レンズ以外のレンズ（例えば凸レンズ）でもよい。 The lens 56 of this modification is provided on the back surface S2 of the substrate 51 as a part of the substrate 51. Specifically, the lens 56 of this modification is a concave lens, and is formed as a part of the substrate 51 by etching the back surface S2 of the substrate 51 into a concave shape. The lens 56 of this modification may be a lens other than a concave lens (for example, a convex lens).
　複数の発光素子５３から出射された光は、基板５１内を表面Ｓ１から裏面Ｓ２へと透過し、複数のレンズ５６に入射する。図１５に示すように、各発光素子５３から出射された光は、対応する１個のレンズ５６に入射する。これにより、各発光素子５３から出射された光を、対応するレンズ５６により好適な形状に成形することが可能となる。 The light emitted from the plurality of light emitting elements 53 is transmitted from the front surface S1 to the back surface S2 in the substrate 51 and is incident on the plurality of lenses 56. As shown in FIG. 15, the light emitted from each light emitting element 53 is incident on one corresponding lens 56. As a result, the light emitted from each light emitting element 53 can be formed into a suitable shape by the corresponding lens 56.
　なお、本変形例のレンズ５６を通過した光は、補正レンズ４６（図２）を通過して、被写体（図１）に照射される。 The light that has passed through the lens 56 of this modification passes through the correction lens 46 (FIG. 2) and is applied to the subject (FIG. 1).
　本変形例の発光装置１は、例えば図４および図５に示す方法により製造可能である。本変形例の発光装置１を製造する際には、例えば図５のＢに示す工程の後に基板５１にレンズ５６を形成する。 The light emitting device 1 of this modification can be manufactured by, for example, the methods shown in FIGS. 4 and 5. When manufacturing the light emitting device 1 of this modification, for example, the lens 56 is formed on the substrate 51 after the step shown in FIG. 5B.
　以上のように、本実施形態のアンダーフィル材４９のガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］は、８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５の関係を満たす。よって、本実施形態によれば、基板５１と基板５６との間に設けられた発光装置１の構成部分（例えば発光素子５３）に掛かる応力を低減することが可能となり、アンダーフィル材４９に起因する発光装置１の性能の低下を抑制することが可能となる。 As described above, the glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the underfill material 49 of the present embodiment satisfy the relationship of 80 ≦ Tp ≦ (Tg + 115) /1.5. Therefore, according to the present embodiment, it is possible to reduce the stress applied to the constituent portion (for example, the light emitting element 53) of the light emitting device 1 provided between the substrate 51 and the substrate 56, which is caused by the underfill material 49. It is possible to suppress the deterioration of the performance of the light emitting device 1.
　本実施形態のアンダーフィル材４９のガラス転移温度Ｔｇ［℃］はさらに、Ｔｇ≧９０の関係を満たすことが望ましい。これにより、アンダーフィル材４９に起因する発光装置１の性能の低下をさらに抑制することが可能となる。 It is desirable that the glass transition temperature Tg [° C.] of the underfill material 49 of the present embodiment further satisfies the relationship of Tg ≧ 90. This makes it possible to further suppress the deterioration of the performance of the light emitting device 1 due to the underfill material 49.
　なお、本実施形態の発光装置１は、測距装置の光源として使用されているが、その他の態様で使用されてもよい。例えば、本実施形態の発光装置１は、プリンタなどの光学機器の光源として使用されてもよいし、照明装置として使用されてもよい。また、本実施形態のアンダーフィル材４９は、発光装置１以外の半導体装置や、発光素子５３以外の半導体装置の構成部分に対して使用されてもよい。 Although the light emitting device 1 of the present embodiment is used as a light source of the distance measuring device, it may be used in other embodiments. For example, the light emitting device 1 of the present embodiment may be used as a light source for an optical device such as a printer, or may be used as a lighting device. Further, the underfill material 49 of the present embodiment may be used for a semiconductor device other than the light emitting device 1 or a component portion of the semiconductor device other than the light emitting device 53.
　以上、本開示の実施形態について説明したが、本開示の実施形態は、本開示の要旨を逸脱しない範囲内で、種々の変更を加えて実施してもよい。例えば、いくつかの実施形態を組み合わせて実施してもよい。 Although the embodiments of the present disclosure have been described above, the embodiments of the present disclosure may be implemented with various modifications without departing from the gist of the present disclosure. For example, some embodiments may be combined and carried out.
　なお、本開示は、以下のような構成を取ることもできる。 Note that this disclosure can also have the following structure.
　（１）
　第１基板と、
　前記第１基板に対向している第２基板と、
　前記第１基板と前記第２基板との間に設けられた充填樹脂とを備え、
　前記充填樹脂のガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］は、
　　８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５
　の関係を満たす、半導体装置。 (1)
With the first board
The second board facing the first board and
A filling resin provided between the first substrate and the second substrate is provided.
The glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin are
80 ≦ Tp ≦ (Tg + 115) /1.5
A semiconductor device that satisfies the relationship.
　（２）
　前記充填樹脂の前記ガラス転移温度Ｔｇ［℃］は、
　　Ｔｇ≧９０
　の関係を満たす、（１）に記載の半導体装置。 (2)
The glass transition temperature Tg [° C.] of the filling resin is
Tg ≧ 90
The semiconductor device according to (1), which satisfies the above relationship.
　（３）
　前記充填樹脂は、アクリル系樹脂である、（１）に記載の半導体装置。 (3)
The semiconductor device according to (1), wherein the filling resin is an acrylic resin.
　（４）
　前記第１基板と前記第２基板は、異なる線膨張係数を有する、（１）に記載の半導体装置。 (4)
The semiconductor device according to (1), wherein the first substrate and the second substrate have different coefficients of linear expansion.
　（５）
　前記第１基板と前記第２基板の前記線膨張係数の差は、２．０×１０－６［１／Ｋ］以上である、（４）に記載の半導体装置。 (5)
The semiconductor device according to (4), wherein the difference in the coefficient of linear expansion between the first substrate and the second substrate is 2.0 × 10 -6 [1 / K] or more.
　（６）
　前記第１基板は、ガリウム（Ｇａ）およびヒ素（Ａｓ）を含む半導体基板である、（１）に記載の半導体装置。 (6)
The semiconductor device according to (1), wherein the first substrate is a semiconductor substrate containing gallium (Ga) and arsenic (As).
　（７）
　前記第２基板は、シリコン（Ｓｉ）を含む半導体基板である、（１）に記載の半導体装置。 (7)
The semiconductor device according to (1), wherein the second substrate is a semiconductor substrate containing silicon (Si).
　（８）
　前記第１基板の第１面に対して突出した複数の突出部をさらに備え、
　前記第２基板は、前記第１基板の前記第１面に対向している、（１）に記載の半導体装置。 (8)
A plurality of protrusions protruding from the first surface of the first substrate are further provided.
The semiconductor device according to (1), wherein the second substrate faces the first surface of the first substrate.
　（９）
　前記突出部は、前記第１基板の前記第１面から第２面に光を出射する発光素子を含む、（８）に記載の半導体装置。 (9)
The semiconductor device according to (8), wherein the protruding portion includes a light emitting element that emits light from the first surface to the second surface of the first substrate.
　（１０）
　前記突出部は、前記第１基板側と前記第２基板側とを電気的に接続する接続部を含む、（８）に記載の半導体装置。 (10)
The semiconductor device according to (8), wherein the protruding portion includes a connecting portion that electrically connects the first substrate side and the second substrate side.
　（１１）
　前記接続部は、半田またはバンプを含む、（１０）に記載の半導体装置。 (11)
The semiconductor device according to (10), wherein the connection portion includes solder or bumps.
　（１２）
　前記第１基板の第２面に、前記第１基板の一部として設けられた複数のレンズをさらに備える、（８）に記載の半導体装置。 (12)
The semiconductor device according to (8), further comprising a plurality of lenses provided as a part of the first substrate on the second surface of the first substrate.
　（１３）
　第１基板と第２基板とを互いに対向するように配置し、
　前記第１基板と前記第２基板との間に充填樹脂を形成する、
　ことを含み、
　前記充填樹脂のガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］は、
　　８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５
　の関係を満たす、半導体装置の製造方法。 (13)
The first substrate and the second substrate are arranged so as to face each other.
A filling resin is formed between the first substrate and the second substrate.
Including that
The glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin are
80 ≦ Tp ≦ (Tg + 115) /1.5
A method for manufacturing a semiconductor device that satisfies the above relationship.
　（１４）
　前記充填樹脂の前記ガラス転移温度Ｔｇ［℃］は、
　　Ｔｇ≧９０
　の関係を満たす、（１３）に記載の半導体装置の製造方法。 (14)
The glass transition temperature Tg [° C.] of the filling resin is
Tg ≧ 90
The method for manufacturing a semiconductor device according to (13), which satisfies the above relationship.
　（１５）
　前記第１基板と前記第２基板との間の前記充填樹脂を熱硬化させることをさらに含み、
　前記充填樹脂は、１７０～２２０℃で熱硬化される、（１３）に記載の半導体装置の製造方法。 (15)
Further comprising thermosetting the filling resin between the first substrate and the second substrate.
The method for manufacturing a semiconductor device according to (13), wherein the filling resin is thermoset at 170 to 220 ° C.
　（１６）
　前記第１基板の第１面に対して突出した複数の突出部を形成することをさらに含み、
　前記第２基板は、前記第１基板の前記第１面に対向するように配置される、（１３）に記載の半導体装置の製造方法。 (16)
Further comprising forming a plurality of protrusions with respect to the first surface of the first substrate.
The method for manufacturing a semiconductor device according to (13), wherein the second substrate is arranged so as to face the first surface of the first substrate.
　（１７）
　前記突出部に掛かる最大主応力は、１５０ＭＰａ以下である、（１６）に記載の半導体装置の製造方法。 (17)
The method for manufacturing a semiconductor device according to (16), wherein the maximum principal stress applied to the protrusion is 150 MPa or less.
　（１８）
　前記突出部は、前記第１基板側と前記第２基板側とを電気的に接続する接続部を含み、
　前記接続部の材料を前記第１基板と前記第２基板との間に供給して加熱により溶融させることで、前記第１基板側と前記第２基板側とを前記接続部により電気的に接続することをさらに含む、（１６）に記載の半導体装置の製造方法。 (18)
The protrusion includes a connection portion that electrically connects the first substrate side and the second substrate side.
By supplying the material of the connection portion between the first substrate and the second substrate and melting it by heating, the first substrate side and the second substrate side are electrically connected by the connection portion. The method for manufacturing a semiconductor device according to (16), further comprising the above.
　（１９）
　ガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］が、
　　８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５
　の関係を満たす、充填樹脂。 (19)
The glass transition temperature Tg [° C] and the curing temperature Tp [° C] are
80 ≦ Tp ≦ (Tg + 115) /1.5
Filling resin that satisfies the relationship.
　（２０）
　前記ガラス転移温度Ｔｇ［℃］が、
　　Ｔｇ≧９０
　の関係を満たす、（１９）に記載の充填樹脂。 (20)
The glass transition temperature Tg [° C.] is
Tg ≧ 90
The filling resin according to (19), which satisfies the above-mentioned relationship.
　１：発光装置、２：撮像装置、３：制御装置、
　１１：発光部、１２：駆動回路、１３：電源回路、１４：発光側光学系、
　２１：イメージセンサ、２２：画像処理部、２３：撮像側光学系、３１：測距部、
　４１：ＬＤチップ、４２：ＬＤＤ基板、４３：実装基板、
　４４：放熱基板、４５：補正レンズ保持部、４６：補正レンズ、
　４７：配線、４８：半田、４９：アンダーフィル材、
　５１：基板、５２：積層膜、５３：発光素子、５４：電極、
　５５：絶縁膜、５６：レンズ、６１：基板、６２：接続パッド 1: Light emitting device, 2: Image pickup device, 3: Control device,
11: Light emitting part, 12: Drive circuit, 13: Power supply circuit, 14: Light emitting side optical system,
21: Image sensor, 22: Image processing unit, 23: Imaging side optical system, 31: Distance measuring unit,
41: LD chip, 42: LDD board, 43: mounting board,
44: Heat dissipation board, 45: Correction lens holder, 46: Correction lens,
47: Wiring, 48: Solder, 49: Underfill material,
51: Substrate, 52: Laminated film, 53: Light emitting element, 54: Electrode,
55: Insulating film, 56: Lens, 61: Substrate, 62: Connection pad

Claims (20)

  1. 　第１基板と、
    　前記第１基板に対向している第２基板と、
    　前記第１基板と前記第２基板との間に設けられた充填樹脂とを備え、
    　前記充填樹脂のガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］は、
    　　８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５
    　の関係を満たす、半導体装置。     With the first board
    The second board facing the first board and
    A filling resin provided between the first substrate and the second substrate is provided.
    The glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin are
    80 ≦ Tp ≦ (Tg + 115) /1.5
    A semiconductor device that satisfies the relationship.
  2. 　前記充填樹脂の前記ガラス転移温度Ｔｇ［℃］は、
    　　Ｔｇ≧９０
    　の関係を満たす、請求項１に記載の半導体装置。     The glass transition temperature Tg [° C.] of the filling resin is
    Tg ≧ 90
    The semiconductor device according to claim 1, wherein the semiconductor device satisfies the above-mentioned relationship.
  3. 　前記充填樹脂は、アクリル系樹脂である、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the filling resin is an acrylic resin.
  4. 　前記第１基板と前記第２基板は、異なる線膨張係数を有する、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first substrate and the second substrate have different coefficient of linear expansion.
  5. 　前記第１基板と前記第２基板の前記線膨張係数の差は、２．０×１０－６［１／Ｋ］以上である、請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the difference between the linear expansion coefficients of the first substrate and the second substrate is 2.0 × 10 -6 [1 / K] or more.
  6. 　前記第１基板は、ガリウム（Ｇａ）およびヒ素（Ａｓ）を含む半導体基板である、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first substrate is a semiconductor substrate containing gallium (Ga) and arsenic (As).
  7. 　前記第２基板は、シリコン（Ｓｉ）を含む半導体基板である、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the second substrate is a semiconductor substrate containing silicon (Si).
  8. 　前記第１基板の第１面に対して突出した複数の突出部をさらに備え、
    　前記第２基板は、前記第１基板の前記第１面に対向している、請求項１に記載の半導体装置。     A plurality of protrusions protruding from the first surface of the first substrate are further provided.
    The semiconductor device according to claim 1, wherein the second substrate faces the first surface of the first substrate.
  9. 　前記突出部は、前記第１基板の前記第１面から第２面に光を出射する発光素子を含む、請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein the protruding portion includes a light emitting element that emits light from the first surface to the second surface of the first substrate.
  10. 　前記突出部は、前記第１基板側と前記第２基板側とを電気的に接続する接続部を含む、請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein the protruding portion includes a connecting portion that electrically connects the first substrate side and the second substrate side.
  11. 　前記接続部は、半田またはバンプを含む、請求項１０に記載の半導体装置。 The semiconductor device according to claim 10, wherein the connection portion includes solder or bumps.
  12. 　前記第１基板の第２面に、前記第１基板の一部として設けられた複数のレンズをさらに備える、請求項８に記載の半導体装置。 The semiconductor device according to claim 8, further comprising a plurality of lenses provided as a part of the first substrate on the second surface of the first substrate.
  13. 　第１基板と第２基板とを互いに対向するように配置し、
    　前記第１基板と前記第２基板との間に充填樹脂を形成する、
    　ことを含み、
    　前記充填樹脂のガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］は、
    　　８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５
    　の関係を満たす、半導体装置の製造方法。     The first substrate and the second substrate are arranged so as to face each other.
    A filling resin is formed between the first substrate and the second substrate.
    Including that
    The glass transition temperature Tg [° C.] and the curing temperature Tp [° C.] of the filling resin are
    80 ≦ Tp ≦ (Tg + 115) /1.5
    A method for manufacturing a semiconductor device that satisfies the above relationship.
  14. 　前記充填樹脂の前記ガラス転移温度Ｔｇ［℃］は、
    　　Ｔｇ≧９０
    　の関係を満たす、請求項１３に記載の半導体装置の製造方法。     The glass transition temperature Tg [° C.] of the filling resin is
    Tg ≧ 90
    13. The method for manufacturing a semiconductor device according to claim 13.
  15. 　前記第１基板と前記第２基板との間の前記充填樹脂を熱硬化させることをさらに含み、
    　前記充填樹脂は、１７０～２２０℃で熱硬化される、請求項１３に記載の半導体装置の製造方法。     Further comprising thermosetting the filling resin between the first substrate and the second substrate.
    The method for manufacturing a semiconductor device according to claim 13, wherein the filling resin is thermoset at 170 to 220 ° C.
  16. 　前記第１基板の第１面に対して突出した複数の突出部を形成することをさらに含み、
    　前記第２基板は、前記第１基板の前記第１面に対向するように配置される、請求項１３に記載の半導体装置の製造方法。     Further comprising forming a plurality of protrusions with respect to the first surface of the first substrate.
    The method for manufacturing a semiconductor device according to claim 13, wherein the second substrate is arranged so as to face the first surface of the first substrate.
  17. 　前記突出部に掛かる最大主応力は、１５０ＭＰａ以下である、請求項１６に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 16, wherein the maximum principal stress applied to the protruding portion is 150 MPa or less.
  18. 　前記突出部は、前記第１基板側と前記第２基板側とを電気的に接続する接続部を含み、
    　前記接続部の材料を前記第１基板と前記第２基板との間に供給して加熱により溶融させることで、前記第１基板側と前記第２基板側とを前記接続部により電気的に接続することをさらに含む、請求項１６に記載の半導体装置の製造方法。     The protrusion includes a connection portion that electrically connects the first substrate side and the second substrate side.
    By supplying the material of the connection portion between the first substrate and the second substrate and melting it by heating, the first substrate side and the second substrate side are electrically connected by the connection portion. The method for manufacturing a semiconductor device according to claim 16, further comprising the above.
  19. 　ガラス転移温度Ｔｇ［℃］と硬化温度Ｔｐ［℃］が、
    　　８０≦Ｔｐ≦（Ｔｇ＋１１５）／１．５
    　の関係を満たす、充填樹脂。     The glass transition temperature Tg [° C] and the curing temperature Tp [° C] are
    80 ≦ Tp ≦ (Tg + 115) /1.5
    Filling resin that satisfies the relationship.
  20. 　前記ガラス転移温度Ｔｇ［℃］が、
    　　Ｔｇ≧９０
    　の関係を満たす、請求項１９に記載の充填樹脂。     The glass transition temperature Tg [° C.] is
    Tg ≧ 90
    19. The filling resin according to claim 19.
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