WO2021254467A1 - 多链路设备的信道接入方法及相关装置 - Google Patents
多链路设备的信道接入方法及相关装置 Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W74/00—Wireless channel access
- H04W74/08—Non-scheduled access, e.g. ALOHA
- H04W74/0808—Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA]
- H04W74/0816—Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W74/00—Wireless channel access
- H04W74/08—Non-scheduled access, e.g. ALOHA
- H04W74/0833—Random access procedures, e.g. with 4-step access
- H04W74/0841—Random access procedures, e.g. with 4-step access with collision treatment
- H04W74/085—Random access procedures, e.g. with 4-step access with collision treatment collision avoidance
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W24/00—Supervisory, monitoring or testing arrangements
- H04W24/08—Testing, supervising or monitoring using real traffic
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W76/00—Connection management
- H04W76/10—Connection setup
- H04W76/15—Setup of multiple wireless link connections
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W84/00—Network topologies
- H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
- H04W84/10—Small scale networks; Flat hierarchical networks
- H04W84/12—WLAN [Wireless Local Area Networks]
Definitions
- FIG. 4 is a schematic flowchart of a channel access method for a multi-link device according to an embodiment of the present application
- AP multi-link devices can be communication entities such as communication servers, routers, switches, bridges, or AP multi-link devices can include various forms of macro base stations, micro base stations, relay stations, etc.
- AP multi-link devices It can also be the chip and processing system in these various forms of equipment.
- the multi-link device in the embodiment of the present application may be a device with a single antenna or a device with multiple antennas.
- it can be a device with more than two antennas.
- the embodiment of the present application does not limit the number of antennas included in the multi-link device.
- the multi-link device may allow services of the same access category (AC) to be transmitted on different links, and even allow the same data packet to be transmitted on different links; it may not be allowed. Services of the same access level are transmitted on different links, but services of different access levels are allowed to be transmitted on different links.
- AC access category
- CW contention window
- CWmin the minimum value, that is, CWmin.
- CWmax the maximum value of CW
- data transmission and transmission data generally refer to communication, where “data” generally refers to communication information, and is not limited to data information, and may also be signaling information.
- the above-mentioned first channel competition and the above-mentioned second channel competition are taken to distinguish two channel competitions.
- the two channel competitions ie, the first channel competition and the second channel competition
- the two channel competitions can be of the same type.
- Channel competition mechanism For example, the two channel competitions (that is, the first channel competition and the second channel competition) are both the CSMA/CA mechanism, or the two channel competitions are both the EDCA channel competition mechanism.
- the multilink device can use link2 to transmit data after the backoff counter on link2 reaches 0. After the state of link1 is restored to the idle state, the multi-link device can compete for the channel on link1 again, and use link1 to transmit data after the backoff counter of this channel contention has backed off to 0.
- FIG. 5c is a schematic diagram of a third type of sequence of multi-link channel access provided in an embodiment of the present application.
- the first link is link1 and the second link is link2.
- Multi-link devices compete for channels on two links (link1 and link2). Assuming that the multi-link device backs off to 0 on link1, the multi-link device suspends link1 and waits for the multi-link device to perform on link2 Channel competition. If link1 is waiting, the state of link1 becomes busy, and after the backoff counter on link2 is backed off to 0, the state of link1 is still busy.
- FIG. 6 is a schematic diagram of a single link and multiple channels provided by an embodiment of the present application.
- a single link may include N channels, where channel 1, channel 5, ..., channel N-3 are configured as channels for channel access.
- the foregoing first link and the foregoing second link may correspond to the first channel (such as channel 1) and the second channel (such as channel 5) in a single link multi-channel access scenario.
- the value of the contention window when the multi-link device competes for the channel again on the link is the same as the value of the contention window when the channel competed on the link last time; or the multi-link device is on the link again
- the value of the contention window during channel contention is the minimum value, that is, CWmin.
- the embodiments of the present application also provide corresponding devices or equipment.
- the above-mentioned processing unit 11 is further configured to: perform channel competition on the second link, and when the value of the backoff counter becomes 0 in the channel competition, detect the state of the first link; When the state of the first link is in the busy state, the second link is suspended; when the state of the first link changes from the busy state to the idle state, the processing unit 11 is used to perform operations on the first link The second channel competition.
- Multi-link devices including processors.
- the processor is configured to: perform a first channel contention on the first link, the initial value of the backoff counter in the first channel contention is determined based on the first value of the contention window; when the value of the backoff counter changes in the first channel contention When the value is 0 and the multilink device is not transmitting on the first link, the second channel contention is performed on the first link, and the initial value of the backoff counter in the second channel contention is based on the first value of the contention window.
- Two-value determination the second value of the competition window is equal to the first value of the competition window, or the second value of the competition window is equal to the minimum value of the competition window.
- the multi-link device described in the embodiment of the present application may be implemented by a general-purpose processor.
- a general-purpose processor that implements a multi-link device includes a processing circuit.
- the processing circuit is configured to: perform a first channel contention on the first link, and the initial value of the backoff counter in the first channel contention is determined based on the first value of the contention window; when the value of the backoff counter is in the first channel contention When it becomes 0 and the multi-link device is not transmitting on the first link, the second channel contention is performed on the first link, and the initial value of the backoff counter in the second channel contention is based on the contention window
- the second value determines that the second value of the competition window is equal to the first value of the competition window, or the second value of the competition window is equal to the minimum value of the competition window.
- the general-purpose processor may further include a storage medium for storing instructions executed by the processing circuit.
- the general-purpose processor may also include an input and output interface for internal connection and communication with the processing circuit. The input and output interface is used to support the communication between the general-purpose processor and other devices, for example: when the state of the second link is idle, data is transmitted in parallel on the first link and the second link ; Or, when the state of the first link is busy, data is transmitted on the second link.
- the multi-link device described in the embodiments of this application can also be implemented using the following: one or more FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device), control Any combination of devices, state machines, gate logic, discrete hardware components, any other suitable circuits, or circuits capable of performing the various functions described throughout this application.
- FPGA Field Programmable Gate Array
- PLD Programmable Logic Device
- the embodiment of the present application also provides a communication device, which may exist in the form of a chip product.
- the structure of the device includes a processor and an interface circuit.
- the processor is used to communicate with other devices through the interface circuit so that the device executes the foregoing The method in the embodiment.
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Abstract
Description
AC(接入等级) | CWmin | CWmax | AIFSN(仲裁帧间距数) |
AC_BK | 31 | 1023 | 7 |
AC_BE | 31 | 1023 | 3 |
AC_VI | 15 | 31 | 2 |
AC_VO | 7 | 15 | 2 |
legacy(遗留) | 15 | 1023 | 2 |
Claims (20)
- 一种多链路设备的信道接入方法,其特征在于,包括:多链路设备在第一链路上进行第一信道竞争,所述第一信道竞争中退避计数器的初始值基于竞争窗口的第一值确定;在所述第一信道竞争中所述退避计数器的值变为0且所述多链路设备未在所述第一链路上进行传输的情况下,所述多链路设备在所述第一链路上进行第二信道竞争,所述第二信道竞争中所述退避计数器的初始值基于所述竞争窗口的第二值确定,所述竞争窗口的第二值等于所述竞争窗口的第一值、或者所述竞争窗口的第二值等于所述竞争窗口的最小值。
- 根据权利要求1所述的方法,其特征在于,所述多链路设备未在所述第一链路上进行传输包括:当所述第一链路等待第二链路上进行信道竞争的时间超过预设时间时,所述第二链路的状态为繁忙状态。
- 根据权利要求1所述的方法,其特征在于,所述多链路设备未在所述第一链路上进行传输包括:当所述第一信道竞争中所述退避计数器的值变为0后,所述多链路设备在第二链路上接收到的数据包的长度超过预设时间。
- 根据权利要求2或3所述的方法,其特征在于,所述第一链路与所述第二链路之间不支持同时发送和接收STR。
- 根据权利要求1-4任一项所述的方法,其特征在于,所述多链路设备在第一链路上进行第二信道竞争之前,所述方法还包括:所述多链路设备检测所述第一链路在第一时间段内的状态;若所述第一链路在所述第一时间段内的状态为空闲状态,则所述多链路设备将竞争窗口的第一值确定为第二值,或将所述竞争窗口的第二值确定为所述竞争窗口的最小值。
- 根据权利要求1-5任一项所述的方法,其特征在于,所述多链路设备在所述第一链路上进行第二信道竞争之前,所述方法还包括:所述多链路设备在第二链路上进行信道竞争,并在所述信道竞争中所述退避计数器的值变为0时,检测所述第一链路的状态;若所述第一链路的状态为繁忙状态,则所述多链路设备挂起所述第二链路;当所述第一链路的状态从繁忙状态变为空闲状态时,触发所述多链路设备执行在所述第一链路上进行第二信道竞争。
- 根据权利要求6所述的方法,其特征在于,所述多链路设备在所述第一链路上进行第二信道竞争之后,所述方法还包括:当所述第二信道竞争中所述退避计数器的值变为0时,所述多链路设备检测所述第二链路的状态;若所述第二链路的状态为空闲状态,则所述多链路设备在所述第一链路和所述第二链路上并行传输数据。
- 根据权利要求1-5任一项所述的方法,其特征在于,所述多链路设备在所述第一链路上进行第二信道竞争之前,所述方法还包括:所述多链路设备在第二链路上进行信道竞争,并在所述信道竞争中所述退避计数器的 值变为0时,检测所述第一链路的状态;若所述第一链路的状态为繁忙状态,则所述多链路设备在所述第二链路上传输数据。
- 一种通信装置,其特征在于,应用于多链路设备中,包括:处理单元,用于在第一链路上进行第一信道竞争,所述第一信道竞争中退避计数器的初始值基于竞争窗口的第一值确定;在所述第一信道竞争中所述退避计数器的值变为0且所述多链路设备未在所述第一链路上进行传输的情况下,所述处理单元还用于在所述第一链路上进行第二信道竞争,所述第二信道竞争中所述退避计数器的初始值基于所述竞争窗口的第二值确定,所述竞争窗口的第二值等于所述竞争窗口的第一值、或者所述竞争窗口的第二值等于所述竞争窗口的最小值。
- 根据权利要求9所述的通信装置,其特征在于,所述多链路设备未在所述第一链路上进行传输包括:当所述第一链路等待第二链路上进行信道竞争的时间超过预设时间时,所述第二链路的状态为繁忙状态。
- 根据权利要求9所述的通信装置,其特征在于,所述多链路设备未在所述第一链路上进行传输包括:当所述第一信道竞争中所述退避计数器的值变为0后,所述多链路设备在第二链路上接收到的数据包的长度超过预设时间。
- 根据权利要求10或11所述的通信装置,其特征在于,所述第一链路与所述第二链路之间不支持同时发送和接收STR。
- 根据权利要求9-12任一项所述的通信装置,其特征在于,所述处理单元,还用于:检测所述第一链路在第一时间段内的状态;当所述第一链路在所述第一时间段内的状态为空闲状态时,将竞争窗口的第一值确定为第二值,或将所述竞争窗口的第二值确定为所述竞争窗口的最小值。
- 根据权利要求9-13任一项所述的通信装置,其特征在于,所述处理单元,还用于:在第二链路上进行信道竞争,并在所述信道竞争中所述退避计数器的值变为0时,检测所述第一链路的状态;当所述第一链路的状态为繁忙状态时,挂起所述第二链路;当所述第一链路的状态从繁忙状态变为空闲状态时,所述处理单元用于在所述第一链路上进行第二信道竞争。
- 根据权利要求14所述的通信装置,其特征在于,所述处理单元,还用于当所述第二信道竞争中所述退避计数器的值变为0时,所述多链路设备检测所述第二链路的状态;所述通信装置还包括收发单元,用于当所述第二链路的状态为空闲状态时,在所述第一链路和所述第二链路上并行传输数据。
- 根据权利要求9-13任一项所述的通信装置,其特征在于,所述处理单元,还用于在第二链路上进行信道竞争,并在所述信道竞争中所述退避计数器的值变为0时,检测所述第一链路的状态;所述通信装置还包括收发单元,用于当所述第一链路的状态为繁忙状态时,在所述第二链路上传输数据。
- 一种通信装置,其特征在于,包括处理器,所述处理器用于:在第一链路上进行第一信道竞争,所述第一信道竞争中退避计数器的初始值基于竞争窗口的第一值确定;在所述第一信道竞争中所述退避计数器的值变为0且多链路设备未在所述第一链路上进行传输的情况下,在所述第一链路上进行第二信道竞争,所述第二信道竞争中所述退避计数器的初始值基于所述竞争窗口的第二值确定,所述竞争窗口的第二值等于所述竞争窗口的第一值、或者所述竞争窗口的第二值等于所述竞争窗口的最小值。
- 一种计算机可读存储介质,所述计算机可读存储介质中存储有指令,当所述指令在计算机上运行时,使得所述计算机执行如权利要求1-8任一项所述的方法。
- 一种包含指令的计算机程序产品,当所述指令在计算机上运行时,使得所述计算机执行如权利要求1-8任一项所述的方法。
- 一种芯片或芯片系统,包括处理电路,所述处理电路用于执行如权利要求1-8任一项所述的方法。
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EP21826058.6A EP4156836A4 (en) | 2020-06-18 | 2021-06-18 | CHANNEL ACCESS METHOD FOR A MULTILINK DEVICE AND ASSOCIATED APPARATUS |
AU2021292120A AU2021292120B2 (en) | 2020-06-18 | 2021-06-18 | Channel access method for multi-link device, and related apparatus |
MX2022016558A MX2022016558A (es) | 2020-06-18 | 2021-06-18 | Método de acceso a canal para dispositivo multienlace y aparato relacionado. |
CA3183213A CA3183213A1 (en) | 2020-06-18 | 2021-06-18 | Channel access method for multi-link device, and related apparatus |
JP2022577686A JP7379733B2 (ja) | 2020-06-18 | 2021-06-18 | マルチリンクデバイスのためのチャネルアクセス方法、および関連装置 |
BR112022025921A BR112022025921A2 (pt) | 2020-06-18 | 2021-06-18 | Método de acesso de canal para dispositivo multienlace, e aparelho relacionado |
US18/067,355 US20230121480A1 (en) | 2020-06-18 | 2022-12-16 | Channel access method for multi-link device, and related apparatus |
JP2023186594A JP2024014880A (ja) | 2020-06-18 | 2023-10-31 | マルチリンクデバイスのためのチャネルアクセス方法、および関連装置 |
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AU2021292120A1 (en) | 2023-02-02 |
CN116744468A (zh) | 2023-09-12 |
EP4156836A1 (en) | 2023-03-29 |
CN116744468B (zh) | 2024-04-26 |
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KR20230023790A (ko) | 2023-02-17 |
US20230121480A1 (en) | 2023-04-20 |
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BR112022025921A2 (pt) | 2023-03-14 |
JP7379733B2 (ja) | 2023-11-14 |
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