WO2021254467A1 - 多链路设备的信道接入方法及相关装置 - Google Patents

多链路设备的信道接入方法及相关装置 Download PDF

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Publication number
WO2021254467A1
WO2021254467A1 PCT/CN2021/100783 CN2021100783W WO2021254467A1 WO 2021254467 A1 WO2021254467 A1 WO 2021254467A1 CN 2021100783 W CN2021100783 W CN 2021100783W WO 2021254467 A1 WO2021254467 A1 WO 2021254467A1
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WIPO (PCT)
Prior art keywords
link
value
channel
contention
state
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Ceased
Application number
PCT/CN2021/100783
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English (en)
French (fr)
Chinese (zh)
Inventor
郭宇宸
李云波
李伊青
淦明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2022577686A priority Critical patent/JP7379733B2/ja
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP24202107.9A priority patent/EP4507441A3/en
Priority to MX2022016558A priority patent/MX2022016558A/es
Priority to CA3183213A priority patent/CA3183213A1/en
Priority to KR1020267009900A priority patent/KR20260049336A/ko
Priority to EP21826058.6A priority patent/EP4156836B1/en
Priority to AU2021292120A priority patent/AU2021292120B2/en
Priority to BR112022025921A priority patent/BR112022025921A2/pt
Priority to KR1020237001601A priority patent/KR102947686B1/ko
Priority to ES21826058T priority patent/ES3004658T3/es
Publication of WO2021254467A1 publication Critical patent/WO2021254467A1/zh
Priority to MX2025008495A priority patent/MX2025008495A/es
Priority to US18/067,355 priority patent/US12389463B2/en
Anticipated expiration legal-status Critical
Priority to JP2023186594A priority patent/JP7601989B2/ja
Priority to AU2024205784A priority patent/AU2024205784B2/en
Priority to JP2024211182A priority patent/JP7758837B2/ja
Priority to US19/273,538 priority patent/US20250351198A1/en
Priority to JP2025170332A priority patent/JP2025185084A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W74/00—Wireless channel access
    • H04W74/08—Non-scheduled access, e.g. ALOHA
    • H04W74/0808—Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA]
    • H04W74/0816—Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W74/00—Wireless channel access
    • H04W74/08—Non-scheduled access, e.g. ALOHA
    • H04W74/0833—Random access procedures, e.g. with 4-step access
    • H04W74/0841—Random access procedures, e.g. with 4-step access with collision treatment
    • H04W74/085—Random access procedures, e.g. with 4-step access with collision treatment collision avoidance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W24/00—Supervisory, monitoring or testing arrangements
    • H04W24/08—Testing, supervising or monitoring using real traffic
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W76/00—Connection management
    • H04W76/10—Connection setup
    • H04W76/15—Setup of multiple wireless link connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W84/00—Network topologies
    • H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
    • H04W84/10—Small scale networks; Flat hierarchical networks
    • H04W84/12—WLAN [Wireless Local Area Networks]

Definitions

  • FIG. 4 is a schematic flowchart of a channel access method for a multi-link device according to an embodiment of the present application
  • AP multi-link devices can be communication entities such as communication servers, routers, switches, bridges, or AP multi-link devices can include various forms of macro base stations, micro base stations, relay stations, etc.
  • AP multi-link devices It can also be the chip and processing system in these various forms of equipment.
  • the multi-link device in the embodiment of the present application may be a device with a single antenna or a device with multiple antennas.
  • it can be a device with more than two antennas.
  • the embodiment of the present application does not limit the number of antennas included in the multi-link device.
  • the multi-link device may allow services of the same access category (AC) to be transmitted on different links, and even allow the same data packet to be transmitted on different links; it may not be allowed. Services of the same access level are transmitted on different links, but services of different access levels are allowed to be transmitted on different links.
  • AC access category
  • CW contention window
  • CWmin the minimum value, that is, CWmin.
  • CWmax the maximum value of CW
  • data transmission and transmission data generally refer to communication, where “data” generally refers to communication information, and is not limited to data information, and may also be signaling information.
  • the above-mentioned first channel competition and the above-mentioned second channel competition are taken to distinguish two channel competitions.
  • the two channel competitions ie, the first channel competition and the second channel competition
  • the two channel competitions can be of the same type.
  • Channel competition mechanism For example, the two channel competitions (that is, the first channel competition and the second channel competition) are both the CSMA/CA mechanism, or the two channel competitions are both the EDCA channel competition mechanism.
  • the multilink device can use link2 to transmit data after the backoff counter on link2 reaches 0. After the state of link1 is restored to the idle state, the multi-link device can compete for the channel on link1 again, and use link1 to transmit data after the backoff counter of this channel contention has backed off to 0.
  • FIG. 5c is a schematic diagram of a third type of sequence of multi-link channel access provided in an embodiment of the present application.
  • the first link is link1 and the second link is link2.
  • Multi-link devices compete for channels on two links (link1 and link2). Assuming that the multi-link device backs off to 0 on link1, the multi-link device suspends link1 and waits for the multi-link device to perform on link2 Channel competition. If link1 is waiting, the state of link1 becomes busy, and after the backoff counter on link2 is backed off to 0, the state of link1 is still busy.
  • FIG. 6 is a schematic diagram of a single link and multiple channels provided by an embodiment of the present application.
  • a single link may include N channels, where channel 1, channel 5, ..., channel N-3 are configured as channels for channel access.
  • the foregoing first link and the foregoing second link may correspond to the first channel (such as channel 1) and the second channel (such as channel 5) in a single link multi-channel access scenario.
  • the value of the contention window when the multi-link device competes for the channel again on the link is the same as the value of the contention window when the channel competed on the link last time; or the multi-link device is on the link again
  • the value of the contention window during channel contention is the minimum value, that is, CWmin.
  • the embodiments of the present application also provide corresponding devices or equipment.
  • the above-mentioned processing unit 11 is further configured to: perform channel competition on the second link, and when the value of the backoff counter becomes 0 in the channel competition, detect the state of the first link; When the state of the first link is in the busy state, the second link is suspended; when the state of the first link changes from the busy state to the idle state, the processing unit 11 is used to perform operations on the first link The second channel competition.
  • Multi-link devices including processors.
  • the processor is configured to: perform a first channel contention on the first link, the initial value of the backoff counter in the first channel contention is determined based on the first value of the contention window; when the value of the backoff counter changes in the first channel contention When the value is 0 and the multilink device is not transmitting on the first link, the second channel contention is performed on the first link, and the initial value of the backoff counter in the second channel contention is based on the first value of the contention window.
  • Two-value determination the second value of the competition window is equal to the first value of the competition window, or the second value of the competition window is equal to the minimum value of the competition window.
  • the multi-link device described in the embodiment of the present application may be implemented by a general-purpose processor.
  • a general-purpose processor that implements a multi-link device includes a processing circuit.
  • the processing circuit is configured to: perform a first channel contention on the first link, and the initial value of the backoff counter in the first channel contention is determined based on the first value of the contention window; when the value of the backoff counter is in the first channel contention When it becomes 0 and the multi-link device is not transmitting on the first link, the second channel contention is performed on the first link, and the initial value of the backoff counter in the second channel contention is based on the contention window
  • the second value determines that the second value of the competition window is equal to the first value of the competition window, or the second value of the competition window is equal to the minimum value of the competition window.
  • the general-purpose processor may further include a storage medium for storing instructions executed by the processing circuit.
  • the general-purpose processor may also include an input and output interface for internal connection and communication with the processing circuit. The input and output interface is used to support the communication between the general-purpose processor and other devices, for example: when the state of the second link is idle, data is transmitted in parallel on the first link and the second link ; Or, when the state of the first link is busy, data is transmitted on the second link.
  • the multi-link device described in the embodiments of this application can also be implemented using the following: one or more FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device), control Any combination of devices, state machines, gate logic, discrete hardware components, any other suitable circuits, or circuits capable of performing the various functions described throughout this application.
  • FPGA Field Programmable Gate Array
  • PLD Programmable Logic Device
  • the embodiment of the present application also provides a communication device, which may exist in the form of a chip product.
  • the structure of the device includes a processor and an interface circuit.
  • the processor is used to communicate with other devices through the interface circuit so that the device executes the foregoing The method in the embodiment.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
PCT/CN2021/100783 2020-06-18 2021-06-18 多链路设备的信道接入方法及相关装置 Ceased WO2021254467A1 (zh)

Priority Applications (17)

Application Number Priority Date Filing Date Title
ES21826058T ES3004658T3 (en) 2020-06-18 2021-06-18 Channel access method for multi-link device and related apparatus
EP24202107.9A EP4507441A3 (en) 2020-06-18 2021-06-18 Channel access method for multi-link device, and related apparatus
MX2022016558A MX2022016558A (es) 2020-06-18 2021-06-18 Método de acceso a canal para dispositivo multienlace y aparato relacionado.
CA3183213A CA3183213A1 (en) 2020-06-18 2021-06-18 Channel access method for multi-link device, and related apparatus
KR1020267009900A KR20260049336A (ko) 2020-06-18 2021-06-18 멀티 링크 디바이스의 채널 접근 방법 및 관련 장치
EP21826058.6A EP4156836B1 (en) 2020-06-18 2021-06-18 Channel access method for multi-link device and related apparatus
AU2021292120A AU2021292120B2 (en) 2020-06-18 2021-06-18 Channel access method for multi-link device, and related apparatus
BR112022025921A BR112022025921A2 (pt) 2020-06-18 2021-06-18 Método de acesso de canal para dispositivo multienlace, e aparelho relacionado
KR1020237001601A KR102947686B1 (ko) 2020-06-18 2021-06-18 멀티 링크 디바이스의 채널 접근 방법 및 관련 장치
JP2022577686A JP7379733B2 (ja) 2020-06-18 2021-06-18 マルチリンクデバイスのためのチャネルアクセス方法、および関連装置
MX2025008495A MX2025008495A (es) 2020-06-18 2022-12-16 Metodo de acceso a canal para dispositivo multienlace y aparato relacionado
US18/067,355 US12389463B2 (en) 2020-06-18 2022-12-16 Channel access method for multi-link device, and related apparatus
JP2023186594A JP7601989B2 (ja) 2020-06-18 2023-10-31 マルチリンクデバイスのためのチャネルアクセス方法、および関連装置
AU2024205784A AU2024205784B2 (en) 2020-06-18 2024-08-15 Channel access method for multi-link device, and related apparatus
JP2024211182A JP7758837B2 (ja) 2020-06-18 2024-12-04 マルチリンクデバイスのためのチャネルアクセス方法、および関連装置
US19/273,538 US20250351198A1 (en) 2020-06-18 2025-07-18 Channel access method for multi-link device, and related apparatus
JP2025170332A JP2025185084A (ja) 2020-06-18 2025-10-08 マルチリンクデバイスのためのチャネルアクセス方法、および関連装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010562039.8A CN113825248A (zh) 2020-06-18 2020-06-18 多链路设备的信道接入方法及相关装置
CN202010562039.8 2020-06-18

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US18/067,355 Continuation US12389463B2 (en) 2020-06-18 2022-12-16 Channel access method for multi-link device, and related apparatus

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US (2) US12389463B2 (https=)
EP (2) EP4507441A3 (https=)
JP (4) JP7379733B2 (https=)
KR (2) KR20260049336A (https=)
CN (2) CN113825248A (https=)
AU (2) AU2021292120B2 (https=)
BR (1) BR112022025921A2 (https=)
CA (1) CA3183213A1 (https=)
ES (1) ES3004658T3 (https=)
MX (2) MX2022016558A (https=)
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JP2024014880A (ja) 2024-02-01
JP2023531435A (ja) 2023-07-24
CA3183213A1 (en) 2021-12-23
ES3004658T3 (en) 2025-03-12
MX2022016558A (es) 2023-04-14
EP4156836B1 (en) 2024-10-30
JP7758837B2 (ja) 2025-10-22
AU2021292120B2 (en) 2024-05-23
JP2025185084A (ja) 2025-12-18
US20230121480A1 (en) 2023-04-20
CN116744468B (zh) 2024-04-26
JP7379733B2 (ja) 2023-11-14
EP4507441A2 (en) 2025-02-12
KR20230023790A (ko) 2023-02-17
KR102947686B1 (ko) 2026-04-01
KR20260049336A (ko) 2026-04-13
EP4156836A4 (en) 2023-10-25
US12389463B2 (en) 2025-08-12
BR112022025921A2 (pt) 2023-03-14
MX2025008495A (es) 2025-08-01
JP2025028100A (ja) 2025-02-28
AU2024205784B2 (en) 2026-01-22
EP4156836A1 (en) 2023-03-29
JP7601989B2 (ja) 2024-12-17
CN116744468A (zh) 2023-09-12
EP4507441A3 (en) 2025-03-19
AU2024205784A1 (en) 2024-09-05
AU2021292120A1 (en) 2023-02-02
CN113825248A (zh) 2021-12-21
US20250351198A1 (en) 2025-11-13

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