WO2021253912A1

WO2021253912A1 - Chip packaging device, and electronic device

Info

Publication number: WO2021253912A1
Application number: PCT/CN2021/083617
Authority: WO
Inventors: 胡星; 虞学犬; 刘辰钧; 程维昶
Original assignee: 华为技术有限公司
Priority date: 2020-06-18
Filing date: 2021-03-29
Publication date: 2021-12-23
Also published as: CN113823622A

Abstract

The present application relates to the technical field of chip packaging and provides a chip packaging device, and an electronic device, capable of improving an EMI shielding effect of a chip packaging structure. The chip packaging device comprises a substrate and a chip provided on the substrate; the chip packaging device further comprises a solder resist layer and a packaging structure; the packaging structure is connected to the area, around the chip, of the substrate by means of a first adhesive layer; the solder resist layer is located on the surface, provided with the chip, of the substrate, and a hollow area is provided in a connection area between the packaging structure and the substrate on the solder resist layer; the first bonding layer is a conductive adhesive; or, the first bonding layer is a non-conductive adhesive having a dielectric constant greater than or equal to 7 and a loss factor greater than or equal to 0.02.

Description

Chip packaging devices and electronic equipment

This application claims the priority of a Chinese patent application submitted to the State Intellectual Property Office on June 18, 2020, the application number is 202010562083.9, and the invention title is "Chip Package Devices and Electronic Equipment", the entire content of which is incorporated into this application by reference .

Technical field

This application relates to the field of chip packaging technology, and in particular to a chip packaging device and electronic equipment.

Background technique

In the chip packaging structure, the chip (die) will generate electromagnetic interference (EMI). If the EMI is not shielded, it will cause various EMI problems and the problem of product radiation emission (RE) test exceeding the standard. Especially with the increase in chip integration and speed year by year, the external radiation of the chip is getting larger and larger, so improving the EMI shielding effect of the chip has become a hot spot of concern at present.

Summary of the invention

The embodiments of the present application provide a chip packaging device and electronic equipment, which can improve the shielding effect of the chip packaging structure on EMI.

The present application provides a chip package device, including a substrate and a chip arranged on the substrate; the chip package device further includes a solder resist layer and a package structure; the package structure is connected to the area of the substrate around the chip through a first adhesive layer; solder resist The layer is located on the surface of the substrate on the side where the chip is provided, and the solder resist layer is provided with a hollow area in the connection area between the package structure and the substrate; the first adhesive layer adopts conductive glue; or, the first adhesive layer adopts a dielectric constant greater than or A non-conductive adhesive equal to 7 and a loss factor greater than or equal to 0.02.

In the chip package device of the present application, on the one hand, the solder resist layer is located in the connection area of the package structure and the substrate by opening a window (that is, a hollow area is provided) to remove part or all of the low DK material solder resist located in the connection area On the other hand, non-conductive glue (DK≥7, DF≥0.02) is used between the package structure and the substrate, which can greatly increase the coupling plane capacitance density between the package structure and the substrate, and reduce the connection between the package structure and the substrate Impedance suppresses cavity resonance; or the packaging structure is directly connected to the substrate by means of conductive glue to form a shielding cavity; thus, the shielding effect of the cavity between the packaging structure and the substrate is improved, and electromagnetic interference and other problems are effectively solved.

In some possible implementation manners, the chip package device further includes a heat sink; the package structure includes a chip package cover; the chip package cover is connected to the area of the substrate around the chip through a first adhesive layer, and the first adhesive layer has a dielectric constant A non-conductive adhesive greater than or equal to 7 and a loss factor greater than or equal to 0.02; the chip packaging cover and the surface of the chip away from the substrate are connected through the first thermal conductive adhesive; the heat sink and the surface of the chip packaging cover away from the chip are connected through the second Thermal glue connection.

In this case, the solder resist layer is located in the connection area between the chip package cover and the substrate by opening a window (that is, a hollow area is provided) to remove part or all of the low-DK material solder resist located in the connection area; and in the chip package cover Non-conductive glue (DK≥7, DF≥0.02) is used between the chip package cover and the substrate, which can greatly increase the coupling plane capacitance density between the chip package cover and the substrate, reduce the connection impedance between the chip package cover and the substrate, and suppress the cavity Resonance; or the chip packaging cover is directly connected to the substrate by means of conductive glue to form a shielding cavity; thus, the shielding effect of the cavity between the chip packaging cover and the substrate is improved, and problems such as electromagnetic interference are effectively solved.

In some possible implementations, the chip packaging device further includes a heat sink; the packaging structure includes a chip packaging ring; the chip packaging ring is connected to the area of the substrate around the chip through the first adhesive layer; the heat sink is connected to the side of the chip away from the substrate. The surface is connected by a third thermally conductive adhesive, and the heat sink is connected with the surface of the chip packaging ring away from the substrate through the second adhesive layer; the second adhesive layer is made of conductive adhesive; or the second adhesive layer has a dielectric constant greater than Or equal to 7, and the loss factor is greater than or equal to 0.02 non-conductive adhesive.

In this case, by opening a window (ie, setting a hollow area) in the solder resist layer in the connection area between the chip package ring and the substrate, remove part or all of the low-DK material solder resist located in the connection area; and replace it in the chip package The non-conductive glue (DK≥7, DF≥0.02) is used between the substrate and the heat sink, which reduces the connection impedance between the heat sink and the substrate, improves the shielding effect of the cavity between the heat sink and the substrate, and effectively solves the problem. Problems such as electromagnetic interference.

In some possible implementations, both the first adhesive layer and the second adhesive layer are made of conductive glue; to ensure that the heat sink and the chip packaging ring to the substrate can be connected to the substrate with low impedance and form a relatively complete shielding cavity. Maximize the shielding effect of the cavity between the chip packaging ring and the substrate.

In some possible implementations, both the first adhesive layer and the second adhesive layer use non-conductive adhesives with a dielectric constant greater than or equal to 7 and a loss factor greater than or equal to 0.02; on the one hand, it can greatly improve the chip packaging ring. The coupling plane capacitance density between the chip packaging ring and the substrate reduces the connection impedance between the chip packaging ring and the substrate, and suppresses cavity resonance, thereby improving the cavity shielding effect between the chip packaging ring and the substrate; on the other hand, compared to the use of conductive glue In the long-term use process, the shielding effect is likely to be reduced due to aging, delamination, and electrochemical corrosion. The use of the above-mentioned non-conductive adhesive can effectively ensure the stability of the shielding effect between the chip packaging ring and the substrate.

In some possible implementation manners, the formation of the second adhesive layer has elasticity; in the process of bonding the heat sink through the second adhesive layer and the chip packaging ring, in the thickness direction (that is, the thickness direction of the chip packaging device) Tolerances generated on the above are absorbed.

In some possible implementations, the second adhesive layer includes a flexible material.

In some possible implementation manners, an elastic member is provided in the second adhesive layer.

In some possible implementations, the thickness of the first adhesive layer is less than or equal to 0.1 mm. In this case, the coupling plane capacitance density between the chip package structure and the substrate can be further improved, so that the plane parasitic inductance between the chip package structure and the substrate is reduced, and the connection impedance is reduced, which is more conducive to the chip package structure and the substrate. The shielding effect of the cavity between the substrates is improved.

In some possible implementation manners, the conductive glue used in the first adhesive layer includes at least one of conductive silver glue, nickel-carbon glue, and silver-copper glue.

In some possible implementation manners, the non-conductive adhesive used in the first adhesive layer includes at least one of silicone-based and epoxy-based non-conductive adhesives filled with high dielectric constant materials.

In some possible implementation manners, the conductive glue used in the second adhesive layer includes at least one of conductive foam and conductive silicone rubber.

In some possible implementation manners, the non-conductive adhesive used in the second adhesive layer includes at least one of foam-based and rubber-based non-conductive adhesives filled with high dielectric constant wave-absorbing powder.

In some possible implementations, the first bonding layer is a closed ring-shaped bonding pattern.

In some possible implementation manners, the first adhesive layer is provided with a plurality of adhesive patterns at intervals, and the distance between two adjacent adhesive patterns is less than or equal to one-tenth of the minimum wavelength of electromagnetic waves in the shielding frequency band; Avoid gap field leakage between two adjacent bonding patterns.

In some possible implementations, the hollow area is a continuous ring-shaped hollow pattern.

In some possible implementation manners, the hollow area includes a plurality of hollow patterns arranged at intervals.

An embodiment of the present application also provides an electronic device including a printed circuit board and a chip package device in any one of the foregoing possible implementation modes, and the chip package device is connected to the printed circuit board.

Description of the drawings

FIG. 1 is a schematic structural diagram of a chip package device provided by an embodiment of the application;

FIG. 2 is a schematic cross-sectional view of the chip package device of FIG. 1;

FIG. 3 is a schematic structural diagram of a solder resist layer in a chip package device provided by an embodiment of the application;

4 is a schematic structural diagram of a solder resist layer in a chip package device provided by an embodiment of the application;

FIG. 5 is a schematic structural diagram of a chip package device provided by an embodiment of the application;

FIG. 6 is a schematic structural diagram of a chip package device provided by an embodiment of the application;

FIG. 7 is a top view of the chip package device shown in FIG. 6;

FIG. 8 is a schematic structural diagram of a chip package device provided by an embodiment of the application.

detailed description

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be described clearly and completely in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are part of the embodiments of this application. , Not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

The terms "first" and "second" in the specification embodiments, claims and drawings of this application are only used for the purpose of distinguishing description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating Or imply the order. Similar words such as "connected" and "connected" are used to express the intercommunication or interaction between different components, which can include direct connection or indirect connection through other components. At least one (item)" refers to one or more, and "multiple" refers to two or more. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions, For example, it contains a series of steps or units. The method, system, product or device need not be limited to those clearly listed steps or units, but may include those that are not clearly listed or are inherent to these processes, methods, products or devices. Other steps or units. "Up", "Down", "Left", "Right", etc. are only used relative to the orientation of the parts in the drawings. These directional terms are relative concepts, and they are used to Relative to the description and clarification, it can be changed correspondingly according to the changes in the orientation of the components in the drawings.

An embodiment of the application provides an electronic device. The electronic device can be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet and other electronic products. The embodiments of the present application do not impose special restrictions on the specific form of the above-mentioned electronic equipment.

The electronic equipment includes a printed circuit board (PCB) and a chip package device connected to the printed circuit board.

The chip package device provided by the embodiment of the application has a high EMI shielding effect, and can effectively solve various electromagnetic interference problems; the specific arrangement structure of the chip package device provided by the embodiment of the application will be further described below.

For chip package devices, it can be divided into two types according to the packaging method: one is the packaging method that uses the chip packaging lid (lid) (ie the lid packaging method); the other is to shorten the heat conduction path and reduce the thermal resistance. A packaging method without a chip packaging cover (ie, a lidless packaging method); the chip packaging devices in the two packaging methods are described below through specific embodiments.

Example one

This embodiment provides a chip packaged device, the chip packaged device adopts lid packaging, as shown in FIGS. 1 and 2 (a schematic cross-sectional view of FIG. 1), the chip packaged device includes a substrate 1 and a chip disposed on the substrate 1 2. It is understandable that the chip 2 and the substrate 1 can be connected by flip-chip bonding, and of course can also be connected by wire bonding, which is not limited in this application, and FIG. 2 is only an illustration. Take the flip-chip connection method of the chip 2 and the substrate 1 as an example for description.

On this basis, as shown in FIG. 2, the chip package device further includes a chip package lid (lid) 4 (that is, the package structure, which is mostly made of metal materials). Wherein, the chip package cover 4 and the upper surface of the chip 2 (that is, the surface on the side facing away from the substrate 1) are connected by a first thermally conductive adhesive 61, and the chip package cover 4 is located around the chip 2 with the substrate 1 through the first adhesive layer 51 The first adhesive can be a conductive adhesive, or a non-conductive adhesive with a dielectric constant (DK) greater than or equal to 7, and a damping factor (DF) greater than or equal to 0.02; The non-conductive adhesives mentioned below all refer to non-conductive adhesives that meet DK≥7 and DF≥0.02.

In addition, the substrate 1 is provided with a solder resist layer 3 on the surface where the chip is provided, and the solder resist layer 3 is provided with a hollow area 31 in the connection area between the chip package cover 4 and the substrate 1 (refer to FIGS. 4 and 5). Illustratively, the solder resist layer 3 may be a green oil solder resist layer, but it is not limited to this, and may also be a solder resist layer of other colors.

It is understandable that the solder resist layer 3 is generally made of a low dielectric constant (DK) material (for example, acrylic oligomer), which acts as a protective layer and coats the area on the upper surface of the substrate 1 that does not need to be soldered to Play the role of protecting the substrate. Since the solder mask 3 is made of low-DK materials, the coupling plane capacitance density between the chip package cover 4 and the substrate 1 will be reduced, and the connection impedance between the chip package cover 4 and the substrate 1 will be higher, resulting in shielding of EMI The problem of inefficiency.

For the conductive glue used between the chip package cover 4 and the substrate 1, the conductive glue itself has very low connection impedance, and the conductive glue is generally doped with a large proportion of metal conductive particles, which can then be used between the chip package cover 4 and the substrate 1. An effective shielding cavity is formed between the substrates 1.

For the use of non-conductive glue (DK≥7, DF≥0.02) between the chip package cover 4 and the substrate 1, it can greatly increase the coupling plane capacitance density between the chip package cover and the substrate, and reduce the gap between the chip package cover and the substrate. The impedance is connected, and at the same time, part of the harmonic clutter generated in the cavity can be absorbed and the cavity resonance can be suppressed, thereby improving the cavity shielding effect between the chip package cover and the substrate.

To sum up, in the chip package device provided by this embodiment, on the one hand, by opening a window (that is, setting a hollow area) in the solder resist layer in the connection area between the chip package cover and the substrate, part or all of the connection area is removed. The solder resist of low DK material; on the other hand, non-conductive glue (DK≥7, DF≥0.02) is used between the chip package cover and the substrate, which can greatly increase the coupling plane capacitance density between the chip package cover and the substrate , Reduce the connection impedance of the chip package cover and the substrate to suppress cavity resonance; or directly connect the chip package cover to the substrate by means of conductive glue to form a shielding cavity; thereby improving the cavity shielding between the chip package cover and the substrate Effect, effectively solve the problem of electromagnetic interference.

As shown in Figure 3, in some chip packaging devices provided by this embodiment, a heat sink 7 may also be provided, and the heat sink 7 and the upper surface of the chip packaging cover 4 (that is, the surface on the side away from the substrate 1) pass through the second The thermally conductive adhesive 62 is connected, so that the heat emitted by the chip 2 can be transferred to the chip packaging cover 4 through the first thermally conductive adhesive 61, and then transferred from the chip packaging cover 4 to the heat sink 7 through the second thermally conductive adhesive 62 for heat dissipation.

The composition of the first thermally conductive adhesive 61 and the second thermally conductive adhesive 62 may be the same or different. This application does not specifically limit this, and can be selected and set according to actual needs. Illustratively, the first thermally conductive adhesive 61 and the second thermally conductive adhesive 62 may both adopt thermal interface material (thermal interface material, TIM).

It should be noted that the specific shape of the hollow area 31 on the solder resist layer 3 is not limited in this embodiment; for example, as shown in FIG. 4, in some possible implementation manners, the hollow area 31 may be continuous The ring-shaped hollow pattern, that is, the solder resist layer 3 is provided with a continuous ring-shaped hollow pattern along the connection area of the chip package cover 4 and the substrate 1 around the chip 2. For another example, as shown in FIG. 5, in some possible implementation manners, the hollow area 31 may include a plurality of hollow patterns arranged at intervals; that is, the connection area between the chip package cover 4 and the substrate 1 located around the chip 2 is scattered at intervals. There are multiple hollow patterns; of course, the shape of the hollow patterns can be selected and set according to actual needs, and this application does not limit this, for example, it may be a circle, a square, and the like.

In addition, the specific composition of the non-conductive glue or the conductive glue used for the first adhesive layer 51 is not limited in this embodiment.

Illustratively, in some possible implementation manners, the conductive adhesive used in the first adhesive layer 51 may be at least one of conductive silver adhesive, nickel-carbon adhesive, and silver-copper adhesive.

For example, in some embodiments, the first adhesive layer 51 may use conductive silver glue; for another example, in some embodiments, the first adhesive layer 51 may also use silver copper glue; for another example, in some embodiments , The first adhesive layer 5 can also be a mixture of nickel-carbon glue and silver-copper glue.

Illustratively, in some possible implementation manners, the non-conductive adhesive used in the first adhesive layer 51 may be at least one of silicone-based and epoxy-based non-conductive adhesives filled with high-DK materials.

For example, in some embodiments, the first adhesive layer 51 may be a silicone-based non-conductive glue filled with high DK materials; for another example, in some embodiments, the first adhesive layer 51 may be filled with high DK materials. For example, in some embodiments, the first adhesive layer 51 may be a silicone-based non-conductive adhesive filled with a high-DK material and an epoxy resin filled with a high-DK material. A mixture of non-conductive adhesives.

In the following, the use of non-conductive glue for the first adhesive layer 51 is taken as an example to further describe the first adhesive layer 51.

In some possible implementation manners, under the premise of ensuring the bonding effect between the chip package cover and the substrate, the thickness of the first bonding layer 51 may be set to be less than or equal to 0.1 mm (ie, ≤0.1 mm); in this case Next, the use of non-conductive glue between the chip package cover and the substrate to form a thinner adhesive layer can further increase the coupling plane capacitance density between the chip package cover and the substrate, thereby making the plane parasitic between the chip package cover and the substrate The inductance increases and the connection impedance decreases, which is more conducive to the improvement of the shielding effect of the cavity between the chip package cover and the substrate.

In addition, this embodiment does not impose excessive restrictions on the shape of the first adhesive layer 51, and it can be set according to actual needs.

For example, in some possible implementation manners, the first adhesive layer 51 may be a closed ring-shaped adhesive pattern; that is, a circle is provided along the connection area between the chip package cover 4 and the substrate 1 around the chip 2 Closed continuous loop bonding pattern connection.

For another example, in some possible implementation manners, the first bonding layer 51 may be provided with multiple bonding patterns at intervals; that is, in the connection area between the chip package cover 4 and the substrate 1 located around the chip 2, there are multiple bonding patterns. A bonding pattern.

In this case, in order to avoid leakage of the gap field between two adjacent bonding patterns as much as possible, in some embodiments, a plurality of spaced bonding patterns forming the first bonding layer 51 may be set, any phase The distance between two adjacent bonding patterns is less than or equal to one-tenth of the minimum wavelength of electromagnetic waves in the shielding frequency band.

Example two

This embodiment provides a chip packaged device, as shown in FIGS. 6 and 7 (a top view of FIG. 6), the chip packaged device adopts a lidless packaging method (that is, a windowed packaging method), and the chip packaged device includes a substrate 1 and a chip 2 arranged on the substrate 1. It is understandable that the chip 2 and the substrate 1 can be connected by flip-chip bonding, and of course can also be connected by wire bonding, which is not limited in this application, and FIG. 6 is only an illustration. Take the flip-chip connection method of the chip 2 and the substrate 1 as an example for description.

On this basis, as shown in FIG. 6 and FIG. 7, the chip packaging device includes a chip packaging ring (ring) R (that is, a packaging structure, which is mostly made of metal materials); the chip packaging ring R passes through the first adhesive layer 51 is connected to the area of the substrate 1 around the chip 2, and the first adhesive layer 51 can be made of conductive glue or non-conductive glue (DK≥7, DF≥0.02).

In addition, as shown in FIG. 6, the substrate 1 is provided with a solder resist layer 3 on the surface on the side where the chip 2 is provided, and the solder resist layer 3 is provided with a hollow area 31 (reference Figure 4, Figure 5). Illustratively, the solder resist layer 3 may be a green oil solder resist layer, but it is not limited to this, and may also be a solder resist layer of other colors.

It can be understood here that the solder resist layer 3 is generally made of a low-DK material (for example, acrylic oligomer), and it is used as a protective layer to coat the area on the upper surface of the substrate 1 that does not need to be soldered to the chip 2 to Play the role of protecting the substrate. Since the solder mask layer 3 uses low-DK materials, the coupling plane capacitance density between the chip packaging ring R and the substrate 1 will be reduced, resulting in a higher connection impedance between the chip packaging ring R and the substrate 1, resulting in a shielding efficiency for EMI The problem is not high.

In this case, it can be understood that by opening a window (ie, setting a hollow area) in the solder resist layer in the connection area between the chip package ring and the substrate, part or all of the low DK material solder resist located in the connection area is removed. It can avoid the problem of low capacitance density and high connection impedance of the coupling plane between the chip package ring and the substrate caused by the solder resist layer in the connection area between the chip package ring and the substrate, resulting in poor cavity shielding efficiency.

In addition, as shown in FIG. 8, in the lidless packaging method, the chip package device further includes a heat sink 7, and the heat sink 7 and the upper surface of the chip 2 (that is, the surface on the side facing away from the substrate 1) pass through a third thermal conductive glue 63 (for example, TIM can be used), and the heat sink 7 is connected to the upper surface of the chip packaging ring R (that is, the surface on the side away from the substrate 1) through the second adhesive layer 52; the second adhesive layer 52 can be Conductive glue, non-conductive glue (DK≥7, DF≥0.02) can also be used.

In this case, in the chip package device, the heat dissipated by the chip 2 is directly transferred to the heat sink 7 through the third thermal conductive glue 63 for heat dissipation; compared to the lid package method adopted in the first embodiment, the heat dissipation path is reduced , The thermal resistance is reduced, which is more favorable for heat dissipation; especially suitable for high-power, large-size, high-integration chip packaging devices.

In this embodiment, the first adhesive layer 51 may use one of conductive adhesive and non-conductive adhesive, and the second adhesive layer 52 may also use one of conductive adhesive and non-conductive adhesive; The types of adhesives used in the first adhesive layer 51 and the second adhesive layer 52 are not specifically limited, and can be selected and set according to actual needs.

For example, the first adhesive layer 51 and the second adhesive layer 52 may both use conductive adhesives, and both may use the same conductive adhesive or different conductive adhesives, which is not limited in this embodiment; for example, the first The first adhesive layer 51 and the second adhesive layer 52 can both be made of non-conductive glue, and both can use the same non-conductive glue or different non-conductive glues, which is not limited in this embodiment; for another example, the first One of the first bonding layer 51 and the second bonding layer 52 is made of conductive glue, and the other is made of non-conductive glue.

In some possible implementation manners, it may be provided that the first adhesive layer 51 and the second adhesive layer 52 may both use conductive glue to ensure that the heat sink 7 and the chip packaging ring R can be connected to the substrate 1 with low impedance grounding, and A relatively complete shielding cavity is formed to maximize the shielding effect of the cavity between the chip packaging ring and the substrate.

In some possible implementation manners, it may be provided that the first adhesive layer 51 and the second adhesive layer 52 may both use non-conductive glue; on the one hand, it can greatly increase the coupling plane capacitance density between the chip packaging ring and the substrate, and reduce The connection impedance between the small chip packaging ring and the substrate suppresses cavity resonance, thereby improving the shielding effect of the cavity between the chip packaging ring and the substrate; on the other hand, compared to the use of conductive glue, it is easy to break due to aging during long-term use As far as the shielding effect is reduced due to delamination and electrochemical corrosion, the use of the above-mentioned non-conductive adhesive can effectively ensure the stability of the shielding effect between the chip packaging ring and the substrate.

In summary, in the chip package device provided by this embodiment, on the one hand, by opening a window (ie, setting a hollow area) in the solder mask layer in the connection area between the chip package ring and the substrate, part or all of the connection area is removed. Low DK material solder resist; on the other hand, non-conductive glue (DK≥7, DF≥0.02) or conductive glue is used between the chip package and the substrate and the heat sink, thereby reducing the connection between the heat sink and the substrate Impedance improves the shielding effect of the cavity between the heat sink and the substrate, and effectively solves problems such as electromagnetic interference.

It should be noted that the specific shape of the hollow area 31 on the solder resist layer 3 is not made in this embodiment. The hollow area 31 may be a continuous ring-shaped hollow pattern, or may be a plurality of hollow patterns arranged at intervals; for details, reference may be made to FIGS. 3 and 4 and the related description in the first embodiment, which will not be repeated here.

In addition, the specific composition of the non-conductive glue or conductive glue used in the first adhesive layer 51 is not limited in this embodiment. For example, in some possible implementation manners, the first adhesive layer 51 may use one or more of conductive silver glue, nickel-carbon glue, and silver-copper glue; for another example, in some possible implementation manners, the first adhesive layer 51 The adhesive layer 51 may be a silicone-based or epoxy-based non-conductive adhesive filled with a high-DK material; for details, reference may be made to the relevant description in the first embodiment, which will not be repeated here.

Taking the use of non-conductive adhesive for the first adhesive layer 51 as an example, in some possible implementation manners, the thickness of the first adhesive layer 51 can be set to be less than or equal to 0.1 mm (that is, ≤0.1 mm). The use of high DK materials to form a thinner bonding layer can further increase the coupling plane capacitance density between the chip packaging ring and the substrate, thereby reducing the plane parasitic inductance and connection impedance between the chip packaging ring and the substrate. This is more conducive to the improvement of the shielding effect of the cavity between the chip packaging ring and the substrate.

In addition, the present application does not impose excessive restrictions on the shape of the first adhesive layer 51, and it can be set according to actual needs. For example, in some possible implementation manners, the first adhesive layer 51 may be a closed ring-shaped adhesive pattern. For another example, in some possible implementation manners, the first bonding layer 51 may be provided with a plurality of bonding patterns at intervals; of course, in this case, in order to avoid as much as possible a gap field between two adjacent bonding patterns For leakage, in some embodiments, a plurality of bonding patterns can be arranged at intervals, and the distance between any two adjacent bonding patterns is less than or equal to one-tenth of the minimum wavelength of electromagnetic waves in the shielding frequency band. For details, reference may be made to the related description in Embodiment 1, which will not be repeated here.

The specific arrangement of the second adhesive layer 52 in this embodiment will be further described below.

It is understandable that during the bonding process of the heat sink device 7 and the chip package ring R through the second bonding layer 52, a certain tolerance will be generated in the thickness direction (that is, the thickness direction of the chip package device). Based on this, in order to Absorption produces tolerances in the thickness direction. In some possible implementations, the second adhesive layer 52 can be set as a flexible layer, that is, the second adhesive layer 52 has elasticity.

In some possible implementation manners, a flexible material may be used in the second adhesive layer 52.

Illustratively, when the second adhesive layer 52 uses conductive glue, the conductive glue may include at least one of conductive foam and conductive silicone rubber. For example, the second adhesive layer 52 may be formed of conductive foam; for another example, the second adhesive layer 52 may also be formed of conductive silicone rubber; for another example, the second adhesive layer 52 may also be formed of conductive foam and conductive silicon. The rubber is mixed and formed.

Illustratively, when the second adhesive layer 52 adopts a non-conductive adhesive, the non-conductive adhesive may include at least one of a foam type and a rubber type non-conductive adhesive filled with high-dielectric constant wave-absorbing powder. For example, the second adhesive layer 52 can be made of foamed non-conductive adhesive filled with high-dielectric constant wave-absorbing powder; for another example, the second adhesive layer 52 can be made of foam-type non-conductive glue filled with high-dielectric constant wave-absorbing powder. Rubber-based non-conductive adhesive; for another example, the second adhesive layer 52 can be a foam-based non-conductive adhesive filled with high-dielectric constant wave-absorbing powder and a rubber-based non-conductive rubber filled with high-dielectric constant wave-absorbing powder. The glue is mixed to form.

In some possible implementation manners, an elastic member may be provided in the second adhesive layer 52; for example, a retractable structure such as a reed may be provided in the second adhesive layer 52.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A chip packaging device, characterized by comprising a substrate and a chip arranged on the substrate;

The chip packaging device further includes a solder resist layer and a packaging structure;

The packaging structure is connected to the area of the substrate located around the chip through a first adhesive layer;

The solder resist layer is located on the surface of the substrate on the side where the chip is provided, and the solder resist layer is provided with a hollow area in the connection area between the packaging structure and the substrate;

The first adhesive layer is made of conductive adhesive; or, the first adhesive layer is made of non-conductive adhesive with a dielectric constant greater than or equal to 7 and a loss factor greater than or equal to 0.02.
The chip package device according to claim 1, wherein the chip package device further comprises a heat sink, and the package structure comprises a chip package cover;

The chip package cover is connected to the area of the substrate located around the chip through the first adhesive layer, and the first adhesive layer has a dielectric constant greater than or equal to 7 and a loss factor greater than or equal to 0.02 Non-conductive glue;

The chip packaging cover and the surface of the chip on the side facing away from the substrate are connected by a first thermally conductive glue;

The heat sink device and the surface of the chip packaging cover away from the chip are connected by a second thermally conductive glue.
The chip package device according to claim 1, wherein the chip package device further comprises a heat sink, and the package structure comprises a chip package ring;

The chip packaging ring is connected to the area of the substrate located around the chip through the first adhesive layer;

The heat sink is connected to the surface of the chip on the side away from the substrate through a third thermally conductive adhesive, and the heat sink is connected to the surface of the chip packaging ring on the side away from the substrate through a second adhesive layer;

The second adhesive layer is made of conductive adhesive; or, the second adhesive layer is made of non-conductive adhesive with a dielectric constant greater than or equal to 7 and a loss factor greater than or equal to 0.02.
The chip package device according to claim 3, wherein:

Both the first adhesive layer and the second adhesive layer are made of conductive glue;

Alternatively, both the first adhesive layer and the second adhesive layer use a non-conductive adhesive with a dielectric constant greater than or equal to 7 and a loss factor greater than or equal to 0.02.
The chip package device according to claim 3, wherein:

The second adhesive layer has elasticity.
The chip package device according to any one of claims 1-5, wherein:

The thickness of the first adhesive layer is less than or equal to 0.1 mm.
The chip package device according to any one of claims 1-6, wherein:

The conductive glue used in the first adhesive layer includes at least one of conductive silver glue, nickel-carbon glue, and silver-copper glue;

Alternatively, the non-conductive adhesive used in the first adhesive layer includes at least one of silicone-based and epoxy-based non-conductive adhesives filled with high dielectric constant materials.
The chip package device according to any one of claims 3-7, wherein:

The conductive glue used in the second adhesive layer includes at least one of conductive foam and conductive silicone rubber;

Alternatively, the non-conductive adhesive used in the second adhesive layer includes at least one of foamed and rubber-based non-conductive adhesives filled with high dielectric constant wave-absorbing powder.
The chip package device of claims 1-8, wherein:

The first bonding layer is a closed ring-shaped bonding pattern;

Alternatively, the first bonding layer has a plurality of bonding patterns arranged at intervals, and the distance between two adjacent bonding patterns is less than or equal to one-tenth of the minimum wavelength of electromagnetic waves in the shielding frequency band.
The chip package device according to any one of claims 1-9, wherein:

The hollow area is a continuous ring-shaped hollow pattern;

Alternatively, the hollow area includes a plurality of hollow patterns arranged at intervals.
An electronic device, characterized by comprising a printed circuit board and the chip package device according to any one of claims 1-10, and the chip package device is connected to the printed circuit board.