WO2021251206A1 - 学習装置、推論装置、およびプログラマブルロジックデバイスの開発用ツールチェーン - Google Patents

学習装置、推論装置、およびプログラマブルロジックデバイスの開発用ツールチェーン Download PDF

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WO2021251206A1
WO2021251206A1 PCT/JP2021/020784 JP2021020784W WO2021251206A1 WO 2021251206 A1 WO2021251206 A1 WO 2021251206A1 JP 2021020784 W JP2021020784 W JP 2021020784W WO 2021251206 A1 WO2021251206 A1 WO 2021251206A1
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programmable logic
technology
routing
placement
learning
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French (fr)
Japanese (ja)
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敦弘 森
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to US17/920,848 priority Critical patent/US12380264B2/en
Priority to JP2022530483A priority patent/JP7466643B2/ja
Priority to CN202180039757.XA priority patent/CN115699010A/zh
Publication of WO2021251206A1 publication Critical patent/WO2021251206A1/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/337—Design optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Definitions

  • This disclosure relates to a toolchain for developing learning devices, inference devices, and programmable logic devices.
  • Patent Document 1 in an EDA tool for semiconductor circuit design, in order to improve performance, a feature vector of the circuit is extracted and a feature amount library is referred to to generate a first placement and routing topology recommended by the tool. do. Patent Document 1 describes a method for generating yet another recommended placement and routing topology based on the first placement and routing topology.
  • Patent Document 1 an appropriate topology for placement and routing is recommended by obtaining the feature amount of the circuit.
  • the method described in Patent Document 1 is specialized in ASIC circuit design, and its application to programmable logic devices is not considered.
  • An object of the present disclosure is to provide a learning device, an inference device, and a tool chain for developing a programmable logic device that can realize high-speed placement and routing when developing a user application circuit using a programmable logic device. ..
  • the learning device of the present disclosure is programmable in resource utilization data for each technology and timing slack information at the time of technology mapping, and resource utilization data for each technology and timing slack information at the time of technology mapping in the tool chain for developing programmable logic devices.
  • a data acquisition unit that acquires training data including the target clock frequency and parameters for iterative synthesis of the toolchain for developing logic devices, and resources for each technology in the toolchain for developing programmable logic devices using the training data. It is equipped with a model generator that generates a trained model for inferring parameters for iterative synthesis given to the toolchain for developing programmable logic devices for successful placement and routing from utilization data and timing slack information during technology mapping. ..
  • the inference device of the present disclosure includes a data acquisition unit that acquires resource utilization data for each technology and timing slack information at the time of technology mapping in a tool chain for developing programmable logic devices, and resource utilization data for each technology and at the time of technology mapping.
  • Resource usage rate for each technology acquired by the data acquisition unit using a trained model for inferring the parameters for iterative synthesis given to the toolchain for developing programmable logic devices for successful placement and routing from the timing slack information of It is equipped with an inference unit that outputs parameters for iterative synthesis for successful placement and routing from timing slack information during data and technology mapping.
  • the learning device of the present disclosure includes a target clock frequency of a toolchain for developing a programmable logic device, parameters for iterative synthesis, resource utilization data for each technology of the toolchain for developing a programmable logic device, and timing at the time of technology mapping.
  • a data acquisition unit that acquires learning data including slack information, a target clock frequency of the tool chain for developing programmable logic devices using the learning data, parameters for iterative synthesis, and resource utilization data for each technology.
  • a model generator that generates a trained model for inferring the success probability of placement and routing from the timing slack information at the time of technology mapping.
  • the inference device of the present disclosure includes a target clock frequency of a toolchain for developing a programmable logic device, parameters for iterative synthesis, resource utilization data for each technology of the toolchain for developing a programmable logic device, and timing at the time of technology mapping.
  • a target clock frequency of a toolchain for developing a programmable logic device parameters for iterative synthesis, resource utilization data for each technology of the toolchain for developing a programmable logic device, and timing at the time of technology mapping.
  • the success probability of placement and routing is output from the target clock frequency acquired by the data acquisition unit, the parameters for iterative synthesis, the resource usage rate data for each technology, and the timing slack information at the time of technology mapping. It has a reasoning unit.
  • FIG. 3 is a configuration diagram of a learning device 10 relating to a tool chain for developing a programmable logic device according to the first embodiment. It is a flowchart about the learning process of the learning apparatus 10 in Embodiment 1.
  • FIG. FIG. 3 is a configuration diagram of an inference device 30 relating to a tool chain for developing a programmable logic device according to the first embodiment. It is a flowchart which shows the inference procedure of the parameter for iterative synthesis by the inference apparatus 30 in Embodiment 1.
  • FIG. It is a figure which shows the structure of the learning apparatus 10A about the tool chain for development of the programmable logic device in Embodiment 2.
  • FIG. It is a flowchart about the learning process of the learning apparatus 10A in Embodiment 2.
  • FIG. It is a figure which shows the structure of the inference apparatus 30A which concerns on the tool chain for development of the programmable logic device in Embodiment 2.
  • FIG. It is a flowchart which shows the inference procedure of the success probability of the arrangement and wiring of the inference apparatus 30A in Embodiment 2.
  • FIG. 1 is a configuration diagram of a learning device 10 relating to a tool chain for developing a programmable logic device according to the first embodiment.
  • the learning device 10 includes a data acquisition unit 12 and a model generation unit 13.
  • the data acquisition unit 12 acquires the target clock frequency, the iterated synthesis parameter, the resource usage rate data for each technology, and the timing slack information at the time of technology mapping as learning data.
  • the target clock frequency is the target clock frequency at which the programmable logic device is actually operated.
  • Iterative synthesis means trying multiple placements and routings to achieve the target clock frequency after placement and routing.
  • the target clock frequency or a clock frequency higher than the target clock frequency is set as the center frequency X [MHz], and a range of the threshold ⁇ [MHz] is set on the lower side and the higher side of the frequency, that is, (X).
  • the range from ⁇ ) [MHz] to (X + ⁇ ) [MHz] is set, and the trial of placement and routing is repeated while changing the range by the step value ⁇ [MHz].
  • the number of repeated synthesis trials is (2 ⁇ / ⁇ + 1).
  • the parameters for iterative synthesis refer to the above X, ⁇ , and ⁇ .
  • the lower limit value (X- ⁇ ) is set to a value larger than the target clock frequency.
  • the resource usage data for each technology indicates the ratio of the number of usage to the available number for each of the various computational resources in the program logic device.
  • the resource usage data for each technology is, for example, the usage rate of the ALU (arithmetic logic unit) of LE (Logic Element) or PE (Processing Element), the usage rate of the multiplexer, and the adder as a result of the technology mapping of the programmable logic device. Includes usage of the subtractor, usage of the arithmetic shifter, and so on.
  • the model generation unit 13 uses the learning data including the target clock frequency acquired by the data acquisition unit 12, the parameters for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping, to be a programmable logic device. Learned to infer the parameters for iterative synthesis given to the development toolchain of programmable logic devices for successful placement and routing from resource utilization data for each technology in the development toolchain and timing slack information during technology mapping. Generate a model.
  • the parameters for iterative synthesis are the clock center frequency X [MHz] for performing the above-mentioned iterative synthesis, the threshold value ⁇ [MHz] for determining the frequency range on the low side and the high side of the frequency, and the change within the frequency range. It is a step value ⁇ [MHz] for repeating the trial of placement and routing while making it.
  • the "parameters for iterative synthesis for successful placement and routing" are the central clock frequency at which the circuit after placement and routing can achieve the desired signal processing performance, and the probability that each placement and routing result will be successful during execution of iterative synthesis. Is a combination of the threshold value ⁇ [MHz] and the step value ⁇ [MHz] so as to satisfy the condition that is the highest and the number of trials of placement and routing is the smallest.
  • the threshold ⁇ [MHz] and the step value The combination of ⁇ [MHz] is determined.
  • the maximum number of compute resources that can be used is not exceeded, the interconnect resources used do not exceed the maximum number of interconnect resources that can be used on the programmable logic device, and the signal propagation delay time between FFs (Flip Flops) is not exceeded. It is shown that the largest value among them does not exceed the cycle time determined by the target clock frequency.
  • a known algorithm such as supervised learning, unsupervised learning, or reinforcement learning can be used.
  • reinforcement learning an agent (behavior) in a certain environment observes the current state (environmental parameters) and decides the action to be taken. The environment changes dynamically depending on the behavior of the agent, and the agent is rewarded according to the change in the environment. The agent repeats this process and learns the action policy that gives the most reward through a series of actions.
  • Q-learning or TD learning Temporal Difference Learning
  • the general update formula of the action value function Q (s, a) is expressed by the formula (1).
  • st represents the state of the environment at time t. at represents the action at time t.
  • the state changes to st + 1 depending on the action at.
  • rt + 1 represents the reward received by the change of the state.
  • ⁇ represents the discount rate.
  • ⁇ represents the learning coefficient.
  • the range is 0 ⁇ ⁇ 1 and 0 ⁇ ⁇ 1.
  • the parameter for iterative synthesis is behavior at.
  • the resource usage data for each technology and the timing slack information at the time of technology mapping are in the state st.
  • Q-learning the best action at in the state st at time t is learned.
  • the action value Q of the action a having the highest Q value at time t + 1 is larger than the action value Q of the action a executed at time t, the action value Q is increased. However, in the opposite case, the action value Q is reduced. In other words, the action value function Q (s, a) is updated so that the action value Q of the action a at time t approaches the best action value at time t + 1. As a result, the best behavioral value in a certain environment is sequentially propagated to the behavioral value in the previous environment.
  • the model generation unit 13 includes a reward calculation unit 14 and a function update unit 15.
  • the reward calculation unit 14 calculates the reward based on the target clock frequency, the parameters for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping.
  • the reward calculation unit 14 calculates the reward r based on the result of the placement and routing. For example, the reward calculation unit 14 increases the reward r (for example, gives a reward of "1") when the placement and routing is successful, and decreases the reward r when the placement and routing fails (for example,). Give a reward of "-1".).
  • the reward calculation unit 14 increases the reward in proportion to the margin (%) of the usage rate of LE or PE in the programmable logic device when the placement and routing are successful, or the programmable logic device.
  • the reward is increased in proportion to the margin (%) of the interconnect resource in the programmable logic device, or the cycle time in the largest signal propagation delay time (critical path) between FFs (Flip Flop) in the programmable logic device.
  • the reward calculation unit 14 may increase the reward by combining a plurality of elements among the elements for increasing these three rewards (margin of arithmetic resource, margin of interconnect resource, timing margin of critical path). Also, if necessary, each element may be multiplied by a weighting factor to increase the reward.
  • the reward calculation unit 14 reduces the reward in proportion to the overflow degree of LE or PE in the programmable logic device, or reduces the reward in proportion to the overflow degree of the interconnect resource in the programmable logic device. If none of the resources are overflowing, the degree of timing violation (Negative Slack value) for the cycle time in the largest signal propagation delay time (critical path) between FFs (Flip Flops) in the programmable device. ) Or reduce the reward in proportion to the degree of all timing violations (Total Negative Slack value).
  • the reward calculation unit 14 may reduce the reward by combining a plurality of elements among the elements for reducing these three rewards (degree of overflow of arithmetic resources, degree of overflow of interconnect resources, degree of timing violation), and is also necessary. Depending on the situation, each element may be multiplied by a weighting factor to reduce the reward.
  • the function update unit 15 updates the function for determining the iterated synthesis parameter for successful placement and routing according to the reward calculated by the reward calculation unit 14, and outputs the function to the trained model storage unit 20.
  • the function update unit 15 uses the action value function Q (st, at) represented by the equation (1) as a function for calculating parameters for iterative synthesis for successful placement and routing. ..
  • the trained model storage unit 20 stores the action value function Q (st, at) updated by the function update unit 15, that is, the trained model.
  • FIG. 2 is a flowchart relating to the learning process of the learning device 10 according to the first embodiment.
  • step S101 the data acquisition unit 12 acquires the target clock frequency, the iterated synthesis parameter, the resource usage rate data for each technology, and the timing slack information at the time of technology mapping as learning data.
  • step S102 the model generation unit 13 calculates the reward based on the target clock frequency, the parameter for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping. Specifically, the reward calculation unit 14 acquires the target clock frequency, the parameter for iterated synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping, and increases the reward based on the result of the placement and routing. Decide whether to let or reduce. When the reward calculation unit 14 determines that the reward is to be increased, the process proceeds to step S103. When the reward calculation unit 14 determines that the reward is to be reduced, the process proceeds to step S104.
  • step S103 the reward calculation unit 14 increases the reward.
  • step S104 the reward calculation unit 14 reduces the reward.
  • step S105 the function update unit 15 creates an action value function Q (st, at) represented by the equation (1) stored in the trained model storage unit 20 based on the reward calculated by the reward calculation unit 14. Update.
  • the learning device 10 repeatedly executes the above steps S101 to S105, and stores the generated action value function Q (st, at) as a learned model.
  • the learning device 10 stores the trained model in the trained model storage unit 20 provided outside the learning device 10, but the trained model storage unit 20 is stored inside the learning device 10. You may be prepared for.
  • FIG. 3 is a configuration diagram of an inference device 30 relating to a tool chain for developing a programmable logic device according to the first embodiment.
  • the inference device 30 includes a data acquisition unit 31 and an inference unit 32.
  • the data acquisition unit 31 acquires resource usage data for each technology and timing slack information at the time of technology mapping.
  • the inference unit 32 develops a programmable logic device for successful placement and routing from the trained model storage unit 20 from the resource utilization data for each technology of the tool chain for developing the programmable logic device and the timing slack information at the time of technology mapping. Read the trained model for inferring the parameters for iterative synthesis given to the toolchain.
  • the inference unit 32 infers the parameters for iterative synthesis for successful placement and routing by using the data acquired by the data acquisition unit 31 and the trained model. That is, the inference unit 32 inputs the resource usage rate data for each technology acquired by the data acquisition unit 31 and the timing slack information at the time of technology mapping into the trained model, so that the resource usage rate data for each technology and the time of technology mapping are performed. It is possible to infer parameters for iterative synthesis for successful placement and routing suitable for the timing slack information of.
  • the inference unit 32 reads the action value function Q (st, at) from the trained model storage unit 20 as a trained model.
  • the inference unit 32 sets parameters for iterative synthesis (behavior at) based on the action value function Q (s, a) with respect to the resource utilization data for each technology and the timing slack information (state st) at the time of technology mapping. obtain.
  • the iterative synthesis parameter included in this action at is the iterative synthesis parameter for successful placement and routing.
  • the parameters for iterative synthesis for successful placement and routing are output using the trained model learned in the model generation unit 13 of the tool chain for developing a programmable logic device.
  • a trained model may be obtained from the development tool chain of the programmable logic device, and parameters for iterative synthesis for successful placement and routing may be output based on the trained model.
  • FIG. 4 is a flowchart showing the inference procedure of the parameters for iterative synthesis by the inference device 30 in the first embodiment.
  • step S201 the data acquisition unit 31 acquires resource usage data for each technology and timing slack information at the time of technology mapping.
  • step S202 the inference unit 32 inputs the resource usage rate data for each technology and the timing slack information at the time of technology mapping into the trained model stored in the trained model storage unit 20.
  • step S203 the inference unit 32 obtains the parameters for iterative synthesis for successful placement and routing from the trained model.
  • the inference unit 32 outputs the parameters for iterative synthesis for successful placement and routing to the tool chain for developing the programmable logic device.
  • step S204 the tool chain for developing the programmable logic device uses the output parameters for iterative synthesis for successful placement and routing and the circuit configuration information by technology mapping, and the actual PE (Processing Element) on the programmable device. ), LE (Logic Element), SRAM (Static Random Access Memory), and the trial of placement and routing using interconnect resources are repeated, that is, iterative synthesis is performed.
  • the composition constraint of the iterative synthesis is a parameter for iterative synthesis for succeeding the placement and routing output by step S203.
  • reinforcement learning is applied to the learning algorithm used by the inference unit, but the present invention is not limited to this.
  • learning algorithm in addition to reinforcement learning, supervised learning, unsupervised learning, semi-supervised learning, and the like can also be applied.
  • deep learning for learning the extraction of the feature amount itself can also be used.
  • machine learning may be performed according to other known methods such as neural networks, genetic programming, functional logic programming, or support vector machines.
  • the learning device 10 and the inference device 30 may be connected to, for example, a tool chain for developing a programmable logic device via a network, and may be devices separate from the tool chain for developing the programmable logic device. Further, the learning device 10 and the inference device 30 may be built in a tool chain for developing a programmable logic device. Further, the learning device 10 and the inference device 30 may exist on the cloud server.
  • the model generation unit 13 may learn the parameters for iterative synthesis for successful placement and routing by using the learning data acquired from the development tool chain of a plurality of programmable logic devices.
  • the model generation unit 13 may acquire learning data from a tool chain for developing a plurality of programmable logic devices used in the same place, or a plurality of programmable logic devices operating independently in different places. You may get the learning data from the development toolchain of. It is also possible to add or remove a toolchain for developing a programmable logic device that collects learning data from the target on the way. Furthermore, a learning device that has learned parameters for iterative synthesis for successful placement and routing for one programmable logic device development toolchain is applied to another programmable logic device development toolchain. The parameters for iterative synthesis for successful placement and routing may be relearned and updated with respect to the toolchain for developing programmable logic devices.
  • inference by artificial intelligence is performed in the process of repeatedly executing the placement and routing using the development tool chain of the programmable device and finding the clock and timing constraint conditions for successful placement and routing.
  • the clock center frequency and frequency range obtained from the results are used.
  • FIG. 5 is a diagram showing a configuration of a learning device 10A relating to a tool chain for developing a programmable logic device according to a second embodiment.
  • the learning device 10A includes a data acquisition unit 12A and a model generation unit 13A.
  • the data acquisition unit 12A acquires the clock frequency, the iterated synthesis parameter, the resource usage rate data for each technology, and the timing slack information at the time of technology mapping as learning data.
  • the model generation unit 13A is a learning data created based on a combination of the clock frequency output from the data acquisition unit 12A, the parameters for iterative synthesis, the resource usage rate data for each technology, and the timing slack information at the time of technology mapping. Learn the success rate of placement and routing based on. That is, a trained model that infers the success probability of placement and routing from the clock frequency of the toolchain for developing programmable logic devices, the parameters for iterated synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping is generated. ..
  • the learning data is data in which the clock frequency, the parameters for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping are associated with each other.
  • the trained model is the clock frequency at the time of successful placement and routing, parameters for iterative synthesis, resource utilization data for each technology, and timing slack during technology mapping. It is configured as a model for classifying (clustering) information, clock frequency when placement and routing fails, parameters for iterative synthesis, resource utilization data for each technology, and timing slack information at the time of technology mapping.
  • Unsupervised learning is a method of learning the features of the learning data by giving the learning data that does not include the result (label) to the learning device.
  • the model generation unit 13A learns the success probability of placement and routing by so-called unsupervised learning according to, for example, a grouping method based on the K-means method.
  • the K-means method is a non-hierarchical clustering algorithm, which is a method of classifying a given number of clusters into k using the average of clusters.
  • the K-means method is processed in the following flow. First, a cluster is randomly assigned to each data xi. Next, the center Vj of each cluster is calculated based on the allocated data. Then, the distance between each xi and each Vj is obtained, and xi is reassigned to the nearest central cluster. Then, when the allocation of all xi clusters does not change in the above process, or when the amount of change falls below a predetermined threshold value, it is determined that the process has converged and the process ends.
  • the learning data created based on the combination of the clock frequency acquired by the data acquisition unit 12A, the parameters for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping. Learn the success probability of placement and routing by unsupervised learning.
  • the model generation unit 13A generates and outputs a trained model by executing the above learning.
  • the trained model storage unit 20A stores the trained model output from the model generation unit 13A.
  • FIG. 6 is a flowchart relating to the learning process of the learning device 10A according to the second embodiment.
  • step S301 the data acquisition unit 12A acquires the clock frequency, the iterated synthesis parameter, the resource usage rate data for each technology, and the timing slack information at the time of technology mapping. It was assumed that the clock frequency, parameters for iterative synthesis, resource utilization data for each technology, and timing slack information at the time of technology mapping were acquired at the same time, but the clock frequency, parameters for iterative synthesis, resource utilization data for each technology, and It suffices if the timing slack information at the time of technology mapping can be input in association with each other. good.
  • step S302 the model generation unit 13A is created based on the combination of the clock frequency acquired by the data acquisition unit 12A, the parameters for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping. According to the training data, the success probability of placement and routing is learned by so-called unsupervised learning, and a trained model is generated.
  • step S303 the trained model storage unit 20A stores the trained model generated by the model generation unit 13A.
  • FIG. 7 is a diagram showing a configuration of an inference device 30A relating to a tool chain for developing a programmable logic device according to the second embodiment.
  • the inference device 30A includes a data acquisition unit 31A and an inference unit 32A.
  • the data acquisition unit 31A acquires clock frequency, iterated synthesis parameters, resource usage data for each technology, and timing slack information at the time of technology mapping.
  • the inference unit 32A infers the success probability of the placement and routing obtained by using the learned model stored in the learned model storage unit 20A. That is, the inference unit 32A inputs the clock frequency acquired by the data acquisition unit 31A, the parameter for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping into the trained model, thereby inputting the clock frequency. , Parameters for iterative synthesis, resource utilization data for each technology, and timing slack information at the time of technology mapping can be inferred to which cluster, and the inference result can be output as the success probability of placement and routing.
  • the inference unit 32A uses the clock frequency input to the trained model, parameters for iterative synthesis, resource utilization data for each technology, and timing slack during technology mapping. Determine if the information belongs to a cluster that indicates successful placement and routing or a cluster that indicates failure in placement and routing. Then, if it belongs to a cluster indicating the success of the placement and routing, the inference unit 32A infers that the placement and routing is successful. On the other hand, if it belongs to a cluster indicating a placement and routing failure, the inference unit infers that the placement and routing fails.
  • the inference unit 32A inputs the clock frequency acquired by the data acquisition unit 31A, the parameter for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping into the trained model, thereby inputting the clock frequency.
  • Parameters for iterative synthesis, resource utilization data for each technology, and timing slack information at the time of technology mapping may be inferred and output to the probability that they belong to the cluster indicating the success of placement and routing. For example, the smaller the distance between the clock frequency entered in the trained model, the parameters for iterative synthesis, the resource utilization data for each technology, and the timing slack information during technology mapping, and the center of gravity of the cluster indicating the success of the placement and routing. , The probability of belonging to a cluster indicating the success of placement and routing may be increased.
  • the model generation unit 13A uses the soft clustering method instead of the K-means method to generate a model that generates the probability of belonging to the cluster indicating the success of the placement and routing, and the inference unit 32A uses the soft clustering method. Then, the probability of belonging to the cluster indicating the success of the placement and routing may be inferred from the generated model.
  • the success probability of placement and routing is output using the trained model learned in the model generation part of the tool chain for developing a programmable logic device, but it is a tool for developing other programmable logic devices.
  • a trained model may be acquired from the outside such as a chain, and the success probability of placement and routing may be output based on this trained model.
  • the inference unit 32A determines the success probability of the placement and routing obtained based on the clock frequency, the parameter for iterated synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping of the programmable logic device.
  • FIG. 8 is a flowchart showing the inference procedure of the success probability of the placement and wiring of the inference device 30A in the second embodiment.
  • step S401 the data acquisition unit 31A acquires the clock frequency, the iterated synthesis parameter, the resource usage rate data for each technology, and the timing slack information at the time of technology mapping.
  • step S402 the inference unit 32A inputs the clock frequency, the parameter for iterative synthesis, the resource utilization data for each technology, and the timing slack information at the time of technology mapping into the trained model stored in the trained model storage unit 20A. , Obtain the success probability of placement and routing.
  • step S403 the inference unit 32A outputs the success probability of the placement and routing obtained by the trained model to the tool chain for developing the programmable logic device.
  • step S404 the tool chain for developing the programmable logic device considers the success probability of the output placement and routing, and actually PE (Processing Element), LE (Logic Element), SRAM (Static Random Access) on the programmable device. Repeated trials of placement and routing using Memory) and interconnect resources, that is, iterative synthesis. As a result, the success probability of placement and wiring can be displayed on a display device such as a display.
  • PE Processing Element
  • LE Logic Element
  • SRAM Static Random Access
  • the present invention is not limited to this.
  • the learning algorithm it is also possible to apply reinforcement learning, supervised learning, semi-supervised learning, or the like, in addition to unsupervised learning.
  • deep learning which learns the extraction of the feature amount itself, can be used, and other known methods may be used.
  • the learning device 10A and the inference device 30A are connected to, for example, a tool chain for developing a programmable logic device via a network, and are devices separate from the tool chain for developing the programmable logic device. May be good. Further, the learning device 10A and the inference device 30A may be built in a tool chain for developing a programmable logic device. Further, the learning device 10A and the inference device 30A may exist on the cloud server.
  • the model generation unit 13A may learn the success probability of placement and routing according to the learning data created for the development tool chain of a plurality of programmable logic devices.
  • the model generation unit 13A may acquire learning data from a tool chain for developing a plurality of programmable logic devices used in the same area, or may acquire learning data from a plurality of programmable logic devices that operate independently in different areas. You may learn the success probability of placement and routing by using the learning data collected from the development tool chain of. It is also possible to add or remove a toolchain for developing a programmable logic device that collects learning data from the target on the way.
  • a learning device that has learned the success probability of placement and routing for a tool chain for developing a programmable logic device is applied to a tool chain for developing another programmable logic device, and is used for developing another programmable logic device.
  • the success probability of placement and routing may be relearned and updated with respect to the tool chain.
  • FIG. 9 is a diagram showing a hardware configuration of a learning device 10, 10A, an inference device 30, 30A, or a tool chain 40 for developing a programmable logic device.
  • the learning device 10, 10A, the inference device 30, 30A, and the tool chain 40 for developing a programmable logic device can configure the corresponding operation with the hardware or software of the digital circuit.
  • the functions of the learning devices 10, 10A, the inference devices 30, 30A, and the tool chain 40 for developing the programmable logic device are realized by using software, the learning devices 10, 10A, the inference devices 30, 30A, and the programmable logic
  • the device development tool chain 40 includes, for example, a processor 51 connected by a bus 53 and a memory 52, as shown in FIG. 9, so that the processor 51 executes a program stored in the memory 52. Can be done.
  • 10,10A learning device 12,12A data acquisition unit, 13,13A model generation unit, 14 reward calculation unit, 15 function update unit, 20,20A learned model storage unit, 31,31A data acquisition unit, 32,32A inference Department, 40 Programmable logic device development tool chain, 51 processor, 52 memory, 53 bus.

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