CN115699010A - 学习装置、推理装置以及可编程逻辑器件的开发用工具链 - Google Patents

学习装置、推理装置以及可编程逻辑器件的开发用工具链 Download PDF

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Publication number
CN115699010A
CN115699010A CN202180039757.XA CN202180039757A CN115699010A CN 115699010 A CN115699010 A CN 115699010A CN 202180039757 A CN202180039757 A CN 202180039757A CN 115699010 A CN115699010 A CN 115699010A
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China
Prior art keywords
programmable logic
logic device
learning
time
data
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CN202180039757.XA
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Chinese (zh)
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森敦弘
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of CN115699010A publication Critical patent/CN115699010A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/337—Design optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Medical Informatics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Artificial Intelligence (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
CN202180039757.XA 2020-06-09 2021-06-01 学习装置、推理装置以及可编程逻辑器件的开发用工具链 Pending CN115699010A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020100016 2020-06-09
JP2020-100016 2020-06-09
PCT/JP2021/020784 WO2021251206A1 (ja) 2020-06-09 2021-06-01 学習装置、推論装置、およびプログラマブルロジックデバイスの開発用ツールチェーン

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CN115699010A true CN115699010A (zh) 2023-02-03

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US (1) US12380264B2 (https=)
JP (1) JP7466643B2 (https=)
CN (1) CN115699010A (https=)
WO (1) WO2021251206A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12353809B2 (en) * 2021-12-21 2025-07-08 Synopsys, Inc. Transformations for multicycle path prediction of clock signals
CN114371970B (zh) * 2022-01-10 2023-05-02 电子科技大学 一种基于图强化学习的fpga互联资源测试方法
US12561498B2 (en) * 2022-06-13 2026-02-24 Mitsubishi Electric Research Laboratories, Inc. GaN distributed RF power amplifier automation design with deep reinforcement learning

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JP2007538474A (ja) * 2004-05-19 2007-12-27 アルテラ コーポレイション 集積回路の性能を調整するための装置および方法
US8024675B1 (en) * 2006-08-04 2011-09-20 Tela Innovations, Inc. Method and system for wafer topography-aware integrated circuit design analysis and optimization
JP2016095606A (ja) * 2014-11-13 2016-05-26 国立大学法人電気通信大学 データ処理装置およびデータ処理方法、並びにプログラム
CN105930609A (zh) * 2016-05-04 2016-09-07 华中科技大学 一种用于相干解调的fpga时序优化方法
US9792397B1 (en) * 2017-01-08 2017-10-17 Alphaics Corporation System and method for designing system on chip (SoC) circuits through artificial intelligence and reinforcement learning
US20180165400A1 (en) * 2016-12-12 2018-06-14 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Method and Computer Program for Determining a Placement of at least one Circuit for a Reconfigurable Logic Device

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US7500216B1 (en) * 2007-02-07 2009-03-03 Altera Corporation Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines
US8365111B2 (en) * 2008-02-29 2013-01-29 Et International, Inc. Data driven logic simulation
US8347243B2 (en) * 2008-05-15 2013-01-01 Universiteit Gent Parameterized configuration for a programmable logic device
US9703920B2 (en) * 2015-06-30 2017-07-11 International Business Machines Corporation Intra-run design decision process for circuit synthesis
US10192016B2 (en) 2017-01-17 2019-01-29 Xilinx, Inc. Neural network based physical synthesis for circuit designs
US10437954B1 (en) 2017-06-30 2019-10-08 Cadence Design Systems, Inc. System and method for recommending integrated circuit placement and routing options

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007538474A (ja) * 2004-05-19 2007-12-27 アルテラ コーポレイション 集積回路の性能を調整するための装置および方法
US8024675B1 (en) * 2006-08-04 2011-09-20 Tela Innovations, Inc. Method and system for wafer topography-aware integrated circuit design analysis and optimization
JP2016095606A (ja) * 2014-11-13 2016-05-26 国立大学法人電気通信大学 データ処理装置およびデータ処理方法、並びにプログラム
CN105930609A (zh) * 2016-05-04 2016-09-07 华中科技大学 一种用于相干解调的fpga时序优化方法
US20180165400A1 (en) * 2016-12-12 2018-06-14 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Method and Computer Program for Determining a Placement of at least one Circuit for a Reconfigurable Logic Device
US9792397B1 (en) * 2017-01-08 2017-10-17 Alphaics Corporation System and method for designing system on chip (SoC) circuits through artificial intelligence and reinforcement learning

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ALTERA公司: "使用Stratix Ⅲ FPGA实现功耗更低、性能更高的系统", 世界电子元器件, no. 2, 13 March 2007 (2007-03-13), pages 104 - 108 *
黄娟等: "可编程逻辑阵列减少毛刺的低功耗布线算法", 计算机辅助设计与图形学学报, vol. 22, no. 10, 11 November 2010 (2010-11-11), pages 1664 - 1670 *

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JP7466643B2 (ja) 2024-04-12
US20230342530A1 (en) 2023-10-26
US12380264B2 (en) 2025-08-05
WO2021251206A1 (ja) 2021-12-16
JPWO2021251206A1 (https=) 2021-12-16

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