WO2021244252A1

WO2021244252A1 - Serdes control method and apparatus, and storage medium

Info

Publication number: WO2021244252A1
Application number: PCT/CN2021/093634
Authority: WO
Inventors: 严海消
Original assignee: 中兴通讯股份有限公司
Priority date: 2020-06-01
Filing date: 2021-05-13
Publication date: 2021-12-09
Also published as: CN113760807A

Abstract

The present application relates to the field of communications, and provides a SerDes control method and apparatus, and a storage medium. The method comprises: acquiring a speed change time point of SerDes; and in response to determining that a working time point of the SerDes reaches the speed change time point, controlling the speed of the SerDes to switch between a first preset speed and a second preset speed.

Description

SerDes control method, device and storage medium

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on June 1, 2020, with an application number of 202010486625.9, and the entire content of this application is incorporated into this application by reference.

Technical field

This application relates to the field of communication technology, for example, to a SerDes control method, device, and storage medium.

Background technique

At present, with the widespread use of multi-antenna technology in the 4th generation mobile communication technology (4G) and the 5th generation mobile networks (5G), in order to quickly deliver communications The system realizes many important functions of the communication system through Field Programmable Gate Array (FPGA) or Field Programmable System Chip (FPSC), and a large number of embedded in FPGA or FPSC High-speed serial interface (SERializer DESerializer, SerDes), so the power consumption of FPGA or FPSC is related to the power consumption of SerDes. With the iteration of the communication system, the scale of FPGA or FPSC used in the communication system is getting bigger and bigger. Therefore, the power consumption of the communication system is also getting bigger and bigger, which will generate more heat and bring serious problems to the communication system. In the case of poor heat dissipation, the FPGA and other devices will be in a high temperature state, which will affect the normal use of FPGA or FPSC and other devices, thereby affecting the function of the communication system.

Summary of the invention

This application provides a SerDes control method, device, and storage medium to reduce the power consumption of FPGA or FPSC and other devices, and reduce the heat dissipation pressure of the communication system.

In the first aspect, this application provides a SerDes control method, including:

Acquiring the rate change time of the SerDes;

In response to determining that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to switch between a first preset rate and a second preset rate, where the first preset rate is greater than the first preset rate 2. Preset rate.

In the second aspect, the present application also provides a SerDes control device. The SerDes control device includes a processor, a memory, a program stored in the memory and executable by the processor, and a program for implementing the processor and The data bus for connection and communication between the memories, wherein when the program is executed by the processor, any SerDes control method as provided in the specification of this application is implemented.

In a third aspect, the present application also provides a storage medium for computer-readable storage. The storage medium stores at least one program, and the at least one program can be executed by at least one processor to implement the Any of the SerDes control methods.

Description of the drawings

FIG. 1 is a schematic flowchart of a SerDes control method provided by an embodiment of the present application;

Fig. 2 is a schematic flow diagram of sub-steps of the SerDes control method in Fig. 1;

Fig. 3 is a schematic flow diagram of sub-steps of the SerDes control method in Fig. 2;

FIG. 4 is a schematic block diagram of the structure of a SerDes control device provided by an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

The flowchart shown in the drawings is only an example, and does not necessarily include all contents and operations/steps, nor does it have to be executed in the described order. For example, some operations/steps can also be decomposed, combined or partially combined, so the actual execution order may be changed according to actual conditions.

It should be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in the specification of this application and the appended claims, unless the context clearly indicates other circumstances, the singular forms "a", "an" and "the" are intended to include plural forms.

The embodiments of the present application provide a SerDes control method, device, and storage medium. Among them, the SerDes control method can be applied to devices, chips, and communication systems installed with SerDes, and the chips include FPGAs, FPSCs, and so on.

Hereinafter, some embodiments of the present application will be described in detail with reference to the accompanying drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of a SerDes control method provided by an embodiment of the present application.

As shown in FIG. 1, the SerDes control method includes steps S101 to S102.

Step S101: Obtain the rate change time of the SerDes.

Wherein, the rate change moment includes the moment when the rate of the SerDes starts to decrease from the first preset rate to the second preset rate, that is, the first moment and the moment when the rate of the SerDes starts to increase from the second preset rate to the first preset rate. It is assumed that the moment of the rate is the second moment, the first preset rate is greater than the second preset rate, and the first preset rate and the second preset rate are determined according to the protocol adopted by SerDes, which is not limited in this application. For example, the protocol adopted by the SerDes is the Common Public Radio Interface (CPRI) protocol, the first preset rate is 24330.24 Mbit/s, and the second preset rate is 614.4 Mbit/s.

In one embodiment, as shown in FIG. 2, step S101 includes S1011 to S1012.

S1011: Acquire a low-speed time period of the SerDes.

The low-speed time period is determined according to the transmission situation of SerDes. For example, in a Time Division Duplex (TDD) communication system, the 5ms frame format is DDDDDDDSUU, and there are 7 downlink time slots (slots) ( D time slot), 1 special slot (S downlink uplink conversion time slot) and 2 uplink slots (U time slot). When it is confirmed that there is only one direction of data transmission, the SerDes can be decelerated so that the SerDes rate is at Low speed, thereby reducing the power consumption of SerDes. Through the 5ms frame format DDDDDDDSUU, it can be determined that the length of the low-speed time period of SerDes in the downlink (receiving) direction is 7 D time slots + 1 S time slot, a total of 3.5 ms + S time slot The downlink symbol time of SerDes in the uplink (transmission) direction is 2 U time slots + 1 S time slot, totaling 1ms+S time slot uplink symbol time, that is, data is transmitted in the downlink direction. When the SerDes is decelerated in the upstream direction, and when data is transmitted in the upstream direction, the SerDes is decelerated in the downstream direction. For another example, SerDes in a certain communication system transmits data in the first 5ms of every 10ms period and does not transmit data in the last 5ms. Therefore, the low-speed period of SerDes is the last 5ms of every 10ms period, that is, the last 5ms of every 10ms period. At the same time, SerDes is reduced in the receiving and sending directions, so that the rate of SerDes is at a low speed, thereby reducing the power consumption of SerDes.

S1012. Determine the first time and the second time according to the low-speed time period.

The first moment is the moment when the rate of SerDes is reduced from the first preset rate to the second preset rate, and the second moment is the moment when the rate of SerDes is restored from the second preset rate to the first preset rate.

In one embodiment, as shown in FIG. 3, step S1012 includes steps S1012a to S1012c.

S1012a. Acquire a start time and an end time in the low-speed time period, and use the start time as the first time.

S1012b. The second time duration required for the rate of acquiring the SerDes to be restored from the second preset rate to the first preset rate.

S1012c. Determine the second time according to the end time and the second time length.

Among them, the time required for the rate of SerDes to decrease from the first preset rate to the second preset rate is the first duration, and the time required for the rate of SerDes to be restored from the second preset rate to the first preset rate is The second duration, the sum of the first duration and the second duration is less than the duration of the low-speed time period, the SerDes rate is always the second preset rate between the start time + the first duration and the end time-the second duration, The second moment is the end moment-the second duration.

For example, the time required for the rate of SerDes to decrease from the first preset rate to the second preset rate, that is, the first duration is 0.5 ms, and the rate of SerDes is restored from the second preset rate to the first preset rate. Duration, that is, the second duration is 0.5ms, the low-speed period of SerDes is the last 5ms of every 10ms period, denoted as t ₁ ～t ₂ , the time length is 5ms, the start time is t ₁ , the end time is t ₂ , low speed The time length of the time period of 5 ms is greater than the sum of the first time length of 0.5 ms and the second time length of 0.5 ms. Therefore, the starting time t _{1 is taken} as the first time, that is, the rate of SerDes is reduced from the first preset rate to the second preset At the time of the rate, the end time t ₂ -0.5ms is taken as the second time, that is, the time when the rate of SerDes increases from the second preset rate to the first preset rate. It can be known that the rate of SerDes is at t ₁ +0.5ms~ t is always between _{2 -0.5ms} a second predetermined rate, i.e., the SerDes t ₁ + 0.5ms ~ t between _{2 -0.5ms} (total 4ms) in the low speed state.

For another example, the low-speed time period of SerDes is the upward direction within 5 ms, which is denoted as t ₁ ～t ₂ , and the time length of the low-speed time period is 1.5 ms, the start time is t ₁ , the end time is t ₂ , and the low-speed time period The time length of 1.5ms is greater than the sum of the first time length 0.5ms and the second time length 0.5ms, so the starting time t _{1 is taken} as the first time, that is, the rate of SerDes is reduced from the first preset rate to the second preset rate At time, the end time t ₂ -0.5ms is taken as the second time, that is, the time when the rate of SerDes is increased from the second preset rate to the first preset rate. It can be known that the rate of SerDes is t ₁ +0.5ms-t ₂ The second preset rate is always between -0.5ms, that is, SerDes is in a low-speed state between _{t 1} +0.5ms and t _{2 -0.5ms (total 0.5ms).}

For another example, the low-speed time period of SerDes is the downlink direction within 5 ms, which is denoted as t ₁ ～t ₂ , and the time length of the low-speed time period is 4 ms, the start time is t ₁ , the end time is t ₂ , and the low-speed time period is The time length of 4 ms is greater than the sum of the first time length of 0.5 ms and the second time length of 0.5 ms, so the starting time t _{1 is taken} as the first time, that is, the time when the rate of SerDes decreases from the first preset rate to the second preset rate, Taking the end time t ₂ -0.5ms as the second time, that is, the time when the rate of SerDes increases from the second preset rate to the first preset rate, it can be known that the rate of SerDes is t ₁ +0.5ms-t ₂ -0.5 ms is always between the second predetermined rate, i.e., the SerDes t ₁ + 0.5ms ~ t between _{2 -0.5ms} (total 3ms) in the low speed state.

In one embodiment, the rate of SerDes is reduced from the first preset rate to the time required for the second preset rate, that is, the first time and the rate of SerDes is required to be restored from the second preset rate to the first preset rate. The duration of, that is, the second duration, is obtained through testing. For example, control the rate of SerDes to decrease from the first preset rate to the second preset rate, and record the start time of the decrease rate and decrease to the second preset rate At the completion time of the rate, the first duration is determined according to the start time of the rate reduction and the completion time of the reduction to the second preset rate; similarly, the rate of controlling SerDes is restored from the second preset rate to the first preset rate, and Record the start time of the restoration rate and the completion time of the restoration to the first preset rate, and determine the second duration according to the start time of the restoration rate and the completion time of the restoration to the first preset rate. Among them, the first time length and the second time length can be tested multiple times in the above-mentioned manner, and finally the largest first time length and the largest second time length are selected.

Step S102: When it is determined that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to switch between a first preset rate and a second preset rate, where the first preset rate is greater than The second preset rate.

After obtaining the rate change moment of SerDes, when it is determined that the working moment of SerDes reaches the rate change moment, the rate of SerDes is controlled to switch between the first preset rate and the second preset rate, that is, under normal circumstances, SerDes Work at the first preset rate. When it is determined that the working time of SerDes reaches the first moment, the rate of controlling SerDes is reduced from the first preset rate to the second preset rate, and maintained for a period of time. After the SerDes rate is changed from the first After a preset rate is reduced to a second preset rate, when it is determined that the working time of SerDes reaches the second moment, the rate of controlling the SerDes is restored from the second preset rate to the first preset rate. Among them, suppose the low-speed time period is t ₁ ～t ₂ , the first time period required for the rate of SerDes to decrease from the first preset rate to the second preset rate is T ₁ , and the rate of SerDes is restored from the second preset rate to The second duration required for the first preset rate is T ₂ , then between t ₁ +T ₁ ～t ₂ -T ₂ , the rate of SerDes maintains the second preset rate, that is, at t ₁ +T ₁ ～t SerDes works at a low rate between _{2 and} T _2.

In one embodiment, when it is determined that the working time of SerDes has not reached the time of rate change, the rate of SerDes is controlled to remain at the first preset rate or the second preset rate, that is, when the rate of SerDes is the first preset rate, The rate of controlling the SerDes remains unchanged at the first preset rate, and when the rate of SerDes is the second preset rate, the rate of controlling SerDes remains unchanged at the second preset rate.

In an embodiment, when it is determined that the working time of SerDes reaches the time of rate change, at least one of the following is performed: controlling the rate of the sending direction of SerDes to switch between the first preset rate and the second preset rate; controlling the SerDes The rate in the receiving direction is switched between the first preset rate and the second preset rate. For example, in a scenario where data is transmitted in the sending direction of SerDes and no data is transmitted in the receiving direction of SerDes, when it is determined that the working time of SerDes reaches the first moment, the rate of controlling the receiving direction of SerDes is reduced from the first preset rate to the first. 2. The preset rate, when it is determined that the working moment of the SerDes reaches the second moment, the rate of controlling the receiving direction of the SerDes is restored from the second preset rate to the first preset rate.

For another example, in a scenario where data is transmitted in the receiving direction of SerDes but no data is transmitted in the sending direction of SerDes, when it is determined that the working time of SerDes reaches the first moment, the rate of controlling the sending direction of SerDes is reduced from the first preset rate to The second preset rate, when it is determined that the working moment of the SerDes reaches the second moment, the rate of controlling the sending direction of the SerDes is restored from the second preset rate to the first preset rate. For another example, in the scenario where SerDes transmits data in the first 5ms of every 10ms period, and does not transmit data in the next 5ms, when it is determined that the working time of SerDes reaches the first time, the rate of the sending and receiving directions of SerDes is controlled by the first preset at the same time. It is assumed that the rate is reduced to the second preset rate, and when it is determined that the working time of SerDes reaches the second moment, the rate of controlling the sending and receiving directions of SerDes is restored from the second preset rate to the first preset rate.

The SerDes control method provided by the embodiments of the present application obtains the rate change time of SerDes, and when the working time of SerDes reaches the rate change time, the rate of SerDes is controlled between the first preset rate and the second preset rate. Switching, that is, controlling the rate of SerDes to switch between high rate and low rate, can reduce the power consumption of SerDes while ensuring the normal operation of SerDes, thereby reducing the power consumption of FPGA or FPSC and other devices, and reducing the heat dissipation pressure of the communication system , To ensure the normal operation of the communication system.

Please refer to FIG. 4, which is a schematic block diagram of a SerDes control device provided by an embodiment of the present application.

As shown in FIG. 4, the SerDes control device 200 includes a processor 201 and a memory 202. The processor 201 and the memory 202 are connected by a bus 203. The bus is, for example, an I2C (Inter-integrated Circuit) bus. The SerDes control device 200 can be applied to FPGA and FPSC etc.

The processor 201 is configured to provide calculation and control capabilities to support the operation of the entire SerDes control device. The processor 201 may be a central processing unit (CPU), and the processor 201 may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), application specific integrated circuits (ASICs). ), discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.

The memory 202 may be a Flash chip, a read-only memory (ROM, Read-Only Memory) disk, an optical disk, a U disk, or a mobile hard disk.

Those skilled in the art can understand that the structure shown in FIG. 4 is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the SerDes control device to which the solution of the present application is applied. The server may include More or fewer components are shown in the figure, or some components are combined, or have different component arrangements.

Wherein, the processor is configured to run a program stored in a memory, and when executing the program, implement any one of the SerDes control methods provided in the embodiments of the present application.

In one embodiment, the processor is configured to run a program stored in the memory, and the following steps are implemented when the program is executed:

Acquiring the rate change time of the SerDes;

When it is determined that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to switch between a first preset rate and a second preset rate, and the first preset rate is greater than the first preset rate. 2. Preset rate.

In one embodiment, the rate change moment includes the moment when the rate of the SerDes starts to decrease from the first preset rate to the second preset rate, that is, the first moment and the rate of the SerDes starts from the second preset rate. The moment when the rate is increased to the first preset rate is the second moment.

In an embodiment, the processor is configured to obtain the rate change time of the SerDes in the following manner:

Acquiring the low-speed time period of the SerDes;

The first time and the second time are determined according to the low-speed time period.

In an embodiment, the processor is configured to determine the first time and the second time according to the low-speed time period in the following manner:

Acquiring a start time and an end time in the low-speed time period, and use the start time as the first time;

The second duration required for the rate of acquiring the SerDes to be restored from the second preset rate to the first preset rate;

Determine the second time according to the end time and the second time length.

In one embodiment, the rate of the SerDes is reduced from the first preset rate to the first time period required for the second preset rate and the rate of the SerDes is restored from the second preset rate to the first preset rate. The sum of the required second time length is less than the time length of the low-speed time period.

In one embodiment, the processor is configured to control the rate of the SerDes between the first preset rate and the second preset rate when it is determined that the working moment of the SerDes reaches the rate change moment in the following manner Switch between:

When it is determined that the working time of the SerDes reaches the first time, the rate of controlling the SerDes is reduced from a first preset rate to a second preset rate;

When it is determined that the working time of the SerDes reaches the second time, the rate of controlling the SerDes is restored from the second preset rate to the first preset rate.

In an embodiment, the first preset rate and the second preset rate are determined according to a protocol adopted by the SerDes.

In an embodiment, the processor is configured to control the rate of the SerDes to switch between the first preset rate and the second preset rate by at least one of the following methods:

Controlling the rate of the sending direction of the SerDes to switch between a first preset rate and a second preset rate;

The rate of controlling the receiving direction of the SerDes is switched between the first preset rate and the second preset rate.

It should be noted that those skilled in the art can clearly understand that for the convenience and brevity of the description, the working process of the SerDes control device described above can refer to the corresponding process in the aforementioned SerDes control method embodiment, which will not be repeated here. Go into details.

An embodiment of the present application also provides a storage medium, the storage medium stores at least one program, and the at least one program can be executed by at least one processor to implement the following steps:

Acquiring the rate change time of the SerDes;

Acquiring the low-speed time period of the SerDes;

Determine the second time according to the end time and the second time length.

The storage medium may be the internal storage unit of the SerDes control device described in the foregoing embodiment, such as the hard disk or memory of the SerDes control device. The storage medium may also be an external storage device of the SerDes control device, such as a plug-in hard disk equipped on the SerDes control device, a smart memory card (Smart Media Card, SMC), or Secure Digital (SD) Card, Flash Card, etc. In some embodiments, the storage medium may also be FPGA, FPSC, or the like.

A person of ordinary skill in the art can understand that all or some of the steps, functional modules/units in the system, and apparatus in the methods disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. In the hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may consist of several physical components. The components are executed cooperatively. Certain physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit . Such software may be distributed on a computer-readable medium, and the computer-readable medium may include a computer storage medium (or a non-transitory medium) and a communication medium (or a transitory medium). As is well known by those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile data implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Sexual, removable and non-removable media. Computer storage media include but are not limited to Random Access Memory (RAM), Read-Only Memory (ROM), Electrically Erasable Programmable Read-Only Memory, EEPROM) , Flash memory or other storage technology, CD-ROM (Compact Disc Read-Only Memory, CD-ROM), Digital Versatile Disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage A device, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium usually contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium. .

It should be understood that the term "and/or" used in the specification and appended claims of this application refers to any combination and all possible combinations of at least one of the associated listed items, and includes these combinations. It should be noted that in this article, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements, It also includes other elements not explicitly listed, or elements inherent to the process, method, article, or system. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, article, or system that includes the element.

Claims

A SerDes control method, including:

Acquiring the rate change time of the SerDes;

In response to determining that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to switch between a first preset rate and a second preset rate, where the first preset rate is greater than the first preset rate 2. Preset rate.
The SerDes control method according to claim 1, wherein the rate change moment includes the moment when the rate of the SerDes starts to decrease from a first preset rate to a second preset rate, that is, the first moment and the rate of the SerDes The moment when the second preset rate starts to increase to the first preset rate is the second moment.
The SerDes control method according to claim 2, wherein said acquiring the time of change of the rate of said SerDes comprises:

Acquiring the low-speed time period of the SerDes;

The first time and the second time are determined according to the low-speed time period.
The SerDes control method according to claim 3, wherein the determining the first time and the second time according to the low-speed time period comprises:

Acquiring a start time and an end time in the low-speed time period, and use the start time as the first time;

The second duration required for the rate of acquiring the SerDes to be restored from the second preset rate to the first preset rate;

Determine the second time according to the end time and the second time length.
The SerDes control method according to claim 3, wherein the first time length required for the rate of the SerDes to be reduced from the first preset rate to the second preset rate and the rate of the SerDes are restored from the second preset rate The sum of the second duration required for the first preset rate is less than the duration of the low-speed time period.
The SerDes control method according to claim 2, wherein, in response to determining that the working moment of the SerDes reaches the rate change moment, the rate of the SerDes is controlled to be between a first preset rate and a second preset rate Switch between, including:

In response to determining that the working moment of the SerDes reaches the first moment, controlling the rate of the SerDes to decrease from a first preset rate to a second preset rate;

In response to determining that the working moment of the SerDes reaches the second moment, the rate of the SerDes is controlled to be restored from the second preset rate to the first preset rate.
The SerDes control method according to any one of claims 1 to 6, wherein the first preset rate and the second preset rate are determined according to a protocol adopted by the SerDes.
The SerDes control method according to any one of claims 1 to 6, wherein the controlling the rate of the SerDes to switch between a first preset rate and a second preset rate includes at least one of the following:

Controlling the rate of the sending direction of the SerDes to switch between a first preset rate and a second preset rate;

The rate of controlling the receiving direction of the SerDes is switched between the first preset rate and the second preset rate.
A SerDes control device includes a processor, a memory, a program stored on the memory and executable by the processor, and a data bus used to realize the connection and communication between the processor and the memory, wherein When the program is executed by the processor, the SerDes control method according to any one of claims 1 to 8 is realized.
A storage medium storing at least one program, and the at least one program can be executed by at least one processor to implement the SerDes control method according to any one of claims 1 to 8.