CN116560486A - Method and apparatus for adjusting interface parameters of storage medium - Google Patents

Method and apparatus for adjusting interface parameters of storage medium Download PDF

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Publication number
CN116560486A
CN116560486A CN202210102365.XA CN202210102365A CN116560486A CN 116560486 A CN116560486 A CN 116560486A CN 202210102365 A CN202210102365 A CN 202210102365A CN 116560486 A CN116560486 A CN 116560486A
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China
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interface
storage medium
control circuit
odt
system performance
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CN202210102365.XA
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Chinese (zh)
Inventor
李由
徐奎
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202210102365.XA priority Critical patent/CN116560486A/en
Priority to PCT/CN2022/126617 priority patent/WO2023142546A1/en
Publication of CN116560486A publication Critical patent/CN116560486A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3278—Power saving in modem or I/O interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Power Sources (AREA)

Abstract

The application provides a method for adjusting interface parameters of a storage medium and a controller of the storage medium, which can avoid delay of service transmission. The method comprises the following steps: the control circuit determines interface parameters of a storage medium matched with the target interface rate according to the target interface rate, and the control circuit is a control circuit corresponding to the storage medium; when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, the control circuit transmits the interface parameters of the storage medium rate-matched with the target interface to the interface of the storage medium.

Description

Method and apparatus for adjusting interface parameters of storage medium
Technical Field
The present application relates to the field of communications, and more particularly, to a method and apparatus for adjusting interface parameters of a storage medium.
Background
With the development of cloud/computing/server services, the performance requirements of a system on a storage medium increase year by year, and in order to match the performance requirements of the system, the input/output (IO) interface rate of the storage medium and the IO interface rate of a corresponding controller are also higher and higher. In order to match the high-speed IO interface rate and meet the corresponding Signal Integrity (SI) requirement of data communication, the driving capability of the IO interface is continuously improved, the driving resistance of the IO interface is continuously reduced, and the power consumption of the corresponding IO interface is continuously increased.
In practical business application, the performance requirements of the system are different in different time periods; for example, the performance requirements of the system may vary greatly between day and night due to the different liveness of the users. In a low-performance requirement scene, the IO interface rate of the storage medium and the IO interface rate of a controller corresponding to the storage medium are lower; in the scene of high performance requirement, the IO interface rate of the storage medium and the IO interface rate of the controller corresponding to the storage medium are higher.
Because adjusting the interface parameters of the storage medium changes the integrity of the signals transmitted by the IO interface, when the interface parameters of the IO interface of the storage medium are adjusted according to the IO interface rate of the storage medium, the service transmission of the IO interface of the current storage medium is stopped. The memory Firmware (FW) waits for the traffic transmission of the IO interface to stop before the interface parameters of the IO interface can be adjusted. However, when the service transmission is stopped within a period of time, delay fluctuation of service access of the system is caused, and the system cannot adapt to actual application in a scene that the interface parameters need to be continuously adjusted.
Disclosure of Invention
The application provides a method for adjusting interface parameters of a storage medium and a controller of the storage medium, which can avoid delay of service transmission.
In a first aspect, a method for adjusting interface parameters of a storage medium is provided, comprising: the control circuit determines interface parameters of the storage medium matched with the target interface rate according to the target interface rate, wherein the control circuit is a control circuit corresponding to the storage medium; when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, the control circuit sends the interface parameters to the interface of the storage medium.
Based on the above scheme, the control circuit corresponding to the storage medium can determine the interface parameter of the storage medium matched with the target interface rate according to the target interface rate, and when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, the interface parameter is sent to the interface of the storage medium. Compared with the prior art that the interface parameters of the interface of the memory are adjusted at the time of stopping service transmission, the interface parameters are adjusted when the connecting bus between the interface of the control circuit and the interface of the storage medium is in an idle state, and the ongoing service transmission is not required to be stopped, so that the delay of the service transmission can be avoided.
In one possible implementation, the interface parameters include a magnitude of a drive resistance of an interface of the storage medium, a magnitude of an on-chip termination resistance ODT, and an operating clock signal.
In one possible implementation, the control circuit determines, according to a target interface rate, an interface parameter of the storage medium that matches the target interface rate, including: the control circuit determines the size of the driving resistor, the size of the ODT and the working frequency of the interface of the storage medium matched with the target interface rate according to the target interface rate; the control circuit sends a clock adjustment request to a clock generation circuit, wherein the clock adjustment request comprises the working frequency and is used for requesting the clock generation circuit to generate the working clock signal of the working frequency; the control circuit receives the operating clock signal generated by the clock generating circuit.
In one possible implementation, the control circuit decreases the magnitude of the drive resistance, connects the ODT, or decreases the magnitude of the ODT when the target interface rate increases; when the target interface rate decreases, the control circuit increases the magnitude of the driving resistance, does not connect the ODT, or increases the magnitude of the ODT.
It should be appreciated that the greater the target interface rate, the greater the requirements for signal integrity, and reducing the magnitude of the drive resistance and the magnitude of the ODT of the interface may enhance the integrity of the signals transmitted by the interface. The smaller the target interface rate, the lower the requirement on signal integrity, and the size of the drive resistor and the ODT of the interface are increased, so that the power consumption of the interface can be reduced, and the power consumption of a memory system can be reduced.
In one possible implementation, the method further includes: the control circuit determines the target interface rate based on current system performance requirements including at least one of: bandwidth of access to the storage medium and access latency of access to the storage medium.
In one possible implementation, the method further includes: the system performance sensing circuit senses the current system performance requirement; the system performance aware circuit sends the current system performance requirements to the control circuit.
In one possible implementation, the memory includes a plurality of memory granules, and the storage medium is one or more of the plurality of memory granules.
It will be appreciated that each memory granule corresponds to an interface, and that the interface of each memory granule is connected to the interface of the control circuit via a connection bus. In the prior art, interface parameters of all storage particles in a memory need to be adjusted during the service transmission period of interfaces corresponding to all storage particles on the memory, and when a connection bus between an interface of a control circuit and an interface of a certain (or some) storage particles in the memory is in an idle state, the interface parameters of the corresponding storage particles are adjusted, so that service transmission on interfaces of other storage particles in the memory is not affected.
In a second aspect, there is provided a controller for a storage medium, comprising: the control circuit is used for determining interface parameters of the storage medium matched with the target interface rate according to the target interface rate, and the control circuit is a control circuit corresponding to the storage medium; the control circuit is further configured to send the interface parameter to the interface of the storage medium when a connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state.
In one possible implementation, the interface parameters include a magnitude of a drive resistance of an interface of the storage medium, a magnitude of an on-chip termination resistance ODT, and an operating clock signal.
In one possible implementation, the controller further includes a clock generation circuit; the control circuit is specifically used for: determining the size of the driving resistor, the size of the ODT and the working frequency of the interface of the storage medium matched with the target interface rate according to the target interface rate; sending a clock adjustment request to the clock generation circuit, wherein the clock adjustment request comprises the working frequency and is used for requesting the clock generation circuit to generate the working clock signal of the working frequency; the operating clock signal generated by the clock generating circuit is received.
In one possible implementation, the control circuit is specifically configured to: decreasing the magnitude of the drive resistance, connecting the ODT, or decreasing the magnitude of the ODT when the target interface rate increases; when the target interface rate decreases, the magnitude of the driving resistance is increased, the ODT is not connected, or the magnitude of the ODT is increased.
In one possible implementation, the control circuit is further configured to determine the target interface rate according to a current system performance requirement, where the current system performance requirement includes at least one of: bandwidth of access to the storage medium and access latency of access to the storage medium.
In one possible implementation, the controller further includes a system performance aware circuit; the system performance sensing circuit is used for sensing the current system performance requirement; the system performance aware circuit is also configured to send the current system performance requirement to the control circuit.
In one possible implementation, the memory includes a plurality of memory granules, and the storage medium is one or more of the plurality of memory granules.
In a third aspect, a communications device is provided comprising a processor and a transceiver for receiving computer code or instructions and transmitting to the processor, the processor executing the computer code or instructions to implement a method as in any one of the possible implementations of the first aspect.
In a fourth aspect, a computer readable storage medium is provided, on which a computer program is stored which, when executed by a communication device, causes the communication device to implement a method as in any one of the possible implementations of the above aspect.
In a fifth aspect, there is provided a computer program product comprising instructions which, when executed by a computer, cause a communication device to implement a method as in any one of the possible implementations of the above aspect.
Drawings
Fig. 1 is a schematic block diagram of FW static adjustment of interface parameters of an IO interface of a storage medium.
Fig. 2 is a schematic flow chart of a method of adjusting interface parameters of a storage medium according to an embodiment of the present application.
Fig. 3 is an example of a method of adjusting interface parameters of a storage medium according to an embodiment of the present application.
Fig. 4 is another example of a method of adjusting interface parameters of a storage medium according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a controller of a storage medium according to an embodiment of the present application.
Fig. 6 is an example of a controller of a storage medium provided in an embodiment of the present application.
Fig. 7 is a schematic block diagram of a communication device according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described below with reference to the accompanying drawings.
The embodiment of the application can be applied to various flash (flash) storage devices. For example: solid State Disk (SSD), secure digital Card (secure digital Card, SD Card), embedded multimedia Card (embedded multi media Card, eMMC), universal flash memory (universal flash storage, UFS), and custom flash memory devices. Taking an embedded multimedia card as an example, the embedded multimedia card comprises a digital camera memory card, an MP3 walkman memory card, a small U disk and the like.
With the development of cloud/computing/server services, the performance requirements of a system on a storage medium are increased year by year, and in order to match the performance requirements of the system, the IO interface rate of the storage medium and the IO interface rate of a corresponding controller are also higher and higher. In order to match the high-speed IO interface rate and meet the corresponding Signal Integrity (SI) requirement of data communication, the driving capability of the IO interface is continuously improved, the driving resistance of the IO interface is continuously reduced, and the power consumption of the corresponding IO interface is continuously increased.
In practical business applications, the performance requirements of the system are different in different time periods. For example, the performance requirements of the system may vary greatly between day and night due to the different liveness of the users. In a low-performance requirement scene or a lower-performance requirement scene, the IO interface rate of the storage medium and the IO interface rate of a controller corresponding to the storage medium are lower; in a high-performance requirement scene or a higher-performance requirement scene, the IO interface rate of the storage medium and the IO interface rate of the controller corresponding to the storage medium are higher.
At present, in a system power-on stage, parameters such as working frequency, size of a driving resistor, size of on-chip termination (ODT) and size of reference voltage (voltage reference, vref) of an IO interface of a storage medium and an IO interface of a controller corresponding to the storage medium can be matched according to interface rates required to be supported by the IO interface of the current storage medium and the IO interface of the controller corresponding to the storage medium.
Stopping service transmission of the current IO interface in the process of switching the high-performance requirement scene to the low-performance requirement scene or in the process of switching the low-performance requirement scene to the high-performance requirement scene; and according to the interface rate which the IO interface needs to support, adjusting the interface parameters such as the size of the drive resistor, the size of the ODT, the working clock signal, vref, the process, the voltage, the temperature (process, voltage, temperature, PVT) and the like of the IO interface of the storage medium and the IO interface of the controller corresponding to the storage medium.
Because adjusting the interface parameters of the IO interface changes the integrity of the signals transmitted by the IO interface, when the interface parameters of the IO interface are adjusted, current service transmission of the IO interface is stopped. FW waits for the traffic transmission of the IO interface to stop, and can adjust the interface parameters of the IO interface. However, when the service data transmission is stopped within a period of time, delay fluctuation of the system on service access is caused; in the scene that the interface parameters need to be continuously adjusted, the method cannot be suitable for practical application. As shown in fig. 1, a schematic block diagram of interface parameters of an IO interface of a FW static adjustment memory is shown, where, taking a flash memory as an example, the FW static adjustment of the interface parameters of the IO interface of the flash memory is implemented by using a full software method.
Therefore, the embodiment of the application provides a method for adjusting interface parameters of a storage medium, which can avoid delay of service transmission.
As shown in fig. 2, a schematic flow chart of a method 200 of adjusting interface parameters of a storage medium according to an embodiment of the present application is shown.
210, the control circuit determines the interface parameter of the storage medium matching the target interface rate according to the target interface rate, and the control circuit is a control circuit corresponding to the storage medium, that is, the control circuit is a circuit in the controller corresponding to the storage medium. The target interface rate is determined by the control circuit according to the system performance requirement of the current storage system; the system performance requirements include at least one of: the bandwidth of accessing the storage medium, the access delay of accessing the storage medium, etc. may be the bandwidth of accessing the storage medium by the central processing unit, the access delay of accessing the storage medium by the central processing unit, etc., for example, the bandwidth of the SSD disk/UFS card/eMMC card, the IO (IO per second) requirement of processing per second, etc.
Optionally, the system performance sensing circuit senses a current system performance requirement and sends the current system performance requirement to the control circuit. Correspondingly, the control circuit receives the current system performance requirement sent by the system performance sensing circuit, and determines the target interface rate which needs to be supported by the interface of the storage medium and the interface of the controller corresponding to the storage medium according to the current system performance requirement. For different system performance requirements, the target interface rate that the interface of the storage medium and the interface of the controller corresponding to the storage medium need to support are the same, and the interface parameters of the interface of the storage medium and the interface parameters of the interface of the controller corresponding to the storage medium may be the same.
Illustratively, the interface parameters of the storage medium include a magnitude of a drive resistance of an interface of the storage medium, a magnitude of an on-chip termination resistance, and an operating clock signal. Optionally, the interface parameters of the storage medium may further include interface parameters such as Vref and PVT of the interface of the storage medium. It should be understood that the interface parameters of the interface of the storage medium and the interface parameters of the interface of the controller to which the storage medium corresponds may also be different. For example, the magnitude of the driving resistance of the interface of the memory medium and the magnitude of the driving resistance of the ODT of the interface of the controller corresponding to the memory medium may be different from each other but the operation clock signal of the interface of the memory medium and the operation clock signal of the interface of the controller corresponding to the memory medium are the same, in which case the magnitude of the driving resistance of the interface of the memory medium and the magnitude of the driving resistance of the ODT of the interface of the controller corresponding to the memory medium are in one-to-one correspondence.
For example, the control circuit may determine a magnitude of a driving resistance, a magnitude of ODT, and an operating frequency of an interface of the storage medium that is rate-matched to the target interface according to the target interface rate. The control circuit sends a clock adjustment request to the clock generation circuit, wherein the clock adjustment request comprises the working frequency determined by the control circuit; the clock generation circuit generates a working clock signal of the working frequency and sends the working clock signal to the control circuit; the control circuit receives the operation clock signal generated by the clock generating circuit. The clock generating circuit is also a circuit in the controller corresponding to the storage medium.
Illustratively, the control circuit decreases the magnitude of the drive resistance of the interface of the memory medium, the ODT of the interface of the memory medium, increases the operating frequency of the operating clock signal, or decreases the magnitude of the ODT of the interface of the memory medium when the target interface rate increases; connecting ODT is understood to mean connecting an ODT with a smaller resistance or a specific ODT. When the target interface rate decreases, the control circuit increases the magnitude of the drive resistance of the interface of the memory medium, turns off the ODT, or increases the magnitude of the ODT of the interface of the memory medium, decreases the magnitude of the operating frequency of the operating clock signal; the disconnection of ODT is understood to mean the connection of an ODT having a larger resistance, which is equivalent to a suspended or disconnected state due to the larger resistance of the connected ODT.
It should be appreciated that the greater the target interface rate, the greater the signal integrity requirements, and reducing the size of the drive resistor and ODT of the interface may enhance the integrity of the signals transmitted by the interface, while at the same time, the power consumption of the interface may also increase. The smaller the target interface rate, the lower the requirement on signal integrity, and the size of the drive resistor and the ODT of the interface are increased, so that the power consumption of the interface can be reduced, and the power consumption of a memory system can be reduced.
220, the control circuit sends the interface parameters to the interface of the storage medium when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state. When the connection bus between the interface of the control circuit and the interface of the storage medium is not in an idle state, the service transmission is not stopped, and the service transmission is waited for to be completed. It will be appreciated that since all read and write commands and traffic transmissions are initiated by the controller, the control circuitry in the controller can accurately predict the behavior on the connection bus between the interface of the control circuitry and the interface of the storage medium. Specifically, the control circuit may dynamically acquire the usage right of the connection bus and the control right of the storage medium according to the type of the currently transmitted service and the transmission stage of the service transmitted on the current connection bus.
The connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, which is understood to mean that the control circuit does not access the storage medium, or that the control circuit does not access the bus operation of the storage medium. When the connection bus between the interface of the control circuit and the interface of the storage medium is not in an idle state, there may be data transmission, command transmission, address transmission or in a timing control state related to the transmission process on the connection bus, that is, there is traffic transmission on the connection bus.
Correspondingly, the control circuit determines the interface parameters of the interface of the control circuit matched with the target interface rate according to the target interface rate, and the control circuit can also quickly adjust the interface parameters of the interface of the control circuit, wherein the interface parameters of the interface of the control circuit and the interface parameters of the interface of the storage medium may be the same.
Illustratively, when a connection bus between an interface of the control circuit and an interface of the storage medium is in an idle state, the control circuit sends a drive resistance of the interface of the storage medium, a termination resistance on chip, and an operating clock signal to the interface of the storage medium. Optionally, the control circuit may also send parameters such as Vref and PVT of the interface of the storage medium to the interface of the storage medium.
Illustratively, the memory includes a plurality of memory granules, and the memory medium in the embodiments of the present application may be one or more memory granules in the memory, that is, the memory medium is a part of the memory granules in the plurality of memory granules. Taking a memory as an example of flash, the control circuit is simultaneously connected with one or more groups of flash bare chips (die), each group of flash die comprises 8 flash die, and each flash die corresponds to one interface. The storage particles may be one or more flash die in the flash, and when a connection bus between an interface of the control circuit and the interface of the one or more flash die is in an idle state, interface parameters are sent to the interface of the one or more flash die. That is, when the connection bus between the interface of the control circuit and the interface of one (or some) of the storage particles in the memory is in an idle state, the interface parameters of the corresponding storage particles are adjusted, so that the traffic transmission on the interfaces of other storage particles in the memory is not affected.
In the technical solution provided in the embodiments of the present application, a control circuit corresponding to a storage medium may determine, according to a target interface rate, an interface parameter of the storage medium that matches the target interface rate, and when a connection bus between an interface of the control circuit and an interface of the storage medium is in an idle state, send the interface parameter to the interface of the storage medium. Compared with the prior art that the interface parameters of the interface of the memory are adjusted at the time of stopping service transmission, the interface parameters are adjusted when the connecting bus between the interface of the control circuit and the interface of the storage medium is in an idle state, and the ongoing service transmission is not required to be stopped, so that the delay of the service transmission can be avoided.
As shown in fig. 3, an example of a method of adjusting interface parameters of a storage medium according to an embodiment of the present application is shown. The operating frequency for the interface is switched from high frequency to low frequency.
301, a system performance sensing circuit senses a change in a current system performance requirement, which sends the current system performance requirement to a control circuit in a controller. Alternatively, the control circuit may include a power consumption control circuit and an IO control circuit. The interface of the IO control circuit is the interface of the control circuit. The system performance sensing circuit may be a circuit in the controller or may be a circuit outside the controller connected to the controller.
The system performance aware circuit may, for example, send current system performance requirements to power consumption control circuitry in the controller.
302, the power consumption control circuit receives the current system performance requirement sent by the system performance sensing circuit, and starts the system power consumption control.
Specifically, the power consumption control circuit determines a target interface rate matched with the current system performance requirement according to the current system performance requirement; the power consumption control circuit determines parameters such as the size of a driving resistor, the size of ODT and the working frequency of an interface of a storage medium matched with the target interface rate according to the target interface rate.
The operating frequency of the interface is switched from high frequency to low frequency, that is, the target interface rate is switched from high rate to low rate. Because the target interface rate is reduced, the power consumption control circuit increases the size of the drive resistance of the interface of the memory medium, does not connect the ODT, or increases the size of the ODT of the interface of the memory medium, reduces the operating frequency of the operating clock signal, and can reduce the power consumption of the interface, thereby being capable of reducing the power consumption of the memory system.
The power consumption control circuit sends an IO power consumption control request to the IO control circuit, wherein the IO power consumption control request comprises parameters such as the size of a driving resistor of an interface of a storage medium, the size of ODT, the working frequency and the like, and the parameters are matched with the target interface in rate.
303, the IO control circuit receives the IO power consumption control request sent by the power consumption control circuit.
The IO control circuit sends a clock adjustment request to a clock generation circuit in the controller, wherein the clock adjustment request comprises the working frequency of an interface of the storage medium which is matched with the target interface in rate, and the clock adjustment request is used for requesting the clock generation circuit to generate a working clock signal of the working frequency.
The IO control circuit receives the operation clock signal of the operation frequency generated by the clock generation circuit.
304, the IO control circuit predicts the behavior on the connection bus between the interface of the IO control circuit/controller and the interface of the storage medium. When the connection bus between the interface of the IO control circuit/controller and the interface of the storage medium is in an idle state, the IO control circuit/controller sends interface parameters such as the size of a driving resistor of the interface of the storage medium, the size of ODT, a working clock signal and the like which are matched with the target interface rate to the interface of the storage medium. Optionally, the interface parameters of the storage medium may further include interface parameters such as Vref and PVT of the interface of the storage medium.
When the connection bus between the interface of the IO control circuit/controller/control circuit and the interface of the storage medium is not in an idle state, the current service transmission is not stopped, and the completion of the service data transmission is waited.
Illustratively, when a connection bus between an interface of the IO control circuit/controller and an interface of the storage medium is in an idle state, the IO control circuit/controller sends first indication information/first instructions to the interface of the storage medium, where the first indication information/first instructions include interface parameters such as a magnitude of a driving resistor of the interface of the storage medium, a magnitude of ODT, and an operating clock signal, which are rate-matched with a target interface.
The IO control circuit adjusts interface parameters of the interface of the IO control circuit/controller, which may be the same as interface parameters of the interface of the storage medium 305.
It should be appreciated that the IO control circuit and the power consumption control circuit may be integrated circuits, collectively referred to as control circuits. The IO control circuit and the power consumption control circuit may be separate and distinct hardware circuits.
305 and 304 may be out of order, 305 may precede 304, or 305 may be performed simultaneously with 304. The present application is not particularly limited thereto.
As shown in fig. 4, another example of a method of adjusting interface parameters of a storage medium according to an embodiment of the present application is shown. The operating frequency for the interface is switched from low frequency to high frequency.
The system performance sensing circuit senses 401 a change in the current system performance requirement and sends the current system performance requirement to a control circuit in the controller. Alternatively, the control circuit may include a power consumption control circuit and an IO control circuit. The interface of the IO control circuit is the interface of the control circuit. The system performance sensing circuit may be a circuit in the controller or may be a circuit outside the controller connected to the controller.
The system performance aware circuit may, for example, send current system performance requirements to power consumption control circuitry in the controller.
402, the power consumption control circuit receives the current system performance requirement sent by the system performance sensing circuit, and starts the system power consumption control.
Specifically, the power consumption control circuit determines a target interface rate matched with the current system performance requirement according to the current system performance requirement; the power consumption control circuit determines parameters such as the size of a driving resistor, the size of ODT and the working frequency of an interface of a storage medium matched with the target interface rate according to the target interface rate.
The operating frequency of the interface is switched from low to high frequency, that is, the target interface rate is switched from low to high rate. Because the target interface rate increases, the power consumption control circuit decreases the size of the driving resistance of the interface of the memory medium, connects the ODT, or decreases the size of the ODT of the interface of the memory medium, increases the operating frequency of the operating clock signal. The larger the target interface speed is, the higher the requirement on signal integrity is, and the reduction of the size of the drive resistor and the ODT of the interface can enhance the signal integrity transmitted by the interface.
The power consumption control circuit sends an IO power consumption control request to the IO control circuit, wherein the IO power consumption control request comprises parameters such as the size of a driving resistor of an interface of a storage medium, the size of ODT, the working frequency and the like, and the parameters are matched with the target interface in rate.
403, the IO control circuit receives the IO power consumption control request sent by the power consumption control circuit.
The IO control circuit sends a clock adjustment request to a clock generation circuit in the controller, wherein the clock adjustment request comprises the working frequency of an interface of the storage medium which is matched with the target interface in rate, and the clock adjustment request is used for requesting the clock generation circuit to generate a working clock signal of the working frequency.
The IO control circuit receives the operation clock signal of the operation frequency generated by the clock generation circuit.
404, the IO control circuit predicts the behavior on the connection bus between the interface of the IO control circuit/controller and the interface of the storage medium. When the connection bus between the interface of the IO control circuit/controller and the interface of the storage medium is in an idle state, the IO control circuit/controller sends interface parameters such as the size of a driving resistor of the interface of the storage medium, the size of ODT, a working clock signal and the like which are matched with the target interface rate to the interface of the storage medium. Optionally, the interface parameters of the storage medium may further include interface parameters such as Vref and PVT of the interface of the storage medium.
When the connection bus between the interface of the IO control circuit/controller/control circuit and the interface of the storage medium is not in an idle state, the current service transmission is not stopped, and the completion of the service data transmission is waited.
Illustratively, when a connection bus between an interface of the IO control circuit/controller and an interface of the storage medium is in an idle state, the IO control circuit/controller sends first indication information/first instructions to the interface of the storage medium, where the first indication information/first instructions include interface parameters such as a magnitude of a driving resistor of the interface of the storage medium, a magnitude of ODT, and an operating clock signal, which are rate-matched with a target interface.
The IO control circuit adjusts 405 interface parameters of an interface of the IO control circuit/controller, which may be the same as interface parameters of an interface of the storage medium.
It should be appreciated that the IO control circuit and the power consumption control circuit may be integrated circuits, collectively referred to as control circuits. The IO control circuit and the power consumption control circuit may be separate and distinct hardware circuits.
405 and 404 may be out of order, 405 may precede 404, or 405 may be performed simultaneously with 404. The present application is not particularly limited thereto.
As shown in fig. 5, a schematic diagram of a controller 500 of a storage medium according to an embodiment of the present application is shown, where the controller 500 includes:
a control circuit 510, configured to determine, according to a target interface rate, an interface parameter of the storage medium that matches the target interface rate, where the control circuit is a control circuit corresponding to the storage medium;
the control circuit 510 is further configured to send the interface parameter to the interface of the storage medium when a connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state.
Optionally, the interface parameters include a magnitude of a drive resistance of an interface of the storage medium, a magnitude of an on-chip termination resistance ODT, and an operating clock signal.
Optionally, the controller further includes a clock generation circuit 520;
the control circuit 510 is specifically configured to:
determining the size of the driving resistor, the size of the ODT and the working frequency of the interface of the storage medium matched with the target interface rate according to the target interface rate;
sending a clock adjustment request to the clock generation circuit 520, wherein the clock adjustment request includes the operating frequency, and the clock adjustment request is used for requesting the clock generation circuit 520 to generate the operating clock signal of the operating frequency;
The operating clock signal generated by the clock generation circuit 520 is received.
Optionally, the control circuit 510 is specifically configured to:
decreasing the magnitude of the drive resistance, connecting the ODT, or decreasing the magnitude of the ODT when the target interface rate increases;
when the target interface rate decreases, the magnitude of the driving resistance is increased, the ODT is not connected, or the magnitude of the ODT is increased.
Optionally, the control circuit 510 is further configured to determine the target interface rate according to a current system performance requirement, where the current system performance requirement includes at least one of: bandwidth of access to the storage medium and access latency of access to the storage medium.
Optionally, the controller further includes a system performance sensing circuit 530;
the system performance sensing circuit 530 is configured to sense the current system performance requirement;
the system performance aware circuit 530 is further configured to send the current system performance requirement to the control circuit;
the control circuit 510 is further configured to receive the current system performance requirements from the system performance aware circuit 530. It should be appreciated that the system performance aware circuit 530 may also be a circuit external to the controller that is coupled to the controller. Optionally, the memory includes a plurality of storage granules, and the storage medium is one or more of the storage granules.
As shown in fig. 6, an example of a controller 600 of a storage medium provided in an embodiment of the present application is shown.
The controller includes: IO control circuit 611, power consumption control circuit 612, clock generation circuit 620, system performance aware circuit 630, and adjustment recording circuit 640. The IO control circuit 611 and the power consumption control circuit 612 may be collectively referred to as a control circuit. The IO control circuit 611 and the power consumption control circuit 612 may be the control circuit 510 in fig. 5.
A system performance sensing circuit 630 for sensing a change in a current system performance requirement, the current system performance requirement comprising at least one of: a bandwidth of accessing the storage medium and an access delay of accessing the storage medium;
the system performance aware circuit 630 is also used to send current system performance requirements to the power consumption control circuit 612 in the controller. It should be appreciated that the system performance aware circuit 630 may also be a circuit external to the controller that is connected to the controller.
A power consumption control circuit 612 for:
receiving a current system performance requirement sent by the system performance aware circuit 630;
determining a target interface rate matched with the current system performance requirement according to the current system performance requirement;
And determining parameters such as the size of a driving resistor, the size of ODT (ODT) and the working frequency of an interface of the storage medium matched with the target interface rate according to the target interface rate. Optionally, the memory includes a plurality of storage granules, and the storage medium may be one or more of the plurality of storage granules.
The power consumption control circuit 612 is further configured to send an IO power consumption control request to the IO control circuit 611, where the IO power consumption control request includes parameters such as a size of a driving resistor of an interface of the storage medium rate-matched with the target interface, a size of ODT, and an operating frequency.
The IO control circuit 611 is configured to:
receiving an IO power consumption control request sent by the power consumption control circuit 612;
a clock adjustment request is sent to the clock generation circuit 620, where the clock adjustment request includes an operating frequency of an interface of the storage medium that is rate matched to the target interface, and the clock adjustment request is used to request the clock generation circuit 620 to generate an operating clock signal of the operating frequency.
The clock generation circuit 620 is configured to generate an operation clock signal of the operation frequency, and send the operation clock signal of the operation frequency to the IO control circuit 611.
The IO control circuit 611 is also used to predict behavior on the connection bus between the interface of the IO control circuit and the interface of the storage medium. When a connecting bus between an interface of the IO control circuit and an interface of the storage medium is in an idle state, the IO control circuit sends interface parameters such as the size of a driving resistor, the size of ODT (on-die termination) and a working clock signal of the interface of the storage medium, which is matched with the target interface in rate, to the interface of the storage medium. Optionally, the interface parameters of the storage medium may further include interface parameters such as Vref and PVT of the interface of the storage medium.
The IO control circuit 611 is further configured to adjust an interface parameter of an interface of the IO control circuit, where the interface parameter of the interface of the IO control circuit may be the same as an interface parameter of an interface of the storage medium.
An adjustment recording circuit 640 for recording which storage media in memory have their interface parameters adjusted and/or which storage media in memory have their interface parameters not adjusted. Alternatively, the adjustment recording circuit 640 may be integrated in the IO control circuit 611.
The present embodiment provides a communication device 700, and as shown in fig. 7, a schematic block diagram of a communication device 700 of the present embodiment is shown.
The apparatus 700 includes: a processor 710 and a transceiver 720, said transceiver 720 being adapted to receive computer code or instructions and to transmit them to said processor 710, said processor 710 executing said computer code or instructions as a method in any possible implementation in embodiments of the present application.
The processor 710 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a digital signal processor (digital signal processor, DSP), an application specific integrated circuit (application specific integrated circuit, ASIC), an off-the-shelf programmable gate array (field programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.
The present application also provides a computer-readable storage medium having stored thereon a computer program for implementing the method in the above method embodiments. The computer program, when run on a computer or processor, causes the computer or processor to perform the method of the method embodiments described above.
Embodiments of the present application also provide a computer program product comprising computer program code for causing the method of the above-described method embodiments to be performed when said computer program code is run on a computer.
The embodiment of the application also provides a chip, which comprises a processor, wherein the processor is connected with a memory, the memory is used for storing a computer program, and the processor is used for executing the computer program stored in the memory, so that the chip executes the method in the embodiment of the method.
In addition, the term "and/or" in this application is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship; the term "at least one" in the present application may mean "one" and "two or more", for example, A, B and C may mean: the seven cases are that A alone, B alone, C alone, A and B together, A and C together, C and B together, A and B together, and C together.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may implement the described functionality using different approaches for each particular application, but such implementation is not to be considered as beyond the scope of this application.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the system, apparatus and unit described above may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.
In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (17)

1. A method of adjusting interface parameters of a storage medium, comprising:
the control circuit determines interface parameters of the storage medium matched with the target interface rate according to the target interface rate, wherein the control circuit is a control circuit corresponding to the storage medium;
when the connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state, the control circuit sends the interface parameters to the interface of the storage medium.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the interface parameters include a magnitude of a driving resistance of an interface of the memory medium, a magnitude of an on-chip termination resistance ODT, and an operating clock signal.
3. The method of claim 2, wherein the control circuit determining the interface parameters of the storage medium that match the target interface rate based on the target interface rate comprises:
The control circuit determines the size of the driving resistor, the size of the ODT and the working frequency of the interface of the storage medium matched with the target interface rate according to the target interface rate;
the control circuit sends a clock adjustment request to a clock generation circuit, wherein the clock adjustment request comprises the working frequency and is used for requesting the clock generation circuit to generate the working clock signal of the working frequency;
the control circuit receives the operating clock signal generated by the clock generating circuit.
4. A method according to claim 2 or 3, characterized in that,
when the target interface rate increases, the control circuit decreases the magnitude of the driving resistance, connects the ODT, or decreases the magnitude of the ODT;
when the target interface rate decreases, the control circuit increases the magnitude of the drive resistance, turns off the ODT, or increases the magnitude of the ODT.
5. The method according to any one of claims 1 to 4, further comprising:
the control circuit determines the target interface rate based on current system performance requirements including at least one of:
A bandwidth of accessing the storage medium or an access delay of accessing the storage medium.
6. The method according to any one of claims 1 to 5, further comprising:
the system performance sensing circuit senses the current system performance requirement;
the system performance aware circuit sends the current system performance requirements to the control circuit.
7. The method according to any one of claim 1 to 6, wherein,
the memory includes a plurality of memory granules, and the memory medium is one or more of the plurality of memory granules.
8. A controller for a storage medium, comprising:
the control circuit is used for determining interface parameters of the storage medium matched with the target interface rate according to the target interface rate, and the control circuit is a control circuit corresponding to the storage medium;
the control circuit is further configured to send the interface parameter to the interface of the storage medium when a connection bus between the interface of the control circuit and the interface of the storage medium is in an idle state.
9. The controller according to claim 8, wherein,
The interface parameters include a magnitude of a driving resistance of an interface of the memory medium, a magnitude of an on-chip termination resistance ODT, and an operating clock signal.
10. The controller of claim 9, further comprising a clock generation circuit;
the control circuit is specifically used for:
determining the size of the driving resistor, the size of the ODT and the working frequency of the interface of the storage medium matched with the target interface rate according to the target interface rate;
sending a clock adjustment request to the clock generation circuit, wherein the clock adjustment request comprises the working frequency and is used for requesting the clock generation circuit to generate the working clock signal of the working frequency;
the operating clock signal generated by the clock generating circuit is received.
11. The controller according to claim 9 or 10, wherein the control circuit is specifically configured to:
decreasing the magnitude of the drive resistance, connecting the ODT, or decreasing the magnitude of the ODT when the target interface rate increases;
when the target interface rate decreases, the magnitude of the driving resistance is increased, the ODT is not connected, or the magnitude of the ODT is increased.
12. The controller according to any one of claims 8 to 11, wherein,
the control circuitry is further configured to determine the target interface rate based on current system performance requirements, the current system performance requirements including at least one of:
bandwidth of access to the storage medium and access latency of access to the storage medium.
13. The controller according to any one of claims 8 to 12, further comprising a system performance aware circuit;
the system performance sensing circuit is used for sensing the current system performance requirement;
the system performance aware circuit is also configured to send the current system performance requirement to the control circuit.
14. The controller according to any one of claims 8 to 13, wherein,
the memory includes a plurality of memory granules, and the memory medium is one or more of the plurality of memory granules.
15. A communication device, comprising: a processor and a transceiver for receiving computer code or instructions and transmitting to the processor, the processor executing the computer code or instructions to implement the method of any one of claims 1 to 7.
16. A computer-readable storage medium, comprising:
the computer readable storage medium has a computer program stored therein;
the computer program, when run on a computer or a processor, causes the computer or the processor to perform the method of any of claims 1 to 7.
17. A computer program product comprising a computer program which, when executed, causes the method of any one of claims 1 to 7 to be implemented.
CN202210102365.XA 2022-01-27 2022-01-27 Method and apparatus for adjusting interface parameters of storage medium Pending CN116560486A (en)

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