WO2021241201A1 - Power supply system, and plasma processing device - Google Patents

Power supply system, and plasma processing device Download PDF

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Publication number
WO2021241201A1
WO2021241201A1 PCT/JP2021/017853 JP2021017853W WO2021241201A1 WO 2021241201 A1 WO2021241201 A1 WO 2021241201A1 JP 2021017853 W JP2021017853 W JP 2021017853W WO 2021241201 A1 WO2021241201 A1 WO 2021241201A1
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WIPO (PCT)
Prior art keywords
power supply
node
switch
supply system
output
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PCT/JP2021/017853
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French (fr)
Japanese (ja)
Inventor
洋 大友
清一 岡本
崇央 進藤
靖 森田
龍夫 松土
Original Assignee
東京エレクトロン株式会社
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Publication of WO2021241201A1 publication Critical patent/WO2021241201A1/en

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
    • H05H1/00—Generating plasma; Handling plasma
    • H05H1/24—Generating plasma
    • H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy

Definitions

  • An exemplary embodiment of the present disclosure relates to a power supply system and a plasma processing apparatus.
  • a plasma processing device is used for substrate processing such as film formation and etching.
  • the plasma processing device produces plasma from the gas in the chamber.
  • One type of such plasma treatment is described in Patent Document 1.
  • a pulsed DC voltage is used for generating plasma.
  • the present disclosure provides a technique for overshooting a pulsed DC voltage and reducing power consumption.
  • a power supply system includes a DC power supply, a first parallel circuit, a first switch, a second parallel circuit, a second switch, and an output.
  • the first parallel circuit includes a first node, a second node, a first damping resistor, and a first inductor.
  • the first damping resistor and the first inductor are connected in parallel between the first node and the second node.
  • the first switch is connected between the positive electrode of the DC power supply and the first node.
  • the second parallel circuit includes a third node, a fourth node, a second damping resistor, and a second inductor.
  • the second damping resistor and the second inductor are connected in parallel between the third node and the fourth node.
  • the second switch is connected between the negative electrode of the DC power supply and the third node.
  • the output is connected to a second node and a fourth node.
  • 3A and 3B are diagrams showing an example of a voltage waveform and an example of a current waveform at the output of the power supply system according to the first comparative example, respectively.
  • 4A and 4B are diagrams showing an example of a voltage waveform at the output of the power supply system according to the second comparative example and an example of a current waveform at the second damping resistor, respectively.
  • 5 (a), 5 (b), and 5 (c) are examples of voltage waveforms at the output of the power supply system 100B shown in FIG. 2, examples of current waveforms at the second damping resistor, and first.
  • FIG. 7 is a diagram showing an example of a pulsed DC voltage that can be output by the power supply system shown in FIG. 7. It is a figure which shows the plasma processing apparatus which concerns on one exemplary Embodiment. It is a figure which shows the plasma processing apparatus which concerns on another exemplary embodiment. It is a figure which shows the plasma processing apparatus which concerns on still another exemplary Embodiment. It is a figure which shows the example of the voltage waveform in the output of the power-source system of the plasma processing apparatus which concerns on a comparative example. It is a figure which shows an example of a circuit model.
  • a power supply system includes a DC power supply, a first parallel circuit, a first switch, a second parallel circuit, a second switch, and an output.
  • the first parallel circuit includes a first node, a second node, a first damping resistor, and a first inductor.
  • the first damping resistor and the first inductor are connected in parallel between the first node and the second node.
  • the first switch is connected between the positive electrode of the DC power supply and the first node.
  • the second parallel circuit includes a third node, a fourth node, a second damping resistor, and a second inductor.
  • the second damping resistor and the second inductor are connected in parallel between the third node and the fourth node.
  • the second switch is connected between the negative electrode of the DC power supply and the third node.
  • the output is connected to a second node and a fourth node.
  • the first switch and the second switch are alternately in a conductive state, so that a pulsed DC voltage is output from the output.
  • the overshoot at the rising and falling edges of the pulsed DC voltage is reduced by the first damping resistor and the second damping resistor.
  • the current flows through the first inductor or the second inductor, so that the power consumption in the first damping resistor and the second damping resistor is suppressed. Will be done. Therefore, according to this power supply system, power consumption is reduced.
  • the positive electrode of the DC power supply may be connected to ground.
  • a unipolar pulse is generated as a pulsed DC voltage.
  • the DC power supply may include a first DC power supply and a second DC power supply.
  • the negative electrode of the first DC power supply constitutes the negative electrode of the DC power supply device.
  • the positive electrode of the first DC power supply and the negative electrode of the second DC power supply are connected to the ground.
  • the positive electrode of the second DC power supply constitutes the positive electrode of the DC power supply device.
  • a bipolar pulse is generated as a pulsed DC voltage.
  • the power supply system may further include a third parallel circuit and a third switch.
  • the third parallel circuit includes a fifth node, a sixth node, a third damping resistor, and a third inductor.
  • the sixth node is connected to the output of the power supply system.
  • the third damping resistor and the third inductor are connected in parallel between the fifth node and the sixth node.
  • the third switch is connected between the ground and the fifth node.
  • the output is connected to ground when both the first switch and the second switch are in the non-conducting state and the third switch is in the conducting state.
  • the first parallel circuit may further include a first diode.
  • the anode of the first diode is connected to the first damping resistor and the cathode of the first diode is connected to the second node.
  • the second parallel circuit may further include a second diode.
  • the anode of the second diode is connected to the fourth node and the cathode of the second diode is connected to the second damping resistor.
  • the first diode breaks the current loop between the first inductor and the first damping resistor when the first switch is open. Therefore, the energy from the first inductor is suppressed from being consumed in the first damping resistor.
  • the second diode breaks the current loop between the second inductor and the second damping resistor when the second switch is open. Therefore, the energy from the second inductor is suppressed from being consumed in the second damping resistor.
  • the power supply system may further include a diode having an anode connected to the negative electrode of the DC power supply and a cathode connected to the first node. With this diode, the energy from the first inductor when the first switch is opened is regenerated to the DC power supply.
  • the power supply system may further include a diode having a cathode connected to the positive electrode of the DC power supply and an anode connected to the second node. With this diode, the energy from the second inductor when the second switch is opened is regenerated to the DC power supply.
  • the power supply system may further include a control unit.
  • the control unit may be configured to control the first switch and the second switch so that the first switch and the second switch are alternately in a conductive state.
  • the power supply system may further include a control unit.
  • the control unit is configured to be capable of executing control that sets the first switch to the conductive state and sets the second switch and the third switch to the non-conducting state. Further, the control unit is configured to be capable of executing control for setting the third switch to the conductive state and setting the first switch and the second switch to the non-conducting state. Further, the control unit is configured to be capable of executing control for setting the second switch to the conductive state and setting the first switch and the third switch to the non-conducting state.
  • a plasma processing apparatus in another exemplary embodiment, includes a chamber, a substrate support, electrodes, and a power supply system.
  • the board support is configured to support the board in the chamber.
  • the power supply system is any of the various exemplary embodiments described above.
  • the power supply system is electrically connected to the electrodes to generate plasma in the chamber or to draw ions from the plasma in the chamber to the substrate supported by the substrate support.
  • the power supply system according to various exemplary embodiments described below can be used in a plasma processing apparatus.
  • FIG. 1 is a diagram showing a power supply system according to one exemplary embodiment.
  • the power supply system 100A shown in FIG. 1 includes a DC power supply device 102, a first parallel circuit 110, a first switch 115, a second parallel circuit 120, a second switch 125, and an output 140.
  • the power supply system 100A is configured to output a pulsed DC voltage from the output 140.
  • the power supply system 100A is configured to generate a unipolar pulse as a pulsed DC voltage.
  • the positive electrode of the DC power supply device 102 is connected to the ground.
  • the DC power supply 102 may include a DC power supply 102a.
  • the DC power supply 102a may be a variable DC power supply.
  • the positive electrode of the DC power supply 102a may constitute the positive electrode of the DC power supply device 102.
  • the negative electrode of the DC power supply device 102 may constitute the negative electrode of the DC power supply device 102.
  • the first parallel circuit 110 includes a node 111 (first node), a node 112 (second node), a first damping resistor 110r, and a first inductor 110i.
  • the first damping resistor 110r and the first inductor 110i are connected in parallel between the node 111 and the node 112.
  • Node 112 is connected to output 140.
  • the first switch 115 is connected between the positive electrode of the DC power supply device 102 and the node 111. When the first switch 115 is in the conductive state, the positive electrode of the DC power supply 102 is connected to the node 111. When the first switch 115 is in the non-conducting state, the connection between the positive electrode of the DC power supply 102 and the node 111 is disconnected.
  • the first switch 115 is, for example, a switching transistor.
  • the second parallel circuit 120 includes a node 121 (third node), a node 122 (fourth node), a second damping resistor 120r, and a second inductor 120i.
  • the second damping resistor 120r and the second inductor 120i are connected in parallel between the node 121 and the node 122.
  • the node 122 is connected to the output 140.
  • the second switch 125 is connected between the negative electrode of the DC power supply device 102 and the node 121.
  • the negative electrode of the DC power supply 102 is connected to the node 121.
  • the second switch 125 is in the non-conducting state, the connection between the negative electrode of the DC power supply 102 and the node 121 is cut off.
  • the second switch 125 is, for example, a switching transistor.
  • the power supply system 100A shown in FIG. 1 may further include a control unit 150.
  • the control unit 150 is configured to control the first switch 115 and the second switch 125 by giving control signals to the first switch 115 and the second switch 125, respectively.
  • the control signal from the control unit 150 is given to the control terminal of the first switch 115 and the control terminal of the second switch 125, respectively. Be done.
  • the control unit 150 may control the first switch 115 and the second switch 125 so that the first switch 115 and the second switch 125 are alternately in a conductive state.
  • the control unit 150 may include a microprocessor.
  • the output 140 is connected to the ground when the first switch 115 is in the conductive state and the second switch 125 is in the non-conducting state.
  • the output 140 is connected to the negative electrode of the DC power supply device 102, and a negative voltage is output from the output 140. Therefore, in the power supply system 100A, the unipolar pulse is output as a pulsed DC voltage when the first switch 115 and the second switch 125 are alternately in a conductive state.
  • the overshoot at the rising and falling edges of the pulsed DC voltage is reduced by the first damping resistor 110r and the second damping resistor 120r. Further, during the period when the level of the pulsed DC voltage is stable, the current flows through the first inductor 110i or the second inductor 120i, so that the first damping resistor 110r and the second damping resistor 120r have a current. Power consumption is suppressed. Therefore, according to the power supply system 100A, the power consumption is reduced.
  • FIG. 2 is a diagram showing a power supply system according to another exemplary embodiment.
  • the power supply system 100B shown in FIG. 2 is different from the power supply system 100A in that it generates a bipolar pulse as a pulsed DC voltage.
  • the differences between the power supply system 100B and the power supply system 100A will be described.
  • the DC power supply device 102 includes a DC power supply 102b (second DC power supply) in addition to the DC power supply 102a (first DC power supply).
  • Each of the DC power supply 102a and the DC power supply 102b may be a variable DC power supply.
  • the DC power supply 102a and the DC power supply 102b are connected in series. Specifically, the positive electrode of the DC power supply 102a and the negative electrode of the DC power supply 102b are connected to each other. The positive electrode of the DC power supply 102a and the negative electrode of the DC power supply 102b are connected to the ground.
  • the negative electrode of the DC power supply 102a constitutes the negative electrode of the DC power supply device 102.
  • the positive electrode of the DC power supply 102b constitutes the positive electrode of the DC power supply device 102.
  • the output 140 is connected to the positive electrode of the DC power supply device 102, and a positive voltage is supplied from the output 140. It is output. Further, when the first switch 115 is in the non-conducting state and the second switch 125 is in the conducting state, the output 140 is connected to the negative electrode of the DC power supply device 102, and a negative voltage is output from the output 140. .. Therefore, in the power supply system 100B, the first switch 115 and the second switch 125 are alternately switched to the conduction state, so that a bipolar pulse is output as a pulsed DC voltage.
  • the overshoot at the rising and falling edges of the pulsed DC voltage is reduced by the first damping resistor 110r and the second damping resistor 120r, as in the power supply system 100A. Further, also in the power supply system 100B, the power consumption in the first damping resistor 110r and the second damping resistor 120r is suppressed as in the power supply system 100A. Therefore, according to the power supply system 100B, the power consumption is reduced as in the power supply system 100A.
  • the power supply system 100B will be considered while comparing it with the power supply system of the first comparative example and the power supply system of the second comparative example.
  • the power supply system of the first comparative example is different from the power supply system 100B in that it does not include the first parallel circuit 110 and the second parallel circuit 120.
  • the first switch 115 is connected between the positive electrode of the DC power supply device 102 and the output 140.
  • the second switch 125 is connected between the negative electrode of the DC power supply device 102 and the output 140.
  • the power supply system of the second comparative example is different from the power supply system 100B in that it does not include the first inductor 110i and the second inductor 120i.
  • the first damping resistor 110r is connected between the first switch 115 and the output 140.
  • the second damping resistor 120r is connected between the second switch 125 and the output 140.
  • FIG. 3 and (b) of FIG. 3 are diagrams showing an example of a voltage waveform and an example of a current waveform at the output of the power supply system according to the first comparative example, respectively.
  • the power supply system of the first comparative example does not include the first damping resistor 110r and the second damping resistor 120r. Therefore, in the power supply system of the first comparative example, as shown in FIG. 3A, an overshoot occurs in the voltage Vout at the output 140. Further, in the power supply system of the first comparative example, as shown in FIG. 3B, the positive electrode to the negative electrode of the DC power supply device 102 during the period when the voltage Vout at the output 140 is low and stable. A current (eg, a current of about 1 A) flows toward.
  • a current eg, a current of about 1 A
  • FIG. 4 and (b) of FIG. 4 are diagrams showing an example of a voltage waveform at the output of the power supply system according to the second comparative example and an example of a current waveform at the second damping resistor, respectively.
  • the power supply system of the second comparative example includes a first damping resistor 110r and a second damping resistor 120r. Therefore, in the power supply system of the second comparative example, overshoot of the voltage Vout at the output 140 is suppressed as shown in FIG. 4 (a). However, in the power supply system of the second comparative example, as shown in FIG. 4B, the current is applied to the second damping resistor 120r during the period when the voltage Vout at the output 140 is at a low level and is stable.
  • a current of about 1 A flows.
  • a current flows through the first damping resistor 110r and the second damping resistor 120r during the period when the voltage Vout at the output 140 is stable. Therefore, the power consumption of the power supply system of the second comparative example is large.
  • 5 (a), 5 (b), and 5 (c) are examples of voltage waveforms at the output of the power supply system 100B shown in FIG. 2, examples of current waveforms at the second damping resistor, and first. It is a figure which shows the example of the current waveform in 2 inductors.
  • the second damping resistor is used during the period when the voltage Vout at the output 140 is at a low level and is stable.
  • FIG. 6 is a diagram showing a power supply system according to still another exemplary embodiment. Similar to the power supply system 100B, the power supply system 100C shown in FIG. 6 generates a bipolar pulse as a pulsed DC voltage. Hereinafter, the differences between the power supply system 100C and the power supply system 100B will be described.
  • the first parallel circuit 110 further includes the first diode 110d.
  • the first diode 110d is connected between the first damping resistor 110r and the node 112.
  • the anode of the first diode 110d is connected to the first damping resistor 110r.
  • the cathode of the first diode 110d is connected to the node 112.
  • the first diode 110d breaks the current loop between the first inductor 110i and the first damping resistor 110r when the first switch is open. Therefore, the energy from the first inductor 110i is suppressed from being consumed in the first damping resistor 110r.
  • the second parallel circuit 120 further includes the second diode 120d.
  • the second diode 120d is connected between the second damping resistor 120r and the node 122.
  • the cathode of the second diode 120d is connected to the second damping resistor 120r.
  • the anode of the second diode 120d is connected to the node 122.
  • the second diode 120d breaks the current loop between the second inductor 120i and the second damping resistor 120r when the second switch is open. Therefore, the energy from the second inductor 120i is suppressed from being consumed in the second damping resistor 120r.
  • the power supply system 100C may further include a diode 161 and a diode 162.
  • the diode 161 is connected between the negative electrode of the DC power supply 102 and the node 111.
  • the anode of the diode 161 is connected to the negative electrode of the DC power supply 102.
  • the cathode of the diode 161 is connected to the node 111.
  • the diode 162 is connected between the positive electrode of the DC power supply 102 and the node 121.
  • the cathode of the diode 162 is connected to the positive electrode of the DC power supply 102.
  • the anode of the diode 162 is connected to the node 121.
  • the diode 161 regenerates the energy from the first inductor 110i when the first switch is opened to the DC power supply 102. Further, the energy from the second inductor 120i when the second switch is opened by the diode 162 is regenerated to the DC power supply device 102.
  • FIG. 7 is a diagram showing a power supply system according to still another exemplary embodiment.
  • FIG. 8 is a diagram showing an example of a pulsed DC voltage that can be output by the power supply system shown in FIG. 7. Similar to the power supply system 100B, the power supply system 100D shown in FIG. 7 generates a bipolar pulse as a pulsed DC voltage. Hereinafter, the differences between the power supply system 100D and the power supply system 100B will be described.
  • the power supply system 100D shown in FIG. 7 further includes a third parallel circuit 130 and a third switch 135.
  • the third parallel circuit 130 includes a node 131 (fifth node), a node 132 (sixth node), a third damping resistor 130r, and a third inductor 130i.
  • the node 132 is connected to the output 140.
  • the third damping resistor 130r and the third inductor 130i are connected in parallel between the node 131 and the node 132.
  • the third switch 135 is connected between the ground and the node 131. In one embodiment, the third switch 135 is connected between the node and the node 131 to which the positive electrode of the DC power supply 102a and the negative electrode of the DC power supply 102b are connected.
  • the third switch 135 is, for example, a switching transistor.
  • the control unit 150 gives control signals to the first switch 115, the second switch 125, and the third switch 135, respectively, to give a control signal to the first switch 115, the second switch 125, and the third switch 135. It controls the third switch 135.
  • the third switch 135 is a switching transistor, the control signal from the control unit 150 is given to the control terminal of the third switch 135.
  • the control unit 150 can execute control for setting the first switch 115 in the conductive state and setting the second switch 125 and the third switch 135 in the non-conducting state.
  • the control unit 150 may execute control for setting the second switch 125 to the conductive state and setting the first switch 115 and the third switch 135 to the non-conducting state. Further, the control unit 150 may execute control for setting the third switch 135 to the conductive state and setting the first switch 115 and the second switch 125 to the non-conducting state.
  • the power supply system 100B when the first switch 115 is in the conductive state, the second switch 125 is in the non-conducting state, and a positive voltage is output from the output 140. Further, in the power supply system 100B, when the first switch 115 is in the non-conducting state, the second switch 125 is in the conducting state, and a negative voltage is output from the output 140.
  • the pulsed DC voltage when the pulsed DC voltage is periodically output, the time length of the period in which the positive DC voltage is output and the time length of the period in which the negative DC voltage is output are set in the cycle. , Depend on each other. That is, in the power supply system 100B, when the time length of the period in which the positive DC voltage is output is determined in the cycle, the time length of the period in which the negative DC voltage is output in the cycle is uniquely determined.
  • the output 140 can be connected not only to the positive electrode and the negative electrode of the DC power supply device 102 but also to the ground.
  • the pulsed DC voltage when the pulsed DC voltage is periodically output, one or more periods in which the output 140 is connected to the ground can be provided in the periodic PC.
  • the time length of the period in which the positive voltage is output and the time length of the period in which the negative voltage is output can be set independently of each other.
  • the pulsed DC voltage output from the power supply system 100D may be a negative voltage during the period P1 in the periodic PC. Further, as in the example of FIG. 8, the pulsed DC voltage output from the power supply system 100D may be a positive voltage during the period P2 in the periodic PC. As in the example of FIG. 8, the output 140 may be connected to the ground in the period before the period P1 in the periodic PC. Further, as in the example of FIG. 8, the output 140 may be connected to the ground during the period between the period P1 and the period P2 in the periodic PC.
  • the first diode 110d may be connected between the first damping resistor 110r and the node 112.
  • the second diode 120d may be connected between the second damping resistor 120r and the node 122.
  • the diode 161 may be connected between the negative electrode of the DC power supply device 102 and the node 111.
  • the diode 162 may be connected between the positive electrode of the DC power supply device 102 and the node 121.
  • FIG. 9 is a diagram showing a plasma processing apparatus according to one exemplary embodiment.
  • the plasma processing apparatus 1A shown in FIG. 9 is a capacitively coupled plasma processing apparatus.
  • the plasma processing apparatus 1A includes a chamber 10.
  • the chamber 10 provides an internal space 10s therein.
  • the central axis of the internal space 10s is the axis AX extending in the vertical direction.
  • the chamber 10 may include a chamber body 12.
  • the chamber body 12 has a substantially cylindrical shape.
  • the internal space 10s is provided in the chamber body 12.
  • the chamber body 12 is made of, for example, aluminum.
  • the chamber body 12 is electrically grounded.
  • a plasma-resistant film is formed on the inner wall surface of the chamber body 12, that is, the wall surface defining the internal space 10s.
  • This film can be a ceramic film, such as a film formed by anodizing or a film formed from yttrium oxide.
  • a passage 12p is formed on the side wall of the chamber body 12.
  • the substrate W passes through the passage 12p when being conveyed between the internal space 10s and the outside of the chamber 10.
  • a gate valve 12g is provided along the side wall of the chamber body 12 for opening and closing the passage 12p.
  • the plasma processing device 1A further includes a substrate support portion 16.
  • the substrate support portion 16 is configured to support the substrate W placed on the substrate support portion 16 in the chamber 10.
  • the substrate W may have a substantially disk shape.
  • the plasma processing apparatus 1A may further include a support portion 17 that supports the substrate support portion 16.
  • the support portion 17 extends upward from the bottom of the chamber body 12.
  • the support portion 17 has a substantially cylindrical shape.
  • the support portion 17 is formed of an insulating material such as quartz.
  • the substrate support portion 16 may include a lower electrode 18 and an electrostatic chuck 20.
  • the lower electrode 18 and the electrostatic chuck 20 are provided in the chamber 10.
  • the lower electrode 18 is formed of a conductive material such as aluminum and has a substantially disk shape.
  • the lower electrode 18 may provide a flow path 18f therein.
  • the flow path 18f is a flow path for the heat exchange medium.
  • a heat exchange medium for example, a refrigerant may be used.
  • the flow path 18f is connected to a heat exchange medium supply device (for example, a chiller unit). This supply device is provided outside the chamber 10.
  • the heat exchange medium from the supply device is supplied to the flow path 18f via the pipe 23a.
  • the heat exchange medium supplied to the flow path 18f is returned to the supply device via the pipe 23b.
  • the electrostatic chuck 20 is provided on the lower electrode 18.
  • the substrate W is placed on the electrostatic chuck 20 and held by the electrostatic chuck 20 when processed in the internal space 10s.
  • the electrostatic chuck 20 has a main body and electrodes.
  • the main body of the electrostatic chuck 20 is formed of a dielectric such as aluminum oxide or aluminum nitride.
  • the main body of the electrostatic chuck 20 has a substantially disk shape.
  • the central axis of the electrostatic chuck 20 substantially coincides with the axis AX.
  • the electrodes of the electrostatic chuck 20 are provided in the main body.
  • the electrode of the electrostatic chuck 20 has a film shape.
  • a DC power supply is electrically connected to the electrodes of the electrostatic chuck 20 via a switch. When a voltage from a DC power source is applied to the electrodes of the electrostatic chuck 20, electrostatic attraction is generated between the electrostatic chuck 20 and the substrate W. The substrate W is attracted to the electrostatic chuck 20 by the generated electrostatic attraction and is held by the electrostatic chuck 20.
  • the board support portion 16 may support the edge ring ER mounted on the board support portion 16.
  • the edge ring ER has a ring shape and is formed of, for example, silicon or silicon carbide.
  • the edge ring ER may be formed of a dielectric such as quartz.
  • the edge ring ER may be partially mounted on the electrostatic chuck 20.
  • the substrate W is placed on the electrostatic chuck 20 and in the region surrounded by the edge ring ER.
  • the plasma processing apparatus 1A may further include a gas supply line 25.
  • the gas supply line 25 supplies heat transfer gas from the gas supply mechanism, for example, He gas, to the gap between the upper surface of the electrostatic chuck 20 and the back surface (lower surface) of the substrate W.
  • the plasma processing apparatus 1A may further include an insulating region 27.
  • the insulating region 27 is arranged on the support portion 17.
  • the insulating region 27 is arranged outside the lower electrode 18 in the radial direction with respect to the axis AX.
  • the insulating region 27 extends in the circumferential direction along the outer peripheral surface of the lower electrode 18.
  • the insulating region 27 is formed of an insulator such as quartz.
  • the edge ring ER may be partially mounted on the insulating region 27.
  • the plasma processing device 1A further includes an upper electrode 30.
  • the upper electrode 30 is provided above the substrate support portion 16.
  • the upper electrode 30 closes the upper opening of the chamber body 12 together with the member 32.
  • the member 32 has an insulating property.
  • the upper electrode 30 is supported on the upper part of the chamber body 12 via the member 32.
  • the upper electrode 30 may include a top plate 34 and a support 36.
  • the lower surface of the top plate 34 defines the internal space 10s.
  • a plurality of gas discharge holes 34a are formed on the top plate 34. Each of the plurality of gas discharge holes 34a penetrates the top plate 34 in the plate thickness direction (vertical direction).
  • the top plate 34 is, but is not limited to, formed of, for example, silicon.
  • the top plate 34 may have a structure in which a plasma resistant film is provided on the surface of an aluminum member. This film can be a ceramic film, such as a film formed by anodizing or a film formed from yttrium oxide.
  • the support 36 supports the top plate 34 in a detachable manner.
  • the support 36 is made of a conductive material such as aluminum.
  • a gas diffusion chamber 36a is provided inside the support 36.
  • a plurality of gas holes 36b extend downward from the gas diffusion chamber 36a.
  • the plurality of gas holes 36b communicate with the plurality of gas discharge holes 34a, respectively.
  • a gas introduction port 36c is formed on the support 36.
  • the gas introduction port 36c is connected to the gas diffusion chamber 36a.
  • a gas supply pipe 38 is connected to the gas introduction port 36c.
  • the gas source group 40 is connected to the gas supply pipe 38 via the valve group 41, the flow rate controller group 42, and the valve group 43.
  • the gas source group 40, the valve group 41, the flow rate controller group 42, and the valve group 43 constitute the gas supply unit GS.
  • the gas source group 40 includes a plurality of gas sources.
  • Each of the valve group 41 and the valve group 43 includes a plurality of valves (for example, an on-off valve).
  • the flow rate controller group 42 includes a plurality of flow rate controllers.
  • Each of the plurality of flow rate controllers in the flow rate controller group 42 is a mass flow controller or a pressure control type flow rate controller.
  • Each of the plurality of gas sources of the gas source group 40 is connected to the gas supply pipe 38 via the corresponding valve of the valve group 41, the corresponding flow rate controller of the flow rate controller group 42, and the corresponding valve of the valve group 43. It is connected.
  • the plasma processing apparatus 1A can supply gas from one or more gas sources selected from the plurality of gas sources of the gas source group 40 to the internal space 10s at an individually adjusted flow rate.
  • a baffle plate 48 may be provided between the substrate support portion 16 or the support portion 17 and the side wall of the chamber main body 12.
  • the baffle plate 48 may be configured, for example, by coating an aluminum member with a ceramic such as yttrium oxide.
  • a large number of through holes are formed in the baffle plate 48.
  • An exhaust device 50 is connected to the exhaust pipe 52.
  • the exhaust device 50 has a pressure controller such as an automatic pressure control valve and a vacuum pump such as a turbo molecular pump, and can reduce the pressure in the internal space 10s.
  • the plasma processing device 1A further includes a power supply system 100.
  • the power supply system 100 As the power supply system 100, the power supply system 100A, 100B, 100C, or 100D described above is used.
  • the output 140 of the power supply system 100 is connected to the upper electrode 30.
  • a pulsed DC voltage from the power supply system 100 is applied to the upper electrode 30, so that the gas in the chamber 10 is excited and plasma is generated from the gas.
  • the plasma processing device 1A may further include a main control unit MC.
  • the main control unit MC is a computer including a processor, a storage device, an input device, a display device, and the like, and controls each unit of the plasma processing device 1A.
  • the main control unit MC executes a control program stored in the storage device and controls each unit of the plasma processing device 1A based on the recipe data stored in the storage device. Under the control of the main control unit MC, the process specified by the recipe data is executed in the plasma processing apparatus 1A.
  • FIG. 10 is a diagram showing a plasma processing apparatus according to another exemplary embodiment.
  • the differences between the plasma processing apparatus 1B shown in FIG. 10 and the plasma processing apparatus 1A will be described.
  • the plasma processing device 1B further includes a high frequency power supply 60 and a matching device 60 m.
  • the high frequency power supply 60 is a power supply configured to generate high frequency power.
  • the high frequency power supply 60 is connected to the upper electrode 30 via a matching device 60m.
  • the high frequency power supply 60 may be connected to the lower electrode 18 via the matching device 60m instead of the upper electrode 30.
  • the matching device 60m has a matching circuit for matching the impedance of the load of the high frequency power supply 60 with the output impedance of the high frequency power supply 60.
  • a high frequency electric field is formed in the chamber 10 by the high frequency power from the high frequency power supply 60.
  • the high frequency electric field excites the gas in the chamber 10. As a result, plasma is generated in chamber 10.
  • the power supply system 100 is connected to the lower electrode 18.
  • the pulsed DC voltage from the power supply system 100 is used to draw ions from the plasma in the chamber 10 to the substrate W on the substrate support 16. That is, in the plasma processing apparatus 1B, the pulsed DC voltage from the power supply system 100 is used as the bias voltage.
  • FIG. 11 is a diagram showing a plasma processing apparatus according to still another exemplary embodiment.
  • the differences between the plasma processing apparatus 1C shown in FIG. 11 and the plasma processing apparatus 1B will be described.
  • the power supply system 100 is connected to the upper electrode 30 via the filter 200.
  • the filter 200 is a low-pass filter that cuts off or reduces high frequency power towards the power supply system 100.
  • the overshoot of the pulsed DC voltage supplied to the electrode is suppressed. Therefore, in plasma treatment such as film formation and etching on the substrate, the ion impact on the substrate due to an unintended increase in ion energy is suppressed. Further, it is possible to suppress the generation of particles due to the ion impact on the side wall of the chamber body 12 and / or the lower surface of the top plate 34 due to an unintended increase in ion energy. Further, it is prevented that the circuit elements connected to the electrodes (for example, the first switch 115 and the second switch 125 in the power supply system 100) are supplied with power exceeding the withstand voltage.
  • the pulsed DC voltage overshoot is caused by the parasitic LC component in the chamber and / or cable. Therefore, the amount of overshoot depends on the structure of the chamber, the size of the chamber, the type of cable, the length of the cable, and the like. Therefore, the amount of overshoot generated in each of the plurality of plasma processing devices is different even if the setting of the pulsed DC voltage is the same. As a result, even when the same control is performed by a plurality of plasma processing devices, the plasma processing result differs depending on the amount of overshoot.
  • overshoot is suppressed, so that it is possible to suppress a difference in plasma processing results when the same control is performed by a plurality of plasma processing apparatus. Will be done.
  • FIG. 12 is a diagram showing an example of a voltage waveform in the output of the power supply system of the plasma processing apparatus according to the comparative example.
  • the power supply system of the plasma processing apparatus according to the comparative example is different from the power supply system 100A in that it does not have the first parallel circuit and the second parallel circuit.
  • the load impedance seen from the power supply system is determined by the load impedance due to factors other than plasma and the load impedance due to plasma.
  • the load impedance due to factors other than plasma depends on the structure of the cable, chamber, and the like.
  • the load impedance caused by plasma is the input power, the type of gas supplied to the chamber, the pressure in the chamber, the gas flow rate, the gap (distance between the substrate support and the upper electrode), and the difference in film formation status (difference in film formation status). It depends on various factors such as insulating film, metal film, etc.). That is, the load impedance caused by the plasma changes according to the fluctuation of the above-mentioned various factors. Therefore, the load impedance changes easily when the process conditions at the time of plasma generation change. Since the impedance of the plasma is different between the rising period and the falling period of the pulsed voltage, the load impedance is also different.
  • the plasma processing apparatus can adopt circuit element parameters adapted to the change in load impedance due to plasma, so that overshoot can be suppressed.
  • the first optimization method and the second optimization method of the circuit element parameters of the power supply system 100 in the plasma processing apparatus will be described.
  • the first optimization method and the second optimization method can be applied to any of the plasma processing devices according to the various exemplary embodiments described above.
  • plasma is generated in the chamber of the plasma processing apparatus by executing the process specified in the process recipe.
  • a pulsed DC voltage is applied from the power supply system 100 to the electrodes (upper electrode 30 or lower electrode 18). Then, when a pulsed DC voltage is applied to the electrode (upper electrode 30 or lower electrode 18) from the power supply system 100, the voltage waveform at the electrode is acquired.
  • the voltage waveform can be obtained using a voltage sensor.
  • the amount ⁇ V1 of the overshoot (or ringing) of the voltage waveform during the period when the output 140 is connected to the positive electrode of the DC power supply device 102 is reduced to the allowable amount or less.
  • the resistance value of the damping resistance 110r is determined.
  • the resistance value of the second damping resistor 120r is determined so as to reduce the amount ⁇ V2 of the overshoot (or ringing) of the voltage waveform during the period when the output 140 is connected to the negative electrode of the DC power supply device 102 to an allowable amount or less. Will be done.
  • the resistance value of the third damping resistor 130r is further determined.
  • the resistance value of the third damping resistor 130r is determined so as to reduce the amount of overshoot (or ringing) ⁇ V3 of the voltage waveform during the period when the output 140 is connected to the ground to be less than the allowable amount.
  • the minimum inductance of the first inductor 110i and the minimum inductance of the second inductor 120i are determined so that ⁇ V1 and ⁇ V2 do not become larger than the respective allowable amounts.
  • the minimum inductance of the third inductor 130i is determined so that ⁇ V3 does not become larger than the allowable amount.
  • the second optimization method will be described below.
  • plasma is generated in the chamber of the plasma processing apparatus, and the voltage waveform at the electrodes is acquired.
  • a pulsed DC voltage is applied from the power supply system 100 to the electrodes (upper electrode 30 or lower electrode 18).
  • FIG. 13 is a diagram showing an example of a circuit model.
  • the circuit model shown in FIG. 13 includes a resistor 901, an inductor 902, and a capacitor 903 connected in series between the positive electrode and the negative electrode of the DC power supply 102.
  • the resistance value RS of the resistor 901, the inductance L of the inductor 902, and the capacitor 903 that match (fit) the voltage waveform during the period when the output 140 is connected to the positive electrode of the DC power supply device 102.
  • Capacitance C is required.
  • a resistance value R satisfying the following equation (1) is obtained.
  • CR 2 / (4L) 1 ... (1)
  • R-R S -R i is determined as the resistance value of the first damping resistor 110r.
  • R i is the internal resistance value of the DC power supply device 102.
  • the electric capacity C is required.
  • a resistance value R satisfying the equation (1) is obtained.
  • R-R S -R i is determined as the resistance value of the second damping resistor 120r.
  • the minimum inductance of the first inductor 110i is determined so that the amount of ringing during the period when the output 140 is connected to the positive electrode of the DC power supply device 102 does not become larger than the allowable amount. Further, the minimum inductance of the second inductor 120i is determined so that the amount of ringing during the period in which the output 140 is connected to the negative electrode of the DC power supply device 102 does not become larger than the allowable amount.
  • the minimum inductance of the third inductor 130i is set so that the amount of ringing during the period when the output 140 is connected to the ground does not become larger than the allowable amount. It is determined.
  • the impedance monitoring device is connected between the output 140 of the power supply system 100 and the electrode (upper electrode 30 or lower electrode 18) to which the output 140 is connected. Then, in the third optimization method, the circuit element parameter of the power supply system 100 is determined to suppress the overshoot according to the impedance value measured by the impedance monitoring device.
  • the plasma processing apparatus including any of the various exemplary embodiments described above is not limited to the capacitive coupling type plasma processing apparatus.
  • the plasma processing apparatus including any of the various exemplary embodiments may be another type of plasma processing apparatus.
  • Other types of plasma processing devices are, for example, inductively coupled plasma processing devices, electron sacroton resonance (ECR) plasma processing devices, or plasma processing devices that generate plasma by surface waves such as microwaves.
  • ECR electron sacroton resonance

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Abstract

The disclosed power supply system is provided with a direct-current power supply device, a first parallel circuit, a first switch, a second parallel circuit, a second switch, and an output. The first parallel circuit includes a first node, a second node, and a first damping resistor and a first inductor connected in parallel between the first node and the second node. The first switch is connected between the positive electrode of the direct-current power supply device and the first node. The second parallel circuit includes a third node, a fourth node, and a second damping resistor and a second inductor connected in parallel between the third node and the fourth node. The output is connected to the second node and the fourth node.

Description

電源システム及びプラズマ処理装置Power supply system and plasma processing equipment
　本開示の例示的実施形態は、電源システム及びプラズマ処理装置に関するものである。 An exemplary embodiment of the present disclosure relates to a power supply system and a plasma processing apparatus.
　成膜、エッチング等の基板処理では、プラズマ処理装置が用いられている。プラズマ処理装置は、チャンバ内でガスからプラズマを生成する。このようなプラズマ処理の一種は、特許文献１に記載されている。特許文献１に記載されたプラズマ処理装置では、プラズマの生成のために、パルス状の直流電圧が用いられている。 A plasma processing device is used for substrate processing such as film formation and etching. The plasma processing device produces plasma from the gas in the chamber. One type of such plasma treatment is described in Patent Document 1. In the plasma processing apparatus described in Patent Document 1, a pulsed DC voltage is used for generating plasma.
特開２０１９－２１２６４８号公報Japanese Unexamined Patent Publication No. 2019-212648
　本開示は、パルス状の直流電圧のオーバーシュート及び消費電力を低減する技術を提供する。 The present disclosure provides a technique for overshooting a pulsed DC voltage and reducing power consumption.
　一つの例示的実施形態において、電源システムが提供される。電源システムは、直流電源装置、第１の並列回路、第１のスイッチ、第２の並列回路、第２のスイッチ、及び出力を備える。第１の並列回路は、第１のノード、第２のノード、第１のダンピング抵抗、及び第１のインダクタを含む。第１のダンピング抵抗及び第１のインダクタは、第１のノードと第２のノードとの間で並列に接続されている。第１のスイッチは、直流電源装置の正極と第１のノードとの間で接続されている。第２の並列回路は、第３のノード、第４のノード、第２のダンピング抵抗、及び第２のインダクタを含む。第２のダンピング抵抗及び第２のインダクタは、第３のノードと第４のノードとの間で並列に接続されている。第２のスイッチは、直流電源装置の負極と第３のノードとの間で接続されている。出力は、第２のノード及び第４のノードに接続されている。 In one exemplary embodiment, a power supply system is provided. The power supply system includes a DC power supply, a first parallel circuit, a first switch, a second parallel circuit, a second switch, and an output. The first parallel circuit includes a first node, a second node, a first damping resistor, and a first inductor. The first damping resistor and the first inductor are connected in parallel between the first node and the second node. The first switch is connected between the positive electrode of the DC power supply and the first node. The second parallel circuit includes a third node, a fourth node, a second damping resistor, and a second inductor. The second damping resistor and the second inductor are connected in parallel between the third node and the fourth node. The second switch is connected between the negative electrode of the DC power supply and the third node. The output is connected to a second node and a fourth node.
　一つの例示的実施形態によれば、パルス状の直流電圧のパルスのオーバーシュート及び消費電力を低減することが可能となる。 According to one exemplary embodiment, it is possible to reduce overshoot and power consumption of a pulsed DC voltage pulse.
一つの例示的実施形態に係る電源システムを示す図である。It is a figure which shows the power-source system which concerns on one exemplary embodiment. 別の例示的実施形態に係る電源システムを示す図である。It is a figure which shows the power-source system which concerns on another exemplary embodiment. 図３の（ａ）、図３の（ｂ）はそれぞれ、第１比較例に係る電源システムの出力における電圧波形の例、電流波形の例を示す図である。3A and 3B are diagrams showing an example of a voltage waveform and an example of a current waveform at the output of the power supply system according to the first comparative example, respectively. 図４の（ａ）、図４の（ｂ）はそれぞれ、第２比較例に係る電源システムの出力における電圧波形の例、第２のダンピング抵抗における電流波形の例を示す図である。4A and 4B are diagrams showing an example of a voltage waveform at the output of the power supply system according to the second comparative example and an example of a current waveform at the second damping resistor, respectively. 図５の（ａ）、図５の（ｂ）、図５の（ｃ）はそれぞれ、図２に示す電源システム１００Ｂの出力における電圧波形の例、第２のダンピング抵抗における電流波形の例、第２のインダクタにおける電流波形の例を示す図である。5 (a), 5 (b), and 5 (c) are examples of voltage waveforms at the output of the power supply system 100B shown in FIG. 2, examples of current waveforms at the second damping resistor, and first. It is a figure which shows the example of the current waveform in 2 inductors. 更に別の例示的実施形態に係る電源システムを示す図である。It is a figure which shows the power-source system which concerns on still another exemplary Embodiment. 更に別の例示的実施形態に係る電源システムを示す図である。It is a figure which shows the power-source system which concerns on still another exemplary Embodiment. 図７に示す電源システムが出力可能なパルス状の直流電圧の一例を示す図である。FIG. 7 is a diagram showing an example of a pulsed DC voltage that can be output by the power supply system shown in FIG. 7. 一つの例示的実施形態に係るプラズマ処理装置を示す図である。It is a figure which shows the plasma processing apparatus which concerns on one exemplary Embodiment. 別の例示的実施形態に係るプラズマ処理装置を示す図である。It is a figure which shows the plasma processing apparatus which concerns on another exemplary embodiment. 更に別の例示的実施形態に係るプラズマ処理装置を示す図である。It is a figure which shows the plasma processing apparatus which concerns on still another exemplary Embodiment. 比較例に係るプラズマ処理装置の電源システムの出力における電圧波形の例を示す図である。It is a figure which shows the example of the voltage waveform in the output of the power-source system of the plasma processing apparatus which concerns on a comparative example. 回路モデルの一例を示す図である。It is a figure which shows an example of a circuit model.
　以下、種々の例示的実施形態について説明する。 Hereinafter, various exemplary embodiments will be described.
　一つの例示的実施形態において、電源システムが提供される。電源システムは、直流電源装置、第１の並列回路、第１のスイッチ、第２の並列回路、第２のスイッチ、及び出力を備える。第１の並列回路は、第１のノード、第２のノード、第１のダンピング抵抗、及び第１のインダクタを含む。第１のダンピング抵抗及び第１のインダクタは、第１のノードと第２のノードとの間で並列に接続されている。第１のスイッチは、直流電源装置の正極と第１のノードとの間で接続されている。第２の並列回路は、第３のノード、第４のノード、第２のダンピング抵抗、及び第２のインダクタを含む。第２のダンピング抵抗及び第２のインダクタは、第３のノードと第４のノードとの間で並列に接続されている。第２のスイッチは、直流電源装置の負極と第３のノードとの間で接続されている。出力は、第２のノード及び第４のノードに接続されている。 In one exemplary embodiment, a power supply system is provided. The power supply system includes a DC power supply, a first parallel circuit, a first switch, a second parallel circuit, a second switch, and an output. The first parallel circuit includes a first node, a second node, a first damping resistor, and a first inductor. The first damping resistor and the first inductor are connected in parallel between the first node and the second node. The first switch is connected between the positive electrode of the DC power supply and the first node. The second parallel circuit includes a third node, a fourth node, a second damping resistor, and a second inductor. The second damping resistor and the second inductor are connected in parallel between the third node and the fourth node. The second switch is connected between the negative electrode of the DC power supply and the third node. The output is connected to a second node and a fourth node.
　上記実施形態の電源システムでは、第１のスイッチと第２のスイッチが交互に導通状態になることにより、出力からパルス状の直流電圧が出力される。この電源システムでは、パルス状の直流電圧の立ち上がり及び立ち下がりにおけるオーバーシュートが、第１のダンピング抵抗及び第２のダンピング抵抗により低減される。また、パルス状の直流電圧のレベルが安定している期間においては、電流は、第１のインダクタ又は第２のインダクタを流れるので、第１のダンピング抵抗及び第２のダンピング抵抗における電力消費が抑制される。したがって、この電源システムによれば、消費電力が低減される。 In the power supply system of the above embodiment, the first switch and the second switch are alternately in a conductive state, so that a pulsed DC voltage is output from the output. In this power supply system, the overshoot at the rising and falling edges of the pulsed DC voltage is reduced by the first damping resistor and the second damping resistor. Further, during the period when the level of the pulsed DC voltage is stable, the current flows through the first inductor or the second inductor, so that the power consumption in the first damping resistor and the second damping resistor is suppressed. Will be done. Therefore, according to this power supply system, power consumption is reduced.
　一つの例示的実施形態において、直流電源装置の正極はグランドに接続されていてもよい。この実施形態では、パルス状の直流電圧として、ユニポーラパルスが生成される。 In one exemplary embodiment, the positive electrode of the DC power supply may be connected to ground. In this embodiment, a unipolar pulse is generated as a pulsed DC voltage.
　一つの例示的実施形態において、直流電源装置は、第１の直流電源及び第２の直流電源を含んでいてもよい。第１の直流電源の負極は、直流電源装置の負極を構成する。第１の直流電源の正極及び第２の直流電源の負極は、グランドに接続される。第２の直流電源の正極は、直流電源装置の正極を構成する。この実施形態では、パルス状の直流電圧として、バイポーラパルスが生成される。 In one exemplary embodiment, the DC power supply may include a first DC power supply and a second DC power supply. The negative electrode of the first DC power supply constitutes the negative electrode of the DC power supply device. The positive electrode of the first DC power supply and the negative electrode of the second DC power supply are connected to the ground. The positive electrode of the second DC power supply constitutes the positive electrode of the DC power supply device. In this embodiment, a bipolar pulse is generated as a pulsed DC voltage.
　一つの例示的実施形態において、電源システムは、第３の並列回路及び第３のスイッチを更に備えていてもよい。第３の並列回路は、第５のノード、第６のノード、第３のダンピング抵抗、及び第３のインダクタを含む。第６のノードは、電源システムの出力に接続されている。第３のダンピング抵抗及び第３のインダクタは、第５のノードと第６のノードとの間で並列に接続されている。第３のスイッチは、グランドと第５のノードとの間で接続されている。この実施形態では、第１のスイッチ及び第２のスイッチの双方が非導通状態であり、第３のスイッチが導通状態であるときに、出力はグランドに接続される。出力をグランドに接続する期間を設けることにより、周期内で正の電圧が出力される期間の時間長と負の電圧が出力される期間の時間長を、互いから独立的に設定することが可能となる。 In one exemplary embodiment, the power supply system may further include a third parallel circuit and a third switch. The third parallel circuit includes a fifth node, a sixth node, a third damping resistor, and a third inductor. The sixth node is connected to the output of the power supply system. The third damping resistor and the third inductor are connected in parallel between the fifth node and the sixth node. The third switch is connected between the ground and the fifth node. In this embodiment, the output is connected to ground when both the first switch and the second switch are in the non-conducting state and the third switch is in the conducting state. By providing a period for connecting the output to ground, it is possible to set the time length of the period in which the positive voltage is output and the time length of the period in which the negative voltage is output independently of each other. It becomes.
　一つの例示的実施形態において、第１の並列回路は、第１のダイオードを更に含んでいてもよい。第１のダイオードのアノードは、第１のダンピング抵抗に接続され、第１のダイオードのカソードは、第２のノードに接続される。第２の並列回路は、第２のダイオードを更に含んでいてもよい。第２のダイオードのアノードは、第４のノードに接続され、第２のダイオードのカソードは、第２のダンピング抵抗に接続される。この実施形態によれば、第１のダイオードが、第１のインダクタと第１のダンピング抵抗との間で、第１のスイッチが開放になった時の電流ループを切断する。したがって、第１のインダクタからのエネルギーが第１のダンピング抵抗において消費されることが抑制される。また、第２のダイオードが、第２のインダクタと第２のダンピング抵抗との間で、第２のスイッチが開放になった時の電流ループを切断する。したがって、第２のインダクタからのエネルギーが第２のダンピング抵抗において消費されることが抑制される。 In one exemplary embodiment, the first parallel circuit may further include a first diode. The anode of the first diode is connected to the first damping resistor and the cathode of the first diode is connected to the second node. The second parallel circuit may further include a second diode. The anode of the second diode is connected to the fourth node and the cathode of the second diode is connected to the second damping resistor. According to this embodiment, the first diode breaks the current loop between the first inductor and the first damping resistor when the first switch is open. Therefore, the energy from the first inductor is suppressed from being consumed in the first damping resistor. Also, the second diode breaks the current loop between the second inductor and the second damping resistor when the second switch is open. Therefore, the energy from the second inductor is suppressed from being consumed in the second damping resistor.
　一つの例示的実施形態において、電源システムは、直流電源装置の負極に接続されたアノードと第１のノードに接続されたカソードを有するダイオードを更に備えていてもよい。このダイオードにより、第１のスイッチが開放になった時の第１のインダクタからのエネルギーは、直流電源装置に回生される。また、電源システムは、直流電源装置の正極に接続されたカソード及び第２のノードに接続されたアノードを有するダイオードを更に備えていてもよい。このダイオードにより、第２のスイッチが開放になった時の第２のインダクタからのエネルギーは、直流電源装置に回生される。 In one exemplary embodiment, the power supply system may further include a diode having an anode connected to the negative electrode of the DC power supply and a cathode connected to the first node. With this diode, the energy from the first inductor when the first switch is opened is regenerated to the DC power supply. The power supply system may further include a diode having a cathode connected to the positive electrode of the DC power supply and an anode connected to the second node. With this diode, the energy from the second inductor when the second switch is opened is regenerated to the DC power supply.
　一つの例示的実施形態において、電源システムは、制御部を更に備えていてもよい。制御部は、第１のスイッチ及び第２のスイッチが交互に導通状態になるよう第１のスイッチ及び第２のスイッチを制御するように構成されてもよい。 In one exemplary embodiment, the power supply system may further include a control unit. The control unit may be configured to control the first switch and the second switch so that the first switch and the second switch are alternately in a conductive state.
　一つの例示的実施形態において、電源システムは、制御部を更に備えていてもよい。制御部は、第１のスイッチを導通状態に設定し、第２のスイッチ及び第３のスイッチを非導通状態に設定する制御を実行可能であるように構成される。また、制御部は、第３のスイッチを導通状態に設定し、第１のスイッチ及び第２のスイッチを非導通状態に設定する制御を実行可能であるように構成される。さらに、制御部は、第２のスイッチを導通状態に設定し、第１のスイッチ及び第３のスイッチを非導通状態に設定する制御を実行可能であるように構成される。 In one exemplary embodiment, the power supply system may further include a control unit. The control unit is configured to be capable of executing control that sets the first switch to the conductive state and sets the second switch and the third switch to the non-conducting state. Further, the control unit is configured to be capable of executing control for setting the third switch to the conductive state and setting the first switch and the second switch to the non-conducting state. Further, the control unit is configured to be capable of executing control for setting the second switch to the conductive state and setting the first switch and the third switch to the non-conducting state.
　別の例示的実施形態において、プラズマ処理装置が提供される。プラズマ処理装置は、チャンバ、基板支持部、電極、及び電源システムを備える。基板支持部は、チャンバ内で基板を支持するように構成されている。電源システムは、上述した種々の例示的実施形態のうち何れかの電源システムである。電源システムは、チャンバ内でプラズマを生成するため又はチャンバ内のプラズマから基板支持部によって支持された基板にイオンを引き込むために、電極に電気的に接続されている。 In another exemplary embodiment, a plasma processing apparatus is provided. The plasma processing device includes a chamber, a substrate support, electrodes, and a power supply system. The board support is configured to support the board in the chamber. The power supply system is any of the various exemplary embodiments described above. The power supply system is electrically connected to the electrodes to generate plasma in the chamber or to draw ions from the plasma in the chamber to the substrate supported by the substrate support.
　以下、図面を参照して種々の例示的実施形態について詳細に説明する。なお、各図面において同一又は相当の部分に対しては同一の符号を附すこととする。 Hereinafter, various exemplary embodiments will be described in detail with reference to the drawings. In addition, the same reference numerals are given to the same or corresponding parts in each drawing.
　まず、種々の例示的実施形態に係る電源システムについて説明する。以下に説明する種々の例示的実施形態に係る電源システムは、プラズマ処理装置において用いられ得る。 First, the power supply system according to various exemplary embodiments will be described. The power supply system according to various exemplary embodiments described below can be used in a plasma processing apparatus.
　図１は、一つの例示的実施形態に係る電源システムを示す図である。図１に示す電源システム１００Ａは、直流電源装置１０２、第１の並列回路１１０、第１のスイッチ１１５、第２の並列回路１２０、第２のスイッチ１２５、及び出力１４０を備えている。電源システム１００Ａは、出力１４０からパルス状の直流電圧を出力するように構成されている。電源システム１００Ａは、パルス状の直流電圧としてユニポーラパルスを生成するように構成されている。 FIG. 1 is a diagram showing a power supply system according to one exemplary embodiment. The power supply system 100A shown in FIG. 1 includes a DC power supply device 102, a first parallel circuit 110, a first switch 115, a second parallel circuit 120, a second switch 125, and an output 140. The power supply system 100A is configured to output a pulsed DC voltage from the output 140. The power supply system 100A is configured to generate a unipolar pulse as a pulsed DC voltage.
　直流電源装置１０２の正極は、グランドに接続されている。直流電源装置１０２は、直流電源１０２ａを含み得る。直流電源１０２ａは、可変直流電源であってもよい。直流電源１０２ａの正極が、直流電源装置１０２の正極を構成していてもよい。また、直流電源装置１０２の負極が、直流電源装置１０２の負極を構成していてもよい。 The positive electrode of the DC power supply device 102 is connected to the ground. The DC power supply 102 may include a DC power supply 102a. The DC power supply 102a may be a variable DC power supply. The positive electrode of the DC power supply 102a may constitute the positive electrode of the DC power supply device 102. Further, the negative electrode of the DC power supply device 102 may constitute the negative electrode of the DC power supply device 102.
　第１の並列回路１１０は、ノード１１１（第１のノード）、ノード１１２（第２のノード）、第１のダンピング抵抗１１０ｒ、及び第１のインダクタ１１０ｉを含んでいる。第１のダンピング抵抗１１０ｒと第１のインダクタ１１０ｉは、ノード１１１とノード１１２との間で並列に接続されている。ノード１１２は、出力１４０に接続されている。 The first parallel circuit 110 includes a node 111 (first node), a node 112 (second node), a first damping resistor 110r, and a first inductor 110i. The first damping resistor 110r and the first inductor 110i are connected in parallel between the node 111 and the node 112. Node 112 is connected to output 140.
　第１のスイッチ１１５は、直流電源装置１０２の正極とノード１１１との間で接続されている。第１のスイッチ１１５が導通状態であるときには、直流電源装置１０２の正極は、ノード１１１に接続される。第１のスイッチ１１５が非導通状態であるときには、直流電源装置１０２の正極とノード１１１との間の接続が、切断される。第１のスイッチ１１５は、例えばスイッチングトランジスタである。 The first switch 115 is connected between the positive electrode of the DC power supply device 102 and the node 111. When the first switch 115 is in the conductive state, the positive electrode of the DC power supply 102 is connected to the node 111. When the first switch 115 is in the non-conducting state, the connection between the positive electrode of the DC power supply 102 and the node 111 is disconnected. The first switch 115 is, for example, a switching transistor.
　第２の並列回路１２０は、ノード１２１（第３のノード）、ノード１２２（第４のノード）、第２のダンピング抵抗１２０ｒ、及び第２のインダクタ１２０ｉを含んでいる。第２のダンピング抵抗１２０ｒと第２のインダクタ１２０ｉは、ノード１２１とノード１２２との間で並列に接続されている。ノード１２２は、出力１４０に接続されている。 The second parallel circuit 120 includes a node 121 (third node), a node 122 (fourth node), a second damping resistor 120r, and a second inductor 120i. The second damping resistor 120r and the second inductor 120i are connected in parallel between the node 121 and the node 122. The node 122 is connected to the output 140.
　第２のスイッチ１２５は、直流電源装置１０２の負極とノード１２１との間で接続されている。第２のスイッチ１２５が導通状態であるときには、直流電源装置１０２の負極は、ノード１２１に接続される。第２のスイッチ１２５が非導通状態であるときには、直流電源装置１０２の負極とノード１２１との間の接続が、切断される。第２のスイッチ１２５は、例えばスイッチングトランジスタである。 The second switch 125 is connected between the negative electrode of the DC power supply device 102 and the node 121. When the second switch 125 is in the conductive state, the negative electrode of the DC power supply 102 is connected to the node 121. When the second switch 125 is in the non-conducting state, the connection between the negative electrode of the DC power supply 102 and the node 121 is cut off. The second switch 125 is, for example, a switching transistor.
　図１に示す電源システム１００Ａは、制御部１５０を更に備えていてもよい。制御部１５０は、第１のスイッチ１１５及び第２のスイッチ１２５のそれぞれに制御信号を与えることにより、第１のスイッチ１１５及び第２のスイッチ１２５を制御するように構成されている。第１のスイッチ１１５及び第２のスイッチ１２５がスイッチングトランジスタである場合には、制御部１５０からの制御信号は、第１のスイッチ１１５の制御端子及び第２のスイッチ１２５の制御端子のそれぞれに与えられる。制御部１５０は、第１のスイッチ１１５及び第２のスイッチ１２５が交互に導通状態になるように、第１のスイッチ１１５及び第２のスイッチ１２５を制御してもよい。制御部１５０は、マイクロプロセッサを含み得る。 The power supply system 100A shown in FIG. 1 may further include a control unit 150. The control unit 150 is configured to control the first switch 115 and the second switch 125 by giving control signals to the first switch 115 and the second switch 125, respectively. When the first switch 115 and the second switch 125 are switching transistors, the control signal from the control unit 150 is given to the control terminal of the first switch 115 and the control terminal of the second switch 125, respectively. Be done. The control unit 150 may control the first switch 115 and the second switch 125 so that the first switch 115 and the second switch 125 are alternately in a conductive state. The control unit 150 may include a microprocessor.
　電源システム１００Ａでは、第１のスイッチ１１５が導通状態であり、第２のスイッチ１２５が非導通状態であるときに、出力１４０はグランドに接続される。第１のスイッチ１１５が非導通状態であり、第２のスイッチ１２５が導通状態であるときには、出力１４０は直流電源装置１０２の負極に接続され、負の電圧が出力１４０から出力される。したがって、電源システム１００Ａでは、第１のスイッチ１１５及び第２のスイッチ１２５が交互に導通状態になることにより、パルス状の直流電圧としてユニポーラパルスが出力される。 In the power supply system 100A, the output 140 is connected to the ground when the first switch 115 is in the conductive state and the second switch 125 is in the non-conducting state. When the first switch 115 is in the non-conducting state and the second switch 125 is in the conducting state, the output 140 is connected to the negative electrode of the DC power supply device 102, and a negative voltage is output from the output 140. Therefore, in the power supply system 100A, the unipolar pulse is output as a pulsed DC voltage when the first switch 115 and the second switch 125 are alternately in a conductive state.
　電源システム１００Ａでは、パルス状の直流電圧の立ち上がり及び立ち下がりにおけるオーバーシュートが、第１のダンピング抵抗１１０ｒ及び第２のダンピング抵抗１２０ｒにより低減される。また、パルス状の直流電圧のレベルが安定している期間においては、電流は、第１のインダクタ１１０ｉ又は第２のインダクタ１２０ｉを流れるので、第１のダンピング抵抗１１０ｒ及び第２のダンピング抵抗１２０ｒにおける電力消費が抑制される。したがって、電源システム１００Ａによれば、消費電力が低減される。 In the power supply system 100A, the overshoot at the rising and falling edges of the pulsed DC voltage is reduced by the first damping resistor 110r and the second damping resistor 120r. Further, during the period when the level of the pulsed DC voltage is stable, the current flows through the first inductor 110i or the second inductor 120i, so that the first damping resistor 110r and the second damping resistor 120r have a current. Power consumption is suppressed. Therefore, according to the power supply system 100A, the power consumption is reduced.
　以下、図２を参照する。図２は、別の例示的実施形態に係る電源システムを示す図である。図２に示す電源システム１００Ｂは、パルス状の直流電圧として、バイポーラパルスを生成する点で、電源システム１００Ａと異なっている。以下、電源システム１００Ｂの電源システム１００Ａに対する相違点について説明する。 Refer to FIG. 2 below. FIG. 2 is a diagram showing a power supply system according to another exemplary embodiment. The power supply system 100B shown in FIG. 2 is different from the power supply system 100A in that it generates a bipolar pulse as a pulsed DC voltage. Hereinafter, the differences between the power supply system 100B and the power supply system 100A will be described.
　電源システム１００Ｂでは、直流電源装置１０２は、直流電源１０２ａ（第１の直流電源）に加えて、直流電源１０２ｂ（第２の直流電源）を含んでいる。直流電源１０２ａ及び直流電源１０２ｂの各々は、可変直流電源であってもよい。直流電源１０２ａと直流電源１０２ｂは、直列接続されている。具体的に、直流電源１０２ａの正極と直流電源１０２ｂの負極が互いに接続されている。直流電源１０２ａの正極と直流電源１０２ｂの負極は、グランドに接続されている。直流電源１０２ａの負極は、直流電源装置１０２の負極を構成している。直流電源１０２ｂの正極は、直流電源装置１０２の正極を構成している。 In the power supply system 100B, the DC power supply device 102 includes a DC power supply 102b (second DC power supply) in addition to the DC power supply 102a (first DC power supply). Each of the DC power supply 102a and the DC power supply 102b may be a variable DC power supply. The DC power supply 102a and the DC power supply 102b are connected in series. Specifically, the positive electrode of the DC power supply 102a and the negative electrode of the DC power supply 102b are connected to each other. The positive electrode of the DC power supply 102a and the negative electrode of the DC power supply 102b are connected to the ground. The negative electrode of the DC power supply 102a constitutes the negative electrode of the DC power supply device 102. The positive electrode of the DC power supply 102b constitutes the positive electrode of the DC power supply device 102.
　電源システム１００Ｂでは、第１のスイッチ１１５が導通状態であり、第２のスイッチ１２５が非導通状態であるときに、出力１４０は直流電源装置１０２の正極に接続され、正の電圧が出力１４０から出力される。また、第１のスイッチ１１５が非導通状態であり、第２のスイッチ１２５が導通状態であるときに、出力１４０は直流電源装置１０２の負極に接続され、負の電圧が出力１４０から出力される。したがって、電源システム１００Ｂでは、第１のスイッチ１１５及び第２のスイッチ１２５が交互に導通状態に切り替わることにより、パルス状の直流電圧として、バイポーラパルスが出力される。 In the power supply system 100B, when the first switch 115 is in the conductive state and the second switch 125 is in the non-conducting state, the output 140 is connected to the positive electrode of the DC power supply device 102, and a positive voltage is supplied from the output 140. It is output. Further, when the first switch 115 is in the non-conducting state and the second switch 125 is in the conducting state, the output 140 is connected to the negative electrode of the DC power supply device 102, and a negative voltage is output from the output 140. .. Therefore, in the power supply system 100B, the first switch 115 and the second switch 125 are alternately switched to the conduction state, so that a bipolar pulse is output as a pulsed DC voltage.
　電源システム１００Ｂにおいても、電源システム１００Ａと同様に、パルス状の直流電圧の立ち上がり及び立ち下がりにおけるオーバーシュートが、第１のダンピング抵抗１１０ｒ及び第２のダンピング抵抗１２０ｒにより低減される。また、電源システム１００Ｂにおいても、電源システム１００Ａと同様に、第１のダンピング抵抗１１０ｒ及び第２のダンピング抵抗１２０ｒにおける電力消費が抑制される。したがって、電源システム１００Ｂよれば、電源システム１００Ａと同様に、消費電力が低減される。 In the power supply system 100B as well, the overshoot at the rising and falling edges of the pulsed DC voltage is reduced by the first damping resistor 110r and the second damping resistor 120r, as in the power supply system 100A. Further, also in the power supply system 100B, the power consumption in the first damping resistor 110r and the second damping resistor 120r is suppressed as in the power supply system 100A. Therefore, according to the power supply system 100B, the power consumption is reduced as in the power supply system 100A.
　以下、電源システム１００Ｂを、第１比較例の電源システム及び第２比較例の電源システムと比較しつつ考察する。なお、第１比較例の電源システムは、第１の並列回路１１０及び第２の並列回路１２０を備えていない点で、電源システム１００Ｂと相違している。第１比較例の電源システムにおいて、第１のスイッチ１１５は、直流電源装置１０２の正極と出力１４０との間で接続される。第１比較例の電源システムにおいて、第２のスイッチ１２５は、直流電源装置１０２の負極と出力１４０との間で接続されている。また、第２比較例の電源システムは、第１のインダクタ１１０ｉ及び第２のインダクタ１２０ｉを備えていない点で、電源システム１００Ｂと相違している。第２比較例の電源システムにおいて、第１のダンピング抵抗１１０ｒは、第１のスイッチ１１５と出力１４０との間で接続される。第２比較例の電源システムにおいて、第２のダンピング抵抗１２０ｒは、第２のスイッチ１２５と出力１４０との間で接続される。 Hereinafter, the power supply system 100B will be considered while comparing it with the power supply system of the first comparative example and the power supply system of the second comparative example. The power supply system of the first comparative example is different from the power supply system 100B in that it does not include the first parallel circuit 110 and the second parallel circuit 120. In the power supply system of the first comparative example, the first switch 115 is connected between the positive electrode of the DC power supply device 102 and the output 140. In the power supply system of the first comparative example, the second switch 125 is connected between the negative electrode of the DC power supply device 102 and the output 140. Further, the power supply system of the second comparative example is different from the power supply system 100B in that it does not include the first inductor 110i and the second inductor 120i. In the power supply system of the second comparative example, the first damping resistor 110r is connected between the first switch 115 and the output 140. In the power supply system of the second comparative example, the second damping resistor 120r is connected between the second switch 125 and the output 140.
　図３の（ａ）、図３の（ｂ）はそれぞれ、第１比較例に係る電源システムの出力における電圧波形の例、電流波形の例を示す図である。第１比較例の電源システムは、第１のダンピング抵抗１１０ｒ及び第２のダンピング抵抗１２０ｒを備えていない。したがって、第１比較例の電源システムでは、図３の（ａ）に示すように、出力１４０における電圧Ｖｏｕｔにオーバーシュートが発生する。また、第１比較例の電源システムでは、出力１４０における電圧Ｖｏｕｔが低レベルであり、且つ、安定している期間において、図３の（ｂ）に示すように、直流電源装置１０２の正極から負極に向かって電流（例えば、約１Ａの電流）が流れる。 (A) of FIG. 3 and (b) of FIG. 3 are diagrams showing an example of a voltage waveform and an example of a current waveform at the output of the power supply system according to the first comparative example, respectively. The power supply system of the first comparative example does not include the first damping resistor 110r and the second damping resistor 120r. Therefore, in the power supply system of the first comparative example, as shown in FIG. 3A, an overshoot occurs in the voltage Vout at the output 140. Further, in the power supply system of the first comparative example, as shown in FIG. 3B, the positive electrode to the negative electrode of the DC power supply device 102 during the period when the voltage Vout at the output 140 is low and stable. A current (eg, a current of about 1 A) flows toward.
　図４の（ａ）、図４の（ｂ）はそれぞれ、第２比較例に係る電源システムの出力における電圧波形の例、第２のダンピング抵抗における電流波形の例を示す図である。第２比較例の電源システムは、第１のダンピング抵抗１１０ｒ及び第２のダンピング抵抗１２０ｒを備えている。したがって、第２比較例の電源システムでは、図４の（ａ）に示すように、出力１４０における電圧Ｖｏｕｔのオーバーシュートが抑制される。しかしながら、第２比較例の電源システムでは、出力１４０における電圧Ｖｏｕｔが低レベルであり、且つ、安定している期間において、図４の（ｂ）に示すように、第２のダンピング抵抗１２０ｒに電流（例えば、約１Ａの電流）が流れる。このように、第２比較例の電源システムでは、出力１４０における電圧Ｖｏｕｔが安定している期間において、第１のダンピング抵抗１１０ｒ及び第２のダンピング抵抗１２０ｒに電流が流れる。したがって、第２比較例の電源システムの消費電力は大きい。 (A) of FIG. 4 and (b) of FIG. 4 are diagrams showing an example of a voltage waveform at the output of the power supply system according to the second comparative example and an example of a current waveform at the second damping resistor, respectively. The power supply system of the second comparative example includes a first damping resistor 110r and a second damping resistor 120r. Therefore, in the power supply system of the second comparative example, overshoot of the voltage Vout at the output 140 is suppressed as shown in FIG. 4 (a). However, in the power supply system of the second comparative example, as shown in FIG. 4B, the current is applied to the second damping resistor 120r during the period when the voltage Vout at the output 140 is at a low level and is stable. (For example, a current of about 1 A) flows. As described above, in the power supply system of the second comparative example, a current flows through the first damping resistor 110r and the second damping resistor 120r during the period when the voltage Vout at the output 140 is stable. Therefore, the power consumption of the power supply system of the second comparative example is large.
　図５の（ａ）、図５の（ｂ）、図５の（ｃ）はそれぞれ、図２に示す電源システム１００Ｂの出力における電圧波形の例、第２のダンピング抵抗における電流波形の例、第２のインダクタにおける電流波形の例を示す図である。第１のダンピング抵抗１１０ｒ及び第２のダンピング抵抗１２０ｒを備える電源システム１００Ｂでは、図５の（ａ）に示すように、出力１４０における電圧Ｖｏｕｔのオーバーシュートが抑制される。また、電源システム１００Ｂでは、出力１４０における電圧Ｖｏｕｔが低レベルであり、且つ、安定している期間において、図５の（ｂ）及び図５の（ｃ）に示すように、第２のダンピング抵抗１２０ｒに電流が流れず、第２のインダクタ１２０ｉに電流が流れる。同様に、電源システム１００Ｂでは、出力１４０における電圧Ｖｏｕｔが安定している期間において、電流は、第１のダンピング抵抗１１０ｒに流れず、第１のインダクタ１１０ｉに流れる。第１のインダクタ１１０ｉ及び第２のインダクタ１２０ｉは、それらに電流が流れても、電力を消費しない。したがって、電源システム１００Ｂによれば、消費電力が抑制される。 5 (a), 5 (b), and 5 (c) are examples of voltage waveforms at the output of the power supply system 100B shown in FIG. 2, examples of current waveforms at the second damping resistor, and first. It is a figure which shows the example of the current waveform in 2 inductors. In the power supply system 100B provided with the first damping resistor 110r and the second damping resistor 120r, overshoot of the voltage Vout at the output 140 is suppressed as shown in FIG. 5A. Further, in the power supply system 100B, as shown in FIGS. 5 (b) and 5 (c), the second damping resistor is used during the period when the voltage Vout at the output 140 is at a low level and is stable. No current flows through 120r, and current flows through the second inductor 120i. Similarly, in the power supply system 100B, the current does not flow through the first damping resistor 110r but flows through the first inductor 110i during the period when the voltage Vout at the output 140 is stable. The first inductor 110i and the second inductor 120i do not consume electric power even if a current flows through them. Therefore, according to the power supply system 100B, power consumption is suppressed.
　以下、図６を参照する。図６は、更に別の例示的実施形態に係る電源システムを示す図である。図６に示す電源システム１００Ｃは、電源システム１００Ｂと同様に、パルス状の直流電圧として、バイポーラパルスを生成する。以下、電源システム１００Ｃの電源システム１００Ｂに対する相違点について説明する。 Refer to FIG. 6 below. FIG. 6 is a diagram showing a power supply system according to still another exemplary embodiment. Similar to the power supply system 100B, the power supply system 100C shown in FIG. 6 generates a bipolar pulse as a pulsed DC voltage. Hereinafter, the differences between the power supply system 100C and the power supply system 100B will be described.
　電源システム１００Ｃでは、第１の並列回路１１０は、第１のダイオード１１０ｄを更に含んでいる。第１のダイオード１１０ｄは、第１のダンピング抵抗１１０ｒとノード１１２との間で接続されている。第１のダイオード１１０ｄのアノードは、第１のダンピング抵抗１１０ｒに接続されている。第１のダイオード１１０ｄのカソードは、ノード１１２に接続されている。第１のダイオード１１０ｄは、第１のインダクタ１１０ｉと第１のダンピング抵抗１１０ｒとの間で、第１のスイッチが開放になった時の電流ループを切断する。したがって、第１のインダクタ１１０ｉからのエネルギーが第１のダンピング抵抗１１０ｒにおいて消費されることが抑制される。 In the power supply system 100C, the first parallel circuit 110 further includes the first diode 110d. The first diode 110d is connected between the first damping resistor 110r and the node 112. The anode of the first diode 110d is connected to the first damping resistor 110r. The cathode of the first diode 110d is connected to the node 112. The first diode 110d breaks the current loop between the first inductor 110i and the first damping resistor 110r when the first switch is open. Therefore, the energy from the first inductor 110i is suppressed from being consumed in the first damping resistor 110r.
　電源システム１００Ｃでは、第２の並列回路１２０は、第２のダイオード１２０ｄを更に含んでいる。第２のダイオード１２０ｄは、第２のダンピング抵抗１２０ｒとノード１２２との間で接続されている。第２のダイオード１２０ｄのカソードは、第２のダンピング抵抗１２０ｒに接続されている。第２のダイオード１２０ｄのアノードは、ノード１２２に接続されている。第２のダイオード１２０ｄは、第２のインダクタ１２０ｉと第２のダンピング抵抗１２０ｒとの間で、第２のスイッチが開放になった時の電流ループを切断する。したがって、第２のインダクタ１２０ｉからのエネルギーが第２のダンピング抵抗１２０ｒにおいて消費されることが抑制される。 In the power supply system 100C, the second parallel circuit 120 further includes the second diode 120d. The second diode 120d is connected between the second damping resistor 120r and the node 122. The cathode of the second diode 120d is connected to the second damping resistor 120r. The anode of the second diode 120d is connected to the node 122. The second diode 120d breaks the current loop between the second inductor 120i and the second damping resistor 120r when the second switch is open. Therefore, the energy from the second inductor 120i is suppressed from being consumed in the second damping resistor 120r.
　電源システム１００Ｃは、ダイオード１６１及びダイオード１６２を更に備えていてもよい。ダイオード１６１は、直流電源装置１０２の負極とノード１１１との間に接続されている。ダイオード１６１のアノードは、直流電源装置１０２の負極に接続されている。ダイオード１６１のカソードは、ノード１１１に接続されている。ダイオード１６２は、直流電源装置１０２の正極とノード１２１との間に接続されている。ダイオード１６２のカソードは、直流電源装置１０２の正極に接続されている。ダイオード１６２のアノードは、ノード１２１に接続されている。ダイオード１６１により、第１のスイッチが開放になった時の第１のインダクタ１１０ｉからのエネルギーは、直流電源装置１０２に回生される。また、ダイオード１６２により、第２のスイッチが開放になった時の第２のインダクタ１２０ｉからのエネルギーは、直流電源装置１０２に回生される。 The power supply system 100C may further include a diode 161 and a diode 162. The diode 161 is connected between the negative electrode of the DC power supply 102 and the node 111. The anode of the diode 161 is connected to the negative electrode of the DC power supply 102. The cathode of the diode 161 is connected to the node 111. The diode 162 is connected between the positive electrode of the DC power supply 102 and the node 121. The cathode of the diode 162 is connected to the positive electrode of the DC power supply 102. The anode of the diode 162 is connected to the node 121. The diode 161 regenerates the energy from the first inductor 110i when the first switch is opened to the DC power supply 102. Further, the energy from the second inductor 120i when the second switch is opened by the diode 162 is regenerated to the DC power supply device 102.
　以下、図７及び図８を参照する。図７は、更に別の例示的実施形態に係る電源システムを示す図である。図８は、図７に示す電源システムが出力可能なパルス状の直流電圧の一例を示す図である。図７に示す電源システム１００Ｄは、電源システム１００Ｂと同様に、パルス状の直流電圧として、バイポーラパルスを生成する。以下、電源システム１００Ｄの電源システム１００Ｂに対する相違点について説明する。 Refer to FIGS. 7 and 8 below. FIG. 7 is a diagram showing a power supply system according to still another exemplary embodiment. FIG. 8 is a diagram showing an example of a pulsed DC voltage that can be output by the power supply system shown in FIG. 7. Similar to the power supply system 100B, the power supply system 100D shown in FIG. 7 generates a bipolar pulse as a pulsed DC voltage. Hereinafter, the differences between the power supply system 100D and the power supply system 100B will be described.
　図７に示す電源システム１００Ｄは、第３の並列回路１３０及び第３のスイッチ１３５を更に備えている。第３の並列回路１３０は、ノード１３１（第５のノード）、ノード１３２（第６のノード）、第３のダンピング抵抗１３０ｒ、及び第３のインダクタ１３０ｉを含んでいる。 The power supply system 100D shown in FIG. 7 further includes a third parallel circuit 130 and a third switch 135. The third parallel circuit 130 includes a node 131 (fifth node), a node 132 (sixth node), a third damping resistor 130r, and a third inductor 130i.
　ノード１３２は、出力１４０に接続されている。第３のダンピング抵抗１３０ｒ及び第３のインダクタ１３０ｉは、ノード１３１とノード１３２との間で並列に接続されている。第３のスイッチ１３５は、グランドとノード１３１との間で接続されている。一実施形態では、第３のスイッチ１３５は、直流電源１０２ａの正極及び直流電源１０２ｂの負極が接続しているノードとノード１３１との間で接続されている。第３のスイッチ１３５は、例えばスイッチングトランジスタである。 The node 132 is connected to the output 140. The third damping resistor 130r and the third inductor 130i are connected in parallel between the node 131 and the node 132. The third switch 135 is connected between the ground and the node 131. In one embodiment, the third switch 135 is connected between the node and the node 131 to which the positive electrode of the DC power supply 102a and the negative electrode of the DC power supply 102b are connected. The third switch 135 is, for example, a switching transistor.
　電源システム１００Ｄでは、制御部１５０は、第１のスイッチ１１５、第２のスイッチ１２５、及び第３のスイッチ１３５のそれぞれに制御信号を与えて、第１のスイッチ１１５、第２のスイッチ１２５、及び第３のスイッチ１３５を制御する。第３のスイッチ１３５がスイッチングトランジスタである場合には、制御部１５０からの制御信号は、第３のスイッチ１３５の制御端子に与えられる。 In the power supply system 100D, the control unit 150 gives control signals to the first switch 115, the second switch 125, and the third switch 135, respectively, to give a control signal to the first switch 115, the second switch 125, and the third switch 135. It controls the third switch 135. When the third switch 135 is a switching transistor, the control signal from the control unit 150 is given to the control terminal of the third switch 135.
　制御部１５０は、第１のスイッチ１１５を導通状態に設定し、第２のスイッチ１２５及び第３のスイッチ１３５を非導通状態に設定する制御を実行し得る。制御部１５０は、第２のスイッチ１２５を導通状態に設定し、第１のスイッチ１１５及び第３のスイッチ１３５を非導通状態に設定する制御を実行し得る。また、制御部１５０は、第３のスイッチ１３５を導通状態に設定し、第１のスイッチ１１５及び第２のスイッチ１２５を非導通状態に設定する制御を実行し得る。 The control unit 150 can execute control for setting the first switch 115 in the conductive state and setting the second switch 125 and the third switch 135 in the non-conducting state. The control unit 150 may execute control for setting the second switch 125 to the conductive state and setting the first switch 115 and the third switch 135 to the non-conducting state. Further, the control unit 150 may execute control for setting the third switch 135 to the conductive state and setting the first switch 115 and the second switch 125 to the non-conducting state.
　制御部１５０からの制御信号により、第１のスイッチ１１５が導通状態に設定され、第２のスイッチ１２５及び第３のスイッチ１３５が非導通状態に設定されているときには、出力１４０から正の電圧が出力される。制御部１５０からの制御信号により、第２のスイッチ１２５が導通状態に設定され、第１のスイッチ１１５及び第３のスイッチ１３５が非導通状態に設定されているときには、出力１４０から負の電圧が出力される。また、制御部１５０からの制御信号により、第３のスイッチ１３５が導通状態に設定され、第１のスイッチ１１５及び第２のスイッチ１２５が非導通状態に設定されているときには、出力１４０はグランドに接続される。 When the first switch 115 is set to the conductive state and the second switch 125 and the third switch 135 are set to the non-conducting state by the control signal from the control unit 150, a positive voltage is applied from the output 140. It is output. When the second switch 125 is set to the conductive state and the first switch 115 and the third switch 135 are set to the non-conducting state by the control signal from the control unit 150, a negative voltage is applied from the output 140. It is output. Further, when the third switch 135 is set to the conductive state and the first switch 115 and the second switch 125 are set to the non-conducting state by the control signal from the control unit 150, the output 140 is set to the ground. Be connected.
　上述した電源システム１００Ｂでは、第１のスイッチ１１５が導通状態にあるときには、第２のスイッチ１２５が非導通状態になり、正の電圧が出力１４０からは出力される。また、電源システム１００Ｂでは、第１のスイッチ１１５が非導通状態にあるときには、第２のスイッチ１２５が導通状態になり、負の電圧が出力１４０からは出力される。電源システム１００Ｂでは、パルス状の直流電圧が周期的に出力される場合には、周期内で正の直流電圧が出力される期間の時間長と負の直流電圧が出力される期間の時間長が、互いに依存する。即ち、電源システム１００Ｂでは、周期内で正の直流電圧が出力される期間の時間長が決定されると、周期内で負の直流電圧が出力される期間の時間長は、一意に定められる。 In the power supply system 100B described above, when the first switch 115 is in the conductive state, the second switch 125 is in the non-conducting state, and a positive voltage is output from the output 140. Further, in the power supply system 100B, when the first switch 115 is in the non-conducting state, the second switch 125 is in the conducting state, and a negative voltage is output from the output 140. In the power supply system 100B, when the pulsed DC voltage is periodically output, the time length of the period in which the positive DC voltage is output and the time length of the period in which the negative DC voltage is output are set in the cycle. , Depend on each other. That is, in the power supply system 100B, when the time length of the period in which the positive DC voltage is output is determined in the cycle, the time length of the period in which the negative DC voltage is output in the cycle is uniquely determined.
　一方、電源システム１００Ｄでは、出力１４０は、直流電源装置１０２の正極及び負極だけではなく、グランドにも接続可能である。電源システム１００Ｄでは、パルス状の直流電圧を周期的に出力する場合には、出力１４０がグランドに接続している一つ以上の期間を周期ＰＣ内に設けることができる。これにより、電源システム１００Ｄでは、正の電圧が出力される期間の時間長と負の電圧が出力される期間の時間長を、互いから独立的に設定することが可能となる。 On the other hand, in the power supply system 100D, the output 140 can be connected not only to the positive electrode and the negative electrode of the DC power supply device 102 but also to the ground. In the power supply system 100D, when the pulsed DC voltage is periodically output, one or more periods in which the output 140 is connected to the ground can be provided in the periodic PC. As a result, in the power supply system 100D, the time length of the period in which the positive voltage is output and the time length of the period in which the negative voltage is output can be set independently of each other.
　図８の例のように、電源システム１００Ｄから出力されるパルス状の直流電圧は、周期ＰＣ内の期間Ｐ１において負の電圧であってもよい。また、図８の例のように、電源システム１００Ｄから出力されるパルス状の直流電圧は、周期ＰＣ内の期間Ｐ２において正の電圧であってもよい。図８の例のように、周期ＰＣ内の期間Ｐ１の前の期間において，出力１４０はグランドに接続されてもよい。また、図８の例のように、周期ＰＣ内の期間Ｐ１と期間Ｐ２の間の期間において、出力１４０はグランドに接続されてもよい。 As in the example of FIG. 8, the pulsed DC voltage output from the power supply system 100D may be a negative voltage during the period P1 in the periodic PC. Further, as in the example of FIG. 8, the pulsed DC voltage output from the power supply system 100D may be a positive voltage during the period P2 in the periodic PC. As in the example of FIG. 8, the output 140 may be connected to the ground in the period before the period P1 in the periodic PC. Further, as in the example of FIG. 8, the output 140 may be connected to the ground during the period between the period P1 and the period P2 in the periodic PC.
　なお、電源システム１００Ｄにおいても、第１のダイオード１１０ｄが、第１のダンピング抵抗１１０ｒとノード１１２との間に接続されていてもよい。また、電源システム１００Ｄにおいても、第２のダイオード１２０ｄが、第２のダンピング抵抗１２０ｒとノード１２２との間に接続されていてもよい。また、電源システム１００Ｄにおいても、ダイオード１６１が、直流電源装置１０２の負極とノード１１１との間に接続されていてもよい。また、電源システム１００Ｄにおいても、ダイオード１６２が、直流電源装置１０２の正極とノード１２１との間に接続されていてもよい。 Also in the power supply system 100D, the first diode 110d may be connected between the first damping resistor 110r and the node 112. Further, in the power supply system 100D, the second diode 120d may be connected between the second damping resistor 120r and the node 122. Further, in the power supply system 100D, the diode 161 may be connected between the negative electrode of the DC power supply device 102 and the node 111. Further, in the power supply system 100D, the diode 162 may be connected between the positive electrode of the DC power supply device 102 and the node 121.
　以下、種々の例示的実施形態に係るプラズマ処理装置について説明する。 Hereinafter, the plasma processing apparatus according to various exemplary embodiments will be described.
　図９は、一つの例示的実施形態に係るプラズマ処理装置を示す図である。図９に示すプラズマ処理装置１Ａは、容量結合型のプラズマ処理装置である。プラズマ処理装置１Ａは、チャンバ１０を備えている。チャンバ１０は、その中に内部空間１０ｓを提供している。内部空間１０ｓの中心軸線は、鉛直方向に延びる軸線ＡＸである。 FIG. 9 is a diagram showing a plasma processing apparatus according to one exemplary embodiment. The plasma processing apparatus 1A shown in FIG. 9 is a capacitively coupled plasma processing apparatus. The plasma processing apparatus 1A includes a chamber 10. The chamber 10 provides an internal space 10s therein. The central axis of the internal space 10s is the axis AX extending in the vertical direction.
　一実施形態において、チャンバ１０は、チャンバ本体１２を含んでいてもよい。チャンバ本体１２は、略円筒形状を有している。内部空間１０ｓは、チャンバ本体１２の中に提供されている。チャンバ本体１２は、例えばアルミニウムから構成されている。チャンバ本体１２は電気的に接地されている。チャンバ本体１２の内壁面、即ち内部空間１０ｓを画成する壁面には、耐プラズマ性を有する膜が形成されている。この膜は、陽極酸化処理によって形成された膜又は酸化イットリウムから形成された膜といったセラミック製の膜であり得る。 In one embodiment, the chamber 10 may include a chamber body 12. The chamber body 12 has a substantially cylindrical shape. The internal space 10s is provided in the chamber body 12. The chamber body 12 is made of, for example, aluminum. The chamber body 12 is electrically grounded. A plasma-resistant film is formed on the inner wall surface of the chamber body 12, that is, the wall surface defining the internal space 10s. This film can be a ceramic film, such as a film formed by anodizing or a film formed from yttrium oxide.
　チャンバ本体１２の側壁には通路１２ｐが形成されている。基板Ｗは、内部空間１０ｓとチャンバ１０の外部との間で搬送されるときに、通路１２ｐを通過する。この通路１２ｐの開閉のために、ゲートバルブ１２ｇがチャンバ本体１２の側壁に沿って設けられている。 A passage 12p is formed on the side wall of the chamber body 12. The substrate W passes through the passage 12p when being conveyed between the internal space 10s and the outside of the chamber 10. A gate valve 12g is provided along the side wall of the chamber body 12 for opening and closing the passage 12p.
　プラズマ処理装置１Ａは、基板支持部１６を更に備えている。基板支持部１６は、チャンバ１０内で、その上に載置された基板Ｗを支持するように構成されている。基板Ｗは、略円盤形状を有し得る。プラズマ処理装置１Ａは、基板支持部１６を支持する支持部１７を更に備えていてもよい。支持部１７は、チャンバ本体１２の底部から上方に延在している。支持部１７は、略円筒形状を有している。支持部１７は、石英といった絶縁材料から形成されている。 The plasma processing device 1A further includes a substrate support portion 16. The substrate support portion 16 is configured to support the substrate W placed on the substrate support portion 16 in the chamber 10. The substrate W may have a substantially disk shape. The plasma processing apparatus 1A may further include a support portion 17 that supports the substrate support portion 16. The support portion 17 extends upward from the bottom of the chamber body 12. The support portion 17 has a substantially cylindrical shape. The support portion 17 is formed of an insulating material such as quartz.
　基板支持部１６は、下部電極１８及び静電チャック２０を含んでいてもよい。下部電極１８及び静電チャック２０は、チャンバ１０の中に設けられている。下部電極１８は、アルミニウムといった導電性材料から形成されており、略円盤形状を有している。下部電極１８は、その中に流路１８ｆを提供していてもよい。流路１８ｆは、熱交換媒体用の流路である。熱交換媒体としては、例えば冷媒が用いられ得る。流路１８ｆは、熱交換媒体の供給装置（例えば、チラーユニット）に接続される。この供給装置は、チャンバ１０の外部に設けられている。供給装置からの熱交換媒体は、配管２３ａを介して流路１８ｆに供給される。流路１８ｆに供給された熱交換媒体は、配管２３ｂを介して供給装置に戻される。 The substrate support portion 16 may include a lower electrode 18 and an electrostatic chuck 20. The lower electrode 18 and the electrostatic chuck 20 are provided in the chamber 10. The lower electrode 18 is formed of a conductive material such as aluminum and has a substantially disk shape. The lower electrode 18 may provide a flow path 18f therein. The flow path 18f is a flow path for the heat exchange medium. As the heat exchange medium, for example, a refrigerant may be used. The flow path 18f is connected to a heat exchange medium supply device (for example, a chiller unit). This supply device is provided outside the chamber 10. The heat exchange medium from the supply device is supplied to the flow path 18f via the pipe 23a. The heat exchange medium supplied to the flow path 18f is returned to the supply device via the pipe 23b.
　静電チャック２０は、下部電極１８上に設けられている。基板Ｗは、内部空間１０ｓの中で処理されるときに、静電チャック２０上に載置され、静電チャック２０によって保持される。 The electrostatic chuck 20 is provided on the lower electrode 18. The substrate W is placed on the electrostatic chuck 20 and held by the electrostatic chuck 20 when processed in the internal space 10s.
　静電チャック２０は、本体及び電極を有している。静電チャック２０の本体は、酸化アルミニウム又は窒化アルミニウムといった誘電体から形成されている。静電チャック２０の本体は、略円盤形状を有している。静電チャック２０の中心軸線は、軸線ＡＸに略一致している。静電チャック２０の電極は、本体内に設けられている。静電チャック２０の電極は、膜形状を有している。静電チャック２０の電極には、直流電源がスイッチを介して電気的に接続されている。直流電源からの電圧が静電チャック２０の電極に印加されると、静電チャック２０と基板Ｗとの間で静電引力が発生する。発生した静電引力により、基板Ｗは静電チャック２０に引き付けられ、静電チャック２０によって保持される。 The electrostatic chuck 20 has a main body and electrodes. The main body of the electrostatic chuck 20 is formed of a dielectric such as aluminum oxide or aluminum nitride. The main body of the electrostatic chuck 20 has a substantially disk shape. The central axis of the electrostatic chuck 20 substantially coincides with the axis AX. The electrodes of the electrostatic chuck 20 are provided in the main body. The electrode of the electrostatic chuck 20 has a film shape. A DC power supply is electrically connected to the electrodes of the electrostatic chuck 20 via a switch. When a voltage from a DC power source is applied to the electrodes of the electrostatic chuck 20, electrostatic attraction is generated between the electrostatic chuck 20 and the substrate W. The substrate W is attracted to the electrostatic chuck 20 by the generated electrostatic attraction and is held by the electrostatic chuck 20.
　基板支持部１６は、その上に搭載されるエッジリングＥＲを支持していてもよい。エッジリングＥＲは、環形状を有しており、例えばシリコン又は炭化ケイ素から形成されている。エッジリングＥＲは、石英といった誘電体から形成されていてもよい。エッジリングＥＲは、部分的に、静電チャック２０上に搭載されていてもよい。基板Ｗは、静電チャック２０上、且つ、エッジリングＥＲによって囲まれた領域内に載置される。 The board support portion 16 may support the edge ring ER mounted on the board support portion 16. The edge ring ER has a ring shape and is formed of, for example, silicon or silicon carbide. The edge ring ER may be formed of a dielectric such as quartz. The edge ring ER may be partially mounted on the electrostatic chuck 20. The substrate W is placed on the electrostatic chuck 20 and in the region surrounded by the edge ring ER.
　プラズマ処理装置１Ａは、ガス供給ライン２５を更に備えていてもよい。ガス供給ライン２５は、ガス供給機構からの伝熱ガス、例えばＨｅガスを、静電チャック２０の上面と基板Ｗの裏面（下面）との間の間隙に供給する。 The plasma processing apparatus 1A may further include a gas supply line 25. The gas supply line 25 supplies heat transfer gas from the gas supply mechanism, for example, He gas, to the gap between the upper surface of the electrostatic chuck 20 and the back surface (lower surface) of the substrate W.
　プラズマ処理装置１Ａは、絶縁領域２７を更に備えていてもよい。絶縁領域２７は、支持部１７上に配置されている。絶縁領域２７は、軸線ＡＸに対して径方向において下部電極１８の外側に配置されている。絶縁領域２７は、下部電極１８の外周面に沿って周方向に延在している。絶縁領域２７は、石英といった絶縁体から形成されている。エッジリングＥＲは、部分的に絶縁領域２７上に搭載されていてもよい。 The plasma processing apparatus 1A may further include an insulating region 27. The insulating region 27 is arranged on the support portion 17. The insulating region 27 is arranged outside the lower electrode 18 in the radial direction with respect to the axis AX. The insulating region 27 extends in the circumferential direction along the outer peripheral surface of the lower electrode 18. The insulating region 27 is formed of an insulator such as quartz. The edge ring ER may be partially mounted on the insulating region 27.
　プラズマ処理装置１Ａは、上部電極３０を更に備えている。上部電極３０は、基板支持部１６の上方に設けられている。上部電極３０は、部材３２と共にチャンバ本体１２の上部開口を閉じている。部材３２は、絶縁性を有している。上部電極３０は、この部材３２を介してチャンバ本体１２の上部に支持されている。 The plasma processing device 1A further includes an upper electrode 30. The upper electrode 30 is provided above the substrate support portion 16. The upper electrode 30 closes the upper opening of the chamber body 12 together with the member 32. The member 32 has an insulating property. The upper electrode 30 is supported on the upper part of the chamber body 12 via the member 32.
　上部電極３０は、天板３４及び支持体３６を含んでいてもよい。天板３４の下面は、内部空間１０ｓを画成している。天板３４には、複数のガス吐出孔３４ａが形成されている。複数のガス吐出孔３４ａの各々は、天板３４を板厚方向（鉛直方向）に貫通している。この天板３４は、限定されるものではないが、例えばシリコンから形成されている。或いは、天板３４は、アルミニウム製の部材の表面に耐プラズマ性の膜を設けた構造を有し得る。この膜は、陽極酸化処理によって形成された膜又は酸化イットリウムから形成された膜といったセラミック製の膜であり得る。 The upper electrode 30 may include a top plate 34 and a support 36. The lower surface of the top plate 34 defines the internal space 10s. A plurality of gas discharge holes 34a are formed on the top plate 34. Each of the plurality of gas discharge holes 34a penetrates the top plate 34 in the plate thickness direction (vertical direction). The top plate 34 is, but is not limited to, formed of, for example, silicon. Alternatively, the top plate 34 may have a structure in which a plasma resistant film is provided on the surface of an aluminum member. This film can be a ceramic film, such as a film formed by anodizing or a film formed from yttrium oxide.
　支持体３６は、天板３４を着脱自在に支持している。支持体３６は、例えばアルミニウムといった導電性材料から形成されている。支持体３６の内部には、ガス拡散室３６ａが設けられている。ガス拡散室３６ａからは、複数のガス孔３６ｂが下方に延びている。複数のガス孔３６ｂは、複数のガス吐出孔３４ａにそれぞれ連通している。支持体３６には、ガス導入ポート３６ｃが形成されている。ガス導入ポート３６ｃは、ガス拡散室３６ａに接続している。ガス導入ポート３６ｃには、ガス供給管３８が接続されている。 The support 36 supports the top plate 34 in a detachable manner. The support 36 is made of a conductive material such as aluminum. A gas diffusion chamber 36a is provided inside the support 36. A plurality of gas holes 36b extend downward from the gas diffusion chamber 36a. The plurality of gas holes 36b communicate with the plurality of gas discharge holes 34a, respectively. A gas introduction port 36c is formed on the support 36. The gas introduction port 36c is connected to the gas diffusion chamber 36a. A gas supply pipe 38 is connected to the gas introduction port 36c.
　ガス供給管３８には、ガスソース群４０が、バルブ群４１、流量制御器群４２、及びバルブ群４３を介して接続されている。ガスソース群４０、バルブ群４１、流量制御器群４２、及びバルブ群４３は、ガス供給部ＧＳを構成している。ガスソース群４０は、複数のガスソースを含んでいる。バルブ群４１及びバルブ群４３の各々は、複数のバルブ（例えば開閉バルブ）を含んでいる。流量制御器群４２は、複数の流量制御器を含んでいる。流量制御器群４２の複数の流量制御器の各々は、マスフローコントローラ又は圧力制御式の流量制御器である。ガスソース群４０の複数のガスソースの各々は、バルブ群４１の対応のバルブ、流量制御器群４２の対応の流量制御器、及びバルブ群４３の対応のバルブを介して、ガス供給管３８に接続されている。プラズマ処理装置１Ａは、ガスソース群４０の複数のガスソースのうち選択された一以上のガスソースからのガスを、個別に調整された流量で、内部空間１０ｓに供給することが可能である。 The gas source group 40 is connected to the gas supply pipe 38 via the valve group 41, the flow rate controller group 42, and the valve group 43. The gas source group 40, the valve group 41, the flow rate controller group 42, and the valve group 43 constitute the gas supply unit GS. The gas source group 40 includes a plurality of gas sources. Each of the valve group 41 and the valve group 43 includes a plurality of valves (for example, an on-off valve). The flow rate controller group 42 includes a plurality of flow rate controllers. Each of the plurality of flow rate controllers in the flow rate controller group 42 is a mass flow controller or a pressure control type flow rate controller. Each of the plurality of gas sources of the gas source group 40 is connected to the gas supply pipe 38 via the corresponding valve of the valve group 41, the corresponding flow rate controller of the flow rate controller group 42, and the corresponding valve of the valve group 43. It is connected. The plasma processing apparatus 1A can supply gas from one or more gas sources selected from the plurality of gas sources of the gas source group 40 to the internal space 10s at an individually adjusted flow rate.
　基板支持部１６又は支持部１７とチャンバ本体１２の側壁との間には、バッフルプレート４８が設けられていてもよい。バッフルプレート４８は、例えば、アルミニウム製の部材に酸化イットリウム等のセラミックを被覆することにより構成され得る。このバッフルプレート４８には、多数の貫通孔が形成されている。バッフルプレート４８の下方においては、排気管５２がチャンバ本体１２の底部に接続されている。この排気管５２には、排気装置５０が接続されている。排気装置５０は、自動圧力制御弁といった圧力制御器、及び、ターボ分子ポンプなどの真空ポンプを有しており、内部空間１０ｓの圧力を減圧することができる。 A baffle plate 48 may be provided between the substrate support portion 16 or the support portion 17 and the side wall of the chamber main body 12. The baffle plate 48 may be configured, for example, by coating an aluminum member with a ceramic such as yttrium oxide. A large number of through holes are formed in the baffle plate 48. Below the baffle plate 48, the exhaust pipe 52 is connected to the bottom of the chamber body 12. An exhaust device 50 is connected to the exhaust pipe 52. The exhaust device 50 has a pressure controller such as an automatic pressure control valve and a vacuum pump such as a turbo molecular pump, and can reduce the pressure in the internal space 10s.
　プラズマ処理装置１Ａは、電源システム１００を更に備えている。電源システム１００としては、上述した電源システム１００Ａ、１００Ｂ、１００Ｃ、又は１００Ｄが用いられる。電源システム１００の出力１４０は、上部電極３０に接続されている。プラズマ処理装置１Ａでは、電源システム１００からのパルス状の直流電圧が上部電極３０に与えられることにより、チャンバ１０内のガスが励起されて、当該ガスからプラズマが生成される。 The plasma processing device 1A further includes a power supply system 100. As the power supply system 100, the power supply system 100A, 100B, 100C, or 100D described above is used. The output 140 of the power supply system 100 is connected to the upper electrode 30. In the plasma processing apparatus 1A, a pulsed DC voltage from the power supply system 100 is applied to the upper electrode 30, so that the gas in the chamber 10 is excited and plasma is generated from the gas.
　プラズマ処理装置１Ａは、主制御部ＭＣを更に備えていてもよい。主制御部ＭＣは、プロセッサ、記憶装置、入力装置、表示装置等を備えるコンピュータであり、プラズマ処理装置１Ａの各部を制御する。主制御部ＭＣは、記憶装置に記憶されている制御プログラムを実行し、当該記憶装置に記憶されているレシピデータに基づいてプラズマ処理装置１Ａの各部を制御する。主制御部ＭＣによる制御により、レシピデータによって指定されたプロセスがプラズマ処理装置１Ａにおいて実行される。 The plasma processing device 1A may further include a main control unit MC. The main control unit MC is a computer including a processor, a storage device, an input device, a display device, and the like, and controls each unit of the plasma processing device 1A. The main control unit MC executes a control program stored in the storage device and controls each unit of the plasma processing device 1A based on the recipe data stored in the storage device. Under the control of the main control unit MC, the process specified by the recipe data is executed in the plasma processing apparatus 1A.
　以下、図１０を参照する。図１０は、別の例示的実施形態に係るプラズマ処理装置を示す図である。以下、図１０に示すプラズマ処理装置１Ｂのプラズマ処理装置１Ａに対する相違点について説明する。 Refer to FIG. 10 below. FIG. 10 is a diagram showing a plasma processing apparatus according to another exemplary embodiment. Hereinafter, the differences between the plasma processing apparatus 1B shown in FIG. 10 and the plasma processing apparatus 1A will be described.
　プラズマ処理装置１Ｂは、高周波電源６０及び整合器６０ｍを更に備えている。高周波電源６０は、高周波電力を発生するように構成された電源である。高周波電源６０は、整合器６０ｍを介して上部電極３０に接続されている。なお、高周波電源６０は、上部電極３０ではなく、整合器６０ｍを介して下部電極１８に接続されていてもよい。整合器６０ｍは、高周波電源６０の負荷のインピーダンスを高周波電源６０の出力インピーダンスに整合させるための整合回路を有している。プラズマ処理装置１Ｂでは、高周波電源６０からの高周波電力により、高周波電界がチャンバ１０の中で形成される。高周波電界は、チャンバ１０の中のガスを励起させる。その結果、プラズマがチャンバ１０内で生成される。 The plasma processing device 1B further includes a high frequency power supply 60 and a matching device 60 m. The high frequency power supply 60 is a power supply configured to generate high frequency power. The high frequency power supply 60 is connected to the upper electrode 30 via a matching device 60m. The high frequency power supply 60 may be connected to the lower electrode 18 via the matching device 60m instead of the upper electrode 30. The matching device 60m has a matching circuit for matching the impedance of the load of the high frequency power supply 60 with the output impedance of the high frequency power supply 60. In the plasma processing apparatus 1B, a high frequency electric field is formed in the chamber 10 by the high frequency power from the high frequency power supply 60. The high frequency electric field excites the gas in the chamber 10. As a result, plasma is generated in chamber 10.
　プラズマ処理装置１Ｂでは、電源システム１００は、下部電極１８に接続されている。プラズマ処理装置１Ｂでは、電源システム１００からのパルス状の直流電圧は、チャンバ１０内のプラズマから基板支持部１６上の基板Ｗにイオンを引き込むために、用いられる。即ち、プラズマ処理装置１Ｂでは、電源システム１００からのパルス状の直流電圧は、バイアス電圧として用いられる。 In the plasma processing apparatus 1B, the power supply system 100 is connected to the lower electrode 18. In the plasma processing apparatus 1B, the pulsed DC voltage from the power supply system 100 is used to draw ions from the plasma in the chamber 10 to the substrate W on the substrate support 16. That is, in the plasma processing apparatus 1B, the pulsed DC voltage from the power supply system 100 is used as the bias voltage.
　以下、図１１を参照する。図１１は、更に別の例示的実施形態に係るプラズマ処理装置を示す図である。以下、図１１に示すプラズマ処理装置１Ｃのプラズマ処理装置１Ｂに対する相違点について説明する。 Refer to FIG. 11 below. FIG. 11 is a diagram showing a plasma processing apparatus according to still another exemplary embodiment. Hereinafter, the differences between the plasma processing apparatus 1C shown in FIG. 11 and the plasma processing apparatus 1B will be described.
　プラズマ処理装置１Ｃでは、電源システム１００は、フィルタ２００を介して上部電極３０に接続されている。フィルタ２００は、ローパスフィルタであり、電源システム１００に向かう高周波電力を遮断するか、或いは、低減する。 In the plasma processing apparatus 1C, the power supply system 100 is connected to the upper electrode 30 via the filter 200. The filter 200 is a low-pass filter that cuts off or reduces high frequency power towards the power supply system 100.
　上述した種々の例示的実施形態に係るプラズマ処理装置によれば、電極（上部電極又は下部電極）に供給されるパルス状の直流電圧のオーバーシュートが抑制される。したがって、基板に対する成膜、エッチング等のプラズマ処理において、意図しないイオンエネルギーの増大に起因する基板に対するイオン衝撃が、抑制される。また、意図しないイオンエネルギーの増大に起因するチャンバ本体１２の側壁及び／又は天板３４の下面に対するイオン衝撃によりパーティクルが発生することが抑制される。また、電極に接続される回路要素（例えば、電源システム１００中の第１のスイッチ１１５及び第２のスイッチ１２５）に耐電圧を超える電力が供給されることが防止される。 According to the plasma processing apparatus according to the various exemplary embodiments described above, the overshoot of the pulsed DC voltage supplied to the electrode (upper electrode or lower electrode) is suppressed. Therefore, in plasma treatment such as film formation and etching on the substrate, the ion impact on the substrate due to an unintended increase in ion energy is suppressed. Further, it is possible to suppress the generation of particles due to the ion impact on the side wall of the chamber body 12 and / or the lower surface of the top plate 34 due to an unintended increase in ion energy. Further, it is prevented that the circuit elements connected to the electrodes (for example, the first switch 115 and the second switch 125 in the power supply system 100) are supplied with power exceeding the withstand voltage.
　ここで、複数のプラズマ処理装置において、同一制御の下でプラズマ処理を行う場合について考察する。パルス状の直流電圧のオーバーシュートは、チャンバ及び／又はケーブルにおける寄生ＬＣ成分によって発生する。したがって、オーバーシュートの量は、チャンバの構造、チャンバのサイズ、ケーブルの種類、ケーブルの長さ等に依存する。故に、複数のプラズマ処理装置のそれぞれにおいて発生するオーバーシュートの量は、パルス状の直流電圧の設定が同一であっても、異なる。その結果、複数のプラズマ処理装置で同じ制御が行われる場合であっても、オーバーシュートの量に応じてプラズマ処理結果に差が生じる。しかしながら、上述した種々の例示的実施形態に係るプラズマ処理装置によれば、オーバーシュートが抑制されるので、複数のプラズマ処理装置で同じ制御が行われる場合にプラズマ処理結果に差が生じることが抑制される。 Here, a case where plasma processing is performed under the same control in a plurality of plasma processing devices will be considered. The pulsed DC voltage overshoot is caused by the parasitic LC component in the chamber and / or cable. Therefore, the amount of overshoot depends on the structure of the chamber, the size of the chamber, the type of cable, the length of the cable, and the like. Therefore, the amount of overshoot generated in each of the plurality of plasma processing devices is different even if the setting of the pulsed DC voltage is the same. As a result, even when the same control is performed by a plurality of plasma processing devices, the plasma processing result differs depending on the amount of overshoot. However, according to the plasma processing apparatus according to the various exemplary embodiments described above, overshoot is suppressed, so that it is possible to suppress a difference in plasma processing results when the same control is performed by a plurality of plasma processing apparatus. Will be done.
　以下、図１２を参照する。図１２は、比較例に係るプラズマ処理装置の電源システムの出力における電圧波形の例を示す図である。比較例に係るプラズマ処理装置の電源システムは、第１の並列回路及び第２の並列回路を有していない点では電源システム１００Ａと異なっている。電源システムから見た負荷インピーダンスは、プラズマ以外の要因による負荷インピーダンス及びプラズマに起因する負荷インピーダンスで決定される。プラズマ以外の要因による負荷インピーダンスは、ケーブル、チャンバの構造等に依存する。プラズマに起因する負荷インピーダンスは、投入電力、チャンバに供給されるガスの種類、チャンバ内の圧力、ガスの流量、ギャップ（基板支持部と上部電極との間の距離）、成膜状況の違い（絶縁膜、メタル膜等）等の種々の要因に依存する。即ち、プラズマに起因する負荷インピーダンスは、上記の種々の要因の変動に応じて変化する。したがって、プラズマの生成時のプロセス条件が変化すると、負荷インピーダンスは容易に変化する。パルス状の電圧の立ち上がりの期間と立ち下がりの期間では、プラズマのインピーダンスが異なるので、負荷インピーダンスも異なる。したがって、電源システムにおいて対策がなされていない場合には、図１２に示す比較例のように、パルス状の電圧の立ち上がりと立ち下がりにおいて互いに異なる形状を有するオーバーシュートが発生し、これを抑制することができない。或いは、そのような電源システムは、限られた範囲内の負荷インピーダンスの変動に起因するオーバーシュートを抑制することしかできず、その適用範囲は極めて狭い。一方、上述した種々の例示的実施形態に係るプラズマ処理装置は、プラズマに起因する負荷インピーダンスの変化に適応した回路素子パラメータを採用することができるので、オーバーシュートを抑制することが可能である。 Refer to FIG. 12 below. FIG. 12 is a diagram showing an example of a voltage waveform in the output of the power supply system of the plasma processing apparatus according to the comparative example. The power supply system of the plasma processing apparatus according to the comparative example is different from the power supply system 100A in that it does not have the first parallel circuit and the second parallel circuit. The load impedance seen from the power supply system is determined by the load impedance due to factors other than plasma and the load impedance due to plasma. The load impedance due to factors other than plasma depends on the structure of the cable, chamber, and the like. The load impedance caused by plasma is the input power, the type of gas supplied to the chamber, the pressure in the chamber, the gas flow rate, the gap (distance between the substrate support and the upper electrode), and the difference in film formation status (difference in film formation status). It depends on various factors such as insulating film, metal film, etc.). That is, the load impedance caused by the plasma changes according to the fluctuation of the above-mentioned various factors. Therefore, the load impedance changes easily when the process conditions at the time of plasma generation change. Since the impedance of the plasma is different between the rising period and the falling period of the pulsed voltage, the load impedance is also different. Therefore, if no countermeasure is taken in the power supply system, overshoots having different shapes occur at the rising and falling edges of the pulsed voltage as shown in the comparative example shown in FIG. 12, and this is suppressed. Can't. Alternatively, such a power supply system can only suppress overshoot due to load impedance fluctuations within a limited range, and its scope of application is extremely narrow. On the other hand, the plasma processing apparatus according to the various exemplary embodiments described above can adopt circuit element parameters adapted to the change in load impedance due to plasma, so that overshoot can be suppressed.
　以下、プラズマ処理装置における電源システム１００の回路素子パラメータの第１の最適化方法及び第２の最適化方法について説明する。第１の最適化方法及び第２の最適化方法は、上述した種々の例示的実施形態に係るプラズマ処理装置の何れにも適用可能である。 Hereinafter, the first optimization method and the second optimization method of the circuit element parameters of the power supply system 100 in the plasma processing apparatus will be described. The first optimization method and the second optimization method can be applied to any of the plasma processing devices according to the various exemplary embodiments described above.
　第１の最適化方法では、プロセスレシピで指定されたプロセスが実行されることにより、プラズマ処理装置のチャンバ内でプラズマが生成される。プラズマの生成中には、電源システム１００からパルス状の直流電圧が電極（上部電極３０又は下部電極１８）に印加される。そして、電源システム１００からパルス状の直流電圧が電極（上部電極３０又は下部電極１８）に印加されているときの当該電極での電圧波形が取得される。電圧波形は、電圧センサを用いて取得され得る。 In the first optimization method, plasma is generated in the chamber of the plasma processing apparatus by executing the process specified in the process recipe. During the generation of plasma, a pulsed DC voltage is applied from the power supply system 100 to the electrodes (upper electrode 30 or lower electrode 18). Then, when a pulsed DC voltage is applied to the electrode (upper electrode 30 or lower electrode 18) from the power supply system 100, the voltage waveform at the electrode is acquired. The voltage waveform can be obtained using a voltage sensor.
　次いで、第１の最適化方法では、出力１４０が直流電源装置１０２の正極に接続されている期間における電圧波形のオーバーシュート（又はリンギング）の量ΔＶ１を許容量以下に減少させるよう、第１のダンピング抵抗１１０ｒの抵抗値が決定される。また、出力１４０が直流電源装置１０２の負極に接続されている期間における電圧波形のオーバーシュート（又はリンギング）の量ΔＶ２を許容量以下に減少させるよう、第２のダンピング抵抗１２０ｒの抵抗値が決定される。なお、電源システム１００として電源システム１００Ｄが用いられている場合には、第３のダンピング抵抗１３０ｒの抵抗値が更に決定される。第３のダンピング抵抗１３０ｒの抵抗値は、出力１４０がグランドに接続されている期間における電圧波形のオーバーシュート（又はリンギング）の量ΔＶ３を許容量以下に減少させるよう、決定される。 Then, in the first optimization method, the amount ΔV1 of the overshoot (or ringing) of the voltage waveform during the period when the output 140 is connected to the positive electrode of the DC power supply device 102 is reduced to the allowable amount or less. The resistance value of the damping resistance 110r is determined. Further, the resistance value of the second damping resistor 120r is determined so as to reduce the amount ΔV2 of the overshoot (or ringing) of the voltage waveform during the period when the output 140 is connected to the negative electrode of the DC power supply device 102 to an allowable amount or less. Will be done. When the power supply system 100D is used as the power supply system 100, the resistance value of the third damping resistor 130r is further determined. The resistance value of the third damping resistor 130r is determined so as to reduce the amount of overshoot (or ringing) ΔV3 of the voltage waveform during the period when the output 140 is connected to the ground to be less than the allowable amount.
　次いで、第１の最適化方法では、ΔＶ１及びΔＶ２がそれぞれの許容量よりも大きくならないように、第１のインダクタ１１０ｉの最小のインダクタンス及び第２のインダクタ１２０ｉの最小のインダクタンスが決定される。なお、電源システム１００として電源システム１００Ｄが用いられている場合には、ΔＶ３が許容量よりも大きくならないように、第３のインダクタ１３０ｉの最小のインダクタンスが決定される。 Next, in the first optimization method, the minimum inductance of the first inductor 110i and the minimum inductance of the second inductor 120i are determined so that ΔV1 and ΔV2 do not become larger than the respective allowable amounts. When the power supply system 100D is used as the power supply system 100, the minimum inductance of the third inductor 130i is determined so that ΔV3 does not become larger than the allowable amount.
　以下、第２の最適化方法について説明する。第２の最適化方法では、第１の最適化方法と同様に、プラズマ処理装置のチャンバ内でプラズマが生成され、電極における電圧波形が取得される。プラズマの生成中には、電源システム１００からパルス状の直流電圧が電極（上部電極３０又は下部電極１８）に印加される。 The second optimization method will be described below. In the second optimization method, as in the first optimization method, plasma is generated in the chamber of the plasma processing apparatus, and the voltage waveform at the electrodes is acquired. During the generation of plasma, a pulsed DC voltage is applied from the power supply system 100 to the electrodes (upper electrode 30 or lower electrode 18).
　次いで、第２の最適化方法では、回路モデルの回路素子パラメータが決定される。図１３は、回路モデルの一例を示す図である。図１３に示す回路モデルは、直流電源装置１０２の正極と負極との間で直列に接続された抵抗９０１、インダクタ９０２、及びコンデンサ９０３を含む。第２の最適化方法では、出力１４０が直流電源装置１０２の正極に接続されている期間の電圧波形に適合（フィット）する抵抗９０１の抵抗値ＲＳ、インダクタ９０２のインダクタンスＬ、及びコンデンサ９０３の静電容量Ｃが求められる。そして、下記の式（１）を満たす抵抗値Ｒが求められる。式（１）が満たされる場合には、リンギングは生じない。
ＣＲ２／（４Ｌ）＝１　　　…（１）
そして、Ｒ－ＲＳ－Ｒｉが、第１のダンピング抵抗１１０ｒの抵抗値として決定される。なお、Ｒｉは、直流電源装置１０２の内部抵抗値である。 Then, in the second optimization method, the circuit element parameters of the circuit model are determined. FIG. 13 is a diagram showing an example of a circuit model. The circuit model shown in FIG. 13 includes a resistor 901, an inductor 902, and a capacitor 903 connected in series between the positive electrode and the negative electrode of the DC power supply 102. In the second optimization method, the resistance value RS of the resistor 901, the inductance L of the inductor 902, and the capacitor 903 that match (fit) the voltage waveform during the period when the output 140 is connected to the positive electrode of the DC power supply device 102. Capacitance C is required. Then, a resistance value R satisfying the following equation (1) is obtained. When equation (1) is satisfied, ringing does not occur.
CR 2 / (4L) = 1 ... (1)
Then, R-R S -R i is determined as the resistance value of the first damping resistor 110r. R i is the internal resistance value of the DC power supply device 102.
　また、第２の最適化方法では、出力１４０が直流電源装置１０２の負極に接続されている期間の電圧波形に適合する抵抗９０１の抵抗値ＲＳ、インダクタ９０２のインダクタンスＬ、及びコンデンサ９０３の静電容量Ｃが求められる。そして、式（１）を満たす抵抗値Ｒが求められる。そして、Ｒ－ＲＳ－Ｒｉが、第２のダンピング抵抗１２０ｒの抵抗値として決定される。 In the second optimization method, the resistance value RS of the resistor 901 matching the voltage waveform during the period when the output 140 is connected to the negative electrode of the DC power supply device 102, the inductance L of the inductor 902, and the static of the capacitor 903. The electric capacity C is required. Then, a resistance value R satisfying the equation (1) is obtained. Then, R-R S -R i is determined as the resistance value of the second damping resistor 120r.
　電源システム１００として電源システム１００Ｄが用いられる場合には、出力１４０がグランドに接続されている期間における電圧波形に適合する抵抗９０１の抵抗値ＲＳ、インダクタ９０２のインダクタンスＬ、及びコンデンサ９０３の静電容量Ｃが求められる。そして、式（１）を満たす抵抗値Ｒが求められる。そして、Ｒ－ＲＳ－Ｒｉが、第３のダンピング抵抗１３０ｒの抵抗値として決定される。 When the power supply system 100D is used as the power supply system 100, the resistance value RS of the resistor 901 matching the voltage waveform while the output 140 is connected to the ground, the inductance L of the inductor 902, and the capacitance of the capacitor 903. Capacity C is required. Then, a resistance value R satisfying the equation (1) is obtained. Then, R-R S -R i is determined as the resistance value of the third damping resistor 130r.
　次いで、出力１４０が直流電源装置１０２の正極に接続されている期間におけるリンギングの量が許容量よりも大きくならないように、第１のインダクタ１１０ｉの最小のインダクタンスが決定される。また、出力１４０が直流電源装置１０２の負極に接続されている期間におけるリンギングの量が許容量よりも大きくならないように、第２のインダクタ１２０ｉの最小のインダクタンスが決定される。電源システム１００として電源システム１００Ｄが用いられている場合には、出力１４０がグランドに接続されている期間におけるリンギングの量が許容量よりも大きくならないように、第３のインダクタ１３０ｉの最小のインダクタンスが決定される。 Next, the minimum inductance of the first inductor 110i is determined so that the amount of ringing during the period when the output 140 is connected to the positive electrode of the DC power supply device 102 does not become larger than the allowable amount. Further, the minimum inductance of the second inductor 120i is determined so that the amount of ringing during the period in which the output 140 is connected to the negative electrode of the DC power supply device 102 does not become larger than the allowable amount. When the power supply system 100D is used as the power supply system 100, the minimum inductance of the third inductor 130i is set so that the amount of ringing during the period when the output 140 is connected to the ground does not become larger than the allowable amount. It is determined.
　以下、第３の最適化方法について説明する。第３の最適化手法では、インピーダンスモニタ装置が、電源システム１００の出力１４０とこの出力１４０が接続される電極（上部電極３０又は下部電極１８）との間に接続される。そして、第３の最適化方法では、電源システム１００の回路素子パラメータは、インピーダンスモニタ装置によって測定されたインピーダンス値に応じて、オーバーシュートを抑制するように決定される。 The third optimization method will be described below. In the third optimization method, the impedance monitoring device is connected between the output 140 of the power supply system 100 and the electrode (upper electrode 30 or lower electrode 18) to which the output 140 is connected. Then, in the third optimization method, the circuit element parameter of the power supply system 100 is determined to suppress the overshoot according to the impedance value measured by the impedance monitoring device.
　以上、種々の例示的実施形態について説明してきたが、上述した例示的実施形態に限定されることなく、様々な追加、省略、置換、及び変更がなされてもよい。また、異なる実施形態における要素を組み合わせて他の実施形態を形成することが可能である。 Although various exemplary embodiments have been described above, various additions, omissions, substitutions, and changes may be made without being limited to the above-mentioned exemplary embodiments. It is also possible to combine elements in different embodiments to form other embodiments.
　上述した種々の例示的実施形態のうち何れかの電源システムを備えるプラズマ処理装置は、容量結合型のプラズマ処理装置に限定されない。種々の例示的実施形態のうち何れかの電源システムを備えるプラズマ処理装置は、他のタイプのプラズマ処理装置であってもよい。他のタイプのプラズマ処理装置は、例えば誘導結合型のプラズマ処理装置、電子サクロトン共鳴（ＥＣＲ）プラズマ処理装置、又はマイクロ波といった表面波によりプラズマを生成するプラズマ処理装置である。 The plasma processing apparatus including any of the various exemplary embodiments described above is not limited to the capacitive coupling type plasma processing apparatus. The plasma processing apparatus including any of the various exemplary embodiments may be another type of plasma processing apparatus. Other types of plasma processing devices are, for example, inductively coupled plasma processing devices, electron sacroton resonance (ECR) plasma processing devices, or plasma processing devices that generate plasma by surface waves such as microwaves.
　以上の説明から、本開示の種々の実施形態は、説明の目的で本明細書で説明されており、本開示の範囲及び主旨から逸脱することなく種々の変更をなし得ることが、理解されるであろう。したがって、本明細書に開示した種々の実施形態は限定することを意図しておらず、真の範囲と主旨は、添付の特許請求の範囲によって示される。 From the above description, it is understood that the various embodiments of the present disclosure are described herein for purposes of explanation and that various modifications can be made without departing from the scope and gist of the present disclosure. Will. Accordingly, the various embodiments disclosed herein are not intended to be limiting, and the true scope and gist is set forth by the appended claims.
　１Ａ，１Ｂ，１Ｃ…プラズマ処理装置、１０…チャンバ、１６…基板支持部、１８…下部電極、３０…上部電極、１００，１００Ａ，１００Ｂ，１００Ｃ，１００Ｄ…電源システム、１０２…直流電源装置、１１０…第１の並列回路、１１０ｒ…第１のダンピング抵抗、１１０ｉ…第１のインダクタ、１１１，１１２…ノード、１１５…第１のスイッチ、１２０…第２の並列回路、１２０ｒ…第２のダンピング抵抗、１２０ｉ…第２のインダクタ、１２１，１２２…ノード、１２５…第２のスイッチ、１４０…出力。 1A, 1B, 1C ... Plasma processing device, 10 ... Chamber, 16 ... Substrate support, 18 ... Lower electrode, 30 ... Upper electrode, 100, 100A, 100B, 100C, 100D ... Power supply system, 102 ... DC power supply, 110 ... 1st parallel circuit, 110r ... 1st damping resistor, 110i ... 1st inductor, 111, 112 ... node, 115 ... 1st switch, 120 ... 2nd parallel circuit, 120r ... 2nd damping resistor , 120i ... second inductor, 121, 122 ... node, 125 ... second switch, 140 ... output.

Claims (9)

  1. 　直流電源装置と、
    　第１のノード、第２のノード、並びに、該第１のノードと該第２のノードとの間で並列に接続された第１のダンピング抵抗及び第１のインダクタを含む第１の並列回路と、
    　前記直流電源装置の正極と前記第１のノードとの間で接続された第１のスイッチと、
    　第３のノード、第４のノード、並びに、該第３のノードと該第４のノードとの間で並列に接続された第２のダンピング抵抗及び第２のインダクタを含む第２の並列回路と、
    　前記直流電源装置の負極と前記第３のノードとの間で接続された第２のスイッチと、
    　前記第２のノードと前記第４のノードとに接続された出力と、
    を備える電源システム。     DC power supply and
    With a first node, a second node, and a first parallel circuit including a first damping resistor and a first inductor connected in parallel between the first node and the second node. ,
    A first switch connected between the positive electrode of the DC power supply device and the first node,
    With a third node, a fourth node, and a second parallel circuit including a second damping resistor and a second inductor connected in parallel between the third node and the fourth node. ,
    A second switch connected between the negative electrode of the DC power supply device and the third node,
    The output connected to the second node and the fourth node,
    Power system with.
  2. 　前記直流電源装置の前記正極はグランドに接続されている、請求項１に記載の電源システム。 The power supply system according to claim 1, wherein the positive electrode of the DC power supply device is connected to the ground.
  3. 　前記直流電源装置は、第１の直流電源及び第２の直流電源を含み、
    　前記第１の直流電源の負極は、前記直流電源装置の前記負極を構成し、
    　前記第１の直流電源の正極及び前記第２の直流電源の負極は、グランドに接続されており、
    　前記第２の直流電源の正極は、前記直流電源装置の前記正極を構成する、
    請求項１に記載の電源システム。     The DC power supply includes a first DC power supply and a second DC power supply.
    The negative electrode of the first DC power supply constitutes the negative electrode of the DC power supply device.
    The positive electrode of the first DC power supply and the negative electrode of the second DC power supply are connected to the ground.
    The positive electrode of the second DC power supply constitutes the positive electrode of the DC power supply device.
    The power supply system according to claim 1.
  4. 　第５のノード、前記出力に接続された第６のノード、並びに、該第５のノードと該第６のノードとの間で並列に接続された第３のダンピング抵抗及び第３のインダクタを含む第３の並列回路と、
    　前記グランドと前記第５のノードとの間で接続された第３のスイッチと、
    を更に備える、請求項３に記載の電源システム。     Includes a fifth node, a sixth node connected to the output, and a third damping resistor and third inductor connected in parallel between the fifth node and the sixth node. With the third parallel circuit,
    A third switch connected between the ground and the fifth node,
    3. The power supply system according to claim 3.
  5. 　前記第１の並列回路は、前記第１のダンピング抵抗に接続されたアノード及び前記第２のノードに接続されたカソードを有する第１のダイオードを更に含み、
    　前記第２の並列回路は、前記第４のノードに接続されたアノード及び前記第２のダンピング抵抗に接続されたカソードを有する第２のダイオードを更に含む、
    請求項３又は４に記載の電源システム。     The first parallel circuit further includes a first diode having an anode connected to the first damping resistor and a cathode connected to the second node.
    The second parallel circuit further includes a second diode having an anode connected to the fourth node and a cathode connected to the second damping resistor.
    The power supply system according to claim 3 or 4.
  6. 　前記直流電源装置の前記負極に接続されたアノード及び前記第１のノードに接続されたカソードを有するダイオードと、
    　前記直流電源装置の前記正極に接続されたカソード及び前記第２のノードに接続されたアノードを有するダイオードと、
    を更に備える、請求項３～５の何れか一項に記載の電源システム。     A diode having an anode connected to the negative electrode of the DC power supply device and a cathode connected to the first node,
    A diode having a cathode connected to the positive electrode of the DC power supply and an anode connected to the second node,
    The power supply system according to any one of claims 3 to 5, further comprising.
  7. 　前記第１のスイッチ及び前記第２のスイッチが交互に導通状態になるよう該第１のスイッチ及び該第２のスイッチを制御するように構成された制御部を更に備える、請求項１～６の何れか一項に記載の電源システム。 Claims 1 to 6, further comprising a control unit configured to control the first switch and the second switch so that the first switch and the second switch are alternately conducted in a conductive state. The power supply system described in any one of the items.
  8. 　　前記第１のスイッチを導通状態に設定し、前記第２のスイッチ及び前記第３のスイッチを非導通状態に設定する制御と、
    　　前記第３のスイッチを導通状態に設定し、前記第１のスイッチ及び前記第２のスイッチを非導通状態に設定する制御と、
    　　前記第２のスイッチを導通状態に設定し、前記第１のスイッチ及び前記第３のスイッチを非導通状態に設定する制御と、
    　を実行するように構成された制御部を更に備える、請求項４に記載の電源システム。     Control to set the first switch to the conductive state and set the second switch and the third switch to the non-conducting state.
    Control to set the third switch to the conductive state and set the first switch and the second switch to the non-conducting state.
    Control to set the second switch to the conductive state and set the first switch and the third switch to the non-conducting state, and
    4. The power supply system according to claim 4, further comprising a control unit configured to perform the above.
  9. 　チャンバと、
    　前記チャンバ内で基板を支持するように構成された基板支持部と、
    　電極と、
    　請求項１～８の何れか一項に記載の電源システムであり、前記チャンバ内でプラズマを生成するため又は前記チャンバ内のプラズマから前記基板支持部によって支持された基板にイオンを引き込むために、前記電極に電気的に接続された、該電源システムと、
    を備えるプラズマ処理装置。     With the chamber
    A substrate support portion configured to support the substrate in the chamber,
    With electrodes
    The power supply system according to any one of claims 1 to 8, for generating plasma in the chamber or for drawing ions from the plasma in the chamber to a substrate supported by the substrate support. With the power supply system electrically connected to the electrodes,
    A plasma processing device equipped with.
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