WO2021230617A1 - Power module - Google Patents

Power module Download PDF

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Publication number
WO2021230617A1
WO2021230617A1 PCT/KR2021/005876 KR2021005876W WO2021230617A1 WO 2021230617 A1 WO2021230617 A1 WO 2021230617A1 KR 2021005876 W KR2021005876 W KR 2021005876W WO 2021230617 A1 WO2021230617 A1 WO 2021230617A1
Authority
WO
WIPO (PCT)
Prior art keywords
ceramic substrate
terminal
electrode pattern
bus bar
power module
Prior art date
Application number
PCT/KR2021/005876
Other languages
French (fr)
Korean (ko)
Inventor
김종욱
Original Assignee
주식회사 아모센스
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Filing date
Publication date
Application filed by 주식회사 아모센스 filed Critical 주식회사 아모센스
Publication of WO2021230617A1 publication Critical patent/WO2021230617A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447Lead-in-hole components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Definitions

  • the present invention relates to a power module, and more particularly, to a power module having improved performance by applying a high output power semiconductor chip.
  • the power module is used to supply high voltage current to drive motors such as hybrid vehicles and electric vehicles.
  • the double-sided cooling power module has a substrate on top and a bottom of a semiconductor chip, respectively, and a heat sink on an outer surface of the substrate, respectively.
  • the double-sided cooling power module has an excellent cooling performance compared to a single-sided cooling power module having a heat sink on one side, and thus its use is gradually increasing.
  • the double-sided cooling power module used in electric vehicles, etc. has a power semiconductor chip such as silicon carbide (SiC) and gallium nitride (GaN) mounted between the two substrates. It is important to satisfy both high strength and high heat dissipation characteristics at the same time.
  • An object of the present invention is to provide a power module that has high strength and high heat dissipation characteristics, has excellent bonding characteristics, can reduce a volume by minimizing a current path, and can improve efficiency and performance.
  • Another object of the present invention is to provide a power module in which resistance is as low as possible and heat generation is minimized by applying a bus bar having a structure that passes a low resistance of a large current or voltage.
  • Another object of the present invention is to provide a power module maximizing the flexibility of a bus bar.
  • Another object of the present invention is to connect both sides of a bus bar to a terminal and an electrode pattern (metal layer) of a ceramic substrate to improve bonding performance and apply a laser welding method to implement a structure for passing large current and voltage. to provide a module.
  • the power module of the present invention includes a ceramic substrate including a ceramic substrate and electrode patterns formed on upper and lower surfaces of the ceramic substrate, and the ceramic substrate is installed at both ends. It includes a housing in which the terminals are disposed, and a bus bar connecting the electrode pattern of the ceramic substrate and the terminal face-to-face.
  • the bus bar may be a copper ribbon having a predetermined area.
  • the bus bar may include a laser welding region bonded to the terminal and a laser on one side and a laser welding region bonded to the electrode pattern and a laser on the other side of the bus bar.
  • an area of a laser welding region bonded to the terminal and a laser may be relatively larger than an area of a laser welding region bonded to the electrode pattern and a laser.
  • the busbar may have a curved structure.
  • the busbar may have a thickness ranging from 0.1 mm to 0.5 mm.
  • the electrode pattern includes a first electrode pattern, a second electrode pattern, and a third electrode pattern
  • the terminal includes a first terminal and a second terminal
  • the bus bar connects the first terminal and the first electrode pattern
  • the first terminal and the third electrode pattern may be connected, and three for connecting the second terminal and the second electrode pattern may be included.
  • the bus bar may have a through slot formed therein.
  • the bus bar includes a first laser welding region bonded to the terminal and a laser on one side and a second laser welding region bonded to the electrode pattern and a laser on the opposite side on the other side, and the through slot includes the first laser welding region and the first laser welding region. It may be formed between two laser welding regions.
  • a plurality of through slots may be formed at regular intervals in the horizontal or vertical direction.
  • the bus bar may be formed to have a relatively high height on the other side compared to one side and to be curved.
  • the bus bar may be formed so that an intermediate portion connecting one side and the other side is curved.
  • the bus bar may be respectively bonded to the terminal and the electrode pattern of the ceramic substrate by laser welding.
  • Laser welding may be formed in a zigzag pattern shape.
  • the present invention has high strength and high heat dissipation characteristics, has excellent bonding characteristics, can reduce a volume by minimizing a current path, and is optimized for high-speed switching to improve efficiency and performance.
  • the present invention has an effect of lowering the resistance as much as possible and minimizing heat generation by applying a bus bar having a structure that passes a low resistance of a large current or voltage.
  • the present invention has the effect of maximizing the bondability of the bus bar by using the laser welding method, and simplifying the process of connecting the bus bar to the terminal and the electrode pattern.
  • the present invention has the effect of maximizing the flexibility of the bus bar even when a relatively thick copper ribbon is applied, thereby preventing deterioration and damage of the copper ribbon due to torsion or vibration between connection parts, and external impact.
  • the present invention has the effect of maximizing the bonding performance by applying a large-area laser welding method to connect both sides of the bus bar to the terminal and the electrode pattern (metal layer) of the ceramic substrate.
  • the present invention performs laser welding in a zigzag pattern shape, a large junction area is secured and a structure that passes a low resistance of a large current or voltage is implemented, while the resistance can be lowered to the maximum and heat generation can be minimized. .
  • FIG. 1 is a perspective view of a power module according to an embodiment of the present invention.
  • FIG. 2 is an exploded perspective view of a power module according to an embodiment of the present invention.
  • FIG 3 is a side cross-sectional view of a power module according to an embodiment of the present invention.
  • FIG. 4 is a perspective view showing a housing according to an embodiment of the present invention.
  • FIG. 5 is a perspective view showing a lower ceramic substrate according to an embodiment of the present invention.
  • FIG. 6 is a view showing an upper surface and a lower surface of a lower ceramic substrate according to an embodiment of the present invention.
  • FIG. 7 is a perspective view showing an upper ceramic substrate according to an embodiment of the present invention.
  • FIG. 8 is a view showing an upper surface and a lower surface of an upper ceramic substrate according to an embodiment of the present invention.
  • FIG. 9 is a plan view of a PCB substrate according to an embodiment of the present invention.
  • connection pin and a bus bar are installed on an upper ceramic substrate according to an embodiment of the present invention.
  • FIG. 11 is a perspective view showing a bus bar according to an embodiment of the present invention.
  • FIG. 12 is a photograph showing a laser welding area of a bus bar according to an embodiment of the present invention.
  • FIG. 13 is a side cross-sectional view illustrating a state in which a bus bar connects a terminal and an electrode pattern according to an embodiment of the present invention.
  • FIG. 14 is a perspective view showing a bus bar according to another embodiment of the present invention.
  • 15 is a cross-sectional view showing a bus bar connecting a terminal and a metal layer of a ceramic substrate according to an embodiment of the present invention.
  • 16 is a perspective view illustrating a shape of a bus bar according to an embodiment of the present invention.
  • 17 is a diagram of a bus bar for explaining a laser welding shape according to an embodiment of the present invention.
  • G semiconductor chip (GaN chip)
  • FIG. 1 is a perspective view of a power module according to an embodiment of the present invention
  • FIG. 2 is an exploded perspective view of a power module according to an embodiment of the present invention.
  • the power module 10 is an electronic component in the form of a package formed by accommodating various components constituting the power module in a housing 100 .
  • the power module 10 is formed in a form to protect by arranging a substrate and elements in the housing 100 .
  • the power module 10 may include a plurality of substrates and a plurality of semiconductor chips.
  • the power module 10 according to the embodiment includes a housing 100 , a lower ceramic substrate 200 , an upper ceramic substrate 300 , a PCB substrate 400 , and a heat sink 500 .
  • the housing 100 has an empty space that is opened vertically in the center, and the first terminal 610 and the second terminal 620 are positioned on both sides.
  • a heat sink 500, a lower ceramic substrate 200, an upper ceramic substrate 300, and a PCB substrate 400 are sequentially stacked at regular intervals up and down in the empty space in the center, and the first terminals on both sides
  • a support bolt 630 for connecting the external terminal to the 610 and the second terminal 620 is fastened.
  • the first terminal 610 and the second terminal 620 are used as input/output terminals of power.
  • the lower ceramic substrate 200 , the upper ceramic substrate 300 , and the PCB substrate 400 are sequentially accommodated in an empty space in the center of the housing 100 .
  • the heat sink 500 is disposed on the lower surface of the housing 100
  • the lower ceramic substrate 200 is attached to the upper surface of the heat sink 500
  • the upper ceramic substrate 300 is on the upper side of the lower ceramic substrate 200.
  • the PCB substrate 400 is arranged at a predetermined interval on the upper ceramic substrate 300 .
  • the state in which the PCB substrate 400 is disposed in the housing 100 is the guide grooves 401 and 402 formed to be recessed into the edge of the PCB substrate 400 and the guide ribs 101 formed in the housing 100 to correspond to the guide grooves 401 and 402 .
  • the locking jaw 102 may be fixed.
  • a plurality of guide grooves 401 and 402 are formed around the edge of the PCB substrate 400 according to the embodiment, and some of the guide grooves 401 are guided by the guide rib 101 formed on the inner surface of the housing 100 . and the guide groove 402 of the remaining part of them is hung through the locking protrusion 102 formed on the inner surface of the housing 100 .
  • the heat sink 500, the lower ceramic substrate 200, and the upper ceramic substrate 300 are accommodated in the empty space in the center of the housing 100, and the state in which the PCB substrate 400 is disposed on the upper surface is a fastening bolt ( (not shown) may be fixed.
  • a fastening bolt (not shown)
  • fixing the PCB substrate 400 to the housing 100 with a guide groove and a clasp structure reduces the assembly time and simplifies the assembly process compared to the case of fixing with a fastening bolt.
  • the housing 100 has fastening holes 103 formed at four corners.
  • the fastening hole 103 communicates with the communication hole 501 formed in the heat sink 500 .
  • the fixing bolt 150 is fastened through the fastening hole 103 and the communication hole 501 , and the end of the fixing bolt 150 passing through the fastening hole 103 and the communication hole 501 is the heat sink 500 . It may be fastened to a fixing hole of a fixing jig to be disposed on the lower surface.
  • the bus bar 700 is connected to the first terminal 610 and the second terminal 620 .
  • the bus bar 700 connects the first terminal 610 and the second terminal 620 to the upper ceramic substrate 300 .
  • Three bus bars 700 are provided.
  • One of the bus bars 700 connects the + terminal of the first terminals 610 to the first electrode pattern a of the upper ceramic substrate 300 , and the other connects the - terminal among the first terminals 610 . It is connected to the three electrode pattern (c), and the other one connects the second terminal 620 to the second electrode pattern (b).
  • the first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c) will be described later with reference to FIGS. 7 and 10 .
  • FIG 3 is a side cross-sectional view of a power module according to an embodiment of the present invention.
  • the power module 10 has a multilayer structure of a lower ceramic substrate 200 and an upper ceramic substrate 300 , and a semiconductor chip between the lower ceramic substrate 200 and the upper ceramic substrate 300 .
  • the semiconductor chip (G) is any one of GaN (Gallium Nitride) chip, MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), JFET (Junction Field Effect Transistor), HEMT (High Electric Mobility Transistor) However, preferably, the semiconductor chip (G) uses a GaN chip.
  • the GaN (Gallium Nitride) chip is a semiconductor chip that functions as a high-power (300A) switch and a high-speed ( ⁇ 1MHz) switch.
  • the GaN chip has the advantage of being stronger in heat than the existing silicon-based semiconductor chip and reducing the size of the chip.
  • the lower ceramic substrate 200 and the upper ceramic substrate 300 are formed of a ceramic substrate including a metal layer brazed to at least one surface of the ceramic substrate and the ceramic substrate to increase the heat dissipation efficiency of the heat generated from the semiconductor chip (G). do.
  • the ceramic substrate may be, for example, any one of alumina (Al 2 O 3 ), AlN, SiN, and Si 3 N 4 .
  • the metal layer is formed of an electrode pattern for mounting a semiconductor chip (G) and an electrode pattern for mounting a driving element, respectively, with a metal foil brazed on a ceramic substrate.
  • the metal layer is formed as an electrode pattern in a region where a semiconductor chip or peripheral components are to be mounted.
  • the metal foil may be an aluminum foil or a copper foil as an example.
  • the metal foil is fired at 780° C. to 1100° C. on a ceramic substrate and brazed to the ceramic substrate.
  • Such a ceramic substrate is called an AMB substrate.
  • AMB substrate As an example, a DBC substrate, a TPC substrate, and a DBA substrate may be applied. However, in terms of durability and heat dissipation efficiency, AMB substrates are most suitable. For the above reasons, the lower ceramic substrate 200 and the upper ceramic substrate 300 are AMB substrates as an example.
  • the PCB substrate 400 is disposed on the upper ceramic substrate 300 . That is, the power module 10 has a three-layer structure of a lower ceramic substrate 200 , an upper ceramic substrate 300 , and a PCB substrate 400 .
  • the semiconductor chip (G) for high power control is disposed between the upper ceramic substrate 200 and the lower ceramic substrate 300 to increase heat dissipation efficiency, and the PCB substrate 400 for low power control is disposed on the uppermost portion of the semiconductor Prevents damage to the PCB substrate 400 due to the heat generated in the chip (G).
  • the lower ceramic substrate 200 , the upper ceramic substrate 300 , and the PCB substrate 400 may be connected or fixed with pins.
  • the heat sink 500 is disposed under the lower ceramic substrate 200 .
  • the heat sink 500 is for dissipating heat generated from the semiconductor chip (G).
  • the heat sink 500 is formed in a rectangular plate shape having a predetermined thickness.
  • the heat sink 500 is formed in an area corresponding to the housing 100 and may be formed of copper or aluminum to increase heat dissipation efficiency.
  • FIG. 4 is a perspective view showing a housing according to an embodiment of the present invention.
  • an empty space is formed in the center of the housing 100 , and a first terminal 610 and a second terminal 620 are positioned at both ends.
  • the housing 100 may be formed by an insert injection method such that the first terminal 610 and the second terminal 620 are integrally fixed at both ends.
  • the housing 100 has fastening holes 103 formed at four corners.
  • the fastening hole 103 communicates with the communication hole 501 formed in the heat sink 500 .
  • a support hole 104 is formed in the first terminal 610 and the second terminal 620 .
  • a support bolt 630 for connecting the first terminal 610 and the second terminal 620 to an external terminal such as a motor is fastened to the support hole 104 (see FIG. 10 ).
  • the housing 100 is formed of a heat insulating material.
  • the housing 100 may be formed of a heat insulating material so that heat generated from the semiconductor chip G is not transferred to the PCB substrate 400 above through the housing 100 .
  • the housing 100 may be made of a heat-dissipating plastic material.
  • the housing 100 may be formed of a heat-dissipating plastic material so that heat generated from the semiconductor chip G can be radiated to the outside through the housing 100 .
  • the housing 100 may be formed of engineering plastic.
  • Engineering plastics have high heat resistance, excellent strength, chemical resistance and abrasion resistance, and can be used for a long time at 150°C or higher.
  • the engineering plastic may be made of one of polyamide, polycarbonate, polyester, and modified polyphenylene oxide.
  • the semiconductor chip (G) operates repeatedly as a switch, which causes the housing 100 to be stressed by high temperature and temperature changes. It also has excellent heat dissipation properties.
  • the housing 100 may be manufactured by insert-injecting a terminal made of aluminum or copper to an engineering plastic material.
  • the housing 100 made of an engineering plastic material radiates heat to the outside by propagating heat.
  • the housing 100 may be made of a high heat dissipation engineering plastic that may have higher thermal conductivity than a general engineering plastic material and is lightweight compared to aluminum by filling the resin with a high thermal conductivity filler.
  • the housing 100 may have heat dissipation properties by applying a graphene heat dissipation coating material to the inside and outside of an engineering plastic or high-strength plastic material.
  • FIG. 5 is a perspective view showing a lower ceramic substrate according to an embodiment of the present invention.
  • the lower ceramic substrate 200 is attached to the upper surface of the heat sink 500 .
  • the lower ceramic substrate 200 is disposed between the semiconductor chip G and the heat sink 500 .
  • the lower ceramic substrate 200 transfers heat generated from the semiconductor chip G to the heat sink 500 and insulates between the semiconductor chip G and the heat sink 500 to prevent a short circuit.
  • the lower ceramic substrate 200 may be soldered to the upper surface of the heat sink 500 .
  • the heat sink 500 is formed in an area corresponding to the housing 100 and may be formed of a copper material to increase heat dissipation efficiency.
  • As a solder for soldering joint SnAg, SnAgCu, etc. may be used.
  • FIG. 6 is a view showing an upper surface and a lower surface of a lower ceramic substrate according to an embodiment of the present invention.
  • the lower ceramic substrate 200 includes a ceramic substrate 201 and metal layers 202 and 203 brazed to upper and lower surfaces of the ceramic substrate 201 .
  • the thickness of the ceramic substrate 201 may be 0.68 t
  • the thickness of the metal layers 202 and 203 formed on the upper and lower surfaces of the ceramic substrate 201 may be 0.8 t.
  • the metal layer 202 of the upper surface 200a of the lower ceramic substrate 200 may be an electrode pattern on which a driving element is mounted.
  • the driving device mounted on the lower ceramic substrate 200 may be the NTC temperature sensor 210 .
  • the NTC temperature sensor 210 is mounted on the upper surface of the lower ceramic substrate 200 .
  • the NTC temperature sensor 210 is for providing temperature information in the power module due to heat generation of the semiconductor chip G.
  • the metal layer 203 of the lower surface 200b of the lower ceramic substrate 200 may be formed on the entire lower surface of the lower ceramic substrate 200 to facilitate heat transfer to the heat sink 500 .
  • An insulating spacer 220 is bonded to the lower ceramic substrate 200 .
  • the insulating spacer 220 is bonded to the upper surface of the lower ceramic substrate 200 and defines a separation distance between the lower ceramic substrate 200 and the upper ceramic substrate 300 .
  • the insulating spacer 220 defines the separation distance between the lower ceramic substrate 200 and the upper ceramic substrate 300 to increase the heat dissipation efficiency of the heat generated by the semiconductor chip G mounted on the lower surface of the upper ceramic substrate 300, Interference between the semiconductor chips G is prevented to prevent an electric shock such as a short circuit.
  • a plurality of insulating spacers 220 are bonded to each other at predetermined intervals around the upper surface edge of the lower ceramic substrate 200 .
  • a gap between the insulating spacers 220 is used as a space to increase heat dissipation efficiency.
  • the insulating spacers 220 are arranged around the edge of the lower ceramic substrate 200 as a reference, and for example, eight insulating spacers 220 are arranged at regular intervals.
  • the insulating spacer 220 is integrally bonded to the lower ceramic substrate 200 .
  • the insulating spacer 220 may be applied to check alignment when the upper ceramic substrate 300 is disposed on the lower ceramic substrate 200 .
  • the insulating spacer 220 is formed on the upper ceramic substrate 300 .
  • the insulating spacer 220 supports the lower ceramic substrate 200 and the upper ceramic substrate 300 , thereby contributing to preventing bending of the lower ceramic substrate 200 and the upper ceramic substrate 300 .
  • the insulating spacer 220 may be formed of a ceramic material for insulation between the chip mounted on the lower ceramic substrate 200 and the chip and the component mounted on the upper ceramic substrate 300 .
  • the insulating spacer may be formed of one selected from Al 2 O 3 , ZTA, Si 3 N 4 , and AlN, or an alloy in which two or more thereof are mixed.
  • Al 2 O 3 , ZTA, Si 3 N 4 , and AlN are insulating materials having excellent mechanical strength and heat resistance.
  • the insulating spacer 220 is brazed to the lower ceramic substrate 200 .
  • the substrate may be damaged due to thermal and mechanical shock during soldering or pressure firing, so that it is bonded by brazing.
  • a brazing bonding layer including an AgCu layer and a Ti layer may be used for the brazing bonding. Heat treatment for brazing can be performed at 780°C to 900°C.
  • the insulating spacer 220 is integrally formed with the metal layer 202 of the lower ceramic substrate 200 .
  • the thickness of the brazing bonding layer is 0.005 mm to 0.08 mm, which is thin enough not to affect the height of the insulating spacer, and the bonding strength is high.
  • An interconnection spacer 230 is installed between the lower ceramic substrate 200 and the upper ceramic substrate 300 .
  • the interconnection spacer 230 may perform electrical connection between electrode patterns in place of a connection pin in a substrate having an upper and lower multilayer structure.
  • the interconnection spacer 230 may directly connect between substrates while preventing electrical loss and short circuit, increase bonding strength, and improve electrical characteristics.
  • One end of the interconnection spacer 230 may be bonded to the electrode pattern of the lower ceramic substrate 200 by a brazing bonding method.
  • the other end of the interconnection spacer 230 may be bonded to the electrode pattern of the upper ceramic substrate 300 by a brazing bonding method or a soldering bonding method.
  • the interconnection spacer 230 may be Cu or a Cu+CuMo alloy.
  • FIG. 7 is a perspective view showing an upper ceramic substrate according to an embodiment of the present invention
  • FIG. 8 is a view showing an upper surface and a lower surface of the upper ceramic substrate according to an embodiment of the present invention.
  • the upper ceramic substrate 300 is disposed on the lower ceramic substrate 200 .
  • the upper ceramic substrate 300 is an intermediate substrate having a stacked structure.
  • the upper ceramic substrate 300 has a semiconductor chip (G) mounted on its lower surface, and constitutes a high-side circuit and a low-side circuit for high-speed switching.
  • G semiconductor chip
  • the upper ceramic substrate 300 includes a ceramic substrate 301 and metal layers 302 and 303 brazed to upper and lower surfaces of the ceramic substrate 301 .
  • the thickness of the ceramic substrate is 0.38t and the thickness of the electrode pattern on the upper surface 300a and the lower surface 300b of the ceramic substrate is 0.3t as an example.
  • the ceramic substrate must have the same pattern thickness on the upper and lower surfaces to prevent distortion during brazing.
  • the electrode pattern formed by the metal layer 302 on the upper surface of the upper ceramic substrate 300 is divided into a first electrode pattern (a), a second electrode pattern (b), and a third electrode pattern (c).
  • the electrode pattern formed by the metal layer 303 on the lower surface of the upper ceramic substrate 300 corresponds to the electrode pattern formed by the metal layer 302 on the upper surface of the upper ceramic substrate 300 .
  • the division of the electrode pattern on the upper surface of the upper ceramic substrate 300 into a first electrode pattern (a), a second electrode pattern (b), and a third electrode pattern (c) is a high-side circuit for high-speed switching. and to separate the low-side circuit.
  • the semiconductor chip G is provided in the form of a flip chip by an adhesive layer such as solder or silver paste on the lower surface 300b of the upper ceramic substrate 300 .
  • an adhesive layer such as solder or silver paste
  • two semiconductor chips G may be connected in parallel for high-speed switching.
  • Two semiconductor chips (G) are disposed at positions connecting the first electrode pattern (a) and the second electrode pattern (b) among the electrode patterns of the upper ceramic substrate 300, and the other two are the second electrode patterns (b). ) and the third electrode pattern (c) are arranged in parallel at a position connecting it.
  • the capacity of one semiconductor chip G is 150A. Therefore, two semiconductor chips (G) are connected in parallel so that the capacity becomes 300A.
  • the semiconductor chip G is a GaN chip.
  • the purpose of the power module using the semiconductor chip G is high-speed switching.
  • the gate drive IC terminal be connected by a very short distance between the gate terminal of the semiconductor chip (G). Therefore, the connection distance between the gate drive IC and the gate terminal is minimized by connecting the semiconductor chips G in parallel.
  • the gate terminal and the source terminal of the semiconductor chip G may be disposed such that the connection pin is connected to the center between the semiconductor chip G and the semiconductor chip G. If the gate terminal and the source terminal do not keep the same distance or the length of the pattern is different, a problem occurs.
  • the gate terminal is a terminal for turning on/off the semiconductor chip G by using a low voltage.
  • the gate terminal may be connected to the PCB substrate 400 through a connection pin.
  • Source terminal is a terminal for high current to enter and exit.
  • the semiconductor chip G includes a drain terminal, and the source terminal and the drain terminal are divided into N-type and P-type so that the direction of the current can be changed.
  • the source terminal and the drain terminal are responsible for input and output of current through the first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c), which are electrode patterns for mounting the semiconductor chip (G).
  • the source terminal and the drain terminal are connected to the first terminal 610 and the second terminal 620 of FIG. 1 in charge of input and output of power.
  • the first terminal 610 shown in FIG. 1 includes a + terminal and a - terminal, and power introduced from the first terminal 610 to the + terminal is the upper portion shown in FIG. 8 .
  • the semiconductor chip (G) and the second electrode pattern (b) disposed between the first electrode pattern (a) and the second electrode pattern (b) 2 is output to the terminal 620 .
  • the power supplied to the second terminal 620 shown in FIG. 1 is disposed between the second electrode pattern (b), the second electrode pattern (b) and the third electrode pattern (c) shown in FIG. 8 . It is output to the - terminal of the first terminal 610 through the semiconductor chip G and the third electrode pattern c.
  • the upper ceramic substrate 300 may have a cutting part 310 formed in a portion corresponding to the NTC temperature sensor 210 .
  • An NTC temperature sensor 210 is mounted on the upper surface of the lower ceramic substrate 200 .
  • the NTC temperature sensor 210 is for providing temperature information in the power module due to heat generation of the semiconductor chip G.
  • the thickness of the NTC temperature sensor 210 is thicker than the gap between the lower ceramic substrate 200 and the upper ceramic substrate 300 , interference between the NTC temperature sensor 210 and the upper ceramic substrate 300 occurs.
  • the upper ceramic substrate 300 of the portion that interferes with the NTC temperature sensor 210 is cut to form a cutting portion 310 .
  • a silicone liquid or epoxy for molding may be injected into the space between the upper ceramic substrate 300 and the lower ceramic substrate 200 through the cutting part 310 .
  • silicone liquid or epoxy In order to insulate between the upper ceramic substrate 300 and the lower ceramic substrate 200, silicone liquid or epoxy must be injected.
  • one side of the upper ceramic substrate 300 may be cut to form a cutting part 310, and the cutting part 310 may be formed. is formed at a position corresponding to the NTC temperature sensor 210 to prevent interference between the upper ceramic substrate 300 and the NTC temperature sensor 210 .
  • Silicon liquid or epoxy is used in the space between the lower ceramic substrate 200 and the upper ceramic substrate 300 and the upper ceramic substrate 300 and the PCB substrate 400 for the purpose of protecting the semiconductor chip (G), alleviating vibration, and insulating. You can fill in the space between them.
  • a through hole 320 is formed in the upper ceramic substrate 300 .
  • the through hole 320 connects the semiconductor chip G mounted on the upper ceramic substrate 300 to the driving device mounted on the PCB substrate 400 in the shortest distance in the substrate structure of the upper and lower multilayers, and the lower ceramic substrate 200 It is for connecting the NTC temperature sensor 210 mounted to the PCB substrate 400 with the driving device mounted on the shortest distance.
  • Eight through-holes 320 are formed at a position where the semiconductor chip is installed, and two through-holes are installed at a position where the NTC temperature sensor is installed, so that a total of 10 can be formed.
  • a plurality of through-holes 320 may be formed in the portion where the first electrode pattern a and the third electrode pattern c are formed in the upper ceramic substrate 300 .
  • the plurality of through-holes 320 formed in the first electrode pattern (a) allow the current flowing into the first electrode pattern (a) of the upper surface of the upper ceramic substrate 300 to be formed on the lower surface of the upper ceramic substrate 300 . It moves to the electrode pattern (a) and flows into the semiconductor chip (G).
  • the plurality of through-holes 320 formed in the third electrode pattern (c) allow the current flowing into the semiconductor chip (G) to pass through the third electrode pattern (c) of the lower surface of the upper ceramic substrate (300) to the upper ceramic substrate (300). ) to move to the third electrode pattern (c) on the upper surface.
  • the through hole 320 may have a diameter of 0.5 mm to 5.0 mm.
  • a connection pin is installed in the through hole 320 to be connected to the electrode pattern of the PCB substrate, and may be connected to the driving device mounted on the PCB substrate 400 through this.
  • the connection between the electrode patterns through the through-holes 320 and the connection pins installed in the through-holes 320 in the upper and lower multi-layered substrate structure eliminates various output losses through the shortest distance connection, thereby improving the constraints according to the size of the power module. can contribute
  • a plurality of via holes 330 may be formed in the electrode pattern of the upper ceramic substrate 300 .
  • the via hole 330 may be processed by at least 50% of the substrate area.
  • the area of the via hole 330 described above has been described as an example in which at least 50% or more of the substrate area is applied, but is not limited thereto, and may be processed to 50% or less.
  • 152 via holes may be formed in the first electrode pattern (a)
  • 207 via holes may be formed in the second electrode pattern (b)
  • 154 via holes may be formed in the third electrode pattern (c).
  • the plurality of via holes 330 formed in each electrode pattern are for conducting a large current and distributing a large current.
  • the via hole 330 is filled with a conductive material.
  • the conductive material may be Ag or an Ag alloy.
  • the Ag alloy may be an Ag-Pd paste.
  • the conductive material filled in the via hole 330 electrically connects the electrode pattern on the upper surface and the electrode pattern on the lower surface of the upper ceramic substrate 300 .
  • the via hole 330 may be formed by laser processing. The via hole 330 can be seen in the enlarged view of FIG. 8 .
  • FIG. 9 is a plan view of a PCB substrate according to an embodiment of the present invention.
  • the PCB substrate 400 is for switching the semiconductor chip G or for switching the semiconductor chip (GaN chip) using information sensed by the NTC temperature sensor (reference numeral 210 in FIG. 7 ).
  • the driving element is mounted.
  • the driving device includes a Gate Drive IC.
  • a capacitor 410 is mounted on the PCB substrate 400 .
  • the capacitor 410 includes a semiconductor chip G disposed to connect the first electrode pattern a and the second electrode pattern b of the upper ceramic substrate 300 and the second electrode pattern (G) of the upper ceramic substrate 300 . It is mounted on the upper surface of the PCB substrate 400 at a position corresponding to a position between the semiconductor chip G disposed to connect b) and the third electrode pattern c.
  • the gate drive IC circuit includes a high side gate drive IC and a low side gate drive IC.
  • connection pin and a bus bar are installed on an upper ceramic substrate according to an embodiment of the present invention.
  • the power module 10 includes a connection pin 910 for performing electrical connection between electrode patterns.
  • connection pin 910 is inserted into the through hole formed in the upper ceramic substrate 300 and the PCB substrate 400 to connect the gate terminal for mounting the semiconductor chip G and the electrode pattern for mounting the driving device. .
  • the connection pin 910 is inserted into a through hole formed in the lower ceramic substrate 200, the upper ceramic substrate 300, and the PCB substrate 400 to mount the terminal and the driving element of the NTC temperature sensor. can be connected
  • the connection pin 910 is inserted into the through hole formed in the upper ceramic substrate 300 and the PCB substrate 400 to connect the electrode pattern on which the semiconductor chip G is mounted and the electrode pattern on which the capacitor is mounted. have.
  • connection pin 910 connects the GaN chip mounted on the upper ceramic substrate 300 to the driving device mounted on the PCB substrate with the shortest distance, thereby eliminating various output losses and enabling high-speed switching.
  • connection pin 910 is installed on the upper ceramic substrate 300 .
  • the connection pin 910 may be manufactured as a bundle type connection pin 900 by connecting a plurality of connection pins 910 to each other in order to maintain the verticality of the pins.
  • the connection pin 910 may be manufactured in the form of a 2 ⁇ 2 pin, a 2 ⁇ 1 pin, or a 4 ⁇ 1 pin.
  • Each of the connecting pins 910 may have a cylindrical shape, and a circular wing portion 911 may be formed on the outer periphery.
  • the cylindrical connecting pin 910 may be inserted into a through hole (reference numeral 320 in FIG. 7 ) and soldered.
  • the bundle type connecting pin 900 may be formed by insert-injecting the plastic structure 920 into the plurality of connecting pins 910 .
  • the spaced electrode structure of the power module there are a plurality of connection pins 910 connecting the spaced apart electrodes. Therefore, when the connecting pin 910 is manufactured as a bundle type connecting pin 900 in a structure for connecting a plurality of connecting pins 910 to each other, the positional accuracy of the connecting pin 910 and the convenience of assembly are increased to enhance the assembly of the power module 10 . Operation reliability can be improved.
  • FIG. 11 is a perspective view showing a bus bar according to an embodiment of the present invention.
  • a bus bar 700 connecting the upper ceramic substrate 300 to terminals 610 and 620 installed at both ends of the housing 100 is included.
  • bus bars 700 there are three bus bars 700 , one connecting the + terminal of the first terminals 610 to the first electrode pattern a of the upper ceramic substrate 300 , and the other one connecting the first terminal 610 .
  • the middle - terminal is connected to the third electrode pattern (c), and the other terminal is connected to the second terminal (620) and the second electrode pattern (b).
  • the bus bar 700 is formed in a copper ribbon shape having a predetermined area and includes a laser welding area 710 bonded to a terminal and a laser on one side and an electrode on the other side. and a laser welding region 720 bonded to the pattern.
  • the bus bar 700 in the shape of a large-area copper ribbon connects the terminals 610 and 620 and the electrode pattern of the upper ceramic substrate 300 by a laser welding method. This maximizes bonding performance, simplifies the process, and reduces resistance as much as possible to facilitate large current movement compared to wire connection or edge bonding.
  • the bus bar 700 has a larger area than the laser welding region 720 in which the laser welding region 710 bonded to the terminals 610 and 620 is bonded to the electrode patterns a, b, and c of the upper ceramic substrate 300 . .
  • the large-area laser welding region 710 reduces the resistance of the large power as much as possible. Furthermore, laser welding over a large area moves the current across the entire width, which lowers the resistance, which is advantageous for high-speed movement of current.
  • FIG. 12 is a photograph showing a laser welding area of a bus bar according to an embodiment of the present invention.
  • the laser welding regions 951 and 953 may be joined in a zigzag shape, and the bonding area is wide.
  • the copper ribbon shape having a predetermined bonding area forms a structure that passes a low resistance of a large current or voltage, and thus has an effect of lowering the resistance as much as possible.
  • a thickness of the copper ribbon forming the bus bar 700 may be 0.1 mm to 0.5 mm.
  • the bus bar 700 may provide flexibility by adopting a curved structure. The flexibility allows the bus bar 700 to act as a buffer when the positions of the terminals and electrode patterns are twisted due to high temperature.
  • FIG. 13 is a side cross-sectional view illustrating a state in which a bus bar connects a terminal and an electrode pattern according to an embodiment of the present invention.
  • the bus bar 700 may be formed in a curved shape such that the portion bonded to the terminal 620 is at a relatively lower position than the portion bonded to the electrode pattern of the upper ceramic substrate 300 .
  • FIG. 14 shows a bus bar according to another embodiment of the present invention.
  • a through slot 730 may be formed in the bus bar 700a of another embodiment.
  • a plurality of through slots 730 are formed in the bus bar 700a connecting the large area laser welding area 710 and the small area laser welding area 720 .
  • the through slot 730 is for maximizing the fluidity of the bus bar 700a.
  • a plurality of through slots 730 are formed in the bus bar 700a.
  • a plurality of through-slots 730 are formed in the horizontal or vertical direction to provide maximum flexibility to the bus bar 700 .
  • a plurality of through slots 730 are formed with a predetermined interval between the large area laser welding area 710 and the small area laser welding area 720 .
  • the bus bar connects the terminal and the electrode pattern with a large junction area, the current can move over the entire width, which is advantageous for high-speed movement of the current. can be minimized.
  • the bus bar can serve as a buffer when the positions of the terminals and electrode patterns are twisted due to high temperature, thereby improving the efficiency and performance of the power module.
  • the present invention provides maximum flexibility by forming a through slot 730 in the bus bar, so that even if a copper ribbon having a thickness of 0.5 mm or more is applied, deterioration and damage of the copper ribbon due to torsion or vibration between connecting parts and external impact are prevented. can be prevented
  • 15 is a cross-sectional view showing a bus bar connecting a terminal and a metal layer of a ceramic substrate according to an embodiment of the present invention.
  • both sides of the bus bar 700 are bonded to the terminals 610 and 620 and the metal layer 302 forming the electrode pattern of the upper ceramic substrate 300 by laser welding. That is, one side of the bus bar 700 is bonded to the terminals 610 and 620 by laser welding, and the other side of the bus bar 700 is bonded to the metal layer 302 of the upper ceramic substrate 300 by laser welding.
  • Laser welding can maximize the bonding performance, simplify the bonding process, and realize a bonding structure that can reduce resistance as much as possible.
  • Laser welding is a welding method performed using a high-density energy beam.
  • the bus bar 700 has a shape in which one side is low and the opposite side is relatively high.
  • the bus bar 700 is formed so that the portion bonded to the terminals 610 and 620 is relatively low compared to the portion bonded to the metal layer 302 of the upper ceramic substrate 300, that is, the electrode patterns a, b, and c. Even if a height difference occurs at the position where the terminal is located, the terminals 610 and 620 and the metal layer 302 can be stably connected.
  • 16 is a perspective view illustrating a shape of a bus bar according to an embodiment of the present invention.
  • the bus bar 700 is formed of a copper ribbon having a predetermined area.
  • the bus bar 700 provides flexibility by adopting a curved structure. The flexibility allows the bus bar 700 to act as a buffer when the positions of the terminals 610 and 620 and the metal layer 302 are twisted due to high temperature.
  • the bus bar 700 includes a first laser welding region 710 bonded to the terminals 610 and 620 with a laser on one side and a second laser welding region 720 bonded to the metal layer 302 and a laser on the opposite side.
  • the bus bar 700 in the form of a large-area copper ribbon connects the terminals 610 and 620 and the metal layer 302 of the upper ceramic substrate 300 face-to-face by a laser welding method. This maximizes bonding performance, simplifies the process, and reduces resistance as much as possible to facilitate large current movement compared to wire connection or edge bonding. Specifically, since the bus bar 700 connects the terminals 610 and 620 and the electrode patterns a, b, and c with a large junction area, the current can move over the entire width of the junction area, which is advantageous for high-speed movement of current, relatively Since the resistance can be lowered by applying a thin copper ribbon, heat generation can also be minimized.
  • the first laser welding region 710 has a larger area than the second laser welding region 720 .
  • the first laser welding region 710 bonded to the terminals 610 and 620 is bonded to the metal layer 302 of the upper ceramic substrate 300 , that is, the electrode patterns a, b, and c. It has a larger area than the second laser welding region 720 .
  • the large-area first laser welding area 710 reduces the resistance of the large power to the maximum to advantageously move the current at high speed. Furthermore, laser welding over a large area moves the current across the entire width, which lowers the resistance, which is advantageous for high-speed movement of current.
  • 17 is a diagram of a bus bar for explaining a laser welding shape according to an embodiment of the present invention.
  • laser welding is formed in a zigzag pattern to secure a bonding area.
  • the zigzag pattern has the effect of increasing the junction area to pass a large current and lowering the resistance as much as possible.
  • a power module pursues a low resistance because a large current or voltage continuously moves due to its characteristics.
  • the laser welding shape for bonding the bus bar 700 to the terminals 610 and 620 or the metal layer 302 may employ a form in which a circular pattern is continuously repeated in addition to the above-described zigzag pattern in order to secure a large bonding area.
  • the bus bar connects the terminal and the electrode pattern with a large junction area, the current can move over the entire width, which is advantageous for high-speed movement of current. can be minimized.
  • the bus bar can serve as a buffer when the positions of the terminals and electrode patterns are twisted due to high temperature, thereby improving the efficiency and performance of the power module.
  • the present invention secures a bonding area, which is advantageous for high-speed movement of a large current.

Abstract

The present invention relates to a power module comprising: a ceramic board (300) which includes a ceramic base material and electrode patterns formed on the top surface and the bottom surface of the ceramic base material; a housing (100) to which the ceramic board (300) is mounted and which has terminals disposed at both ends; and bus bars (700) for connecting the electrode patterns of the ceramic board (300) and the terminals through surface-to-surface bonding. The present invention has the advantage of minimizing resistance and heat generation by using the bus bars having a structure that passes high current or low resistance of voltage.

Description

파워모듈power module
본 발명은 파워모듈에 관한 것으로, 더욱 상세하게는 고출력 전력 반도체 칩을 적용하여 성능을 개선한 파워모듈에 관한 것이다. The present invention relates to a power module, and more particularly, to a power module having improved performance by applying a high output power semiconductor chip.
파워모듈은 하이브리드 자동차, 전기차 등의 모터 구동을 위해 고전압 전류를 공급하기 위해 사용된다.The power module is used to supply high voltage current to drive motors such as hybrid vehicles and electric vehicles.
파워모듈 중 양면 냉각 파워모듈은 반도체 칩의 상, 하부에 각각 기판을 설치하고 그 기판의 외측면에 각각 방열판을 구비한다. 양면 냉각 파워모듈은 단면에 방열판을 구비하는 단면 냉각 파워모듈에 비해 냉각 성능이 우수하여 점차 그 사용이 증가하는 추세이다.Among the power modules, the double-sided cooling power module has a substrate on top and a bottom of a semiconductor chip, respectively, and a heat sink on an outer surface of the substrate, respectively. The double-sided cooling power module has an excellent cooling performance compared to a single-sided cooling power module having a heat sink on one side, and thus its use is gradually increasing.
전기차 등에 사용되는 양면 냉각 파워모듈은 두 기판의 사이에 탄화규소(SiC), 질화갈륨(GaN) 등의 전력 반도체 칩이 실장되므로 고전압으로 인해 높은 발열과 주행 중 진동이 발생하기 때문에 이를 해결하기 위해 고강도와 고방열 특성을 동시에 만족시키는 것이 중요하다. The double-sided cooling power module used in electric vehicles, etc., has a power semiconductor chip such as silicon carbide (SiC) and gallium nitride (GaN) mounted between the two substrates. It is important to satisfy both high strength and high heat dissipation characteristics at the same time.
본 발명의 목적은 고강도와 고방열 특성을 가지고, 접합 특성이 우수하며, 전류 경로를 최소화하여 부피를 줄일 수 있으며 효율 및 성능을 향상시킬 수 있는 파워모듈을 제공하는 것이다.An object of the present invention is to provide a power module that has high strength and high heat dissipation characteristics, has excellent bonding characteristics, can reduce a volume by minimizing a current path, and can improve efficiency and performance.
본 발명의 다른 목적은 대전류 또는 전압의 저저항을 패스(pass)하는 구조의 버스바를 적용하여 저항을 최대한 낮추고 발열을 최소화하도록 한 파워모듈을 제공하는 것이다.Another object of the present invention is to provide a power module in which resistance is as low as possible and heat generation is minimized by applying a bus bar having a structure that passes a low resistance of a large current or voltage.
본 발명의 또 다른 목적은 버스바의 유연성을 극대화한 파워모듈을 제공하는 것이다. Another object of the present invention is to provide a power module maximizing the flexibility of a bus bar.
본 발명의 또 다른 목적은 버스바의 양측을 단자 및 세라믹기판의 전극 패턴(금속층)에 연결하여 접합 성능을 향상시키고 대전류와 전압을 패스(pass)하는 구조를 구현하도록 레이저 웰딩 공법을 적용하는 파워모듈을 제공하는 것이다.Another object of the present invention is to connect both sides of a bus bar to a terminal and an electrode pattern (metal layer) of a ceramic substrate to improve bonding performance and apply a laser welding method to implement a structure for passing large current and voltage. to provide a module.
상기한 바와 같은 목적을 달성하기 위한 본 발명의 특징에 따르면, 본 발명의 파워모듈은 세라믹기재와 상기 세라믹기재의 상면과 하면에 형성된 전극 패턴을 포함하는 세라믹기판과, 세라믹기판이 설치되며 양단에 단자가 배치된 하우징과, 세라믹기판의 전극 패턴과 상기 단자를 면대 면으로 접합하여 연결하는 버스바를 포함하다.According to a feature of the present invention for achieving the above object, the power module of the present invention includes a ceramic substrate including a ceramic substrate and electrode patterns formed on upper and lower surfaces of the ceramic substrate, and the ceramic substrate is installed at both ends. It includes a housing in which the terminals are disposed, and a bus bar connecting the electrode pattern of the ceramic substrate and the terminal face-to-face.
버스바는 소정의 면적을 가지는 구리 리본일 수 있다.The bus bar may be a copper ribbon having a predetermined area.
버스바는 일측에 단자와 레이저로 접합되는 레이저 웰딩 영역을 포함하고 반대편 타측에 전극 패턴과 레이저로 접합되는 레이저 웰딩 영역을 포함할 수 있다.The bus bar may include a laser welding region bonded to the terminal and a laser on one side and a laser welding region bonded to the electrode pattern and a laser on the other side of the bus bar.
버스바는 상기 단자와 레이저로 접합되는 레이저 웰딩 영역이 상기 전극 패턴과 레이저로 접합되는 레이저 웰딩 영역에 비해 면적이 상대적으로 넓을 수 있다.In the bus bar, an area of a laser welding region bonded to the terminal and a laser may be relatively larger than an area of a laser welding region bonded to the electrode pattern and a laser.
버스바는 굴곡진 구조로 될 수 있다.The busbar may have a curved structure.
버스바는 두께가 0.1mm~0.5mm 범위일 수 있다.The busbar may have a thickness ranging from 0.1 mm to 0.5 mm.
전극 패턴은 제1 전극 패턴, 제2 전극 패턴 및 제3 전극 패턴을 포함하고, 단자는 제1 단자와 제2 단자를 포함하며, 버스바는 제1 단자와 제1 전극 패턴을 연결하고, 제1 단자와 제3 전극 패턴을 연결하며, 제2 단자와 제2 전극 패턴을 연결하기 위한 3개를 포함할 수 있다.The electrode pattern includes a first electrode pattern, a second electrode pattern, and a third electrode pattern, the terminal includes a first terminal and a second terminal, the bus bar connects the first terminal and the first electrode pattern, The first terminal and the third electrode pattern may be connected, and three for connecting the second terminal and the second electrode pattern may be included.
버스바는 관통슬롯이 형성될 수 있다.The bus bar may have a through slot formed therein.
버스바는 일측에 단자와 레이저로 접합되는 제1 레이저 웰딩 영역을 포함하고 반대편 타측에 전극 패턴과 레이저로 접합되는 제2 레이저 웰딩 영역을 포함하며, 관통슬롯은 상기 제1 레이저 웰딩 영역과 상기 제2 레이저 웰딩 영역의 사이에 형성될 수 있다.The bus bar includes a first laser welding region bonded to the terminal and a laser on one side and a second laser welding region bonded to the electrode pattern and a laser on the opposite side on the other side, and the through slot includes the first laser welding region and the first laser welding region. It may be formed between two laser welding regions.
관통슬롯은 가로 방향 또는 세로 방향으로 일정 간격을 두고 다수 개가 형성될 수 있다.A plurality of through slots may be formed at regular intervals in the horizontal or vertical direction.
버스바는 일측에 비해 타측의 높이가 상대적으로 높고 굴곡지게 형성될 수 있다.The bus bar may be formed to have a relatively high height on the other side compared to one side and to be curved.
버스바는 일측과 타측을 연결하는 중간 부분이 굴곡지게 형성될 수 있다.The bus bar may be formed so that an intermediate portion connecting one side and the other side is curved.
버스바는 단자와 세라믹기판의 전극 패턴에 각각 레이저 웰딩으로 접합될 수 있다.The bus bar may be respectively bonded to the terminal and the electrode pattern of the ceramic substrate by laser welding.
레이저 웰딩은 지그재그 패턴 형상으로 형성될 수 있다.Laser welding may be formed in a zigzag pattern shape.
본 발명은 고강도와 고방열 특성을 가지고, 접합 특성이 우수하며, 전류 경로를 최소화하여 부피를 줄일 수 있으며 고속 스위칭에 최적화되어 효율 및 성능을 향상시킬 수 있는 효과가 있다.The present invention has high strength and high heat dissipation characteristics, has excellent bonding characteristics, can reduce a volume by minimizing a current path, and is optimized for high-speed switching to improve efficiency and performance.
또한, 본 발명은 대전류 또는 전압의 저저항을 패스(pass)하는 구조의 버스바를 적용하여 저항을 최대한 낮추고 발열을 최소화하는 효과가 있다. In addition, the present invention has an effect of lowering the resistance as much as possible and minimizing heat generation by applying a bus bar having a structure that passes a low resistance of a large current or voltage.
또한, 본 발명은 레이저 웰딩 공법을 이용하여 버스바의 접합성을 극대화할 수 있고, 버스바를 단자 및 전극 패턴에 연결하는 공정을 간편화할 수 있는 효과가 있다.In addition, the present invention has the effect of maximizing the bondability of the bus bar by using the laser welding method, and simplifying the process of connecting the bus bar to the terminal and the electrode pattern.
또한, 본 발명은 상대적으로 두꺼운 두께의 구리 리본을 적용하여도 버스바의 유연성을 극대화하여 연결 부품 간 비틀림 또는 진동, 외부 충격으로 인한 구리 리본의 열화와 파손을 방지할 수 있는 효과가 있다.In addition, the present invention has the effect of maximizing the flexibility of the bus bar even when a relatively thick copper ribbon is applied, thereby preventing deterioration and damage of the copper ribbon due to torsion or vibration between connection parts, and external impact.
또한, 본 발명은 대면적 레이저 웰딩 공법을 적용하여 버스바의 양측을 단자 및 세라믹기판의 전극 패턴(금속층)에 연결하므로 접합 성능을 극대화할 수 있는 효과가 있다. In addition, the present invention has the effect of maximizing the bonding performance by applying a large-area laser welding method to connect both sides of the bus bar to the terminal and the electrode pattern (metal layer) of the ceramic substrate.
또한, 본 발명은 지그재그 패턴 형상의 레이저 웰딩을 수행하므로 넓은 접합면적을 확보하여 대전류 또는 전압의 저저항을 패스(pass)하는 구조를 구현하면서 저항을 최대한으로 낮추고 발열을 최소할 수 있는 효과가 있다.In addition, since the present invention performs laser welding in a zigzag pattern shape, a large junction area is secured and a structure that passes a low resistance of a large current or voltage is implemented, while the resistance can be lowered to the maximum and heat generation can be minimized. .
도 1은 본 발명의 실시예에 의한 파워모듈의 사시도이다. 1 is a perspective view of a power module according to an embodiment of the present invention.
도 2는 본 발명의 실시예에 의한 파워모듈의 분해 사시도이다.2 is an exploded perspective view of a power module according to an embodiment of the present invention.
도 3은 본 발명의 실시예에 의한 파워모듈의 측단면도이다.3 is a side cross-sectional view of a power module according to an embodiment of the present invention.
도 4는 본 발명의 실시예에 의한 하우징을 보인 사시도이다.4 is a perspective view showing a housing according to an embodiment of the present invention.
도 5는 본 발명의 실시예에 의한 하부 세라믹기판을 보인 사시도이다.5 is a perspective view showing a lower ceramic substrate according to an embodiment of the present invention.
도 6은 본 발명의 실시예에 의한 하부 세라믹기판의 상면과 하면을 보인 도면이다.6 is a view showing an upper surface and a lower surface of a lower ceramic substrate according to an embodiment of the present invention.
도 7은 본 발명의 실시예에 의한 상부 세라믹기판을 보인 사시도이다.7 is a perspective view showing an upper ceramic substrate according to an embodiment of the present invention.
도 8은 본 발명의 실시예에 의한 상부 세라믹기판의 상면과 하면을 보인 도면이다.8 is a view showing an upper surface and a lower surface of an upper ceramic substrate according to an embodiment of the present invention.
도 9는 본 발명의 실시예에 의한 PCB 기판의 평면도이다.9 is a plan view of a PCB substrate according to an embodiment of the present invention.
도 10은 본 발명의 실시예에 의한 연결핀 및 버스바가 상부 세라믹기판에 설치된 상태를 보인 사시도이다.10 is a perspective view illustrating a state in which a connection pin and a bus bar are installed on an upper ceramic substrate according to an embodiment of the present invention.
도 11은 본 발명의 실시예에 의한 버스바를 보인 사시도이다.11 is a perspective view showing a bus bar according to an embodiment of the present invention.
도 12는 본 발명의 실시예에 의한 버스바의 레이저 웰딩 영역을 보인 사진이다.12 is a photograph showing a laser welding area of a bus bar according to an embodiment of the present invention.
도 13은 본 발명의 실시예에 의한 버스바가 단자와 전극 패턴을 연결한 상태를 보인 측단면도이다. 13 is a side cross-sectional view illustrating a state in which a bus bar connects a terminal and an electrode pattern according to an embodiment of the present invention.
도 14는 본 발명의 다른 실시예에 의한 버스바를 보인 사시도이다.14 is a perspective view showing a bus bar according to another embodiment of the present invention.
도 15는 본 발명의 실시예로 단자와 세라믹기판의 금속층을 연결한 버스바를 보인 단면도이다.15 is a cross-sectional view showing a bus bar connecting a terminal and a metal layer of a ceramic substrate according to an embodiment of the present invention.
도 16은 본 발명의 실시예에 의한 버스바의 형상을 보인 사시도이다. 16 is a perspective view illustrating a shape of a bus bar according to an embodiment of the present invention.
도 17은 본 발명의 실시예에 의한 레이저 웰딩 형상을 설명하기 위한 버스바의 도면이다.17 is a diagram of a bus bar for explaining a laser welding shape according to an embodiment of the present invention.
*부호의 설명**Description of symbols*
10: 파워모듈 100: 하우징10: power module 100: housing
101: 안내리브 102: 걸림턱101: guide rib 102: locking jaw
103: 체결공 104: 지지공103: fastening hole 104: support hole
200: 하부 세라믹기판 201: 세라믹 기재200: lower ceramic substrate 201: ceramic substrate
202,203: 금속층 210: NTC 온도센서202,203: metal layer 210: NTC temperature sensor
220: 절연 스페이서 230: 인터커넥션 스페이서220: insulation spacer 230: interconnection spacer
300: 상부 세라믹기판 301: 세라믹 기재300: upper ceramic substrate 301: ceramic substrate
302,302: 금속층 310: 커팅부302,302: metal layer 310: cutting part
320: 쓰루홀 330: 비아홀320: through hole 330: via hole
400: PCB 기판 401: 안내홈400: PCB board 401: guide groove
410: 캐패시터 500: 방열판410: capacitor 500: heat sink
501: 연통공 610: 제1 단자501: through hole 610: first terminal
620: 제2 단자 630: 지지볼트620: second terminal 630: support bolt
700: 버스바 900: 연결핀700: bus bar 900: connecting pin
710,720: 레이저 웰딩 영역 730: 관통슬롯710, 720: laser welding area 730: through slot
G: 반도체 칩(GaN 칩)G: semiconductor chip (GaN chip)
이하 본 발명의 실시예를 첨부된 도면을 참조하여 상세하게 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 실시예에 의한 파워모듈의 사시도이고, 도 2는 본 발명의 실시예에 의한 파워모듈의 분해 사시도이다.1 is a perspective view of a power module according to an embodiment of the present invention, and FIG. 2 is an exploded perspective view of a power module according to an embodiment of the present invention.
도 1 및 도 2에 도시된 바에 의하면, 본 발명의 실시예에 따른 파워모듈(10)은 하우징(100)에 파워모듈을 이루는 각종 구성품을 수용하여 형성한 패키지 형태의 전자부품이다. 파워모듈(10)은 하우징(100) 안에 기판 및 소자를 배치하여 보호하는 형태로 형성된다. 1 and 2 , the power module 10 according to the embodiment of the present invention is an electronic component in the form of a package formed by accommodating various components constituting the power module in a housing 100 . The power module 10 is formed in a form to protect by arranging a substrate and elements in the housing 100 .
파워모듈(10)은 다수의 기판 및 다수의 반도체 칩을 포함할 수 있다. 실시예에 따른 파워모듈(10)은 하우징(100), 하부 세라믹기판(200), 상부 세라믹기판(300), PCB 기판(400) 및 방열판(500)을 포함한다.The power module 10 may include a plurality of substrates and a plurality of semiconductor chips. The power module 10 according to the embodiment includes a housing 100 , a lower ceramic substrate 200 , an upper ceramic substrate 300 , a PCB substrate 400 , and a heat sink 500 .
하우징(100)은 중앙에 상하로 개구되는 빈 공간이 형성되며 양측에 제1 단자(610)와 제2 단자(620)가 위치된다. 하우징(100)은 중앙의 빈 공간에 방열판(500), 하부 세라믹기판(200), 상부 세라믹기판(300) 및 PCB 기판(400)이 상하 일정 간격을 두고 순차적으로 적층되며, 양측의 제1 단자(610)와 제2 단자(620)에 외부 단자를 연결하기 위한 지지볼트(630)가 체결된다. 제1 단자(610)와 제2 단자(620)는 전원의 입출력단으로 사용된다.The housing 100 has an empty space that is opened vertically in the center, and the first terminal 610 and the second terminal 620 are positioned on both sides. In the housing 100, a heat sink 500, a lower ceramic substrate 200, an upper ceramic substrate 300, and a PCB substrate 400 are sequentially stacked at regular intervals up and down in the empty space in the center, and the first terminals on both sides A support bolt 630 for connecting the external terminal to the 610 and the second terminal 620 is fastened. The first terminal 610 and the second terminal 620 are used as input/output terminals of power.
도 2에 도시된 바에 의하면, 파워모듈(10)은 하우징(100)의 중앙의 빈 공간에 하부 세라믹기판(200), 상부 세라믹기판(300), PCB 기판(400)이 순차적으로 수용된다. 구체적으로, 하우징(100)의 하면에 방열판(500)이 배치되고, 방열판(500)의 상면에 하부 세라믹기판(200)이 부착되고, 하부 세라믹기판(200)의 상부에 상부 세라믹기판(300)이 일정 간격을 두고 배치되며, 상부 세라믹기판(300)의 상부에 PCB 기판(400)이 일정 간격을 두고 배치된다.As shown in FIG. 2 , in the power module 10 , the lower ceramic substrate 200 , the upper ceramic substrate 300 , and the PCB substrate 400 are sequentially accommodated in an empty space in the center of the housing 100 . Specifically, the heat sink 500 is disposed on the lower surface of the housing 100, the lower ceramic substrate 200 is attached to the upper surface of the heat sink 500, and the upper ceramic substrate 300 is on the upper side of the lower ceramic substrate 200. These are arranged at a predetermined interval, and the PCB substrate 400 is arranged at a predetermined interval on the upper ceramic substrate 300 .
하우징(100)에 PCB 기판(400)이 배치된 상태는 PCB 기판(400)의 가장자리에 요입되게 형성된 안내홈(401,402)과 안내홈(401,402)에 대응되게 하우징(100)에 형성된 안내리브(101) 및 걸림턱(102)에 의해 고정될 수 있다. 실시예에 따른 PCB 기판(400)은 가장자리를 둘러 다수 개의 안내홈(401,402)이 형성되고, 이들 중 일부의 안내홈(401)은 하우징(100)의 내측면에 형성된 안내리브(101)가 안내되고 이들 중 나머지 일부의 안내홈(402)은 하우징(100)의 내측면에 형성된 걸림턱(102)이 통과되어 걸어진다. The state in which the PCB substrate 400 is disposed in the housing 100 is the guide grooves 401 and 402 formed to be recessed into the edge of the PCB substrate 400 and the guide ribs 101 formed in the housing 100 to correspond to the guide grooves 401 and 402 . ) and the locking jaw 102 may be fixed. A plurality of guide grooves 401 and 402 are formed around the edge of the PCB substrate 400 according to the embodiment, and some of the guide grooves 401 are guided by the guide rib 101 formed on the inner surface of the housing 100 . and the guide groove 402 of the remaining part of them is hung through the locking protrusion 102 formed on the inner surface of the housing 100 .
또는, 하우징(100)의 중앙의 빈 공간에 방열판(500), 하부 세라믹기판(200), 상부 세라믹기판(300)이 수용되고, 그 상면에 PCB 기판(400)이 배치된 상태는 체결볼트(미도시)로 고정될 수도 있다. 그러나, 하우징(100)에 PCB 기판(400)을 안내홈과 걸림턱 구조로 고정하는 것이 체결볼트로 고정하는 경우 대비 조립 시간을 줄이고 조립 공정이 간편하다.Alternatively, the heat sink 500, the lower ceramic substrate 200, and the upper ceramic substrate 300 are accommodated in the empty space in the center of the housing 100, and the state in which the PCB substrate 400 is disposed on the upper surface is a fastening bolt ( (not shown) may be fixed. However, fixing the PCB substrate 400 to the housing 100 with a guide groove and a clasp structure reduces the assembly time and simplifies the assembly process compared to the case of fixing with a fastening bolt.
하우징(100)은 네 모서리에 체결공(103)이 형성된다. 체결공(103)은 방열판(500)에 형성된 연통공(501)과 연통된다. 체결공(103)과 연통공(501)을 관통하여 고정볼트(150)가 체결되고, 체결공(103)과 연통공(501)을 관통한 고정볼트(150)의 단부는 방열판(500)의 하면에 배치될 고정지그의 고정공에 체결될 수 있다. The housing 100 has fastening holes 103 formed at four corners. The fastening hole 103 communicates with the communication hole 501 formed in the heat sink 500 . The fixing bolt 150 is fastened through the fastening hole 103 and the communication hole 501 , and the end of the fixing bolt 150 passing through the fastening hole 103 and the communication hole 501 is the heat sink 500 . It may be fastened to a fixing hole of a fixing jig to be disposed on the lower surface.
제1 단자(610)와 제2 단자(620)에 버스바(700)가 연결된다. 버스바(700)는 제1 단자(610)와 제2 단자(620)를 상부 세라믹기판(300)과 연결한다. 버스바(700)는 3개가 구비된다. 버스바(700) 중 하나는 제1 단자(610) 중 +단자를 상부 세라믹기판(300)의 제1 전극 패턴(a)과 연결하고, 다른 하나는 제1 단자(610) 중 -단자를 제3 전극 패턴(c)과 연결하며, 나머지 하나는 제2 단자(620)를 제2 전극 패턴(b)과 연결한다. 제1 전극 패턴(a), 제2 전극 패턴(b) 및 제3 전극 패턴(c)은 후술할 도 7 및 도 10을 참조한다.The bus bar 700 is connected to the first terminal 610 and the second terminal 620 . The bus bar 700 connects the first terminal 610 and the second terminal 620 to the upper ceramic substrate 300 . Three bus bars 700 are provided. One of the bus bars 700 connects the + terminal of the first terminals 610 to the first electrode pattern a of the upper ceramic substrate 300 , and the other connects the - terminal among the first terminals 610 . It is connected to the three electrode pattern (c), and the other one connects the second terminal 620 to the second electrode pattern (b). The first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c) will be described later with reference to FIGS. 7 and 10 .
도 3은 본 발명의 실시예에 의한 파워모듈의 측단면도이다.3 is a side cross-sectional view of a power module according to an embodiment of the present invention.
도 3에 도시된 바에 의하면, 파워모듈(10)은 하부 세라믹기판(200)과 상부 세라믹기판(300)의 복층 구조이며, 하부 세라믹기판(200)과 상부 세라믹기판(300)의 사이에 반도체 칩(G)이 위치된다. 반도체 칩(G)은 GaN(Gallium Nitride) 칩, MOSFET(Metal Oxide Semiconductor Field Effect Transistor), IGBT(Insulated Gate Bipolar Transistor), JFET(Junction Field Effect Transistor), HEMT(High Electric Mobility Transistor) 중 어느 하나일 수 있으나, 바람직하게는 반도체 칩(G)은 GaN 칩을 사용한다. GaN(Gallium Nitride) 칩(G)은 대전력(300A) 스위치 및 고속(~1MHz) 스위치로 기능하는 반도체 칩이다. GaN 칩은 기존의 실리콘 기반 반도체 칩보다 열에 강하면서 칩의 크기도 줄일 수 있는 장점이 있다. As shown in FIG. 3 , the power module 10 has a multilayer structure of a lower ceramic substrate 200 and an upper ceramic substrate 300 , and a semiconductor chip between the lower ceramic substrate 200 and the upper ceramic substrate 300 . (G) is located. The semiconductor chip (G) is any one of GaN (Gallium Nitride) chip, MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), JFET (Junction Field Effect Transistor), HEMT (High Electric Mobility Transistor) However, preferably, the semiconductor chip (G) uses a GaN chip. The GaN (Gallium Nitride) chip (G) is a semiconductor chip that functions as a high-power (300A) switch and a high-speed (~1MHz) switch. The GaN chip has the advantage of being stronger in heat than the existing silicon-based semiconductor chip and reducing the size of the chip.
하부 세라믹기판(200)과 상부 세라믹기판(300)은 반도체 칩(G)으로부터 발생하는 열의 방열 효율을 높일 수 있도록, 세라믹기재와 세라믹기재의 적어도 일면에 브레이징 접합된 금속층을 포함하는 세라믹기판으로 형성된다. The lower ceramic substrate 200 and the upper ceramic substrate 300 are formed of a ceramic substrate including a metal layer brazed to at least one surface of the ceramic substrate and the ceramic substrate to increase the heat dissipation efficiency of the heat generated from the semiconductor chip (G). do.
세라믹기재는 알루미나(Al 2O 3), AlN, SiN, Si 3N 4 중 어느 하나인 것을 일 예로 할 수 있다. 금속층은 세라믹기재 상에 브레이징 접합된 금속박으로 반도체 칩(G)을 실장하는 전극 패턴 및 구동소자를 실장하는 전극 패턴으로 각각 형성된다. 예컨데, 금속층은 반도체 칩 또는 주변 부품이 실장될 영역에 전극 패턴으로 형성된다. 금속박은 알루미늄박 또는 동박인 것을 일 예로 한다. 금속박은 세라믹기재 상에 780℃~1100℃로 소성되어 세라믹기재와 브레이징 접합된 것을 일 예로 한다. 이러한 세라믹기판을 AMB 기판이라 한다. 실시예는 AMB 기판을 예로 들어 설명하나 DBC 기판, TPC 기판, DBA 기판을 적용할 수도 있다. 그러나 내구성 및 방열 효율면에서 AMB 기판이 가장 적합하다. 상기한 이유로, 하부 세라믹기판(200)과 상부 세라믹기판(300)은 AMB 기판임을 일 예로 한다.The ceramic substrate may be, for example, any one of alumina (Al 2 O 3 ), AlN, SiN, and Si 3 N 4 . The metal layer is formed of an electrode pattern for mounting a semiconductor chip (G) and an electrode pattern for mounting a driving element, respectively, with a metal foil brazed on a ceramic substrate. For example, the metal layer is formed as an electrode pattern in a region where a semiconductor chip or peripheral components are to be mounted. The metal foil may be an aluminum foil or a copper foil as an example. For example, the metal foil is fired at 780° C. to 1100° C. on a ceramic substrate and brazed to the ceramic substrate. Such a ceramic substrate is called an AMB substrate. Although the embodiment is described by taking an AMB substrate as an example, a DBC substrate, a TPC substrate, and a DBA substrate may be applied. However, in terms of durability and heat dissipation efficiency, AMB substrates are most suitable. For the above reasons, the lower ceramic substrate 200 and the upper ceramic substrate 300 are AMB substrates as an example.
PCB 기판(400)은 상부 세라믹기판(300)의 상부에 배치된다. 즉, 파워모듈(10)은 하부 세라믹기판(200)과 상부 세라믹기판(300)과 PCB 기판(400)의 3층 구조로 구성된다. 고전력용 제어를 위한 반도체 칩(G)을 상부 세라믹기판(200)과 하부 세라믹기판(300)의 사이에 배치하여 방열 효율을 높이고, 저전력용 제어를 위한 PCB 기판(400)을 최상부에 배치하여 반도체 칩(G)에서 발생하는 열로 인한 PCB 기판(400)의 손상을 방지한다. 하부 세라믹기판(200), 상부 세라믹기판(300), PCB 기판(400)은 핀으로 연결 또는 고정될 수 있다.The PCB substrate 400 is disposed on the upper ceramic substrate 300 . That is, the power module 10 has a three-layer structure of a lower ceramic substrate 200 , an upper ceramic substrate 300 , and a PCB substrate 400 . The semiconductor chip (G) for high power control is disposed between the upper ceramic substrate 200 and the lower ceramic substrate 300 to increase heat dissipation efficiency, and the PCB substrate 400 for low power control is disposed on the uppermost portion of the semiconductor Prevents damage to the PCB substrate 400 due to the heat generated in the chip (G). The lower ceramic substrate 200 , the upper ceramic substrate 300 , and the PCB substrate 400 may be connected or fixed with pins.
방열판(500)은 하부 세라믹기판(200)의 하부에 배치된다. 방열판(500)은 반도체 칩(G)에서 발생하는 열의 방열을 위한 것이다. 방열판(500)은 소정의 두께를 가지는 사각 플레이트 형상으로 형성된다. 방열판(500)은 하우징(100)과 대응되는 면적으로 형성되며 방열 효율을 높이기 위해 구리 또는 알루미늄 재질로 형성될 수 있다.The heat sink 500 is disposed under the lower ceramic substrate 200 . The heat sink 500 is for dissipating heat generated from the semiconductor chip (G). The heat sink 500 is formed in a rectangular plate shape having a predetermined thickness. The heat sink 500 is formed in an area corresponding to the housing 100 and may be formed of copper or aluminum to increase heat dissipation efficiency.
이하에서는 본 발명의 파워모듈의 각 구성별 특징을 더욱 상세하게 설명하기로 한다. 파워모듈의 각 구성별 특징을 설명하는 도면에서는 각 구성별 특징을 강조하기 위해 도면을 확대하거나 과장하여 표현한 부분이 있으므로 도 1에 도시된 기본 도면과 일부 일치하지 않는 부분이 있을 수 있다. Hereinafter, the characteristics of each configuration of the power module of the present invention will be described in more detail. In the drawings for explaining the characteristics of each configuration of the power module, there are parts that are enlarged or exaggerated in order to emphasize the characteristics of each configuration, so there may be parts that do not match the basic drawings shown in FIG. 1 .
도 4는 본 발명의 실시예에 의한 하우징을 보인 사시도이다.4 is a perspective view showing a housing according to an embodiment of the present invention.
도 4에 도시된 바에 의하면, 하우징(100)은 중앙에 빈 공간이 형성되며, 양단에 제1 단자(610)와 제2 단자(620)가 위치된다. 하우징(100)은 양단에 제1 단자(610)와 제2 단자(620)가 일체로 고정되게 인서트 사출 방식으로 형성될 수 있다.As shown in FIG. 4 , an empty space is formed in the center of the housing 100 , and a first terminal 610 and a second terminal 620 are positioned at both ends. The housing 100 may be formed by an insert injection method such that the first terminal 610 and the second terminal 620 are integrally fixed at both ends.
기존의 파워모듈은 이격된 회로를 연결하기 위해 하우징에 연결핀을 인서트 사출하여 적용하고 있으나, 본 실시예는 하우징(100)의 제조시 연결핀을 제외하여 제조한 형상을 갖는다. 이는 하우징(100)의 내부에 연결핀이 위치하지 않음으로써 형상을 단순화하여 파워모듈의 비틀림 모멘트에 유연성을 향상시킨다.Existing power modules are applied by inserting and injecting connecting pins into the housing to connect spaced circuits, but this embodiment has a shape manufactured by excluding the connecting pins when the housing 100 is manufactured. This simplifies the shape because the connecting pin is not located inside the housing 100 to improve flexibility in the torsional moment of the power module.
하우징(100)은 네 모서리에 체결공(103)이 형성된다. 체결공(103)은 방열판(500)에 형성된 연통공(501)과 연통된다. 제1 단자(610)와 제2 단자(620)에는 지지공(104)이 형성된다. 지지공(104)에는 제1 단자(610) 및 제2 단자(620)를 모터 등의 외부 단자와 연결하기 위한 지지볼트(630)가 체결된다(도 10 참조).The housing 100 has fastening holes 103 formed at four corners. The fastening hole 103 communicates with the communication hole 501 formed in the heat sink 500 . A support hole 104 is formed in the first terminal 610 and the second terminal 620 . A support bolt 630 for connecting the first terminal 610 and the second terminal 620 to an external terminal such as a motor is fastened to the support hole 104 (see FIG. 10 ).
하우징(100)은 단열 재질로 형성된다. 하우징(100)은 반도체 칩(G)에서 발생한 열이 하우징(100)을 통해 상부의 PCB 기판(400)에 전달되지 않도록 단열 재질로 형성될 수 있다. The housing 100 is formed of a heat insulating material. The housing 100 may be formed of a heat insulating material so that heat generated from the semiconductor chip G is not transferred to the PCB substrate 400 above through the housing 100 .
또는 하우징(100)은 방열 플라스틱 재질을 적용할 수 있다. 하우징(100)은 반도체 칩(G)에서 발생한 열이 하우징(100)을 통해 외부로 방열될 수 있도록 방열 플라스틱 재질을 적용할 수 있다. 일 예로, 하우징(100)은 엔지니어링 플라스틱으로 형성될 수 있다. 엔지니어링 플라스틱은 높은 내열성과 뛰어난 강도, 내약품성, 내마모성을 가지며 150℃ 이상에서 장시간 사용 가능하다. 엔지니어링 플라스틱은 폴리아미드, 폴리카보네이트, 폴리에스테르, 변성 폴리페닐렌옥사이드 중 하나의 재료로 된 것일 수 있다. Alternatively, the housing 100 may be made of a heat-dissipating plastic material. The housing 100 may be formed of a heat-dissipating plastic material so that heat generated from the semiconductor chip G can be radiated to the outside through the housing 100 . For example, the housing 100 may be formed of engineering plastic. Engineering plastics have high heat resistance, excellent strength, chemical resistance and abrasion resistance, and can be used for a long time at 150℃ or higher. The engineering plastic may be made of one of polyamide, polycarbonate, polyester, and modified polyphenylene oxide.
반도체 칩(G)은 스위치로서 반복 동작을 하는데 그로 인해 하우징(100)은 고온과 온도변화에 스트레스를 받게 되나, 엔지니어링 플라스틱은 고온 안정성이 우수하므로 일반 플라스틱에 비해 고온과 온도변화에 상대적으로 안정적이고 방열 특성도 우수하다.The semiconductor chip (G) operates repeatedly as a switch, which causes the housing 100 to be stressed by high temperature and temperature changes. It also has excellent heat dissipation properties.
실시예는 엔지니어링 플라스틱 소재에 알루미늄 또는 구리로 된 단자를 인서트사출 적용하여 하우징(100)을 제조한 것일 수 있다. 엔지니어링 플라스틱 소재로 된 하우징(100)은 열을 전파시켜 외부로 방열시킨다. 하우징(100)은 수지에 고열 전도율 필러를 충전함으로써 일반 엔지니어링 플라스틱 소재보다 열전도성을 더 높일 수 있고 알루미늄에 비해 경량인 고방열 엔지니어링 플라스틱으로 될 수 있다.In the embodiment, the housing 100 may be manufactured by insert-injecting a terminal made of aluminum or copper to an engineering plastic material. The housing 100 made of an engineering plastic material radiates heat to the outside by propagating heat. The housing 100 may be made of a high heat dissipation engineering plastic that may have higher thermal conductivity than a general engineering plastic material and is lightweight compared to aluminum by filling the resin with a high thermal conductivity filler.
또는, 하우징(100)은 엔지니어링 플라스틱 또는 고강도 플라스틱 소재의 내외부에 그래핀 방열코팅재를 도포하여 방열 특성을 가지도록 한 것일 수 있다. Alternatively, the housing 100 may have heat dissipation properties by applying a graphene heat dissipation coating material to the inside and outside of an engineering plastic or high-strength plastic material.
도 5는 본 발명의 실시예에 의한 하부 세라믹기판을 보인 사시도이다.5 is a perspective view showing a lower ceramic substrate according to an embodiment of the present invention.
도 3 및 도 5에 도시된 바에 의하면, 하부 세라믹기판(200)은 방열판(500)의 상면에 부착된다. 구체적으로, 하부 세라믹기판(200)은 반도체 칩(G)과 방열판(500)의 사이에 배치된다. 하부 세라믹기판(200)은 반도체 칩(G)에서 발생하는 열을 방열판(500)으로 전달하고, 반도체 칩(G)과 방열판(500)의 사이를 절연하여 쇼트를 방지하는 역할을 한다.3 and 5 , the lower ceramic substrate 200 is attached to the upper surface of the heat sink 500 . Specifically, the lower ceramic substrate 200 is disposed between the semiconductor chip G and the heat sink 500 . The lower ceramic substrate 200 transfers heat generated from the semiconductor chip G to the heat sink 500 and insulates between the semiconductor chip G and the heat sink 500 to prevent a short circuit.
하부 세라믹기판(200)은 방열판(500)의 상면에 솔더링 접합될 수 있다. 방열판(500)은 하우징(100)과 대응되는 면적으로 형성되며 방열 효율을 높이기 위해 구리 재질로 형성될 수 있다. 솔더링 접합을 위한 솔더는 SnAg, SnAgCu 등이 사용될 수 있다.The lower ceramic substrate 200 may be soldered to the upper surface of the heat sink 500 . The heat sink 500 is formed in an area corresponding to the housing 100 and may be formed of a copper material to increase heat dissipation efficiency. As a solder for soldering joint, SnAg, SnAgCu, etc. may be used.
도 6은 본 발명의 실시예에 의한 하부 세라믹기판의 상면과 하면을 보인 도면이다.6 is a view showing an upper surface and a lower surface of a lower ceramic substrate according to an embodiment of the present invention.
도 5 및 도 6에 도시된 바에 의하면, 하부 세라믹기판(200)은 세라믹기재(201)와 세라믹기재(201)의 상하면에 브레이징 접합된 금속층(202,203)을 포함한다. 하부 세라믹기판(200)은 세라믹기재(201)의 두께가 0.68t이고, 세라믹기재(201)의 상면과 하면에 형성한 금속층(202,203)의 두께가 0.8t인 것을 일 예로 할 수 있다.5 and 6 , the lower ceramic substrate 200 includes a ceramic substrate 201 and metal layers 202 and 203 brazed to upper and lower surfaces of the ceramic substrate 201 . In the lower ceramic substrate 200 , the thickness of the ceramic substrate 201 may be 0.68 t, and the thickness of the metal layers 202 and 203 formed on the upper and lower surfaces of the ceramic substrate 201 may be 0.8 t.
하부 세라믹기판(200)의 상면(200a)의 금속층(202)은 구동소자를 실장하는 전극 패턴일 수 있다. 하부 세라믹기판(200)에 실장되는 구동소자는 NTC 온도센서(210)일 수 있다. NTC 온도센서(210)는 하부 세라믹기판(200)의 상면에 실장된다. NTC 온도센서(210)는 반도체 칩(G)의 발열로 인한 파워모듈 내의 온도 정보를 제공하기 위한 것이다. 하부 세라믹기판(200)의 하면(200b)의 금속층(203)은 방열판(500)에 열전달을 용이하게 하기 위해 하부 세라믹기판(200)의 하면 전체에 형성될 수 있다.The metal layer 202 of the upper surface 200a of the lower ceramic substrate 200 may be an electrode pattern on which a driving element is mounted. The driving device mounted on the lower ceramic substrate 200 may be the NTC temperature sensor 210 . The NTC temperature sensor 210 is mounted on the upper surface of the lower ceramic substrate 200 . The NTC temperature sensor 210 is for providing temperature information in the power module due to heat generation of the semiconductor chip G. The metal layer 203 of the lower surface 200b of the lower ceramic substrate 200 may be formed on the entire lower surface of the lower ceramic substrate 200 to facilitate heat transfer to the heat sink 500 .
하부 세라믹기판(200)에 절연 스페이서(220)가 접합된다. 절연 스페이서(220)는 하부 세라믹기판(200)의 상면에 접합되며 하부 세라믹기판(200)과 상부 세라믹기판(300)의 이격 거리를 규정한다.An insulating spacer 220 is bonded to the lower ceramic substrate 200 . The insulating spacer 220 is bonded to the upper surface of the lower ceramic substrate 200 and defines a separation distance between the lower ceramic substrate 200 and the upper ceramic substrate 300 .
절연 스페이서(220)는 하부 세라믹기판(200)과 상부 세라믹기판(300)의 이격 거리를 규정하여 상부 세라믹기판(300)의 하면에 실장된 반도체 칩(G)에서 발생하는 열의 방열 효율을 높이고, 반도체 칩(G) 간의 간섭을 방지하여 쇼트와 같은 전기적 충격을 방지한다. The insulating spacer 220 defines the separation distance between the lower ceramic substrate 200 and the upper ceramic substrate 300 to increase the heat dissipation efficiency of the heat generated by the semiconductor chip G mounted on the lower surface of the upper ceramic substrate 300, Interference between the semiconductor chips G is prevented to prevent an electric shock such as a short circuit.
절연 스페이서(220)는 하부 세라믹기판(200)의 상면 가장자리를 둘러 소정 간격을 두고 다수 개가 접합된다. 절연 스페이서(220) 간의 간격은 방열 효율을 높이는 공간으로 활용된다. 도면상 절연 스페이서(220)는 하부 세라믹기판(200)을 기준으로 할 때 가장자리를 둘러 배치되며, 일 예로 8개가 일정 간격을 두고 배치된다.A plurality of insulating spacers 220 are bonded to each other at predetermined intervals around the upper surface edge of the lower ceramic substrate 200 . A gap between the insulating spacers 220 is used as a space to increase heat dissipation efficiency. In the drawing, the insulating spacers 220 are arranged around the edge of the lower ceramic substrate 200 as a reference, and for example, eight insulating spacers 220 are arranged at regular intervals.
절연 스페이서(220)는 하부 세라믹기판(200)에 일체로 접합된다. 절연 스페이서(220)는 하부 세라믹기판(200)의 상부에 상부 세라믹기판(300)을 배치할 때 얼라인을 확인하는 용도로 적용될 수도 있다. 하부 세라믹기판(200)에 절연 스페이서(220)가 접합된 상태에서 그 상부에 반도체 칩(G)이 실장된 상부 세라믹기판(300)을 배치할 때, 절연 스페이서(220)가 상부 세라믹기판(300)의 얼라인을 확인하는 용도로 적용될 수 있다. 또한, 절연 스페이서(220)는 하부 세라믹기판(200)과 상부 세라믹기판(300)을 지지하여 하부 세라믹기판(200)과 상부 세라믹기판(300)의 휨을 방지하는데 기여한다. The insulating spacer 220 is integrally bonded to the lower ceramic substrate 200 . The insulating spacer 220 may be applied to check alignment when the upper ceramic substrate 300 is disposed on the lower ceramic substrate 200 . When the upper ceramic substrate 300 on which the semiconductor chip G is mounted is disposed in a state where the insulating spacer 220 is bonded to the lower ceramic substrate 200 , the insulating spacer 220 is formed on the upper ceramic substrate 300 . ) can be applied to check the alignment of In addition, the insulating spacer 220 supports the lower ceramic substrate 200 and the upper ceramic substrate 300 , thereby contributing to preventing bending of the lower ceramic substrate 200 and the upper ceramic substrate 300 .
절연 스페이서(220)는 하부 세라믹기판(200)에 실장된 칩과 상부 세라믹기판(300)에 실장된 칩 및 부품 간의 절연을 위해 세라믹 소재로 형성될 수 있다. 일 예로, 절연 스페이서는 Al 2O 3, ZTA, Si 3N 4, AlN 중 선택된 1종 또는 이들 중 둘 이상이 혼합된 합금으로 형성될 수 있다. Al 2O 3, ZTA, Si 3N 4, AlN는 기계적 강도, 내열성이 우수한 절연성 재료이다. The insulating spacer 220 may be formed of a ceramic material for insulation between the chip mounted on the lower ceramic substrate 200 and the chip and the component mounted on the upper ceramic substrate 300 . For example, the insulating spacer may be formed of one selected from Al 2 O 3 , ZTA, Si 3 N 4 , and AlN, or an alloy in which two or more thereof are mixed. Al 2 O 3 , ZTA, Si 3 N 4 , and AlN are insulating materials having excellent mechanical strength and heat resistance.
절연 스페이서(220)는 하부 세라믹기판(200)에 브레이징 접합된다. 절연 스페이서(220)를 하부 세라믹기판(200)에 솔더링 접합하면 솔더링 또는 가압 소성시 열적 기계적 충격으로 인해 기판이 파손될 수 있으므로 브레이징 접합한다. 브레이징 접합은 AgCu층과 Ti층을 포함한 브레이징 접합층을 이용할 수 있다. 브레이징을 위한 열처리는 780℃~900℃에서 수행할 수 있다. 브레이징 후, 절연 스페이서(220)는 하부 세라믹기판(200)의 금속층(202)과 일체로 형성된다. 브레이징 접합층의 두께는 0.005mm~0.08mm로 절연 스페이서의 높이에 영향을 미치치 않을 만큼 얇고 접합 강도는 높다. The insulating spacer 220 is brazed to the lower ceramic substrate 200 . When the insulating spacer 220 is soldered to the lower ceramic substrate 200, the substrate may be damaged due to thermal and mechanical shock during soldering or pressure firing, so that it is bonded by brazing. For the brazing bonding, a brazing bonding layer including an AgCu layer and a Ti layer may be used. Heat treatment for brazing can be performed at 780°C to 900°C. After brazing, the insulating spacer 220 is integrally formed with the metal layer 202 of the lower ceramic substrate 200 . The thickness of the brazing bonding layer is 0.005 mm to 0.08 mm, which is thin enough not to affect the height of the insulating spacer, and the bonding strength is high.
하부 세라믹기판(200)과 상부 세라믹기판(300)의 사이에 인터커넥션 스페이서(230)가 설치된다. 인터커넥션 스페이서(230)는 상하 복층 구조의 기판에서 연결핀을 대신하여 전극 패턴 간 전기적 연결을 수행할 수 있다. 인터커넥션 스페이서(230)는 전기적 로스(loss) 및 쇼트(shot)를 방지하면서 기판 간을 직접 연결하고 접합 강도를 높이며 전기적 특성도 개선할 수 있다. 인터커넥션 스페이서(230)는 일단이 브레이징 접합 방식으로 하부 세라믹기판(200)의 전극 패턴에 접합될 수 있다. 또한, 인터커넥션 스페이서(230)는 반대되는 타단이 브레이징 접합 방식 또는 솔더링 접합 방식으로 상부 세라믹기판(300)의 전극 패턴에 접합될 수 있다. 인터커넥션 스페이서(230)는 Cu 또는 Cu+CuMo 합금일 수 있다. An interconnection spacer 230 is installed between the lower ceramic substrate 200 and the upper ceramic substrate 300 . The interconnection spacer 230 may perform electrical connection between electrode patterns in place of a connection pin in a substrate having an upper and lower multilayer structure. The interconnection spacer 230 may directly connect between substrates while preventing electrical loss and short circuit, increase bonding strength, and improve electrical characteristics. One end of the interconnection spacer 230 may be bonded to the electrode pattern of the lower ceramic substrate 200 by a brazing bonding method. In addition, the other end of the interconnection spacer 230 may be bonded to the electrode pattern of the upper ceramic substrate 300 by a brazing bonding method or a soldering bonding method. The interconnection spacer 230 may be Cu or a Cu+CuMo alloy.
도 7은 본 발명의 실시예에 의한 상부 세라믹기판을 보인 사시도이고, 도 8은 본 발명의 실시예에 의한 상부 세라믹기판의 상면과 하면을 보인 도면이다.7 is a perspective view showing an upper ceramic substrate according to an embodiment of the present invention, and FIG. 8 is a view showing an upper surface and a lower surface of the upper ceramic substrate according to an embodiment of the present invention.
도 7 및 도 8에 도시된 바에 의하면, 상부 세라믹기판(300)은 하부 세라믹기판(200)의 상부에 배치된다.7 and 8 , the upper ceramic substrate 300 is disposed on the lower ceramic substrate 200 .
상부 세라믹기판(300)은 적층 구조의 중간 기판이다. 상부 세라믹기판(300)은 하면에 반도체 칩(G)을 실장하고, 고속 스위칭을 위한 하이 사이드(High Side) 회로와 로우 사이드(Low Side) 회로를 구성한다. The upper ceramic substrate 300 is an intermediate substrate having a stacked structure. The upper ceramic substrate 300 has a semiconductor chip (G) mounted on its lower surface, and constitutes a high-side circuit and a low-side circuit for high-speed switching.
상부 세라믹기판(300)은 세라믹기재(301)와 세라믹기재(301)의 상하면에 브레이징 접합된 금속층(302,303)을 포함한다. 상부 세라믹기판(300)은 세라믹기재의 두께가 0.38t이고 세라믹기재의 상면(300a)과 하면(300b)에 전극 패턴의 두께가 0.3t인 것을 일 예로 한다. 세라믹기판은 상면과 하면의 패턴 두께가 동일해야 브레이징시 틀어지지 않는다. The upper ceramic substrate 300 includes a ceramic substrate 301 and metal layers 302 and 303 brazed to upper and lower surfaces of the ceramic substrate 301 . For the upper ceramic substrate 300, the thickness of the ceramic substrate is 0.38t and the thickness of the electrode pattern on the upper surface 300a and the lower surface 300b of the ceramic substrate is 0.3t as an example. The ceramic substrate must have the same pattern thickness on the upper and lower surfaces to prevent distortion during brazing.
상부 세라믹기판(300)의 상면의 금속층(302)이 형성하는 전극 패턴은 제1 전극 패턴(a), 제2 전극 패턴(b), 제3 전극 패턴(c)으로 구분된다. 상부 세라믹기판(300)의 하면의 금속층(303)이 형성하는 전극 패턴은 상부 세라믹기판(300)의 상면의 금속층(302)이 형성하는 전극 패턴과 대응된다. 상부 세라믹기판(300)의 상면의 전극 패턴을 제1 전극 패턴(a), 제2 전극 패턴(b), 제3 전극 패턴(c)으로 구분한 것은 고속 스위칭을 위해 하이 사이드(High Side) 회로와 로우 사이드(Low Side) 회로로 분리하기 위함이다. The electrode pattern formed by the metal layer 302 on the upper surface of the upper ceramic substrate 300 is divided into a first electrode pattern (a), a second electrode pattern (b), and a third electrode pattern (c). The electrode pattern formed by the metal layer 303 on the lower surface of the upper ceramic substrate 300 corresponds to the electrode pattern formed by the metal layer 302 on the upper surface of the upper ceramic substrate 300 . The division of the electrode pattern on the upper surface of the upper ceramic substrate 300 into a first electrode pattern (a), a second electrode pattern (b), and a third electrode pattern (c) is a high-side circuit for high-speed switching. and to separate the low-side circuit.
반도체 칩(G)은 상부 세라믹기판(300)의 하면(300b)에 솔더(Solder), 은 페이스트(Ag Paste) 등의 접착층에 의해 플립칩(flip chip) 형태로 구비된다. 반도체 칩(G)이 상부 세라믹기판(300)의 하면에 플립칩 형태로 구비됨에 따라 와이어 본딩이 생략되어 인덕턴스 값을 최대한 낮출 수가 있게 되어, 이에 의해 방열 성능 또한 개선시킬 수 있다. The semiconductor chip G is provided in the form of a flip chip by an adhesive layer such as solder or silver paste on the lower surface 300b of the upper ceramic substrate 300 . As the semiconductor chip G is provided in the form of a flip chip on the lower surface of the upper ceramic substrate 300 , wire bonding is omitted so that the inductance value can be reduced as much as possible, thereby improving the heat dissipation performance.
도 8에 도시된 바와 같이, 반도체 칩(G)은 고속 스위칭을 위해 2개씩 병렬로 연결될 수 있다. 반도체 칩(G)은 2개가 상부 세라믹기판(300)의 전극 패턴 중 제1 전극 패턴(a)과 제2 전극 패턴(b)을 연결하는 위치에 배치되고, 나머지 2개가 제2 전극 패턴(b)과 제3 전극 패턴(c)을 연결하는 위치에 병렬로 배치된다. 일 예로 반도체 칩(G) 하나의 용량은 150A이다. 따라서 반도체 칩(G) 2개를 병렬 연결하여 용량이 300A가 되도록 한다. 반도체 칩(G)은 GaN 칩이다.As shown in FIG. 8 , two semiconductor chips G may be connected in parallel for high-speed switching. Two semiconductor chips (G) are disposed at positions connecting the first electrode pattern (a) and the second electrode pattern (b) among the electrode patterns of the upper ceramic substrate 300, and the other two are the second electrode patterns (b). ) and the third electrode pattern (c) are arranged in parallel at a position connecting it. For example, the capacity of one semiconductor chip G is 150A. Therefore, two semiconductor chips (G) are connected in parallel so that the capacity becomes 300A. The semiconductor chip G is a GaN chip.
반도체 칩(G)을 사용하는 파워모듈의 목적은 고속 스위칭에 있다. 고속 스위칭을 위해서는 Gate drive IC 단자에서 반도체 칩(G)의 Gate 단자 간이 매우 짧은 거리로 연결되는 것이 중요하다. 따라서 반도체 칩(G) 간을 병렬로 연결하여 Gate drive IC와 Gate 단자 간 연결 거리를 최소화한다. 또한, 반도체 칩(G)이 고속으로 스위칭하기 위해서는 반도체 칩(G)의 Gate 단자와 Source 단자가 동일한 간격을 유지하는 것이 중요하다. 이를 위해 반도체 칩(G)과 반도체 칩(G)의 사이의 중심에 연결핀이 연결되도록 Gate 단자와 Source 단자를 배치할 수 있다. Gate 단자와 Source 단자가 동일한 간격을 유지하지 않거나 패턴의 길이가 달라지면 문제가 발생한다. The purpose of the power module using the semiconductor chip G is high-speed switching. For high-speed switching, it is important that the gate drive IC terminal be connected by a very short distance between the gate terminal of the semiconductor chip (G). Therefore, the connection distance between the gate drive IC and the gate terminal is minimized by connecting the semiconductor chips G in parallel. In addition, in order for the semiconductor chip G to switch at high speed, it is important that the gate terminal and the source terminal of the semiconductor chip G maintain the same distance. To this end, the gate terminal and the source terminal may be disposed such that the connection pin is connected to the center between the semiconductor chip G and the semiconductor chip G. If the gate terminal and the source terminal do not keep the same distance or the length of the pattern is different, a problem occurs.
Gate 단자는 낮은 전압을 이용하여 반도체 칩(G)을 온오프(on/off)시키는 단자이다. Gate 단자는 연결핀을 통해 PCB 기판(400)과 연결될 수 있다. Source 단자는 고전류가 들어오고 나가는 단자이다. 반도체 칩(G)은 Drain 단자를 포함하며, Source 단자와 Drain 단자는 N형과 P형으로 구분되어 전류의 방향을 바꿀 수 있다. Source 단자와 Drain 단자는 반도체 칩(G)을 실장하는 전극 패턴인 제1 전극 패턴(a), 제2 전극 패턴(b), 제3 전극 패턴(c)을 통해 전류의 입출력을 담당한다. Source 단자와 Drain 단자는 전원의 입출력을 담당하는 도 1의 제1 단자(610) 및 제2 단자(620)와 연결된다. The gate terminal is a terminal for turning on/off the semiconductor chip G by using a low voltage. The gate terminal may be connected to the PCB substrate 400 through a connection pin. Source terminal is a terminal for high current to enter and exit. The semiconductor chip G includes a drain terminal, and the source terminal and the drain terminal are divided into N-type and P-type so that the direction of the current can be changed. The source terminal and the drain terminal are responsible for input and output of current through the first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c), which are electrode patterns for mounting the semiconductor chip (G). The source terminal and the drain terminal are connected to the first terminal 610 and the second terminal 620 of FIG. 1 in charge of input and output of power.
도 1 및 도 8을 참조하면, 도 1에 도시된 제1 단자(610)는 +단자와 -단자를 포함하며, 제1 단자(610)에서 +단자로 유입된 전원은 도 8에 도시된 상부 세라믹기판(300)의 제1 전극 패턴(a), 제1 전극 패턴(a)과 제2 전극 패턴(b)의 사이에 배치된 반도체 칩(G) 및 제2 전극 패턴(b)을 통해 제2 단자(620)로 출력된다. 그리고 도 1에 도시된 제2 단자(620)로 유입된 전원은 도 8에 도시된 제2 전극 패턴(b), 제2 전극 패턴(b)과 제3 전극 패턴(c)의 사이에 배치된 반도체 칩(G) 및 제3 전극 패턴(c)을 통해 제1 단자(610)의 -단자로 출력된다. 예컨데, 제1 단자(610)에서 유입되고 반도체 칩(G)을 통과하여 제2 단자(620)로 출력되는 전원을 하이 사이드(High Side), 제2 단자(620)에서 유입되고 반도체 칩(G)을 통과하여 제1 단자(610)로 출력되는 전원을 로우 사이드(Low Side)가 된다.1 and 8 , the first terminal 610 shown in FIG. 1 includes a + terminal and a - terminal, and power introduced from the first terminal 610 to the + terminal is the upper portion shown in FIG. 8 . Through the first electrode pattern (a) of the ceramic substrate 300, the semiconductor chip (G) and the second electrode pattern (b) disposed between the first electrode pattern (a) and the second electrode pattern (b) 2 is output to the terminal 620 . And the power supplied to the second terminal 620 shown in FIG. 1 is disposed between the second electrode pattern (b), the second electrode pattern (b) and the third electrode pattern (c) shown in FIG. 8 . It is output to the - terminal of the first terminal 610 through the semiconductor chip G and the third electrode pattern c. For example, power flowing in from the first terminal 610 and passing through the semiconductor chip G and output to the second terminal 620 is supplied from the high side and the second terminal 620 and the semiconductor chip G ) through the power output to the first terminal 610 becomes a low side (Low Side).
도 7에 도시된 바에 의하면, 상부 세라믹기판(300)은 NTC 온도센서(210)에 대응하는 부분에 커팅부(310)가 형성될 수 있다. 하부 세라믹기판(200)의 상면에 NTC 온도센서(210)가 장착된다. NTC 온도센서(210)는 반도체 칩(G)의 발열로 인한 파워모듈 내의 온도 정보를 제공하기 위한 것이다. 그런데 NTC 온도센서(210)의 두께가 하부 세라믹기판(200)과 상부 세라믹기판(300)의 사이의 간격에 비해 두꺼워 NTC 온도센서(210)와 상부 세라믹기판(300)의 간섭이 발생한다. 이를 해결하기 위해 NTC 온도센서(210)와 간섭되는 부분의 상부 세라믹기판(300)을 커팅하여 커팅부(310)를 형성한다. As shown in FIG. 7 , the upper ceramic substrate 300 may have a cutting part 310 formed in a portion corresponding to the NTC temperature sensor 210 . An NTC temperature sensor 210 is mounted on the upper surface of the lower ceramic substrate 200 . The NTC temperature sensor 210 is for providing temperature information in the power module due to heat generation of the semiconductor chip G. However, since the thickness of the NTC temperature sensor 210 is thicker than the gap between the lower ceramic substrate 200 and the upper ceramic substrate 300 , interference between the NTC temperature sensor 210 and the upper ceramic substrate 300 occurs. In order to solve this problem, the upper ceramic substrate 300 of the portion that interferes with the NTC temperature sensor 210 is cut to form a cutting portion 310 .
커팅부(310)를 통해 상부 세라믹기판(300)과 하부 세라믹기판(200)의 사이 공간에 몰딩을 위한 실리콘액 또는 에폭시를 주입할 수 있다. 상부 세라믹기판(300)과 하부 세라믹기판(200)의 사이를 절연하기 위해 실리콘액 또는 에폭시를 주입해야 한다. 상부 세라믹기판(300)과 하부 세라믹기판(200)에 실리콘액 또는 에폭시를 주입하기 위해 상부 세라믹기판(300)의 한쪽면을 커팅하여 커팅부(310)를 형성할 수 있으며, 커팅부(310)는 NTC 온도센서(210)와 대응되는 위치에 형성하여 상부 세라믹기판(300)과 NTC 온도센서(210)의 간섭도 방지할 수 있다. 실리콘액 또는 에폭시는 반도체 칩(G)의 보호, 진동의 완화 및 절연의 목적으로 하부 세라믹기판(200)과 상부 세라믹기판(300) 사이의 공간과 상부 세라믹기판(300)과 PCB 기판(400) 사이의 공간에 충진할 수 있다.A silicone liquid or epoxy for molding may be injected into the space between the upper ceramic substrate 300 and the lower ceramic substrate 200 through the cutting part 310 . In order to insulate between the upper ceramic substrate 300 and the lower ceramic substrate 200, silicone liquid or epoxy must be injected. In order to inject silicon liquid or epoxy into the upper ceramic substrate 300 and the lower ceramic substrate 200, one side of the upper ceramic substrate 300 may be cut to form a cutting part 310, and the cutting part 310 may be formed. is formed at a position corresponding to the NTC temperature sensor 210 to prevent interference between the upper ceramic substrate 300 and the NTC temperature sensor 210 . Silicon liquid or epoxy is used in the space between the lower ceramic substrate 200 and the upper ceramic substrate 300 and the upper ceramic substrate 300 and the PCB substrate 400 for the purpose of protecting the semiconductor chip (G), alleviating vibration, and insulating. You can fill in the space between them.
상부 세라믹기판(300)에 쓰루홀(Through Hole)(320)이 형성된다. 쓰루홀(320)은 상하 복층의 기판 구조에서 상부 세라믹기판(300)에 실장되는 반도체 칩(G)을 PCB 기판(400)에 실장되는 구동소자와 최단거리로 연결하고, 하부 세라믹기판(200)에 실장된 NTC 온도센서(210)를 PCB 기판(400)에 실장되는 구동소자와 최단거리로 연결하기 위한 것이다. A through hole 320 is formed in the upper ceramic substrate 300 . The through hole 320 connects the semiconductor chip G mounted on the upper ceramic substrate 300 to the driving device mounted on the PCB substrate 400 in the shortest distance in the substrate structure of the upper and lower multilayers, and the lower ceramic substrate 200 It is for connecting the NTC temperature sensor 210 mounted to the PCB substrate 400 with the driving device mounted on the shortest distance.
쓰루홀(320)은 반도체 칩이 설치되는 위치에 2개씩 8개가 형성되고, NTC 온도센서가 설치되는 위치에 2개가 설치되어 총 10개가 형성될 수 있다. 또한, 쓰루홀(320)은 상부 세라믹기판(300)에서 제1 전극 패턴(a)과 제3 전극 패턴(c)이 형성된 부분에 다수 개가 형성될 수 있다. Eight through-holes 320 are formed at a position where the semiconductor chip is installed, and two through-holes are installed at a position where the NTC temperature sensor is installed, so that a total of 10 can be formed. In addition, a plurality of through-holes 320 may be formed in the portion where the first electrode pattern a and the third electrode pattern c are formed in the upper ceramic substrate 300 .
제1 전극 패턴(a)에 형성된 다수 개의 쓰루홀(320)은 상부 세라믹기판(300)의 상면의 제1 전극 패턴(a)으로 유입된 전류가 상부 세라믹기판(300)의 하면에 형성된 제1 전극 패턴(a)으로 이동하고 반도체 칩(G)으로 유입되도록 한다. 제3 전극 패턴(c)에 형성된 다수 개의 쓰루홀(320)은 반도체 칩(G)으로 유입된 전류가 상부 세라믹기판(300)의 하면의 제3 전극 패턴(c)을 통해 상부 세라믹기판(300)의 상면의 제3 전극 패턴(c)으로 이동하도록 한다.The plurality of through-holes 320 formed in the first electrode pattern (a) allow the current flowing into the first electrode pattern (a) of the upper surface of the upper ceramic substrate 300 to be formed on the lower surface of the upper ceramic substrate 300 . It moves to the electrode pattern (a) and flows into the semiconductor chip (G). The plurality of through-holes 320 formed in the third electrode pattern (c) allow the current flowing into the semiconductor chip (G) to pass through the third electrode pattern (c) of the lower surface of the upper ceramic substrate (300) to the upper ceramic substrate (300). ) to move to the third electrode pattern (c) on the upper surface.
쓰루홀(320)의 직경은 0.5mm~5.0mm일 수 있다. 쓰루홀(320)에는 연결핀이 설치되어 PCB 기판의 전극 패턴과 연결되고 이를 통해 PCB 기판(400)에 실장되는 구동소자와 연결될 수 있다. 상하 복층의 기판 구조에서 쓰루홀(320) 및 쓰루홀(320)에 설치되는 연결핀을 통한 전극 패턴 간 연결은 최단 거리 연결을 통해 다양한 출력 손실을 제거하여 파워모듈의 크기에 따른 제약을 개선하는데 기여할 수 있다.The through hole 320 may have a diameter of 0.5 mm to 5.0 mm. A connection pin is installed in the through hole 320 to be connected to the electrode pattern of the PCB substrate, and may be connected to the driving device mounted on the PCB substrate 400 through this. The connection between the electrode patterns through the through-holes 320 and the connection pins installed in the through-holes 320 in the upper and lower multi-layered substrate structure eliminates various output losses through the shortest distance connection, thereby improving the constraints according to the size of the power module. can contribute
상부 세라믹기판(300)의 전극 패턴에는 복수 개의 비아홀(330)이 형성될 수 있다. 비아홀(330)은 기판 면적 대비 최소 50% 이상 가공될 수 있다. 상술한 비아홀(330)의 면적은 기판 면적 대비 최소 50% 이상 적용되는 예로 들어 설명하였으나, 이에 한정되는 것은 아니며 50% 이하로 가공될 수도 있다.A plurality of via holes 330 may be formed in the electrode pattern of the upper ceramic substrate 300 . The via hole 330 may be processed by at least 50% of the substrate area. The area of the via hole 330 described above has been described as an example in which at least 50% or more of the substrate area is applied, but is not limited thereto, and may be processed to 50% or less.
일 예로 제1 전극 패턴(a)에는 152개의 비아홀이 형성되고 제2 전극 패턴(b)에는 207개의 비아홀이 형성되고 제3 전극 패턴(c)에는 154개의 비아홀이 형성될 수 있다. 각 전극 패턴에 형성되는 복수 개의 비아홀(330)은 대전류 통전 및 대전류 분산을 위한 것이다. 하나의 슬롯 형태로 상부 세라믹기판(300)의 상면의 전극 패턴과 하면의 전극 패턴을 도통시키면 한쪽으로만 고전류가 흘러 쇼트, 과열 등의 문제가 발생할 수 있다. For example, 152 via holes may be formed in the first electrode pattern (a), 207 via holes may be formed in the second electrode pattern (b), and 154 via holes may be formed in the third electrode pattern (c). The plurality of via holes 330 formed in each electrode pattern are for conducting a large current and distributing a large current. When the electrode pattern on the upper surface and the electrode pattern on the lower surface of the upper ceramic substrate 300 are conducted in the form of a single slot, a high current flows only to one side, and problems such as short circuit and overheating may occur.
비아홀(330)에는 전도성 물질이 충진된다. 전도성 물질은 Ag 또는 Ag 합금일 수 있다. Ag 합금은 Ag-Pd 페이스트일 수 있다. 비아홀(330)에 충진된 전도성 물질은 상부 세라믹기판(300)의 상면의 전극 패턴과 하면의 전극 패턴을 전기적으로 연결한다. 비아홀(330)은 레이저 가공하여 형성할 수 있다. 비아홀(330)은 도 8의 확대도에서 확인할 수 있다.The via hole 330 is filled with a conductive material. The conductive material may be Ag or an Ag alloy. The Ag alloy may be an Ag-Pd paste. The conductive material filled in the via hole 330 electrically connects the electrode pattern on the upper surface and the electrode pattern on the lower surface of the upper ceramic substrate 300 . The via hole 330 may be formed by laser processing. The via hole 330 can be seen in the enlarged view of FIG. 8 .
도 9는 본 발명의 실시예에 의한 PCB 기판의 평면도이다.9 is a plan view of a PCB substrate according to an embodiment of the present invention.
도 9에 도시된 바에 의하면, PCB 기판(400)은 반도체 칩(G)을 스위칭하거나 NTC 온도센서(도 7의 도면부호 210)가 감지한 정보를 이용하여 반도체 칩(GaN 칩)을 스위칭하기 위한 구동소자가 실장된다. 구동소자는 Gate Drive IC를 포함한다.As shown in FIG. 9 , the PCB substrate 400 is for switching the semiconductor chip G or for switching the semiconductor chip (GaN chip) using information sensed by the NTC temperature sensor (reference numeral 210 in FIG. 7 ). The driving element is mounted. The driving device includes a Gate Drive IC.
PCB 기판(400)은 상면에 캐패시터(410)가 장착된다. 캐패시터(410)는 상부 세라믹기판(300)의 제1 전극 패턴(a)과 제2 전극 패턴(b)을 연결하도록 배치된 반도체 칩(G)과 상부 세라믹기판(300)의 제2 전극 패턴(b)과 제3 전극 패턴(c)을 연결하도록 배치된 반도체 칩(G)의 사이에 해당하는 위치인 PCB 기판(400)의 상면에 장착된다. A capacitor 410 is mounted on the PCB substrate 400 . The capacitor 410 includes a semiconductor chip G disposed to connect the first electrode pattern a and the second electrode pattern b of the upper ceramic substrate 300 and the second electrode pattern (G) of the upper ceramic substrate 300 . It is mounted on the upper surface of the PCB substrate 400 at a position corresponding to a position between the semiconductor chip G disposed to connect b) and the third electrode pattern c.
반도체 칩(G)의 사이에 해당하는 위치인 PCB 기판(400)의 상면에 캐패시터(410)가 장착되면, 연결핀(도 10의 도면부호 900)을 이용하여 반도체 칩(G)과 Drive IC 회로를 최단거리로 연결할 수 있으므로 고속 스위칭에 보다 유리하다. 일 예로, 캐패시터(410)는 용량을 맞추기 위해 10개가 병렬로 연결될 수 있다. 입력단에 디커플링용도로 2.5㎌ 이상을 확보하기 위해서는 고전압의 캐패시터 10개를 연결하여 용량을 확보해야 한다. 관련식은 56㎌/630V×5ea= 2.8㎌에서 확인된다. Gate Drive IC 회로는 High side gate drive IC와 Low side gate drive IC를 포함한다. When the capacitor 410 is mounted on the upper surface of the PCB substrate 400, which is a position between the semiconductor chips G, the semiconductor chip G and the Drive IC circuit using a connection pin (reference numeral 900 in FIG. 10). can be connected in the shortest distance, which is more advantageous for high-speed switching. As an example, ten capacitors 410 may be connected in parallel to match their capacity. In order to secure more than 2.5㎌ for decoupling at the input terminal, 10 high-voltage capacitors must be connected to secure the capacity. The related formula is confirmed at 56㎌/630V×5ea = 2.8㎌. The gate drive IC circuit includes a high side gate drive IC and a low side gate drive IC.
도 10은 본 발명의 실시예에 의한 연결핀 및 버스바가 상부 세라믹기판에 설치된 상태를 보인 사시도이다.10 is a perspective view illustrating a state in which a connection pin and a bus bar are installed on an upper ceramic substrate according to an embodiment of the present invention.
도 10에 도시된 바에 의하면, 파워모듈(10)은 전극 패턴 간 전기적 연결을 수행하기 위한 연결핀(910)을 포함한다. As shown in FIG. 10 , the power module 10 includes a connection pin 910 for performing electrical connection between electrode patterns.
연결핀(910)은 상부 세라믹기판(300)과 PCB 기판(400)에 형성된 쓰루홀(Through Hole)에 끼워져 반도체 칩(G)을 실장하는 게이트 단자와 구동소자를 실장하는 전극 패턴을 연결할 수 있다. 또는, 연결핀(910)은 하부 세라믹기판(200), 상부 세라믹기판(300) 및 PCB 기판(400)에 형성된 쓰루홀(Through Hole)에 끼워져 NTC 온도센서의 단자와 구동소자를 실장하는 전극 패턴을 연결할 수 있다. 또는, 연결핀(910)은 상부 세라믹기판(300)과 PCB 기판(400)에 형성된 쓰루홀(Through Hole)에 끼워져 반도체 칩(G)을 실장하는 전극 패턴과 캐패시터를 실장한 전극 패턴을 연결할 수 있다.The connection pin 910 is inserted into the through hole formed in the upper ceramic substrate 300 and the PCB substrate 400 to connect the gate terminal for mounting the semiconductor chip G and the electrode pattern for mounting the driving device. . Alternatively, the connection pin 910 is inserted into a through hole formed in the lower ceramic substrate 200, the upper ceramic substrate 300, and the PCB substrate 400 to mount the terminal and the driving element of the NTC temperature sensor. can be connected Alternatively, the connection pin 910 is inserted into the through hole formed in the upper ceramic substrate 300 and the PCB substrate 400 to connect the electrode pattern on which the semiconductor chip G is mounted and the electrode pattern on which the capacitor is mounted. have.
연결핀(910)은 상부 세라믹기판(300)에 실장되는 GaN 칩을 PCB 기판에 실장되는 구동소자와 최단거리로 연결하여 다양한 출력 손실을 제거하고 고속 스위칭이 가능하게 한다.The connection pin 910 connects the GaN chip mounted on the upper ceramic substrate 300 to the driving device mounted on the PCB substrate with the shortest distance, thereby eliminating various output losses and enabling high-speed switching.
연결핀(910)은 상부 세라믹기판(300)에 설치다. 연결핀(910)은 핀의 수직도를 유지기 위해 복수 개의 연결핀(910)을 서로 연결하여 묶음 형태 연결핀(900)으로 제작될 수 있다. 연결핀(910)은 2×2 핀 또는 2×1 핀 또는 4×1 핀 형태로 제작될 수 있다. 각각의 연결핀(910)은 원기둥 형상이며, 외주에 원형의 날개부(911)가 형성된 형상일 수 있다. 원기둥 형상의 연결핀(910)은 쓰루홀(도 7의 도면 부호 320)에 끼워지고 솔더링 접합될 수 있다. The connection pin 910 is installed on the upper ceramic substrate 300 . The connection pin 910 may be manufactured as a bundle type connection pin 900 by connecting a plurality of connection pins 910 to each other in order to maintain the verticality of the pins. The connection pin 910 may be manufactured in the form of a 2×2 pin, a 2×1 pin, or a 4×1 pin. Each of the connecting pins 910 may have a cylindrical shape, and a circular wing portion 911 may be formed on the outer periphery. The cylindrical connecting pin 910 may be inserted into a through hole (reference numeral 320 in FIG. 7 ) and soldered.
묶음 형태 연결핀(900)은 복수 개의 연결핀(910)에 플라스틱 구조물(920)을 인서트 사출하여 형성할 수 있다. 파워모듈의 이격 전극 구조에서 이격된 전극을 연결하는 연결핀(910)은 다수 개이다. 따라서 다수 개의 연결핀(910)을 서로 연결하는 구조에서 연결핀(910)을 묶음 형태 연결핀(900)으로 제작하면 연결핀(910)의 위치 정확도와 조립의 편의성을 높여 파워모듈(10)의 동작 신뢰성을 높일 수 있다. The bundle type connecting pin 900 may be formed by insert-injecting the plastic structure 920 into the plurality of connecting pins 910 . In the spaced electrode structure of the power module, there are a plurality of connection pins 910 connecting the spaced apart electrodes. Therefore, when the connecting pin 910 is manufactured as a bundle type connecting pin 900 in a structure for connecting a plurality of connecting pins 910 to each other, the positional accuracy of the connecting pin 910 and the convenience of assembly are increased to enhance the assembly of the power module 10 . Operation reliability can be improved.
도 11은 본 발명의 실시예에 의한 버스바를 보인 사시도이다.11 is a perspective view showing a bus bar according to an embodiment of the present invention.
도 10 및 도 11에 도시된 바에 의하면, 상부 세라믹기판(300)을 하우징(100)의 양단에 설치된 단자(610,620)와 연결하는 버스바(700)를 포함한다. As shown in FIGS. 10 and 11 , a bus bar 700 connecting the upper ceramic substrate 300 to terminals 610 and 620 installed at both ends of the housing 100 is included.
버스바(700)는 3개가 구비되며, 하나는 제1 단자(610) 중 +단자를 상부 세라믹기판(300)의 제1 전극 패턴(a)과 연결하고, 다른 하나는 제1 단자(610) 중 -단자를 제3 전극 패턴(c)과 연결하며, 나머지 하나는 제2 단자(620)를 제2 전극 패턴(b)과 연결한다. There are three bus bars 700 , one connecting the + terminal of the first terminals 610 to the first electrode pattern a of the upper ceramic substrate 300 , and the other one connecting the first terminal 610 . The middle - terminal is connected to the third electrode pattern (c), and the other terminal is connected to the second terminal (620) and the second electrode pattern (b).
도 11에 도시된 바에 의하면, 버스바(700)는 소정의 면적을 갖는 구리 리본(Cu Ribbon) 형상으로 형성되며 일측에 단자와 레이저로 접합되는 레이저 웰딩 영역(710)을 포함하고 반대편 타측에 전극 패턴과 접합되는 레이저 웰딩 영역(720)을 포함한다. 대면적의 구리 리본 형상인 버스바(700)는 레이저 웰딩 공법으로 단자(610,620)와 상부 세라믹기판(300)의 전극 패턴을 연결한다. 이는 와이어 연결이나 가장자리 본딩하여 연결하는 방법 대비 접합 성능이 극대화되고 공정이 단순화되며 저항을 최대한 낮추어 대전류 이동을 용이하게 한다. As shown in FIG. 11 , the bus bar 700 is formed in a copper ribbon shape having a predetermined area and includes a laser welding area 710 bonded to a terminal and a laser on one side and an electrode on the other side. and a laser welding region 720 bonded to the pattern. The bus bar 700 in the shape of a large-area copper ribbon connects the terminals 610 and 620 and the electrode pattern of the upper ceramic substrate 300 by a laser welding method. This maximizes bonding performance, simplifies the process, and reduces resistance as much as possible to facilitate large current movement compared to wire connection or edge bonding.
버스바(700)는 단자(610,620)와 접합되는 레이저 웰딩 영역(710)이 상부 세라믹기판(300)의 전극 패턴(a,b,c)과 접합되는 레이저 웰딩 영역(720)에 비해 대면적이다. 대면적 레이저 웰딩 영역(710)은 대전력의 저항을 최대한 줄인다. 더욱이 대면적으로 레이저 웰딩하면 전체폭으로 전류가 이동하므로 저항을 낮추어 전류의 고속 이동에 유리하다. The bus bar 700 has a larger area than the laser welding region 720 in which the laser welding region 710 bonded to the terminals 610 and 620 is bonded to the electrode patterns a, b, and c of the upper ceramic substrate 300 . . The large-area laser welding region 710 reduces the resistance of the large power as much as possible. Furthermore, laser welding over a large area moves the current across the entire width, which lowers the resistance, which is advantageous for high-speed movement of current.
도 12는 본 발명의 실시예에 의한 버스바의 레이저 웰딩 영역을 보인 사진이다.12 is a photograph showing a laser welding area of a bus bar according to an embodiment of the present invention.
도 12에 도시된 바에 의하면, 레이저 웰딩 영역(951,953)은 지그 재그 형태로 접합될 수 있고, 접합 면적이 넓다. 소정의 접합 면적을 갖는 구리 리본 형상은 대전류 또는 전압의 저저항을 패스(pass)하는 구조를 형성하여 저항을 최대한 낮추는 효과가 있다. 버스바(700)를 형성하는 구리 리본의 두께는 0.1mm~0.5mm인 것을 적용할 수 있다. 버스바(700)가 넓은 접합 면적으로 단자(610,620)와 전극 패턴(a,b,c)을 연결하면 상대적으로 얇은 두께의 구리 리본을 적용하여도 저항을 낮출 수 있고 그에 따라 발열을 최소화할 수 있다. 12 , the laser welding regions 951 and 953 may be joined in a zigzag shape, and the bonding area is wide. The copper ribbon shape having a predetermined bonding area forms a structure that passes a low resistance of a large current or voltage, and thus has an effect of lowering the resistance as much as possible. A thickness of the copper ribbon forming the bus bar 700 may be 0.1 mm to 0.5 mm. When the bus bar 700 connects the terminals 610 and 620 and the electrode patterns a, b, and c with a large bonding area, the resistance can be lowered even when a copper ribbon of a relatively thin thickness is applied, and thus heat generation can be minimized. have.
버스바(700)는 굴곡진 구조를 채용하여 유연성을 부여할 수 있다. 유연성은 고온으로 인해 단자와 전극 패턴의 위치가 비틀렸을 때 버스바(700)가 완충 역할을 할 수 있도록 한다. The bus bar 700 may provide flexibility by adopting a curved structure. The flexibility allows the bus bar 700 to act as a buffer when the positions of the terminals and electrode patterns are twisted due to high temperature.
도 13은 본 발명의 실시예에 의한 버스바가 단자와 전극 패턴을 연결한 상태를 보인 측단면도이다. 13 is a side cross-sectional view illustrating a state in which a bus bar connects a terminal and an electrode pattern according to an embodiment of the present invention.
도 13에 도시된 바에 의하면, 버스바(700)는 단자(620)와 접합되는 부분이 상부 세라믹기판(300)의 전극 패턴과 접합되는 부분에 비해 상대적으로 낮은 위치에 있도록 굴곡진 형상으로 형성될 수 있다. As shown in FIG. 13 , the bus bar 700 may be formed in a curved shape such that the portion bonded to the terminal 620 is at a relatively lower position than the portion bonded to the electrode pattern of the upper ceramic substrate 300 . can
도 14에는 본 발명의 다른 실시예에 의한 버스바가 도시되어 있다. 14 shows a bus bar according to another embodiment of the present invention.
도 14에 도시된 바에 의하면, 다른 실시예의 버스바(700a)는 관통슬롯(730)이 형성될 수 있다. As shown in FIG. 14 , a through slot 730 may be formed in the bus bar 700a of another embodiment.
버스바(700a)는 대면적 레이저 웰딩 영역(710)과 소면적 레이저 웰딩 영역(720)을 연결하는 부분에 다수 개의 관통슬롯(730)이 형성된다. 관통슬롯(730)은 버스바(700a)의 유동성을 극대화하기 위한 것이다. 파워모듈의 대전류 또는 고전압이 이동하는 버스바(700a)로 두께가 0.5mm 이상인 Cu 리본를 적용하는 경우, 연결 부품 간 비틀림 또는 진동, 외부 충격으로 인한 버스바(700a)의 열화와 파손을 방지하기 위해 버스바(700a)에 다수 개의 관통슬롯(730)을 형성한다. 관통슬롯(730)은 가로 또는 세로 방향으로 다수 개가 형성되어 버스바(700)에 유연성을 최대로 부여한다.A plurality of through slots 730 are formed in the bus bar 700a connecting the large area laser welding area 710 and the small area laser welding area 720 . The through slot 730 is for maximizing the fluidity of the bus bar 700a. When a Cu ribbon with a thickness of 0.5 mm or more is applied to the bus bar 700a on which a large current or high voltage of the power module moves, to prevent deterioration and damage of the bus bar 700a due to torsion or vibration between connection parts, or external impact A plurality of through slots 730 are formed in the bus bar 700a. A plurality of through-slots 730 are formed in the horizontal or vertical direction to provide maximum flexibility to the bus bar 700 .
실시예에서, 관통슬롯(730)은 대면적 레이저 웰딩 영역(710)과 소면적 레이저 웰딩 영역(720)의 사이에 일정 간격을 두고 다수 개가 형성된다.In the embodiment, a plurality of through slots 730 are formed with a predetermined interval between the large area laser welding area 710 and the small area laser welding area 720 .
상술한 본 발명은 버스바가 넓은 접합 면적으로 단자와 전극 패턴을 연결하므로 전체폭으로 전류가 이동할 수 있어 전류의 고속 이동에 유리하며, 상대적으로 얇은 두께의 구리 리본을 적용하여 저항을 낮출 수 있으므로 발열을 최소화할 수 있다. In the present invention described above, since the bus bar connects the terminal and the electrode pattern with a large junction area, the current can move over the entire width, which is advantageous for high-speed movement of the current. can be minimized.
또한, 본 발명은 굴곡진 구조의 버스바를 채용하여 유연성을 부여하므로, 고온으로 인해 단자와 전극 패턴의 위치가 비틀렸을 때 버스바가 완충 역할을 할 수 있고 이로 인해 파워모듈의 효율 및 성능을 향상시킬 수 있다. In addition, since the present invention provides flexibility by employing a bus bar having a curved structure, the bus bar can serve as a buffer when the positions of the terminals and electrode patterns are twisted due to high temperature, thereby improving the efficiency and performance of the power module. can
또한, 본 발명은 버스바에 관통슬롯(730)을 형성하여 유연성을 최대로 부여하므로 0.5mm 이상 두께의 구리 리본을 적용하여도 연결 부품 간 비틀림 또는 진동, 외부 충격으로 인한 구리 리본의 열화와 파손을 방지할 수 있다.In addition, the present invention provides maximum flexibility by forming a through slot 730 in the bus bar, so that even if a copper ribbon having a thickness of 0.5 mm or more is applied, deterioration and damage of the copper ribbon due to torsion or vibration between connecting parts and external impact are prevented. can be prevented
도 15는 본 발명의 실시예로 단자와 세라믹기판의 금속층을 연결한 버스바를 보인 단면도이다.15 is a cross-sectional view showing a bus bar connecting a terminal and a metal layer of a ceramic substrate according to an embodiment of the present invention.
도 15에 도시된 바에 의하면, 버스바(700)는 양측이 단자(610,620)와 상부 세라믹기판(300)의 전극 패턴을 형성하는 금속층(302)에 각각 레이저 웰딩으로 접합된다. 즉, 버스바(700)는 일측이 단자(610,620)에 레이저 웰딩으로 접합되고 반대되는 타측이 상부 세라믹기판(300)의 금속층(302)에 레이저 웰딩으로 접합된다.As shown in FIG. 15 , both sides of the bus bar 700 are bonded to the terminals 610 and 620 and the metal layer 302 forming the electrode pattern of the upper ceramic substrate 300 by laser welding. That is, one side of the bus bar 700 is bonded to the terminals 610 and 620 by laser welding, and the other side of the bus bar 700 is bonded to the metal layer 302 of the upper ceramic substrate 300 by laser welding.
레이저 웰딩은 접합 성능을 극대화시키고 접합 공정을 단순화할 수 있으며 저항을 최대한 낮출 수 있는 접합 구조를 구현할 수 있다. 레이저 웰딩은 고밀도의 에너지빔을 이용하여 수행하는 용접법이다.Laser welding can maximize the bonding performance, simplify the bonding process, and realize a bonding structure that can reduce resistance as much as possible. Laser welding is a welding method performed using a high-density energy beam.
버스바(700)는 일측은 낮고 반대되는 타측은 상대적으로 높이가 높은 형상이다. 버스바(700)는 단자(610,620)와 접합되는 부분이 상부 세라믹기판(300)의 금속층(302), 즉 전극 패턴(a,b,c)과 접합되는 부분에 비해 상대적으로 낮게 형성되어, 설치되는 위치에 높이 차가 발생하더라도 단자(610,620)와 금속층(302)을 안정적으로 연결할 수 있다. The bus bar 700 has a shape in which one side is low and the opposite side is relatively high. The bus bar 700 is formed so that the portion bonded to the terminals 610 and 620 is relatively low compared to the portion bonded to the metal layer 302 of the upper ceramic substrate 300, that is, the electrode patterns a, b, and c. Even if a height difference occurs at the position where the terminal is located, the terminals 610 and 620 and the metal layer 302 can be stably connected.
도 16은 본 발명의 실시예에 의한 버스바의 형상을 보인 사시도이다. 16 is a perspective view illustrating a shape of a bus bar according to an embodiment of the present invention.
도 16에 도시된 바에 의하면, 버스바(700)는 소정의 면적을 갖는 구리 리본(Cu Ribbon)으로 형성된다. 버스바(700)는 굴곡진 구조를 채용하여 유연성을 부여한다. 유연성은 고온으로 인해 단자(610,620)와 금속층(302)의 위치가 비틀렸을 때 버스바(700)가 완충 역할을 할 수 있도록 한다. As shown in FIG. 16 , the bus bar 700 is formed of a copper ribbon having a predetermined area. The bus bar 700 provides flexibility by adopting a curved structure. The flexibility allows the bus bar 700 to act as a buffer when the positions of the terminals 610 and 620 and the metal layer 302 are twisted due to high temperature.
버스바(700)는 일측에 단자(610,620)와 레이저로 접합되는 제1 레이저 웰딩 영역(710)을 포함하고 반대되는 타측에 금속층(302)과 레이저로 접합되는 제2 레이저 웰딩 영역(720)을 포함한다. The bus bar 700 includes a first laser welding region 710 bonded to the terminals 610 and 620 with a laser on one side and a second laser welding region 720 bonded to the metal layer 302 and a laser on the opposite side. include
대면적의 구리 리본 형상인 버스바(700)는 레이저 웰딩 공법으로 단자(610,620)와 상부 세라믹기판(300)의 금속층(302)을 면대 면으로 연결한다. 이는 와이어 연결이나 가장자리 본딩하여 연결하는 방법 대비 접합 성능이 극대화되고 공정이 단순화되며 저항을 최대한 낮추어 대전류 이동을 용이하게 한다. 구체적으로, 버스바(700)가 넓은 접합면적으로 단자(610,620)와 전극 패턴(a,b,c)을 연결하므로 접합영역 전체폭으로 전류가 이동할 수 있어 전류의 고속 이동에 유리하며, 상대적으로 얇은 두께의 구리 리본을 적용하여 저항을 낮출 수 있으므로 발열도 최소화할 수 있다. The bus bar 700 in the form of a large-area copper ribbon connects the terminals 610 and 620 and the metal layer 302 of the upper ceramic substrate 300 face-to-face by a laser welding method. This maximizes bonding performance, simplifies the process, and reduces resistance as much as possible to facilitate large current movement compared to wire connection or edge bonding. Specifically, since the bus bar 700 connects the terminals 610 and 620 and the electrode patterns a, b, and c with a large junction area, the current can move over the entire width of the junction area, which is advantageous for high-speed movement of current, relatively Since the resistance can be lowered by applying a thin copper ribbon, heat generation can also be minimized.
제1 레이저 웰딩 영역(710)은 제2 레이저 웰딩 영역(720)에 비해 면적이 넓다. 구체적으로, 버스바(700)는 단자(610,620)와 접합되는 제1 레이저 웰딩 영역(710)이 상부 세라믹기판(300)의 금속층(302) 즉, 전극 패턴(a,b,c)과 접합되는 제2 레이저 웰딩 영역(720)에 비해 대면적이다. 대면적인 제1 레이저 웰딩 영역(710)은 대전력의 저항을 최대한 줄여 전류의 고속 이동을 유리하게 한다. 더욱이 대면적으로 레이저 웰딩하면 전체폭으로 전류가 이동하므로 저항을 낮추어 전류의 고속 이동에 유리하다. The first laser welding region 710 has a larger area than the second laser welding region 720 . Specifically, in the bus bar 700 , the first laser welding region 710 bonded to the terminals 610 and 620 is bonded to the metal layer 302 of the upper ceramic substrate 300 , that is, the electrode patterns a, b, and c. It has a larger area than the second laser welding region 720 . The large-area first laser welding area 710 reduces the resistance of the large power to the maximum to advantageously move the current at high speed. Furthermore, laser welding over a large area moves the current across the entire width, which lowers the resistance, which is advantageous for high-speed movement of current.
도 17은 본 발명의 실시예에 의한 레이저 웰딩 형상을 설명하기 위한 버스바의 도면이다.17 is a diagram of a bus bar for explaining a laser welding shape according to an embodiment of the present invention.
도 17에 도시된 바에 의하면, 레이저 웰딩은 접합면적을 확보하기 위하여 지그재그 패턴으로 형성된다. 지그재그 패턴은 접합면적을 넓혀 대전류를 패스(pass) 하고 저항을 최대한 낮추는 효과가 있다. 파워모듈은 특성상 대전류 또는 전압이 지속적으로 이동하므로 저항이 낮은 것을 추구한다. 버스바(700)를 단자(610,620) 또는 금속층(302)에 접합하는 레이저 웰딩 형상은 넓은 접합면적을 확보하기 위하여 전술한 지그재그 패턴 외에도 원형 패턴이 연속하여 반복되는 형태를 채용할 수도 있다.As shown in FIG. 17 , laser welding is formed in a zigzag pattern to secure a bonding area. The zigzag pattern has the effect of increasing the junction area to pass a large current and lowering the resistance as much as possible. A power module pursues a low resistance because a large current or voltage continuously moves due to its characteristics. The laser welding shape for bonding the bus bar 700 to the terminals 610 and 620 or the metal layer 302 may employ a form in which a circular pattern is continuously repeated in addition to the above-described zigzag pattern in order to secure a large bonding area.
도 12를 참조하면, 레이저 웰딩은 U자형이 상하로 반복되면서 연결되는 지그재그 패턴이 형상으로 형성되고, 넓은 접합면적을 확보함을 확인할 수 있다.Referring to FIG. 12 , in laser welding, it can be confirmed that a zigzag pattern in which a U-shape is repeated up and down is formed in a shape, and a large bonding area is secured.
상술한 본 발명은 버스바가 넓은 접합면적으로 단자와 전극 패턴을 연결하므로 전체폭으로 전류가 이동할 수 있어 전류의 고속 이동에 유리하며, 상대적으로 얇은 두께의 구리 리본을 적용하여 저항을 낮출 수 있으므로 발열을 최소화할 수 있다. In the present invention described above, since the bus bar connects the terminal and the electrode pattern with a large junction area, the current can move over the entire width, which is advantageous for high-speed movement of current. can be minimized.
또한, 본 발명은 굴곡진 구조의 버스바를 채용하여 유연성을 부여하므로, 고온으로 인해 단자와 전극 패턴의 위치가 비틀렸을 때 버스바가 완충 역할을 할 수 있고 이로 인해 파워모듈의 효율 및 성능을 향상시킬 수 있다. In addition, since the present invention provides flexibility by employing a bus bar having a curved structure, the bus bar can serve as a buffer when the positions of the terminals and electrode patterns are twisted due to high temperature, thereby improving the efficiency and performance of the power module. can
또한, 본 발명은 레이저 웰딩이 지그재그 패턴으로 형성되므로 접합면적을 확보하여 대전류의 고속 이동에 유리하다.In addition, since laser welding is formed in a zigzag pattern, the present invention secures a bonding area, which is advantageous for high-speed movement of a large current.
본 발명은 도면과 명세서에 최적의 실시예들이 개시되었다. 여기서, 특정한 용어들이 사용되었으나, 이는 단지 본 발명을 설명하기 위한 목적에서 사용된 것이지 의미 한정이나 청구범위에 기재된 본 발명의 범위를 제한하기 위하여 사용된 것은 아니다. 그러므로 본 발명은 기술분야의 통상의 지식을 가진 자라면, 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 권리범위는 첨부된 청구범위의 기술적 사상에 의해 정해져야 할 것이다.BRIEF DESCRIPTION OF THE DRAWINGS The present invention is disclosed in the drawings and in the specification with preferred embodiments. Here, although specific terms have been used, they are only used for the purpose of describing the present invention and are not used to limit the meaning or scope of the present invention described in the claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments of the present invention are possible therefrom. Accordingly, the true technical scope of the present invention should be defined by the technical spirit of the appended claims.

Claims (14)

  1. 세라믹기재와 상기 세라믹기재의 상면과 하면에 형성된 전극 패턴을 포함하는 세라믹기판; a ceramic substrate including a ceramic substrate and electrode patterns formed on upper and lower surfaces of the ceramic substrate;
    상기 세라믹기판이 설치되며 양단에 단자가 배치된 하우징; 및a housing in which the ceramic substrate is installed and terminals are disposed at both ends; and
    상기 세라믹기판의 전극 패턴과 상기 단자를 면대 면으로 접합하여 연결하는 버스바;a bus bar connecting the electrode pattern of the ceramic substrate and the terminal face to face;
    를 포함하는 파워모듈.A power module comprising a.
  2. 제1항에 있어서, According to claim 1,
    상기 버스바는 소정의 면적을 가지는 구리 리본인 파워모듈. The bus bar is a copper ribbon having a predetermined area.
  3. 제1항에 있어서, According to claim 1,
    상기 버스바는 일측에 상기 단자와 레이저로 접합되는 레이저 웰딩 영역을 포함하고 반대편 타측에 상기 전극 패턴과 레이저로 접합되는 레이저 웰딩 영역을 포함하는 파워모듈. The bus bar includes a laser welding region bonded to the terminal and a laser on one side and a laser welding region bonded to the electrode pattern and a laser on the opposite side on the other side.
  4. 제1항에 있어서, According to claim 1,
    상기 버스바는 상기 단자와 레이저로 접합되는 레이저 웰딩 영역이 상기 전극 패턴과 레이저로 접합되는 레이저 웰딩 영역에 비해 면적이 상대적으로 넓은 것인 파워모듈.In the bus bar, the area of the laser welding area joined to the terminal with a laser is relatively larger than that of the laser welding area where the electrode pattern is joined with the laser.
  5. 제1항에 있어서, According to claim 1,
    상기 버스바는 굴곡진 구조로 된 파워모듈. The bus bar is a power module having a curved structure.
  6. 제1항에 있어서, According to claim 1,
    상기 버스바는 두께가 0.1mm~0.5mm 범위인 파워모듈.The bus bar is a power module having a thickness in the range of 0.1mm to 0.5mm.
  7. 제1항에 있어서, According to claim 1,
    상기 전극 패턴은 제1 전극 패턴, 제2 전극 패턴 및 제3 전극 패턴을 포함하고, The electrode pattern includes a first electrode pattern, a second electrode pattern, and a third electrode pattern,
    상기 단자는 제1 단자와 제2 단자를 포함하며, The terminal includes a first terminal and a second terminal,
    상기 버스바는 상기 제1 단자와 제1 전극 패턴을 연결하고, 상기 제1 단자와 상기 제3 전극 패턴을 연결하며, 상기 제2 단자와 상기 제2 전극 패턴을 연결하기 위한 3개를 포함하는 파워모듈.The bus bar includes three for connecting the first terminal and the first electrode pattern, connecting the first terminal and the third electrode pattern, and connecting the second terminal and the second electrode pattern power module.
  8. 제1항에 있어서, According to claim 1,
    상기 버스바는 관통슬롯이 형성된 파워모듈.The bus bar is a power module in which a through slot is formed.
  9. 제8항에 있어서, 9. The method of claim 8,
    상기 버스바는 일측에 상기 단자와 레이저로 접합되는 제1 레이저 웰딩 영역을 포함하고 반대편 타측에 상기 전극 패턴과 레이저로 접합되는 제2 레이저 웰딩 영역을 포함하며,The bus bar includes a first laser welding region bonded to the terminal and a laser on one side and a second laser welding region bonded to the electrode pattern and a laser on the opposite side on the other side,
    상기 관통슬롯은 상기 제1 레이저 웰딩 영역과 상기 제2 레이저 웰딩 영역의 사이에 형성되는 파워모듈. The through slot is formed between the first laser welding region and the second laser welding region.
  10. 제8항에 있어서, 9. The method of claim 8,
    상기 관통슬롯은 가로 방향 또는 세로 방향으로 일정 간격을 두고 다수 개가 형성된 파워모듈.The power module in which a plurality of the through slots are formed at regular intervals in a horizontal or vertical direction.
  11. 제1항에 있어서, According to claim 1,
    상기 버스바는 일측에 비해 타측의 높이가 상대적으로 높고 굴곡지게 형성된 파워모듈. The bus bar is a power module in which the height of the other side is relatively high and curved compared to one side.
  12. 제11항에 있어서, 12. The method of claim 11,
    상기 버스바는 일측과 타측을 연결하는 중간 부분이 굴곡지게 형성된 파워모듈.The bus bar is a power module in which a middle part connecting one side and the other side is formed to be curved.
  13. 제1항에 있어서, According to claim 1,
    상기 버스바는 상기 단자와 상기 세라믹기판의 전극 패턴에 각각 레이저 웰딩으로 접합된 파워모듈.The bus bar is each connected to the terminal and the electrode pattern of the ceramic substrate by laser welding.
  14. 제13항에 있어서, 14. The method of claim 13,
    상기 레이저 웰딩은 지그재그 패턴 형상으로 형성된 파워모듈.The laser welding is a power module formed in a zigzag pattern shape.
PCT/KR2021/005876 2020-05-15 2021-05-11 Power module WO2021230617A1 (en)

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KR20140135443A (en) * 2013-05-16 2014-11-26 주식회사 케이이씨 method for fabricating semiconductor module and semiconductor module thereof
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