WO2021217471A1 - 一种基于fpga实现电机控制的方法和装置 - Google Patents

一种基于fpga实现电机控制的方法和装置 Download PDF

Info

Publication number
WO2021217471A1
WO2021217471A1 PCT/CN2020/087674 CN2020087674W WO2021217471A1 WO 2021217471 A1 WO2021217471 A1 WO 2021217471A1 CN 2020087674 W CN2020087674 W CN 2020087674W WO 2021217471 A1 WO2021217471 A1 WO 2021217471A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
edge
time point
preset
component
Prior art date
Application number
PCT/CN2020/087674
Other languages
English (en)
French (fr)
Inventor
彭彤
刘华
Original Assignee
深圳怡化电脑股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳怡化电脑股份有限公司 filed Critical 深圳怡化电脑股份有限公司
Priority to CN202080000627.0A priority Critical patent/CN113939855A/zh
Priority to PCT/CN2020/087674 priority patent/WO2021217471A1/zh
Publication of WO2021217471A1 publication Critical patent/WO2021217471A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07D—HANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
    • G07D11/00—Devices accepting coins; Devices accepting, dispensing, sorting or counting valuable papers
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07D—HANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
    • G07D11/00—Devices accepting coins; Devices accepting, dispensing, sorting or counting valuable papers
    • G07D11/20—Controlling or monitoring the operation of devices; Data handling
    • G07D11/22—Means for sensing or detection

Definitions

  • the present invention relates to the technical field of movement control, in particular to a method for realizing motor control based on FPGA and a device for realizing motor control based on FPGA.
  • the container used to store the medium often involves the problem of how to separate the medium in the container.
  • the separation of the medium in the existing container is often achieved by the friction between the separation component in the container and the medium to separate the medium from the container.
  • the original squeezing force on the medium will be gradually released, and the state of the medium and the separating element will exist: tight-loose-no contact, such a state process; the corresponding detection component will have a change of shielding-not shielding, in After detecting the state change of the detection component, the medium carrying component will move the separation component with the medium.
  • the state of the detection component is in the process of being unshielded-concealed. Due to the superimposed effect of the medium hardness, the medium jitters, which may cause the pulse signal of the detection component to form jitter.
  • the embodiments of the present invention are proposed to provide a method for realizing motor control based on FPGA and a corresponding device for realizing motor control based on FPGA, which overcomes the above problems or at least partially solves the above problems.
  • the calculation and control technology avoids the problem that the pulse waveform jitter of the detection component within a preset time caused by the superimposition of the hardness of the medium causes the movement of the medium carrying component to the separation component to stop prematurely.
  • the embodiment of the present invention discloses a method for realizing motor control based on FPGA, and the method includes:
  • a preset motor is used to control the movement of the medium carrying component to the separation component.
  • the sampling signal includes a first sampling signal and a second sampling signal;
  • the edge signal includes a rising edge signal;
  • the edge time point includes a first edge time point; when detecting from the sampling signal When the edge signal is reached, the step of determining the corresponding edge time point when the edge signal is detected includes:
  • the second level type is a low level, it is determined that the time point when the rising edge signal is detected is the first edge time point.
  • the sampling signal includes a first sampling signal and a second sampling signal;
  • the edge signal includes a falling edge signal;
  • the edge time point includes a second edge time point; when detecting from the sampling signal When the edge signal is reached, the step of determining the corresponding edge time point when the edge signal is detected includes:
  • the third level type is a high level, it is determined that the time point at which the falling edge signal is detected is the second edge time point.
  • the step of using a preset motor to control the movement of the medium carrying component to the separation component according to the edge signal and the first level type includes:
  • a preset motor is used to stop moving the medium carrying component to the separation component.
  • the step of using a preset motor to control the movement of the medium carrying component to the separation component according to the edge signal and the first level type includes:
  • a preset motor is used to stop moving the medium carrying component to the separation component.
  • the step of using a preset motor to control the movement of the medium carrying component to the separation component according to the edge signal and the level type further includes:
  • the motor is used to keep moving the medium carrying component to the separation component.
  • the step of using a preset motor to control the movement of the medium carrying component to the separation component according to the edge signal and the level type further includes:
  • the motor is used to keep moving the medium carrying component to the separation component.
  • the embodiment of the present invention also discloses a device for realizing motor control based on FPGA, and the device includes:
  • the pulse signal acquisition module is used to acquire the pulse signal generated by the preset detection component when the preset medium carrying component moves to the preset separation component;
  • a sampling module configured to sample the pulse signal according to a preset clock frequency to obtain a sampling signal
  • An edge time point determination module configured to determine the corresponding edge time point when the edge signal is detected when an edge signal is detected from the sampling signal
  • the target time point determination module is used to determine the target time point after the preset time from the edge time point;
  • a first level type determining module configured to determine the first level type of the pulse signal detected at the target time point
  • the medium carrying component movement control module is configured to use a preset motor to control the movement of the medium carrying component to the separation component according to the edge signal and the first level type.
  • the sampling signal includes a first sampling signal and a second sampling signal;
  • the edge signal includes a rising edge signal;
  • the edge time point includes a first edge time point;
  • the edge time point determination module includes:
  • a second level type determining module configured to determine the second level type of the second sampling signal when the rising edge signal is detected from the first sampling signal
  • the first edge time point determination module is configured to determine the time point at which the rising edge signal is detected as the first edge time point when the second level type is a low level.
  • the sampling signal includes a first sampling signal and a second sampling signal;
  • the edge signal includes a falling edge signal;
  • the edge time point includes a second edge time point;
  • the edge time point determination module includes:
  • the third level type determining module is configured to determine the third level type of the second sampling signal when the falling edge signal is detected from the first sampling signal;
  • the second edge time point determination module is configured to determine the time point when the falling edge signal is detected as the second edge time point when the third level type is a high level.
  • the media bearing component movement control module includes:
  • the first stop movement control module is configured to use a preset motor to stop moving the medium carrying component to the separation component when the edge signal is the rising edge signal and the first level type is high level .
  • the media bearing component movement control module includes:
  • the second stop movement control module is configured to use a preset motor to stop moving the medium carrying component to the separation component when the edge signal is the falling edge signal and the first level type is low level .
  • the media bearing assembly movement control module further includes:
  • the first movement control module is used for when the edge signal is the rising edge signal and the level type is low level, the motor is used to keep moving the medium carrying component to the separation component.
  • the media bearing assembly movement control module further includes:
  • the second movement control module is used for when the edge signal is the falling edge signal and the level type is a high level, the motor is used to keep moving the medium carrying component to the separation component.
  • the embodiment of the present invention also discloses an electronic device, including a memory and a processor, and a computer program is stored in the memory.
  • the computer program is executed by the processor, the processor is executed as in the embodiment of the present invention.
  • the embodiment of the present invention also discloses a computer program, including computer readable code, when the computer readable code runs on a computing processing device, it causes the computing processing device to execute the FPGA-based A method to achieve motor control.
  • the embodiment of the present invention also discloses a computer-readable storage medium in which the computer program as described in the embodiment of the present invention is stored.
  • the embodiment of the present invention includes the following advantages: the embodiment of the present invention determines the detected target time point from the edge time point after the preset time by determining the edge time point of the edge signal in the sampling signal obtained by sampling the pulse signal.
  • the first level type of the received pulse signal is used to determine whether to control the medium carrying component to move to the separation component according to the edge signal and the first level type. This avoids the problem that the pulse waveform of the detection component is jittered within the preset time due to the superimposition of the effect of the medium hardness, so that the movement of the medium carrying component to the separation component stops prematurely.
  • FIG. 1 schematically shows a schematic diagram of a structure of media separation inside a container according to an embodiment of the present invention
  • FIG. 2 schematically shows a schematic diagram of a signal feedback structure in a medium separation process according to an embodiment of the present invention
  • FIG. 3 schematically shows a waveform diagram of a pulse signal generated by the detection component during the movement of the medium carrying component to the separation component according to the embodiment of the present invention
  • Fig. 4 schematically shows a step flow chart of an embodiment of a method for implementing motor control based on FPGA according to an embodiment of the present invention
  • Fig. 5 schematically shows a step flow chart of an embodiment of a method for implementing motor control based on FPGA according to an embodiment of the present invention
  • FIG. 6 schematically shows a schematic diagram of a method for detecting a rising edge of a detection component according to an embodiment of the present invention
  • FIG. 7 schematically shows a schematic diagram of a method for obtaining a target time point according to an embodiment of the present invention
  • FIG. 8 schematically shows a step flow chart of an embodiment of a method for implementing motor control based on FPGA according to an embodiment of the present invention
  • Fig. 9 schematically shows a structural block diagram of an embodiment of an apparatus for implementing motor control based on FPGA according to an embodiment of the present invention.
  • Fig. 10 schematically shows a block diagram of an electronic device for performing the method according to the present invention
  • Fig. 11 schematically shows a storage unit for holding or carrying program codes for implementing the method according to the present invention.
  • FIG. 1 there is schematically shown a schematic structural diagram of a medium separation inside a container according to an embodiment of the present invention, including a separation component 101, a detection component 102, a medium carrying component 103 and a motor 104; wherein, the separation component 101 is provided There is a separation element 1011.
  • the detection component 102 is used to determine the contact state between the medium and the separation element 101.
  • the detection component 102 may be an infrared sensor. The contact state of the element 101.
  • the separating element 101 is used to bring the medium out of the container through friction and squeezing force with the medium.
  • a medium can be placed on the surface of the medium carrying component 103, and the movement of the medium carrying component 103 to the separating component 101 can be controlled by the motor 104 to maintain a certain squeezing force between the medium and the separating element 101, which is convenient for the separating element 101 to bring the medium with friction. Out of the container.
  • the container involved in the embodiment of the present invention is a container that can store media, including but not limited to a cash box for storing banknotes, a bill box for storing bills, and the like.
  • the upper surface of the medium carrying component 103 can be used for stacking media.
  • the medium carrying component 103 can move vertically in the direction of gravity or move laterally in the horizontal direction.
  • the separation assembly 101 can rotate with the center point as the center of the circle to drive the separation element to rotate, and the separation element can bring the medium out of the container through contact and friction with the medium.
  • FIG. 2 a schematic diagram of a signal feedback structure in a medium separation process according to an embodiment of the present invention is schematically shown, including structural components, springs, detection components, and medium bearing components.
  • the detection component can be installed on the top of the container and consists of a light-emitting end and a receiving end; it can form a light path to obtain information about occlusion and non-occlusion according to the light path.
  • Structural components can be used for transmission media.
  • the spring can provide effective resistance to the structural component so that the structural component can drive the medium.
  • the media carrying component moves to the separation component until it touches the structural component, if it continues to move to the separation component, it will squeeze one side of the structural component; the structural component moves in an arc according to the squeezing force, which will squeeze the spring , Thereby changing the squeezing force between the separating element and the medium.
  • the detection component When the spring is deformed to a certain degree, the detection component will form a closed loop of the light path, thereby obtaining occlusion information.
  • the disadvantage of the prior art is that with the separation of the medium, the original squeezing force on the medium will gradually be released, and there will be a state change between the medium and the separating element: tight-loose-no contact.
  • the top detection component will have a change from shading to no shading, and the pulse signal of the detection component will have a high level to low level change (the level of the pulse signal changes according to the state and electrical The corresponding relationship of the level is determined, here it is assumed that the occlusion corresponds to the high level).
  • the medium carrying component After detecting the change of the pulse signal of the detection component, the medium carrying component will carry the medium to the separation component.
  • FIG. 3 schematically shows the pulse waveform 1 shown in the waveform diagram of the pulse signal generated by the detection component during the movement of the medium carrying component to the separation component of the present invention; this form will maintain the millisecond level (specific magnitude and spring selection) Related).
  • waveform 1 Comparing waveform 1 and waveform 2, we can see that the waveform from t0 to tn is the process of detecting the state of the component from unobstructed to obstructed.
  • the waveforms from t1 to tn in Wave 1 are the detection components in the unobstructed state, because the structural components have resistance to the medium, which causes the rigidity of the medium to be continuously superimposed, which makes the medium jitter; therefore, it should not stop moving during this process.
  • Media bearing components but should stop moving the media bearing components at tn.
  • one of the core concepts of the embodiments of the present invention is to provide a method for implementing motor control based on FPGA.
  • the system clock is used for timing, after a preset time, the level type of the pulse information generated by the detection component is detected, and the movement of the medium carrying component to the separation component is stopped when the edge signal and the level type meet the preset conditions.
  • FIG. 4 there is schematically shown a step flow chart of an embodiment of a method for implementing motor control based on FPGA according to an embodiment of the present invention, which may specifically include the following steps:
  • Step 401 Acquire a pulse signal generated by the preset detection component when the preset medium carrying component moves to the preset separation component;
  • the detection component may be an infrared sensor, and the infrared sensor includes a sending end and a receiving end.
  • the sending end can send infrared rays to the medium on the medium bearing assembly, and the receiving end can generate a corresponding pulse signal according to the receiving situation of the infrared rays returned by the medium.
  • the magnitude of the pulse signal collected by the detection component in this process is on the order of milliseconds.
  • an FPGA can be used (Field-Programmable Gate Array) collects pulse signals.
  • the response speed of FPGA can easily reach the nanosecond level, and the accuracy can reach the picosecond level, so the pulse signal generated by the detection component can be accurately collected.
  • the pulse signal generated by the detection component can be obtained in real time through the FPGA during the movement of the medium carrying component to the separation component.
  • Step 402 sampling the pulse signal according to a preset clock frequency to obtain a sampling signal
  • the pulse signal After acquiring the pulse signal of the detection component, the pulse signal can be sampled once or twice to obtain the sampled signal. Generally, two samplings are performed to eliminate the metastable state in the sampling process.
  • the pulse signal can be sampled by the external crystal oscillator source through the system clock generated by the on-chip clock management unit to obtain the sampling signal.
  • Step 403 When an edge signal is detected from the sampling signal, determine the corresponding edge time point when the edge signal is detected;
  • the time point at which the edge signal is detected can be determined as the edge time point.
  • time t1 is the edge time point when the edge signal is detected.
  • Step 404 Determine a target time point after a preset time from the edge time point
  • the system clock is used for timing, and the target time point after the timing duration is obtained.
  • edge signals generated in the pulse signal are ignored, such as the edge signals generated at t2 and t3 in Figure 3, so as to avoid the detection of the edge signal generated by the media jitter and the premature stop of the media carrying component to the separation component The problem of the moving process.
  • the edge signal generated by the media jitter may be detected and the movement of the media carrying component to the separation component is stopped in advance, so the timing duration should be such that the target time point falls after tn .
  • the timing duration is affected by the mechanical design. For example, the spring elasticity and the installation angle of the detection component will all affect the timing duration. Therefore, actual measurement is required in actual applications.
  • the timing duration is 1 millisecond.
  • Step 405 Determine the first level type of the pulse signal detected at the target time point
  • the first level type of the pulse signal at the target time point can be obtained. According to the first level type, the blocking state of the detection component at the target time point can be judged, and then the contact state between the separation element and the medium can be judged.
  • Step 406 According to the edge signal and the first level type, the motor is used to control the movement of the medium carrying component to the separation component.
  • the waveform of the pulse signal of the detection component is waveform 2 in Figure 3
  • the time point at which the first edge signal appears is tn. From the waveform, it can be seen that the detection component enters the blocking state at this time. Stop moving the media carrier assembly. However, in reality, the medium bearing assembly will continue to move for a timed period of time at this time.
  • s unit unit displacement
  • t unit the time consumed by unit displacement without load
  • n the number of standard media sheets placed in the media carrying component
  • the first electrical level of the pulse signal detected at the target time point after the preset time is determined from the edge time point.
  • the level type is used to determine whether to control the movement of the medium carrying component according to the edge signal and the first level type. This avoids the problem of premature stop of the movement of the medium carrying component due to the superimposition of the hardness of the medium.
  • FIG. 5 there is schematically shown a step flow chart of an embodiment of a method for implementing motor control based on FPGA in an embodiment of the present invention.
  • the pulse signal when the pulse signal is at a high level, it indicates that the detection component is in a blocked state. .
  • the rising edge signal in the sampling signal when the rising edge signal in the sampling signal is detected, it indicates that the detection component enters the shielding state.
  • it can include the following steps:
  • Step 501 when the preset medium carrying component moves to the preset separation component, obtain the pulse signal generated by the preset detection component;
  • the detection component may be an infrared detection component, and the infrared detection component includes a sending end and a receiving end.
  • the sending end can send infrared rays to the medium on the medium bearing assembly, and generate a corresponding pulse signal according to the receiving end of the receiving end of the infrared rays returned to the medium.
  • the medium separation process is extremely fast, and the magnitude of the pulse signal collected by the detection component in this process is on the order of milliseconds.
  • an FPGA can be used. Collection of pulse signals. The response speed of FPGA can easily reach the nanosecond level, and the accuracy can reach the picosecond level, so the pulse signal generated by the detection component can be accurately collected.
  • the pulse signal generated by the detection component can be obtained in real time through the FPGA during the movement of the medium carrying component to the separation component.
  • Step 502 sampling the pulse signal according to a preset clock frequency to obtain a sampling signal
  • the pulse signal After acquiring the pulse signal of the detection component, the pulse signal can be sampled once or twice to obtain the sampled signal. Generally, two samplings are performed to eliminate the metastable state in the sampling process.
  • the pulse signal can be sampled by the external crystal oscillator source through the system clock generated by the on-chip clock management unit to obtain the sampling signal.
  • Step 503 When the rising edge signal is detected from the first sampling signal, determine the second level type of the second sampling signal;
  • the second level type of the second sampling signal can be acquired at the same time, so as to eliminate the metastable state in the sampling process according to the second sampling signal.
  • Step 504 When the second level type is a low level, determine that the time point when the rising edge signal is detected is the first edge time point;
  • FIG. 6 a schematic diagram of a method for detecting a rising edge of a detection component according to an embodiment of the present invention is schematically shown.
  • the pulse signal of the detection component is sampled twice according to the system clock to obtain the first sampling signal and the second sampling signal respectively.
  • the time point at which the first sampling signal has a rising edge and the second sampling signal is at a low level is determined as the time point at which the rising edge of the pulse signal of the detection component is detected , And generate the waveform diagram of the rising edge signal of the pulse signal of the detection component accordingly.
  • Step 505 Determine a target time point after a preset time from the edge time point
  • the system clock is used for timing, and the target time point after the timing duration is obtained.
  • Step 506 Determine the first level type of the pulse signal detected at the target time point
  • the first level type of the pulse signal at the target time point can be obtained. According to the first level type, the blocking state of the detection component at the target time point can be judged, and then the contact state between the separation element and the medium can be judged.
  • FIG. 7 a schematic diagram of a method for obtaining a target time point according to an embodiment of the present invention is schematically shown. As shown in FIG. 7, after the first rising edge signal is detected, timing is performed, and the It is assumed that the rising edge signal detected after the timing starts is ignored within the time, and the pulse signal of the detection component is reacquired when the timing ends.
  • Step 507 When the edge signal is the rising edge signal and the first level type is high level, use the motor to stop moving the medium carrying component to the separation component;
  • Step 508 When the edge signal is the rising edge signal and the level type is low, the motor is used to keep moving the medium carrying component to the separation component.
  • the first electrical level of the pulse signal detected at the target time point after the preset time is determined from the edge time point.
  • the flat type is used to determine whether to control the movement of the medium carrying component to the separation component according to the edge signal and the first level type. This avoids the problem that, due to the superimposition of the hardness of the medium, the pulse waveform of the detection component is jittered within the preset time, so that the movement process of the medium carrying component to the detection component stops prematurely.
  • FIG. 8 it schematically shows a step flow chart of an embodiment of a method for implementing motor control based on FPGA in an embodiment of the present invention.
  • the pulse signal when the pulse signal is at a low level, it indicates that the detection component is in a blocking state. .
  • the falling edge signal in the sampling signal when detected, it indicates that the detection component enters the blocking state. Specifically, it can include the following steps:
  • Step 801 when the preset medium carrying component moves to the preset separation component, obtain the pulse signal generated by the preset detection component;
  • the pulse signal generated by the detection component can be obtained in real time through the FPGA during the movement of the medium carrying component to the separation component.
  • Step 802 sampling the pulse signal according to a preset clock frequency to obtain a sampling signal
  • the pulse signal After acquiring the pulse signal of the detection component, the pulse signal can be sampled once or twice to obtain the sampled signal. Generally, two samplings are performed to eliminate the metastable state in the sampling process.
  • the pulse signal can be sampled by the external crystal oscillator source through the system clock generated by the on-chip clock management unit to obtain the sampling signal.
  • Step 803 When the falling edge signal is detected from the first sampling signal, determine the third level type of the second sampling signal;
  • the third level type of the second sampling signal can be acquired at the same time, so as to eliminate the metastable state in the sampling process according to the second sampling signal.
  • Step 804 When the third level type is a high level, determine that the time point when the falling edge signal is detected is the second edge time point;
  • the second level type is a low level, it can be determined that the time point at which the falling edge signal is detected is the second edge time point.
  • Step 805 Determine a target time point after a preset time from the edge time point
  • the system clock is used for timing, and the target time point after the timing duration is obtained.
  • Step 806 Determine the first level type of the pulse signal detected at the target time point
  • the first level type of the pulse signal at the target time point can be obtained. According to the first level type, the blocking state of the detection component at the target time point can be judged, and then the contact state between the separation element and the medium can be judged.
  • Step 807 When the edge signal is the falling edge signal and the first level type is low level, stop moving the medium carrying component to the separation component in the container;
  • Step 808 When the edge signal is the falling edge signal and the level type is high level, continue to move the medium bearing component to the separation component in the container.
  • the first electrical level of the pulse signal detected at the target time point after the preset time is determined from the edge time point.
  • the flat type is used to determine whether to control the movement of the medium carrying component to the separation component according to the edge signal and the first level type. This avoids the problem that the pulse waveform of the detection component is jittered within the preset time, which causes the movement of the medium carrying component to the detection component to stop prematurely due to the superimposition of the hardness of the medium.
  • FIG. 9 it schematically shows a structural block diagram of an embodiment of an apparatus for implementing motor control based on FPGA according to an embodiment of the present invention, which may specifically include the following modules:
  • the pulse signal acquisition module 901 is configured to acquire the pulse signal generated by the preset detection component when the preset medium carrying component moves to the preset separation component;
  • the sampling module 902 is configured to sample the pulse signal according to a preset clock frequency to obtain a sampling signal
  • An edge time point determination module 903, configured to determine the corresponding edge time point when the edge signal is detected when an edge signal is detected from the sampling signal;
  • the target time point determination module 904 is configured to determine a target time point after a preset time from the edge time point;
  • the first level type determining module 905 is configured to determine the first level type of the pulse signal detected at the target time point
  • the medium carrying component movement control module 906 is configured to use a preset motor to control the movement of the medium carrying component to the separation component according to the edge signal and the first level type.
  • the sampling signal includes a first sampling signal and a second sampling signal;
  • the edge signal includes a rising edge signal;
  • the edge time point includes a first edge time point;
  • the edge time point determination module Can include:
  • a second level type determining module configured to determine the second level type of the second sampling signal when the rising edge signal is detected from the first sampling signal
  • the first edge time point determination module is configured to determine the time point at which the rising edge signal is detected as the first edge time point when the second level type is a low level.
  • the sampling signal includes a first sampling signal and a second sampling signal;
  • the edge signal includes a falling edge signal;
  • the edge time point includes a second edge time point;
  • the edge time point determination module Can include:
  • the third level type determining module is configured to determine the third level type of the second sampling signal when the falling edge signal is detected from the first sampling signal;
  • the second edge time point determination module is configured to determine the time point when the falling edge signal is detected as the second edge time point when the second level type is a high level.
  • the media bearing assembly movement control module may include:
  • the first stop movement control module is configured to use a preset motor to stop moving the medium carrying component to the separation component when the edge signal is the rising edge signal and the first level type is high level .
  • the media bearing assembly movement control module may include:
  • the second stop movement control module is configured to use a preset motor to stop moving the medium carrying component to the separation component when the edge signal is the falling edge signal and the first level type is low level .
  • the moving control module to the separation component may further include:
  • the first movement control module is configured to: when the edge signal is the rising edge signal and the level type is a low level, the motor is used to keep moving the medium carrying component to the separation component.
  • the media bearing assembly movement control module may further include:
  • the second movement control module is used for when the edge signal is the falling edge signal and the level type is a high level, the motor is used to keep moving the medium carrying component to the separation component.
  • the embodiment of the present invention also discloses an electronic device, including a memory and a processor, and a computer program is stored in the memory.
  • the computer program is executed by the processor, the processor is executed as in the embodiment of the present invention.
  • the embodiment of the present invention also discloses a computer program, including computer readable code, which when the computer readable code runs on a computing processing device, causes the computing processing device to execute any one of the methods described in the embodiments of the present invention.
  • the described method is based on FPGA to realize motor control.
  • the embodiment of the present invention also discloses a computer-readable storage medium in which the computer program as described in the embodiment of the present invention is stored.
  • the computer-readable recording medium includes any mechanism for storing or transmitting information in a form readable by a computer (eg, a computer).
  • machine-readable media include read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash storage media, electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves). , Infrared signal, digital signal, etc.) etc.
  • the device embodiments described above are merely illustrative.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network units.
  • Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of the embodiments. Those of ordinary skill in the art can understand and implement it without creative work.
  • the various component embodiments of the present invention may be implemented by hardware, or by software modules running on one or more processors, or by a combination of them.
  • a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the computing processing device according to the embodiments of the present invention.
  • DSP digital signal processor
  • the present invention can also be implemented as a device or device program (for example, a computer program and a computer program product) for executing part or all of the methods described herein.
  • Such a program for realizing the present invention may be stored on a computer-readable medium, or may have the form of one or more signals.
  • Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.
  • FIG. 10 shows a computing processing device that can implement the method according to the present invention.
  • the computing processing device traditionally includes a processor 1010 and a computer program product in the form of a memory 1020 or a computer readable medium.
  • the memory 1020 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM.
  • the memory 1020 has a storage space 1030 for executing program codes 1031 of any method steps in the above methods.
  • the storage space 1030 for program codes may include various program codes 1031 respectively used to implement various steps in the above method. These program codes can be read from or written into one or more computer program products.
  • Such computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards, or floppy disks.
  • Such a computer program product is usually a portable or fixed storage unit as described with reference to FIG. 11.
  • the storage unit may have storage segments, storage spaces, etc. arranged similarly to the memory 1020 in the computing processing device of FIG. 10.
  • the program code can be compressed in an appropriate form, for example.
  • the storage unit includes computer-readable code 1031', that is, code that can be read by a processor such as 1010, which, when run by a computing processing device, causes the computing processing device to execute the method described above. The various steps.
  • any reference signs placed between parentheses should not be constructed as a limitation to the claims.
  • the word “comprising” does not exclude the presence of elements or steps not listed in the claims.
  • the word “a” or “an” preceding an element does not exclude the presence of multiple such elements.
  • the invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims listing several devices, several of these devices may be embodied in the same hardware item.
  • the use of the words first, second, and third, etc. do not indicate any order. These words can be interpreted as names.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

一种基于FPGA实现电机控制的方法和装置，所述方法包括：当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点；确定从所述边沿时间点起，预设时间后的目标时间点；确定在所述目标时间点检测到的所述脉冲信号的第一电平类型；根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动。通过本发明实施例，避免了由于介质硬度作用叠加导致的，预设时间内检测组件脉冲波形抖动使得介质承载组件向所述分离组件移动提前停止的问题。

Description

一种基于FPGA实现电机控制的方法和装置 技术领域
本发明涉及移动控制技术领域，特别是涉及一种基于FPGA实现电机控制的方法和一种基于FPGA实现电机控制的装置。
背景技术
用于存储介质的容器往往会涉及到如何分离容器内介质的问题，现有的容器内介质的分离往往是通过容器内分离组件与介质之间的摩擦，来实现将介质从容器内分离出来的技术效果。
随着介质分离，原来对介质的挤压力会逐渐释放，介质与分离元件的状态会存在：紧-松-不接触，这样的状态过程；对应检测组件会存在遮挡-不遮挡的变化，在检测到检测组件的状态变化后，介质承载组件会带着介质向所述分离组件移动。然而，在弹簧的作用力下，检测组件的状态在由不遮挡-遮挡的过程中，由于介质硬度作用叠加，导致介质抖动，可能会造成检测组件的脉冲信号形成抖动。
发明内容
鉴于上述问题，提出了本发明实施例以便提供一种克服上述问题或者至少部分地解决上述问题的一种基于FPGA实现电机控制的方法和相应的一种基于FPGA实现电机控制的装置，通过FPGA的运算与控制技术，避免了由于介质硬度作用叠加导致的，预设时间内检测组件脉冲波形抖动使得介质承载组件向所述分离组件移动提前停止的问题。
本发明实施例公开了一种于基于FPGA实现电机控制的方法，所述的方法包括：
当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；
按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；
当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点；
确定从所述边沿时间点起，预设时间后的目标时间点；
确定在所述目标时间点检测到的所述脉冲信号的第一电平类型；
根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动。
可选地，所述采样信号包括第一采样信号和第二采样信号；所述边沿信号包括上升沿信号；所述边沿时间点包括第一边沿时间点；所述当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点的步骤，包括：
当从所述第一采样信号中检测到所述上升沿信号时，确定所述第二采样信号的第二电平类型；
当所述第二电平类型为低电平时，确定检测到所述上升沿信号的时间点为所述第一边沿时间点。
可选地，所述采样信号包括第一采样信号和第二采样信号；所述边沿信号包括下降沿信号；所述边沿时间点包括第二边沿时间点；所述当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点的步骤，包括：
当从所述第一采样信号中检测到所述下降沿信号时，确定所述第二采样信号的第三电平类型；
当所述第三电平类型为高电平时，确定检测到所述下降沿信号的时间点为所述第二边沿时间点。
可选地，所述根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动的步骤，包括：
当所述边沿信号为所述上升沿信号，且所述第一电平类型为高电平时，采用预设电机停止向所述分离组件移动所述介质承载组件。
可选地，所述根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动的步骤，包括：
当所述边沿信号为所述下降沿信号，且所述第一电平类型为低电平时，采用预设电机停止向所述分离组件移动所述介质承载组件。
可选地，所述根据所述边沿信号和所述电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动的步骤，还包括：
当所述边沿信号为所述上升沿信号，且所述电平类型为低电平时，采用所述电机保持向所述分离组件移动所述介质承载组件。
可选地，所述根据所述边沿信号和所述电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动的步骤，还包括：
当所述边沿信号为所述下降沿信号，且所述电平类型为高电平时，采用所述电机保持向所述分离组件移动所述介质承载组件。
本发明实施例还公开了一种基于FPGA实现电机控制的装置，所述的装置包括：
脉冲信号获取模块，用于当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；
采样模块，用于按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；
边沿时间点确定模块，用于当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点；
目标时间点确定模块，用于确定从所述边沿时间点起，预设时间后的目标时间点；
第一电平类型确定模块，用于确定在所述目标时间点检测到的所述脉冲 信号的第一电平类型；
介质承载组件移动控制模块，用于根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动。
可选地，所述采样信号包括第一采样信号和第二采样信号；所述边沿信号包括上升沿信号；所述边沿时间点包括第一边沿时间点；所述边沿时间点确定模块，包括：
第二电平类型确定模块，用于当从所述第一采样信号中检测到所述上升沿信号时，确定所述第二采样信号的第二电平类型；
第一边沿时间点确定模块，用于当所述第二电平类型为低电平时，确定检测到所述上升沿信号的时间点为所述第一边沿时间点。
可选地，所述采样信号包括第一采样信号和第二采样信号；所述边沿信号包括下降沿信号；所述边沿时间点包括第二边沿时间点；所述边沿时间点确定模块，包括：
第三电平类型确定模块，用于当从所述第一采样信号中检测到所述下降沿信号时，确定所述第二采样信号的第三电平类型；
第二边沿时间点确定模块，用于当所述第三电平类型为高电平时，确定检测到所述下降沿信号的时间点为所述第二边沿时间点。
可选地，所述介质承载组件移动控制模块，包括：
第一停止移动控制模块，用于当所述边沿信号为所述上升沿信号，且所述第一电平类型为高电平时，采用预设电机停止向所述分离组件移动所述介质承载组件。
可选地，所述介质承载组件移动控制模块，包括：
第二停止移动控制模块，用于当所述边沿信号为所述下降沿信号，且所述第一电平类型为低电平时，采用预设电机停止向所述分离组件移动所述介质承载组件。
可选地，所述介质承载组件移动控制模块，还包括：
第一移动控制模块，用于当所述边沿信号为所述上升沿信号，且所述电平类型为低电平时，采用所述电机保持向所述分离组件移动所述介质承载组件。
可选地，所述介质承载组件移动控制模块，还包括：
第二移动控制模块，用于当所述边沿信号为所述下降沿信号，且所述电平类型为高电平时，采用所述电机保持向所述分离组件移动所述介质承载组件。
本发明实施例还公开了一种电子设备，包括存储器及处理器，所述存储器中储存有计算机程序，所述计算机程序被所述处理器执行时，使得所述处理器执行如本发明实施例所述的基于FPGA实现电机控制的方法的步骤。
本发明实施例还公开了一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行根据本发明实施例所述的基于FPGA实现电机控制的方法。
本发明实施例还公开了一种计算机可读存储介质，其中存储了如本发明实施例所述的计算机程序。
本发明实施例包括以下优点：本发明实施例通过确定对脉冲信号进行采样得到的采样信号中的边沿信号的边沿时间点，来确定从边沿时间点起，预设时间后的目标时间点所检测到的脉冲信号的第一电平类型，以根据边沿信号和第一电平类型来判断是否控制介质承载组件向所述分离组件移动。从而避免了由于介质硬度作用叠加导致的，预设时间内检测组件脉冲波形抖动使得介质承载组件向所述分离组件移动提前停止的问题。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性地示出了本发明实施例的一种容器内部进行介质分离结构示意图；
图2示意性地示出了本发明实施例的一种介质分离过程中的信号反馈结构示意图；
图3示意性地示出了本发明实施例的介质承载组件向分离组件移动过程中检测组件产生的脉冲信号的波形图；
图4示意性地示出了本发明实施例的一种基于FPGA实现电机控制的方法实施例的步骤流程图；
图5示意性地示出了本发明实施例的一种基于FPGA实现电机控制的方法实施例的步骤流程图；
图6示意性地示出了本发明实施例的一种检测检测组件上升沿的方法示意图；
图7示意性地示出了本发明实施例的一种获取目标时间点的方法示意图；
图8示意性地示出了本发明实施例的一种基于FPGA实现电机控制的方法实施例的步骤流程图；
图9示意性地示出了本发明实施例的一种基于FPGA实现电机控制的装置实施例的结构框图。
图10示意性地示出了用于执行根据本发明的方法的电子设备的框图；
图11示意性地示出了用于保持或者携带实现根据本发明的方法的程序代码的存储单元。
具体实施例
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参照图1，示意性地示出了本发明实施例的一种容器内部进行介质分离的结构示意图，包括分离组件101、检测组件102、介质承载组件103和电机104；其中，分离组件101上设置有分离元件1011。
其中，检测组件102用于判断介质与分离元件101的接触状态，在一个示例中，该检测组件102可以为红外线传感器，红外线传感器通过向介质表面发射红外线，根据红外线的返回情况来判断介质与分离元件101的接触状态。
分离元件101用于通过与介质之间的摩擦力和挤压力来将介质带出容器。
介质承载组件103表面可放置介质，通过电机104控制介质承载组件103向所述分离组件101移动可以使得介质与分离元件101之间保持一定的挤压力，便于分离元件101通过摩擦力将介质带出容器。
其中，本发明实施例所涉及的容器为可存储介质的容器，包括但不限于存储钞票的钞箱、存储票据的票据箱等。介质承载组件103上表面可用于堆叠介质，介质承载组件103在不同的应用场景中，可以沿重力方向垂直移动，也可以沿水平方向横向移动。分离组件101可以中心点为圆心进行旋转，以带动分离元件转动，分离元件可通过与介质的接触摩擦将介质带出容器。
如图2所示，示意性地示出了本发明实施例的一种介质分离过程中的信号反馈结构示意图，包括结构组件，弹簧，检测组件和介质承载组件。
其中，检测组件可安装于容器顶部，由发光端、接收端组成；可形成光路，以根据光路获取遮挡、不遮挡信息。
结构组件可用于传动介质。
弹簧可为结构组件提供有效的阻力，以使结构组件可以传动介质。
在实际应用中，介质承载组件向分离组件移动直至接触到结构组件后，如果继续向分离组件移动会挤压结构组件一侧；结构组件根据挤压力大小按弧度移动，会对弹簧产生挤压，从而改变分离元件与介质间的挤压力。当弹簧形变到一定程度时，检测组件会形成光路闭环，从而得到遮挡信息。
现有技术的缺陷在于，随着介质的分离，原来对介质的挤压力会逐渐释放，介质与分离元件之间会存在：紧-松-不接触，这样的状态变化。对应地，顶部检测组件会存在遮挡-不遮挡的变化，检测组件的脉冲信号会存在高电平-低电平的变化(脉冲信号的电平变化方式根据所设置的顶部检测组件的状态与电平的对应关系来确定，此处假设遮挡对应高电平)。在检测到检测组件的脉冲信号变化后，介质承载组件会带着介质向分离组件移动。然而， 在弹簧的作用力下，检测组件的状态在由不遮挡-遮挡的过程中，由于介质硬度作用叠加，导致介质抖动，可能会造成检测组件的脉冲信号形成抖动，产生如图3(图3示意性地示出了本发明的介质承载组件向分离组件移动过程中检测组件产生的脉冲信号的波形图)所示的脉冲波形1；该形态会保持毫秒级(具体量级与弹簧选型相关)。
对比波形1和波形2可知，t0到tn段波形是检测组件状态由不遮挡到遮挡的过程。而波形1中的t1至tn段波形，是检测组件处于不遮挡状态下，因为结构组件对介质存在阻力导致介质硬度作用不断叠加，使得介质抖动所产生的；因此在这个过程中不应该停止移动介质承载组件，而是应该在tn的时候停止移动介质承载组件。
然而在实际应用中，当出现波形1时，在t1至tn段采样到高电平，便会提前停止介质承载组件向所述分离组件移动的过程，使得分离元件与介质之间的挤压力和摩擦力不够，出现分空现象。
基于上述问题，本发明实施例的核心构思之一在于，提出了一种基于FPGA实现电机控制的方法，当在介质承载组件向所述分离组件移动的过程中检测到检测组件产生的边沿信号时，通过系统时钟进行定时，经过预设时间后，检测检测组件产生的脉冲信息的电平类型，在边沿信号和电平类型满足预设条件的情况下停止向所述分离组件移动介质承载组件。
以下通过具体实施例进行说明：
参照图4，示意性地示出了本发明实施例的一种基于FPGA实现电机控制的方法实施例的步骤流程图，具体可以包括如下步骤：
步骤401，当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；
在本发明实施例中，检测组件可以为红外线传感器，该红外线传感器包括发送端和接收端。发送端可以向介质承载组件上的介质发送红外线，接收端可以根据介质返回的红外线的接收情况来生成相应的脉冲信号。
在实际的工作场景中，由于介质分离过程极快，检测组件在此过程中采集的脉冲信号的量级为毫秒级，为了准确采集到该脉冲信号，在本发明的一个示例中，可以采用FPGA(Field-Programmable Gate Array，现场可编程门阵列)进行脉冲信号的采集。FPGA的反应速度可以轻易达到纳秒级，精度可达到皮秒级，因此可以准确地采集检测组件产生的脉冲信号。
在本发明实施例中，可以在介质承载组件向所述分离组件移动的过程中，通过FPGA实时获取检测组件产生的脉冲信号。
步骤402，按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；
在获取到检测组件的脉冲信号后，可以对脉冲信号进行一次或二次采样，得到采样信号。一般进行两次采样来消除采样过程中的亚稳态。
具体可以通过外部晶振源经片内时钟管理单元生成的系统时钟来对脉冲信号进行采样，得到采样信号。
步骤403，当从所述采样信号中检测到边沿信号时，确定检测到所述边 沿信号时对应的边沿时间点；
当从采样信号中检测到边沿信号时，可以将检测到边沿信号的时间点确定为边沿时间点。
如当检测到图3波形1中t1时刻的上升沿时，t1时刻即为检测到边沿信号的边沿时间点。
步骤404，确定从所述边沿时间点起，预设时间后的目标时间点；
在确定了边沿时间点后，通过系统时钟进行定时，获取定时时长后的目标时间点。
在定时过程中，会忽略脉冲信号中产生的其他边沿信号，如图3中的t2，t3时刻产生的边沿信号，从而避免因检测到介质抖动产生的边沿信号而提前停止介质承载组件向分离组件移动的过程的问题。
在本发明实施例中，由于目标时间点落在tn之前可能导致检测到介质抖动产生的边沿信号而提前停止介质承载组件向所述分离组件移动，因此定时时长应使得目标时间点落在tn之后。
定时时长的具体数值受机械设计影响，例如弹簧弹性、检测组件安装角度均会影响到定时时长。因此在实际应用中需进行实际测量。在本发明实施例中，定时时长取1毫秒。
步骤405，确定在所述目标时间点检测到的所述脉冲信号的第一电平类型；
在确定了目标时间点后，便可以获取目标时间点处脉冲信号的第一电平类型。根据第一电平类型便可判断在目标时间点处检测组件的遮挡状态，进而判断分离元件与介质之间的接触状态。
步骤406，根据所述边沿信号和所述第一电平类型，采用所述电机控制所述介质承载组件向所述分离组件移动。
在确定了分离元件与介质之间的接触状态后，便可决定是否停止移动介质承载组件。
在本发明一个示例中，当检测组件的脉冲信号的波形为图3的波形2时，出现第一个边沿信号的时间点为tn，从波形可以看出，此时检测组件进入遮挡状态，应停止移动介质承载组件。然而，实际上此时介质承载组件会继续移动定时时长的距离。
根据介质承载组件移动模型v n＝s unit/(t unit±(32*n/1000))
其中，s unit：单位位移量；
t unit：单位位移空载耗时；
n：介质承载组件放置标准介质张数；
可知，在空载和满载的情况下，移动1毫秒的单位位移不足1毫米，分离元件不足以对介质造成过大的挤压力。不会影响介质的正常分离。因此，即使是出现波形2的情况，也可进行正常的介质分离。
本发明实施例通过确定对脉冲信号进行采样得到的采样信号中的边沿信号的边沿时间点，来确定从边沿时间点起，预设时间后的目标时间点所检 测到的脉冲信号的第一电平类型，以根据边沿信号和第一电平类型来判断是否控制介质承载组件移动。从而避免了由于介质硬度作用叠加导致的，预设时间内检测组件脉冲波形抖动使得介质承载组件移动提前停止的问题。
参照图5，示意性地示出了本发明实施例一种基于FPGA实现电机控制的方法实施例的步骤流程图，在本发明实施例中，以脉冲信号为高电平时表示检测组件处于遮挡状态。当检测到采样信号中的上升沿信号时，表示检测组件进入遮挡状态。具体可以包括以下步骤：
步骤501，当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；
在本发明实施例中，检测组件可以为红外线检测组件，该红外线检测组件包括发送端和接收端。发送端可以向介质承载组件上的介质发送红外线，根据接收端对介质返回的红外线的接收情况来生成相应的脉冲信号。
在实际的工作场景中，介质分离过程极快，检测组件在此过程中采集的脉冲信号的量级为毫秒级，为了准确采集到该脉冲信号，在本发明的一个示例中，可以采用FPGA进行脉冲信号的采集。FPGA的反应速度可以轻易达到纳秒级，精度可达到皮秒级，因此可以准确地采集检测组件产生的脉冲信号。
在本发明实施例中，可以在介质承载组件向分离组件移动的过程中，通过FPGA实时获取检测组件产生的脉冲信号。
步骤502，按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；
在获取到检测组件的脉冲信号后，可以对脉冲信号进行一次或二次采样，得到采样信号。一般进行两次采样来消除采样过程中的亚稳态。
具体可以通过外部晶振源经片内时钟管理单元生成的系统时钟来对脉冲信号进行采样，得到采样信号。
步骤503，当从所述第一采样信号中检测到所述上升沿信号时，确定所述第二采样信号的第二电平类型；
当从第一采样信号中检测到上升沿信号时，可以同时获取第二采样信号的第二电平类型，以根据第二采样信号来消除采样过程中的亚稳态。
步骤504，当所述第二电平类型为低电平时，确定检测到所述上升沿信号的时间点为所述第一边沿时间点；
当第二电平类型为低电平时，可以确定检测到上升沿信号的时间点为第一边沿时间点。
参照图6，示意性地示出了本发明实施例的一种检测检测组件上升沿的方法示意图。
如图6所示，按照系统时钟对检测组件的脉冲信号进行两次采样，分别得到第一采样信号和第二采样信号。
在获取到第一采样信号和第二采样信号后，将第一采样信号出现上升沿，且第二采样信号为低电平的时间点确定为检测到检测组件的脉冲信号的上升沿的时间点，依此生成检测组件脉冲信号的上升沿信号的波形图。
步骤505，确定从所述边沿时间点起，预设时间后的目标时间点；
在确定了第一边沿时间点后，通过系统时钟进行定时，获取定时时长后的目标时间点。
步骤506，确定在所述目标时间点检测到的所述脉冲信号的第一电平类型；
在确定了目标时间点后，便可以获取目标时间点处脉冲信号的第一电平类型。根据第一电平类型便可判断在目标时间点处检测组件的遮挡状态，进而判断分离元件与介质之间的接触状态。
如图7所示，示意性地示出了本发明实施例的一种获取目标时间点的方法示意图，如图7所示，在检测到第一个上升沿信号后，会进行定时，在预设时间内忽略定时开始后所检测到的上升沿信号，当定时结束时，重新获取检测组件的脉冲信号。
步骤507，当所述边沿信号为所述上升沿信号，且所述第一电平类型为高电平时，采用所述电机停止向所述分离组件移动所述介质承载组件；
当在采样信号中检测到上升沿信号，且在目标时间点处脉冲信号的电平类型为高电平时，证明检测组件状态已由不遮挡状态转变为遮挡状态，此时需要停止向所述分离组件移动介质承载组件。
步骤508，当所述边沿信号为所述上升沿信号，且所述电平类型为低电平时，采用所述电机保持向所述分离组件移动所述介质承载组件。
当在采样信号中检测到上升沿信号，且在目标时间点处脉冲信号的电平类型为低电平时，证明检测组件仍处在不遮挡状态，此时需要继续向所述分离组件移动介质承载组件。
本发明实施例通过确定对脉冲信号进行采样得到的采样信号中的边沿信号的边沿时间点，来确定从边沿时间点起，预设时间后的目标时间点所检测到的脉冲信号的第一电平类型，以根据边沿信号和第一电平类型来判断是否控制介质承载组件向分离组件移动。从而避免了由于介质硬度作用叠加导致的，预设时间内检测组件脉冲波形抖动使得介质承载组件向所述检测组件的移动过程提前停止的问题。
参照图8，示意性地示出了本发明实施例一种基于FPGA实现电机控制的方法实施例的步骤流程图，在本发明实施例中，以脉冲信号为低电平时表示检测组件处于遮挡状态。当检测到采样信号中的下降沿信号时，表示检测组件进入遮挡状态。具体可以包括以下步骤：
步骤801，当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；
在本发明实施例中，可以在介质承载组件向分离组件移动的过程中，通过FPGA实时获取检测组件产生的脉冲信号。
步骤802，按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；
在获取到检测组件的脉冲信号后，可以对脉冲信号进行一次或二次采样，得到采样信号。一般进行两次采样来消除采样过程中的亚稳态。
具体可以通过外部晶振源经片内时钟管理单元生成的系统时钟来对脉冲信号进行采样，得到采样信号。
步骤803，当从所述第一采样信号中检测到所述下降沿信号时，确定所述第二采样信号的第三电平类型；
当从第一采样信号中检测到下降沿信号时，可以同时获取第二采样信号的第三电平类型，以根据第二采样信号来消除采样过程中的亚稳态。
步骤804，当所述第三电平类型为高电平时，确定检测到所述下降沿信号的时间点为所述第二边沿时间点；
当第二电平类型为低电平时，可以确定检测到下降沿信号的时间点为第二边沿时间点。
步骤805，确定从所述边沿时间点起，预设时间后的目标时间点；
在确定了第二边沿时间点后，通过系统时钟进行定时，获取定时时长后的目标时间点。
步骤806，确定在所述目标时间点检测到的所述脉冲信号的第一电平类型；
在确定了目标时间点后，便可以获取目标时间点处脉冲信号的第一电平类型。根据第一电平类型便可判断在目标时间点处检测组件的遮挡状态，进而判断分离元件与介质之间的接触状态。
步骤807，当所述边沿信号为所述下降沿信号，且所述第一电平类型为低电平时，停止在所述容器内向所述分离组件移动所述介质承载组件；
当在采样信号中检测到下降沿信号，且在目标时间点处脉冲信号的电平类型为低电平时，证明检测组件状态已由不遮挡状态转变为遮挡状态，此时需要停止向分离组件移动介质承载组件。
步骤808，当所述边沿信号为所述下降沿信号，且所述电平类型为高电平时，继续在所述容器内向所述分离组件移动所述介质承载组件。
当在采样信号中检测到下降沿信号，且在目标时间点处脉冲信号的电平类型为高电平时，证明检测组件仍处在不遮挡状态，此时需要继续向分离组件移动介质承载组件。
本发明实施例通过确定对脉冲信号进行采样得到的采样信号中的边沿信号的边沿时间点，来确定从边沿时间点起，预设时间后的目标时间点所检测到的脉冲信号的第一电平类型，以根据边沿信号和第一电平类型来判断是否控制介质承载组件向所述分离组件移动。从而避免了由于介质硬度作用叠加导致的，预设时间内检测组件脉冲波形抖动使得介质承载组件向检测组件的移动提前停止的问题。
需要说明的是，对于方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明实施例并不受所描述的动作顺序的限制，因为依据本发明实施例，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本发明实施例所必须的。
参照图9，示意性地示出了本发明实施例的一种基于FPGA实现电机控制的装置实施例的结构框图，具体可以包括如下模块：
脉冲信号获取模块901，用于当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；
采样模块902，用于按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；
边沿时间点确定模块903，用于当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点；
目标时间点确定模块904，用于确定从所述边沿时间点起，预设时间后的目标时间点；
第一电平类型确定模块905，用于确定在所述目标时间点检测到的所述脉冲信号的第一电平类型；
介质承载组件移动控制模块906，用于根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件的向所述分离组件移动。
在本发明实施例中，所述采样信号包括第一采样信号和第二采样信号；所述边沿信号包括上升沿信号；所述边沿时间点包括第一边沿时间点；所述边沿时间点确定模块，可以包括：
第二电平类型确定模块，用于当从所述第一采样信号中检测到所述上升沿信号时，确定所述第二采样信号的第二电平类型；
第一边沿时间点确定模块，用于当所述第二电平类型为低电平时，确定检测到所述上升沿信号的时间点为所述第一边沿时间点。
在本发明实施例中，所述采样信号包括第一采样信号和第二采样信号；所述边沿信号包括下降沿信号；所述边沿时间点包括第二边沿时间点；所述边沿时间点确定模块，可以包括：
第三电平类型确定模块，用于当从所述第一采样信号中检测到所述下降沿信号时，确定所述第二采样信号的第三电平类型；
第二边沿时间点确定模块，用于当所述第二电平类型为高电平时，确定检测到所述下降沿信号的时间点为所述第二边沿时间点。
在本发明实施例中，所述介质承载组件移动控制模块，可以包括：
第一停止移动控制模块，用于当所述边沿信号为所述上升沿信号，且所述第一电平类型为高电平时，采用预设电机停止向所述分离组件移动所述介质承载组件。
在本发明实施例中，所述介质承载组件移动控制模块，可以包括：
第二停止移动控制模块，用于当所述边沿信号为所述下降沿信号，且所述第一电平类型为低电平时，采用预设电机停止向所述分离组件移动所述介质承载组件。
在本发明实施例中，所述向所述分离组件移动控制模块，还可以包括：
第一移动控制模块，用于当所述边沿信号为所述上升沿信号，且所述电平类型为低电平时，采用所述电机保持向所述分离组件移动所述介质承载组 件。
在本发明实施例中，所述介质承载组件移动控制模块，还可以包括：
第二移动控制模块，用于当所述边沿信号为所述下降沿信号，且所述电平类型为高电平时，采用所述电机保持向所述分离组件移动所述介质承载组件。
本发明实施例还公开了一种电子设备，包括存储器及处理器，所述存储器中储存有计算机程序，所述计算机程序被所述处理器执行时，使得所述处理器执行如本发明实施例所述的基于FPGA实现电机控制的方法的步骤。
本发明实施例还公开了一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行根据本发明实施例中的任一个所述的基于FPGA实现电机控制的方法。
本发明实施例还公开了一种计算机可读存储介质，其中存储了如本发明实施例所述的计算机程序。所述计算机可读记录介质包括用于以计算机(例如计算机)可读的形式存储或传送信息的任何机制。例如，机器可读介质包括只读存储器(ROM)、随机存取存储器(RAM)、磁盘存储介质、光存储介质、闪速存储介质、电、光、声或其他形式的传播信号(例如，载波、红外信号、数字信号等)等。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本发明的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSP)来实现根据本发明实施例的计算处理设备中的一些或者全部部件的一些或者全部功能。本发明还可以实现为用于执行这里所描述的方法的一部分或者全部的设备或者装置程序(例如，计算机程序和计算机程序产品)。这样的实现本发明的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
例如，图10示出了可以实现根据本发明的方法的计算处理设备。该计算处理设备传统上包括处理器1010和以存储器1020形式的计算机程序产品或者计算机可读介质。存储器1020可以是诸如闪存、EEPROM(电可擦除可编程只读存储器)、EPROM、硬盘或者ROM之类的电子存储器。存储器1020具有用于执行上述方法中的任何方法步骤的程序代码1031的存储空间1030。例如，用于程序代码的存储空间1030可以包括分别用于实现上面的方法中的各种步骤的各个程序代码1031。这些程序代码可以从一个或者多个 计算机程序产品中读出或者写入到这一个或者多个计算机程序产品中。这些计算机程序产品包括诸如硬盘，紧致盘(CD)、存储卡或者软盘之类的程序代码载体。这样的计算机程序产品通常为如参考图11所述的便携式或者固定存储单元。该存储单元可以具有与图10的计算处理设备中的存储器1020类似布置的存储段、存储空间等。程序代码可以例如以适当形式进行压缩。通常，存储单元包括计算机可读代码1031’，即可以由例如诸如1010之类的处理器读取的代码，这些代码当由计算处理设备运行时，导致该计算处理设备执行上面所描述的方法中的各个步骤。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本发明的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (11)

  1. 一种基于FPGA实现电机控制的方法，其特征在于，所述的方法包括：
    当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；
    按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；
    当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点；
    确定从所述边沿时间点起，预设时间后的目标时间点；
    确定在所述目标时间点检测到的所述脉冲信号的第一电平类型；
    根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动。
  2. 根据权利要求1所述的方法，其特征在于，所述采样信号包括第一采样信号和第二采样信号；所述边沿信号包括上升沿信号；所述边沿时间点包括第一边沿时间点；所述当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点的步骤，包括：
    当从所述第一采样信号中检测到所述上升沿信号时，确定所述第二采样信号的第二电平类型；
    当所述第二电平类型为低电平时，确定检测到所述上升沿信号的时间点为所述第一边沿时间点。
  3. 根据权利要求1所述的方法，其特征在于，所述采样信号包括第一采样信号和第二采样信号；所述边沿信号包括下降沿信号；所述边沿时间点包括第二边沿时间点；所述当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点的步骤，包括：
    当从所述第一采样信号中检测到所述下降沿信号时，确定所述第二采样信号的第三电平类型；
    当所述第三电平类型为高电平时，确定检测到所述下降沿信号的时间点为所述第二边沿时间点。
  4. 根据权利要求1或2所述的方法，其特征在于，所述根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动的步骤，包括：
    当所述边沿信号为所述上升沿信号，且所述第一电平类型为高电平时，采用预设电机停止向所述分离组件移动所述介质承载组件。
  5. 根据权利要求1或3所述的方法，其特征在于，所述根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件 向所述分离组件移动的步骤，包括：
    当所述边沿信号为所述下降沿信号，且所述第一电平类型为低电平时，采用预设电机停止在向所述分离组件移动所述介质承载组件。
  6. 根据权利要求4所述的方法，其特征在于，所述根据所述边沿信号和所述电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动的步骤，还包括：
    当所述边沿信号为所述上升沿信号，且所述电平类型为低电平时，采用所述电机保持向所述分离组件移动所述介质承载组件。
  7. 根据权利要求5所述的方法，其特征在于，所述根据所述边沿信号和所述电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动的步骤，还包括：
    当所述边沿信号为所述下降沿信号，且所述电平类型为高电平时，采用所述电机保持向所述分离组件移动所述介质承载组件。
  8. 一种基于FPGA实现电机控制的装置，其特征在于，所述的装置包括：
    脉冲信号获取模块，用于当预设介质承载组件向预设分离组件移动时，获取预设检测组件产生的脉冲信号；
    采样模块，用于按照预设时钟频率对所述脉冲信号进行采样，得到采样信号；
    边沿时间点确定模块，用于当从所述采样信号中检测到边沿信号时，确定检测到所述边沿信号时对应的边沿时间点；
    目标时间点确定模块，用于确定从所述边沿时间点起，预设时间后的目标时间点；
    第一电平类型确定模块，用于确定在所述目标时间点检测到的所述脉冲信号的第一电平类型；
    介质承载组件移动控制模块，用于根据所述边沿信号和所述第一电平类型，采用预设电机控制所述介质承载组件向所述分离组件移动。
  9. 一种电子设备，包括存储器及处理器，所述存储器中储存有计算机程序，所述计算机程序被所述处理器执行时，使得所述处理器执行如权利要求1-7中任一项所述的基于FPGA实现电机控制的方法的步骤。
  10. 一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行根据权利要求1-7中的任一个所述的基于FPGA实现电机控制方法。
  11. 一种计算机可读介质，其中存储了如权利要求10所述的计算机程序。
PCT/CN2020/087674 2020-04-29 2020-04-29 一种基于fpga实现电机控制的方法和装置 WO2021217471A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202080000627.0A CN113939855A (zh) 2020-04-29 2020-04-29 一种基于fpga实现电机控制的方法和装置
PCT/CN2020/087674 WO2021217471A1 (zh) 2020-04-29 2020-04-29 一种基于fpga实现电机控制的方法和装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/087674 WO2021217471A1 (zh) 2020-04-29 2020-04-29 一种基于fpga实现电机控制的方法和装置

Publications (1)

Publication Number Publication Date
WO2021217471A1 true WO2021217471A1 (zh) 2021-11-04

Family

ID=78373270

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/087674 WO2021217471A1 (zh) 2020-04-29 2020-04-29 一种基于fpga实现电机控制的方法和装置

Country Status (2)

Country Link
CN (1) CN113939855A (zh)
WO (1) WO2021217471A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115389856A (zh) * 2022-10-27 2022-11-25 季华实验室 信号变化沿检测方法、装置、电子设备及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102262378A (zh) * 2010-05-26 2011-11-30 富士施乐株式会社 图像形成设备、控制装置以及检测传送体上的参考指标的方法
CN104339892A (zh) * 2013-07-24 2015-02-11 富士通电子零件有限公司 打印机和标记检测方法
CN104658100A (zh) * 2015-02-03 2015-05-27 深圳怡化电脑股份有限公司 卷钞轮式暂存部纸币残留检测方法、装置及atm机
CN105654612A (zh) * 2016-01-05 2016-06-08 新达通科技股份有限公司 一种精确控制分钞的atm机分钞装置和系统

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN206133778U (zh) * 2016-10-26 2017-04-26 深圳市信通检测技术有限公司 点钞机测试装置
CN107689101B (zh) * 2017-07-26 2020-06-09 深圳怡化电脑股份有限公司 一种钞箱舌片定位方法、装置及终端设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102262378A (zh) * 2010-05-26 2011-11-30 富士施乐株式会社 图像形成设备、控制装置以及检测传送体上的参考指标的方法
CN104339892A (zh) * 2013-07-24 2015-02-11 富士通电子零件有限公司 打印机和标记检测方法
CN104658100A (zh) * 2015-02-03 2015-05-27 深圳怡化电脑股份有限公司 卷钞轮式暂存部纸币残留检测方法、装置及atm机
CN105654612A (zh) * 2016-01-05 2016-06-08 新达通科技股份有限公司 一种精确控制分钞的atm机分钞装置和系统

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115389856A (zh) * 2022-10-27 2022-11-25 季华实验室 信号变化沿检测方法、装置、电子设备及存储介质

Also Published As

Publication number Publication date
CN113939855A (zh) 2022-01-14

Similar Documents

Publication Publication Date Title
US9237164B2 (en) Systems and methods for capturing, replaying, or analyzing time-series data
CN110490075B (zh) 获取稳定帧的方法、装置以及计算机可读介质
EP2407943A1 (en) Method for event initiated video capturing and a video camera for capture event initiated video
US7257035B2 (en) Method for detecting data strobe signal
US9343123B2 (en) Memory access alignment in a double data rate (‘DDR’) system
WO2021217471A1 (zh) 一种基于fpga实现电机控制的方法和装置
JP2016540291A (ja) メモリモジュールにおけるストローブ信号に基づいた制御信号のトレーニング方法
US9450554B2 (en) Electronic device and method for adjusting volume
CN108900834B (zh) 一种高速相机曝光时间及失帧测量装置及方法
US20180121390A1 (en) Trend correlations
WO2016186676A1 (en) Application thread visualization
CN102254569B (zh) 四倍数据速率qdr控制器及其实现方法
US20220308779A1 (en) Data relocation system
US9342158B2 (en) Sub-frame accumulation method and apparatus for keeping reporting errors of an optical navigation sensor consistent across all frame rates
US10937484B2 (en) Dynamic bandwidth throttling of DRAM accesses for memory tracing
CN109669828B (zh) 一种硬盘检测方法和装置
KR101735590B1 (ko) 트랜잭션 추출 장치 및 방법
CN105092891B (zh) 终端甩屏识别方法及装置
WO2021217472A1 (zh) 一种基于fpga实现电机控制的方法和装置
US10797855B2 (en) Signal detection techniques using clock data recovery
KR20160076204A (ko) 데이터 스트로빙 회로 및 이를 이용한 반도체 장치
US10257312B2 (en) Performance monitor based on user engagement
TW200810358A (en) Apparatus and method of detecting a target peak value and a target bottom value of an input signal
CN101764651A (zh) 一种实现信号测试的方法和装置
CN107730705B (zh) 起止点数据、连续数据采集方法、装置、设备及存储介质

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20933756

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20933756

Country of ref document: EP

Kind code of ref document: A1