WO2021203329A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021203329A1
WO2021203329A1 PCT/CN2020/083829 CN2020083829W WO2021203329A1 WO 2021203329 A1 WO2021203329 A1 WO 2021203329A1 CN 2020083829 W CN2020083829 W CN 2020083829W WO 2021203329 A1 WO2021203329 A1 WO 2021203329A1
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WO
WIPO (PCT)
Prior art keywords
area
layer
display
blind hole
hole area
Prior art date
Application number
PCT/CN2020/083829
Other languages
English (en)
French (fr)
Inventor
周洋
黄耀
张顺
杨慧娟
和玉鹏
张鑫
王予
尚庭华
张祎杨
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000489.6A priority Critical patent/CN114730545B/zh
Priority to PCT/CN2020/083829 priority patent/WO2021203329A1/zh
Priority to US17/619,603 priority patent/US20230157096A1/en
Priority to PCT/CN2021/080875 priority patent/WO2021203917A1/zh
Priority to EP21783922.4A priority patent/EP4135043A4/en
Priority to JP2022503526A priority patent/JP2023520613A/ja
Priority to CN202180000501.8A priority patent/CN113767476A/zh
Publication of WO2021203329A1 publication Critical patent/WO2021203329A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers

Definitions

  • the present disclosure belongs to the field of display technology, and in particular relates to a display substrate, a preparation method thereof, and a display device.
  • the in-screen opening technology requires sacrificing part of the display area (Active Area) of the display panel, and the sacrificial display area is used for arranging optical devices such as cameras and sensors.
  • a display substrate including a display area, a wiring area, at least one via area and at least one blind hole area, the wiring area surrounding the at least one via area and the at least one Blind hole area, the display area surrounds the wiring area
  • the display substrate includes: a base substrate; a driving circuit layer formed on the base substrate, and the driving circuit layer includes Area, the wiring area and the interlayer dielectric layer of the blind hole area, wherein the wiring area includes a plurality of signals arranged on the interlayer dielectric layer around the via area and the blind hole area And the plurality of signal lines do not block the through hole area and the blind hole area, and the display substrate transmits light in the blind hole area.
  • the at least one through hole region includes two through hole regions, the at least one blind hole region includes one blind hole region, and the blind hole region is disposed between the two through hole regions.
  • the through hole area is circular or capsule-shaped.
  • the blind hole area has a rectangular shape or a spliced shape of rectangles with different widths along the length direction.
  • the plurality of signal lines includes a data line, a light emission control signal line, and a gate drive signal line
  • the data line extends in a first direction
  • the light emission control signal line and the gate drive signal The wire extends in a second direction different from the first direction.
  • the data line includes a portion extending around the through hole area or a portion extending around the blind hole area.
  • the light emission control signal line and the gate driving signal line include a portion surrounding the through hole region and a portion surrounding the blind hole region.
  • the display area includes an organic light emitting diode
  • the wiring area further includes a redundant pixel structure, and the redundant pixel structure does not include an anode of the organic light emitting diode.
  • the driving circuit layer includes a first insulating layer, a second insulating layer, and the layer located in the wiring area, the display area, and the blind hole area on the base substrate. Intermediate layer.
  • the driving circuit layer further includes a thin film transistor located in the display area, and the thin film transistor includes an active layer, a gate, a source and a drain, wherein the active layer of the thin film transistor Located on the base substrate, the first insulating layer is located on the side of the active layer away from the base substrate; the gate is located on the side of the first insulating layer away from the active layer , The second insulating layer is located on the side of the gate away from the first insulating layer; the interlayer dielectric layer is located on the side of the second insulating layer away from the first insulating layer; the source The electrode and the drain electrode are located on a side of the interlayer dielectric layer away from the second insulating layer, wherein the plurality of signal lines, the source electrode and the drain electrode are arranged in the same layer.
  • the wiring area further includes redundant vias, the redundant vias are located in the first insulating layer, the second insulating layer, and the interlayer dielectric layer, and penetrate to the Active layer.
  • the display substrate further includes a planarization layer, the planarization layer is located in the display area, the wiring area and the blind hole area, and is formed on the interlayer dielectric layer away from the One side of the base substrate.
  • the display substrate further includes an encapsulation dam region, the encapsulation dam region is located between the wiring region and the through hole region and surrounds the through hole region, and at least one encapsulation dam is disposed on the The encapsulation dam area surrounds the through hole area, and the at least one encapsulation dam is located on a side of the interlayer dielectric layer away from the base substrate.
  • the at least one encapsulation dam includes a first encapsulation dam and a second encapsulation dam, the first encapsulation dam is located on a side of the second encapsulation dam away from the through hole region, and the first The thickness of the two encapsulation dams in a direction perpendicular to the base substrate is greater than the thickness of the first encapsulation dam, the second encapsulation dam includes a first part and a second part arranged on the first part, The first part and the flat layer are arranged in the same layer.
  • the display substrate further includes a first isolation region and a second isolation pillar region, the first isolation region is located between the wiring region and the package dam region, and the second isolation region is located Between the through hole region and the packaging dam region, the display substrate further includes at least one first isolation pillar formed on a side of the interlayer dielectric layer away from the base substrate and located on the first isolation column.
  • the interlayer dielectric layer is located on a side away from the base substrate and located in the second isolation region, the second isolation pillars are arranged around the through hole area, and the sidewalls of the second isolation pillars are provided with grooves ,
  • the first isolation pillar, the second isolation pillar and the plurality of signal lines are arranged in the same layer.
  • the display substrate further includes a first film layer and a second film layer located in the second isolation region, the first film layer surrounds the through hole region, and the second isolation pillar is located at
  • the orthographic projection on the base substrate is located in the orthographic projection of the first film layer on the base substrate; the second film layer surrounds the through hole area, and the second isolation column is located in the
  • the orthographic projection on the base substrate is located in the orthographic projection of the second film layer on the base substrate, the first film layer and the gate are arranged in the same layer, the first isolation column and the
  • Each of the second isolation pillars includes a first metal layer, a second metal layer, and a third metal layer on the side of the interlayer dielectric layer away from the substrate, and the second metal layer is on the interlayer dielectric layer.
  • the outer boundary of the orthographic projection on the first metal layer and the third metal layer are inside the outer boundary of the orthographic projection on the interlayer dielectric layer, so as to form the recess on the sidewall of the isolation column.
  • the first metal layer and the third metal layer are titanium layers
  • the second metal layer is an aluminum layer.
  • the display substrate further includes an encapsulation layer on the organic light-emitting diode, wherein the organic light-emitting diode is located in the display area and includes an anode and a pixel sequentially formed on the flat layer.
  • the encapsulation layer includes a first inorganic encapsulation film layer, an organic encapsulation film layer, and a second inorganic encapsulation film layer stacked in sequence, the first inorganic encapsulation film layer and the second inorganic encapsulation film layer
  • the inorganic packaging film layer is encapsulated in the second isolation area, the encapsulation dam area, the first isolation area, the wiring area, the display area, and the blind hole area;
  • the organic packaging film layer is located in the The encapsulation dam area, the first isolation area, the wiring area, the display area, and the blind hole area, the encapsulation layer is light-transmissive
  • the first encapsulation dam includes an interlayer dielectric layer
  • the third part and the first spacer part on the third part, the second encapsulation dam also includes a second spacer part on the second part, the third part of the first encapsulation dam And the first spacer part, the second part and the second space
  • a display device which includes the above-mentioned display substrate, and the display device further includes: at least one first sensor, which respectively corresponds to the at least one through-hole area located in the display The side of the substrate away from the driving circuit layer; at least one second sensor, which respectively corresponds to the at least one blind hole area and is located on the same side of the display substrate as the at least one first sensor.
  • the at least one first sensor includes a camera
  • the at least one second sensor includes at least one of an infrared sensor, a proximity light sensor, a flood illuminator, and an ambient light sensor.
  • a method for preparing a display substrate including a display area, a wiring area, at least one via area and at least one blind hole area, the wiring area surrounding the at least one via area.
  • a hole area and the at least one blind hole area, the display area surrounds the wiring area the method includes: providing a base substrate; forming a driving circuit layer on the base substrate, the driving circuit layer including An interlayer dielectric layer located in the display area, the wiring area, and the at least one blind hole area, the wiring area including the interlayer dielectric layer surrounding the via area and the blind hole area And the plurality of signal lines do not block the through hole area and the blind hole area, the display substrate transmits light in the blind hole area, wherein the plurality of signal lines and the blind hole area
  • the source and drain of the thin film transistor in the driving circuit layer are formed by the same patterning process.
  • Fig. 1a is a top view of a display substrate according to an embodiment of the present disclosure
  • FIG. 1b is a schematic diagram of the overall circuit structure of a display substrate according to an embodiment of the present disclosure
  • FIG. 2a is an enlarged view of the display substrate in FIG. 1a in the through hole area and the blind hole area;
  • 2b is an enlarged view of the display substrate in the through hole area and the blind hole area according to an embodiment of the present disclosure
  • 2c is an enlarged view of the display substrate in the through hole area and the blind hole area according to an embodiment of the present disclosure
  • Figure 3 is a cross-sectional view along A-A' of Figure 2a;
  • FIG. 4 is a cross-sectional view showing the substrate before cutting the through hole area
  • FIG. 5 is a wiring diagram of a through hole area and a blind hole area according to an embodiment of the present disclosure
  • Figure 6 is a cross-sectional view of the blind hole in the dashed frame B in Figure 4;
  • FIG. 7 is a cross-sectional view of a display area of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a cross-sectional view of a display area of a display substrate according to an embodiment of the present disclosure.
  • FIG. 9 is an enlarged view of the first blocking area in FIG. 4 according to an embodiment of the present disclosure.
  • FIG. 10 is an enlarged view of the second blocking area in FIG. 4 according to an embodiment of the present disclosure.
  • FIG. 11 is an enlarged view of a wiring area according to an embodiment of the present disclosure.
  • FIG. 12 is a cross-sectional view of a redundant pixel structure according to an embodiment of the present disclosure.
  • FIG. 13 is a cross-sectional view of a redundant pixel structure according to an embodiment of the present disclosure.
  • FIG. 14 is a flowchart of a manufacturing method of a display substrate according to an embodiment of the present disclosure.
  • the openings in the display screen include through holes (Punch Hole) and blind holes (Transparent Hole).
  • the advantage of the through-hole design is that there is no film at the opening to block the optical device, which is suitable for components with high transmittance requirements such as cameras.
  • At the blind hole there is still a transparent film at the actual opening.
  • the transmittance is lower than the through hole without a film, but higher than the normal display area of the organic light-emitting diode (OLED) display. Usually used for components that require slightly lower transmittance.
  • the through hole design needs to add a package structure around the through hole to ensure product reliability, which will increase the frame; while the blind hole design does not require a package structure, and it is easier to obtain a narrow frame.
  • the inventor found that related products only have one of through holes and blind holes. If a through hole is used, the through hole is only used to place the camera, and the remaining optical sensors need to be placed on the frame, occupying the frame size. If a blind hole is used, the image quality of the camera is slightly worse due to the loss of transmittance.
  • a display substrate is provided.
  • the display substrate includes a display area 10a, a wiring area 10d, at least one through hole area 10b, and at least one blind hole area 10c.
  • the wiring area 10d surrounds at least one via area 10b and at least one blind hole area 10c, and the display area 10a surrounds the wiring area 10d.
  • the display substrate includes two through hole regions and one blind hole region, and the blind hole region is disposed between the two through hole regions.
  • the through hole area and the blind hole area may also be arranged in other ways as required.
  • the blind hole area is not arranged between the through hole areas, but the blind hole area is arranged outside the two adjacent through hole areas.
  • a through hole is provided in the through hole region 10b, and a blind hole is provided in the blind hole region 10c.
  • the shape of the blind hole and the through hole may be circular, rectangular, or other regular or irregular shapes.
  • the shape of the through holes in the two through hole regions 10b is circular, and the blind holes in the blind hole region 10c between the two through hole regions 10b are formed by splicing two rectangles with different sizes.
  • Figure 2c shows the arrangement of a large through hole area 10b1 and a small through hole area 10b2 adjacent to each other.
  • the small through hole area 10b2 is circular.
  • the size of the through hole and the blind hole can be set according to the needs, as shown in Figure 1a and Figure 2a, when the through hole or the blind hole is circular, the diameter can be in the range of 2mm-4mm.
  • the diameter of the circular through hole can be in the range of 2mm-4mm, and the size of the irregularly shaped blind hole along the length and width directions needs to be matched with the size of the circular through hole as required.
  • the length of the capsule-shaped through hole may be in the range of 9mm-10mm, and the width may be 4mm; the diameter of the circular through hole may be 4mm.
  • the left part of the capsule-shaped through hole 10b1 can correspond to the camera, and the right part of the capsule-shaped through hole 10b1 can correspond to the sensor, that is, the position of the blind hole area 10c shown in Fig. 2b.
  • the spacing between the large through hole 10b1 and the small through hole 10b2 should ensure that the spacing between the packaging dam of 10b1 and the packaging dam of 10b2 meets certain requirements, so that the organic packaging film layer in this area is not too thin.
  • the present disclosure is described by taking the through hole area and the blind hole area shown in FIG. 1a and FIG. 2a as an example.
  • FIG. 1b is a schematic diagram of the overall circuit structure of a display substrate.
  • 1001 represents the overall outer frame of the display substrate;
  • the display substrate includes an effective display area (ie, pixel array area) 10a and a peripheral area located around the effective display area 10a, the effective display area including an array arrangement
  • the peripheral area includes a shift register unit 1003, a plurality of cascaded shift register units 1003 form a gate drive circuit for the pixel unit 1002 arranged in an array of the effective display area 10a of the display substrate 1001
  • the peripheral area also includes a light-emitting control unit 1004, a plurality of cascaded light-emitting control units 1004 constitute a light-emitting control array, used to display the effective display area 10a of the display panel 1001 array
  • the arranged pixel units 1002 provide, for example, a light emission control signal shifted row by row.
  • the data lines D1-DN (N is an integer greater than 1) connected to the data driving chip IC longitudinally pass through the effective display area 10a to provide data signals for the pixel units 1002 arranged in the array; and the shift register
  • the GOA signal line G1-GM (M is an integer greater than 1) connected to the unit 1003 traverses the effective display area 10a to provide gate scanning signals for the pixel units arranged in the array
  • the EOA signal line E1- connected to the light-emitting control unit 1004 EM (M is an integer greater than 1) traverses the effective display area 10a to provide light emission control signals for the pixel units arranged in the array.
  • each pixel unit 1002 may include pixel circuits and light-emitting elements having circuit structures such as 7T1C, 8T2C, or 4T1C in the art. It works under the control of the control signal to drive the light-emitting element to emit light to achieve display and other operations.
  • the light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).
  • the display substrate includes a base substrate 100 and a driving circuit layer 200.
  • the driving circuit layer 200 is formed on the base substrate 100 and includes an interlayer dielectric layer located in the display area 10a, the wiring area 10d, and the blind hole area 10c.
  • the base substrate 100 may include a substrate 101 and a buffer layer 102 disposed on the substrate 101, and the base substrate 100 may be another composite base substrate.
  • the base substrate is a flexible substrate, and the driving circuit layer is disposed on the buffer layer. As shown in FIG.
  • the wiring area 10d includes a plurality of signal lines arranged on the interlayer dielectric layer around the through hole area 10b and the blind hole area 10c, and the multiple signal lines do not cover the through hole area 10b and the blind hole area 10c, and The display substrate transmits light in the blind hole region 10c.
  • the through hole in the through hole area 10b has the highest light transmittance, it can be used for components that require high light transmittance such as cameras; because the blind hole in the blind hole area 10c has low light transmittance, it can be used for infrared sensors, Proximity sensors, flood illuminators, ambient light sensors and other components with low light transmittance. Since the blind hole does not need to be provided with a packaging structure, compared with the through hole design, it is beneficial to increase the proportion of the display area and realize a narrow frame; and the through hole design can improve the imaging quality of the camera. As shown in FIG.
  • the component 104 that requires high light transmittance such as a camera can be arranged directly opposite the through hole on the side of the display substrate away from the driving circuit layer, and can extend into the through hole;
  • Light sensors, flood illuminators, ambient light sensors and other components with low light transmittance 105 are arranged on the side of the display substrate directly opposite to the blind hole, and the components 104 with high light transmittance and components with low light transmittance 105 is arranged on the same side of the display substrate.
  • a plurality of signal lines in the wiring area 10d are arranged around the through hole area 10b and the blind hole area 10c without blocking Through hole area 10b and blind hole area 10c.
  • the wiring 2 in the wiring area 10d also includes a three-layer metal structure similar to the first isolation pillar 1c and the second isolation pillar 1e. The difference between the two is that there is no need to etch the wiring 2 to form a first isolation. Grooves at the second metal layer in the pillars 1c and the second isolation pillars 1e.
  • the signal lines in the wiring area 10d may include an emission control (EOA) signal line 2a, a source signal line 2b, a gate drive (GOA) signal line 2c, and the like.
  • EOA emission control
  • GOA gate drive
  • the thin solid lines represent the source signal line 2b, that is, the data line
  • the short dashed line represents the GOA signal line 2c
  • the dotted line represents the EOA signal line 2a.
  • the EOA signal line 2a and the GOA signal line 2c are mutually connected.
  • the EOA signal line and the GOA signal line surround the through hole and the blind hole area.
  • the holes are arranged to avoid blocking the light entering the blind holes and through holes; in general, the source signal line 2b extends on the display substrate in the direction perpendicular to the EOA signal line 2a and the GOA signal line 2c (the first direction), but only in the through hole. In the hole area and the blind hole area, the source signal line is arranged around the through hole and the blind hole to avoid blocking the light entering the blind hole and the through hole. As shown in FIG.
  • the EOA signal line 2a, the source signal line 2b, and the GOA signal line 2c are all located on the side of the transition area 10e away from the through hole; in the blind hole area, since the transition area 10e is not provided , The EOA signal line 2a, the source signal line 2b and the GOA signal line 2c are all located around the blind hole area.
  • the plurality of signal lines 2 include a fourth metal layer, a fifth metal layer, and a sixth metal layer on the interlayer dielectric layer 203, and the fourth metal layer, the fifth metal layer and the sixth metal layer are respectively The first metal layer 306, the second metal layer 307, and the third metal layer 308 are arranged in the same layer.
  • the wiring area 10d is also provided with a redundant pixel structure 208.
  • the redundant pixel structure 208 is connected to the EOA signal line and the data line, and is also connected to the GOA signal line (not shown in the figure).
  • the specific structure of the remaining pixel structure 208 is shown in FIG. 12 or 13.
  • the wiring area further includes redundant vias 209.
  • the redundant vias are formed when the interlayer dielectric layer is punched. The vias expose the active layer.
  • the redundant vias may be located in addition to the redundant vias.
  • the wiring area outside the pixel structure and the signal line is generally located between the redundant pixel structure and the signal line, and the space can no longer be provided with a redundant pixel structure.
  • redundant vias can be set, and the size of the redundant vias can be adjusted according to The size of the space is set, and the number is not limited.
  • the purpose is to balance the difference in via density between the wiring area and the display area, and to ensure the uniformity of TFT characteristics.
  • the driving circuit layer is located in the wiring area 10d, the display area 10a, and the blind hole area 10c, and is sequentially provided with a first insulating layer 201 and a second insulating layer 202 on the side away from the base substrate 100. And interlayer dielectric layer 203.
  • the B area at the blind hole area 10c shows the blind hole area 10c.
  • area B includes a first insulating layer 201, a second insulating layer 202 and an interlayer dielectric layer 203 arranged in sequence.
  • the wiring area 10d and the display area 10a have the same first insulating layer 201, second insulating layer 202, and interlayer dielectric layer 203 as the blind hole area 10c, which will not be repeated here.
  • the driving circuit layer 200 further includes a thin film transistor located in the display area 10a.
  • the thin film transistor may be a top-gate type, including an active layer, a gate, a source, and a drain. 7 is a cross-sectional view of the display area 10a, the active layer 204 of the thin film transistor is located on the base substrate 100, the first insulating layer 201 is located on the active layer 204; the gate 205 is located on the first insulating layer 201, and the first insulating layer 201 is located on the The two insulating layers are located on the gate 205; the source 210 and the drain 211 are located on the interlayer dielectric layer 203, and are respectively located on opposite sides of the gate 205, the source 210 and the drain 211 can respectively pass through vias (for example : Metal vias) are in contact with opposite sides of the active layer 204. It should be understood that this thin film transistor may also be a bottom gate type.
  • the multiple signal lines, the source 210 and the drain 211 are
  • the capacitor structure may include a first electrode plate 230 and a second electrode plate 231.
  • the first electrode plate 230 and the gate electrode 205 are arranged in the same layer, and the second electrode plate 231 is located on the second gate insulating layer 202 and the layer Between the dielectric layers 203 and opposite to the first electrode plate 230.
  • the materials of the gate 205, the first electrode plate 230, and the second electrode plate 231 may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the source 210 and the drain 211 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc., for example, the multi-layer structure is a multi-metal laminated layer, such as titanium, aluminum, Titanium three-layer metal laminate (Al/Ti/Al), etc.
  • the display substrate further includes a planarization layer 206.
  • the planarization layer may be located in the display area 10a, the wiring area 10d, and the blind hole area 10c, and is formed on the interlayer dielectric layer 203 .
  • the planarization layer 206 transmits light.
  • the planarization layer 206 may be made of materials such as silicon nitride and silicon oxide.
  • the display panel further includes a transition area 10e.
  • the transition region 10e includes an encapsulation dam region 10e2 located between the wiring region 10d and the via region 10b and surrounding the via region 10b.
  • At least one package dam is disposed in the package dam area 10e2 and is located on the side of the interlayer dielectric layer 103 away from the base substrate 100 surrounding the through hole area 10b.
  • the at least one package dam includes a first package dam 1a and a second package dam 1b.
  • the first package dam 1a is located on a side of the second package dam 1b away from the through hole region 10b.
  • the thickness of the dam 1b in the direction perpendicular to the base substrate 100 is greater than the thickness of the first packaging dam 1a.
  • the second packaging dam 1b includes a first portion 303 and a first portion disposed on the first portion. Two parts 304, the first part 303 and the flat layer 206 are arranged in the same layer.
  • the transition area 10e further includes a first isolation area 10e1, and the first isolation area 10e1 is located between the wiring area 10d and the packaging dam area 10e2.
  • the display substrate further includes at least one first isolation pillar 1c, which is formed on a side of the interlayer dielectric layer 206 away from the base substrate 100 and located in the first isolation region 10e1.
  • the pillar 1c is arranged around the first packaging dam 1a, and the side wall of the first isolation pillar 1c is provided with a groove.
  • the at least one first isolation pillar 1c can block the organic light-emitting material to prevent water and oxygen from invading the light-emitting device.
  • the transition area 10e further includes a second isolation area 10e3, and the second isolation area 10e3 is located between the via area 10b and the encapsulation dam area 10e2.
  • the display substrate further includes at least one second isolation pillar 1e, which is formed on a side of the interlayer dielectric layer 203 away from the base substrate 100 and located in the second isolation region 10e3.
  • the pillars 1e are arranged around the through hole region 10b, and the sidewalls of the second isolation pillars 1e are provided with grooves to isolate the organic light-emitting materials to prevent water and oxygen from invading the light-emitting devices.
  • the cutting line for cutting the through hole is also marked, and the area between the cutting line of the through hole and the display area 10a constitutes the frame of the through hole.
  • the frame includes a transition area 10e and a wiring area 10d, usually in the range of 400um-1mm.
  • the distance between the through holes or between the through holes and the blind holes needs to meet the requirements of setting windings and isolation columns, and/or packaging dams. .
  • the first isolation pillar 1c and the second isolation pillar 1e includes a first metal layer 306, a second metal layer 307, and a third metal layer 306 on the interlayer dielectric layer 203, and the orthographic projection of the second metal layer 307 on the interlayer dielectric layer 203
  • the outer boundary of is located inside the outer boundary of the orthographic projection of the first metal layer 306 and the third metal layer 308 on the interlayer dielectric layer 203, so as to form the groove on the sidewall of the isolation column
  • the first metal layer 306 and the third metal layer 308 are titanium layers
  • the second metal layer 307 is an aluminum layer.
  • the first isolation pillars 1c in FIG. 8 have a first interval 1d between them
  • the second isolation pillars in FIG. 9 have a second interval 1f between them.
  • FIG. 9 and FIG. 8 The difference between FIG. 9 and FIG. 8 is that a first film layer 233 and a second film layer 234 are further provided corresponding to the second isolation pillar 1e.
  • the first film layer 233 and the second film layer 234 are both located in the second isolation region 10e3, the first film layer 233 surrounds the through hole region 10b, and the second isolation pillar 1e is located on the base substrate 100
  • the orthographic projection is in the orthographic projection of the first film layer 233 on the base substrate 100; the second film layer 234 surrounds the through hole region 10b, and the second spacer 1e is on the substrate
  • the orthographic projection on the substrate 100 is in the orthographic projection of the second film layer 234 on the base substrate.
  • the first film layer 233 and the first gate electrode are provided in the same layer, and the second film layer 234 and the second electrode plate 231 are provided in the same layer.
  • the first film layer 233 and the second film layer 234 may be made of metal corresponding to the gate and the second electrode plate 231 respectively, and are used to raise the second isolation column 1e, and can also alleviate cracks in the base substrate.
  • the first isolation pillar 1c, the second isolation pillar 1e and the multiple signal lines are arranged in the same layer.
  • the display substrate further includes a display device and an encapsulation layer 118 on the display device.
  • the display device is located in the display area, and includes a first electrode 212, a pixel defining portion 213, an organic functional layer 214, and a second electrode 215 sequentially formed on the flat layer 206.
  • the organic light emitting diode includes a first electrode 212, an organic functional layer 214, and a second electrode 215.
  • the first electrode 212 may be an anode
  • the second electrode 215 may be a cathode.
  • a supporting portion 232 is further provided between the pixel defining portion 213 and the second electrode 215, and the supporting portion 232 may be made of the same layer and the same material as the pixel defining portion 213.
  • the encapsulation layer 118 includes a first inorganic encapsulation film layer 118a, an organic encapsulation film layer 118b, and a second inorganic encapsulation film layer 118c that are stacked in sequence. As shown in FIG.
  • the first inorganic encapsulation film layer 118a and the second inorganic encapsulation film layer 118c are encapsulated in the second isolation region 10e3, the encapsulation dam region 10e2, the first isolation region 10e1, The wiring area 10d, the display area 10a, and the blind hole area 10c.
  • the organic encapsulation film layer 118b is located in the first isolation region 10e1, the wiring region 10d, the display region 10a and the blind hole region 10c, and the encapsulation layer 118 is light-transmissive.
  • the first electrode 212 may also be electrically connected to the drain 211 through the transfer electrode 133.
  • the planarization layer 206 may have a double-layer structure, and specifically may include a first planarization film (PLN1) layer 206a and a second planarization film (PLN1) layer 206a and a second planarization film (PLN1) formed in sequence.
  • a passivation film (PVX) layer 134 can be formed between the first planarization film layer 116a and the interlayer dielectric layer 103.
  • the passivation film layer 134 can be made of silicon oxide, nitride
  • the passivation film layer 134 covers the source electrode 110 and the drain electrode 111; and the transfer electrode 133 is formed between the first planarization film layer 116a and the second planarization film layer 116b, and
  • the first electrode 112 can be electrically connected to the drain 111 through the via holes (such as metal vias) on the first planarization film layer 116a and the passivation film layer 134 in turn;
  • the hole (for example, a metal via) is electrically connected to the transfer electrode 133.
  • the first packaging dam 1a includes a third portion 301 on the interlayer dielectric layer 203 and a first spacer portion 302 on the third portion, so
  • the second packing dam 1b further includes a second spacer portion 305 on the second portion 304, the third portion 301 and the first spacer portion 302 of the first packing dam 1a, the second packing dam
  • the second part 304 and the second spacer part 305 of 1b are arranged in the same layer as the pixel defining part 213.
  • the film structure in the blind hole region 10c includes a base substrate 100, a first insulating layer 201, a second insulating layer 202, an interlayer dielectric layer 203, a flat layer 206, and an encapsulation layer. 118. It is also possible to etch multiple film layers in the blind hole region 10c to retain part of the above-mentioned film layer structure.
  • the film layer in the blind hole region 10c may include a first insulating layer 201, a second insulating layer 202, and interlayers.
  • the dielectric layer 203, the planarization layer 206, and the encapsulation layer 118 such as including only an insulating layer 201, a second insulating layer 202, and an interlayer dielectric layer 203, or only a first insulating layer 201, a second insulating layer An insulating layer 202, an interlayer dielectric layer 203, and a flat layer 206.
  • the blind hole region 10c retains the layers shown in FIG. 4 to keep the thickness of the display substrate from greatly changing, and to avoid the generation of bonding bubbles between the layers when the bonding process is used to bond the layers.
  • the light passes through each film layer along the light incident direction to reach the sensor 105 corresponding to the blind hole.
  • the base substrate 100, the first insulating layer 201, the second insulating layer 202, the interlayer dielectric layer 203, the flat layer 206 and the encapsulation layer 118 are all made of transparent materials.
  • the base substrate 100 may be made of organic materials such as polyimide and may be a composite substrate including a substrate, a barrier layer, and a buffer layer.
  • the first insulating layer 201, the second insulating layer 202, and the interlayer dielectric layer 203 can be made of silicon oxide, silicon oxynitride, or the like.
  • the flat layer 206 can be made of organic materials, such as photoresist, acrylic-based polymer, silicon-based polymer, and the like.
  • the first inorganic encapsulation film layer 118a and the second inorganic encapsulation film layer 118c of the encapsulation layer 118 are used to prevent water and oxygen from entering the display device in the display area 10a from the display side of the display function and the through hole area 10b;
  • the packaging film layer 118a and the second inorganic packaging film layer 118c can be made of inorganic materials such as silicon nitride and silicon oxide.
  • the organic encapsulation film layer 118b is used to achieve a planarization effect to facilitate the production of the second inorganic encapsulation film layer 118c.
  • the organic encapsulation film layer 118b can be made of acrylic-based polymer, silicon-based polymer, or other materials.
  • a display device including the display substrate of the above-mentioned embodiment and a driving circuit for driving the display panel.
  • the display device further includes at least one first sensor 104, which are respectively arranged opposite to the through holes in the through hole region 10b and are located on the side of the display substrate away from the driving circuit layer, and are extendable Into the through hole; at least one second sensor 105, which respectively faces the blind hole in the at least one blind hole area 10c and is located on the same side of the display substrate as the at least one first sensor 104, as shown in FIG. 3 .
  • the at least one first sensor 104 includes, for example, a camera
  • the at least one second sensor 105 includes, for example, an infrared sensor, a proximity light sensor, a flood illuminator, and an ambient light sensor.
  • a method for preparing a display substrate including the following steps: S110, providing a base substrate; S120, forming a driving circuit layer on the base substrate.
  • the driving circuit layer includes an interlayer dielectric layer located in the display area, the wiring area and the blind hole area.
  • the wiring area includes a plurality of signal lines arranged around the through hole area and the blind hole area on the interlayer dielectric layer, and the plurality of signal lines do not block the through hole area and the blind hole area, and the display substrate is The blind hole area transmits light.
  • laser cutting or mechanical punching can be used to cut the display substrate at the through hole region 10b to obtain a display substrate with through holes.
  • the at least one through hole region may be formed to include two through hole regions, the at least one blind hole region is formed to include one blind hole region, and the blind hole region is disposed in the two through hole regions. Between the through hole regions, the through hole regions are formed in a circular shape or a capsule shape, and the blind hole regions are formed in a rectangular shape or a spliced shape of rectangles with different widths along the length direction.
  • forming the driving circuit layer on the base substrate in the display area further includes: forming an active layer on the base substrate; A first insulating layer is formed on the side of the first insulating layer; a gate is formed on the side of the first insulating layer away from the active layer; a second insulating layer is formed on the side of the gate away from the first insulating layer An interlayer dielectric layer is formed on the side of the second insulating layer away from the gate; source and drain electrodes are formed on the side of the interlayer dielectric layer away from the second insulating layer, wherein , The driving circuit layer includes the first insulating layer, the second insulating layer, and the interlayer dielectric layer in the blind hole area, the wiring area, and the display area, and the plurality of signal lines , The source electrode and the drain electrode are formed by the same patterning process.
  • the plurality of signal lines include data lines, light emission control signal lines, and gate drive signal lines, the data lines are formed to extend in a first direction, and the light emission control signal lines and the gate drive signal lines are formed to extend along and The first direction is different from the second direction, the data line includes a portion extending around the through hole region or the blind hole region, and the light emission control signal line and the gate driving signal line include The part of the through hole area and the part surrounding the blind hole area.
  • the preparation method further includes forming a planarization layer on a side of the driving electrode layer away from the base substrate, and the planarization layer is located in the display area, the wiring area, and the Blind hole area.
  • the display substrate further includes an encapsulation dam region, a first isolation region, and a second isolation region, the encapsulation dam region is located between the wiring region and the through hole region and surrounds the through hole Area, at least one package dam is arranged in the package dam area and surrounds the through hole area on the side of the interlayer dielectric layer away from the base substrate, and the at least one package dam includes a first package dam And a second encapsulation dam, the first encapsulation dam is located on the side of the second encapsulation dam away from the through hole area, and the thickness of the second encapsulation dam in the direction perpendicular to the base substrate is greater than The thickness of the first encapsulation dam, the second encapsulation dam includes a first part and a second part disposed on the first part, the first part and the flat layer are formed by the same patterning process; The first isolation region is located between the wiring region and the packaging dam region, and the display substrate further includes at least one first isolation pillar formed on a side of the
  • the preparation method further includes forming an organic light emitting diode in the display area and a redundant pixel structure in the wiring area on the side of the interlayer dielectric layer away from the base substrate, and thereafter An encapsulation layer is formed, wherein the display device is located in the display area, and the first electrode (anode), the pixel defining portion, the organic functional layer and the second electrode of the display device are sequentially formed on the flat layer ( Cathode), the redundant pixel structure does not include the anode of the organic light emitting diode.
  • Forming the encapsulation layer includes sequentially laminating and forming a first inorganic encapsulation film layer, an organic encapsulation film layer, and a second inorganic encapsulation film layer on a base substrate for forming a display device, the first inorganic encapsulation film layer and the second inorganic encapsulation film layer
  • the inorganic packaging film layer is encapsulated in the second isolation area, the encapsulation dam area, the first isolation area, the wiring area, the display area, and the blind hole area; the organic packaging film layer is located in the The packaging dam area, the first isolation area, the wiring area, the display area and the blind hole area.
  • the first encapsulation dam of the display substrate includes a third part located on a side of the interlayer dielectric layer away from the base substrate, and a third part of the third part away from the interlayer
  • the first spacer part on the side of the dielectric layer, the second encapsulation dam further includes a second spacer part on the side of the second part away from the base substrate, and the third spacer part of the first encapsulation dam
  • the first spacer part, the second part and the second spacer part of the second packaging dam, and the pixel defining part are formed by the same patterning process.
  • the same film structure as the driving circuit layer can be formed in the wiring area 10d and the through-hole area 10b as a redundant pixel structure (Dummy pixel).
  • the redundant pixel structure of the through hole area may be the same as the pixel structure shown in FIG. 7 or FIG. Of course, the redundant pixel structure may not be provided.
  • the redundant pixel structure 208 located in the wiring area can be arranged at a position other than the signal line routing.
  • the redundant pixel structure is connected to the EOA signal line of the corresponding row, and the GOA signal line is connected.
  • the redundant pixel structure is connected to the data of the corresponding column.
  • the wires are also connected and can be set to emit light if necessary.
  • FIG. 12 shows a redundant pixel structure 208 according to an embodiment of the present disclosure.
  • the redundant pixel structure 208 has no anode 212 (to avoid light reflection) and corresponding wiring.
  • FIG. 13 shows a redundant pixel structure 208 according to another embodiment of the present disclosure.
  • the redundant pixel structure 208 has an anode 212, but there is no gap between the anode 212 and the drain 211.
  • the opening avoids the connection between the two, and the other structure is exactly the same as the pixel structure in the display area 10a.
  • the redundant pixel structure at the via area 10b is removed, leaving only the redundant pixel structure at the wiring area 10d.
  • a positioning mark structure 107 is further provided on the display substrate in the through hole region 10b for cutting and positioning.
  • the positioning mark structure 107 can be formed by the same patterning process as the source and drain layers. There is no redundant pixel structure at the location of the positioning mark structure 107.
  • the pixel defining layer 213 may be completely removed from the wiring area, or the pixel defining layer may be all retained, and the pixel defining layer may not be provided for accommodating organic light.
  • the pixel defining layer can also be reserved in an area of a few pixels in a circle near the display area in the wiring area, except that the pixel defining layer is completely removed from the wiring area.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括显示区（10a）、布线区（10d）、至少一个通孔区（10b）和至少一个盲孔区（10c），布线区（10d）围绕至少一个通孔区（10b）和至少一个盲孔区（10c），显示区（10a）围绕布线区（10d），显示基板包括：衬底基板（100）；驱动电路层（200），其形成在衬底基板（100）上，驱动电路层（200）包括位于显示区（10a）、布线区（10d）和盲孔区（10c）的层间介质层（203），其中，布线区（10d）包括在层间介质层（203）上围绕通孔区（10b）和盲孔区（10c）设置的多条信号线，并且多条信号线不遮挡通孔区（10b）和盲孔区（10c），显示基板在盲孔区（10c）透光。

Description

显示基板及其制备方法、显示装置 技术领域
本公开属于显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
已经对柔性面板进行挖槽、挖孔等来满足用户对电子设备产品日益提高的屏占比要求。目前较为成熟的、屏占比最高的技术为屏内开孔技术。
屏内开孔技术需牺牲显示面板的部分显示区域(Active Area)，该牺牲的显示区域用于布置摄像头、传感器等光学器件。
发明内容
根据本公开的一个方面，提供了一种显示基板，包括显示区、布线区、至少一个通孔区和至少一个盲孔区，所述布线区围绕所述至少一个通孔区和所述至少一个盲孔区，所述显示区围绕所述布线区，其中，所述显示基板包括：衬底基板；驱动电路层，其形成在所述衬底基板上，所述驱动电路层包括位于所述显示区、所述布线区和所述盲孔区的层间介质层，其中，所述布线区包括在所述层间介质层上围绕所述通孔区和所述盲孔区设置的多条信号线，并且所述多条信号线不遮挡所述通孔区和所述盲孔区，所述显示基板在所述盲孔区透光。
在一些实施例中，所述至少一个通孔区包括两个通孔区，所述至少一个盲孔区包括一个盲孔区，并且该盲孔区设置于所述两个通孔区之间。
在一些实施例中，所述通孔区为圆形或胶囊形。
在一些实施例中，所述盲孔区为矩形或宽度不同的矩形沿长度方向的拼接形状。
在一些实施例中，所述多条信号线包括数据线、发光控制信号 线和栅极驱动信号线，所述数据线沿第一方向延伸，所述发光控制信号线和所述栅极驱动信号线沿与所述第一方向不同的第二方向延伸。
在一些实施例中，所述数据线包括围绕所述通孔区延伸的部分或围绕所述盲孔区延伸的部分。
在一些实施例中，所述发光控制信号线和所述栅极驱动信号线包括围绕所述通孔区的部分和围绕所述盲孔区的部分。
在一些实施例中，所述显示区包括有机发光二极管，所述布线区还包括冗余像素结构，所述冗余像素结构不包括有机发光二极管的阳极。
在一些实施例中，所述驱动电路层包括位于所述衬底基板上的位于所述布线区、所述显示区和所述盲孔区的第一绝缘层、第二绝缘层和所述层间介质层。
在一些实施例中，所述驱动电路层还包括位于所述显示区的薄膜晶体管，所述薄膜晶体管包括有源层、栅极、源极和漏极，其中，所述薄膜晶体管的有源层位于所述衬底基板上，所述第一绝缘层位于所述有源层远离所述衬底基板的一侧；所述栅极位于所述第一绝缘层远离所述有源层的一侧，所述第二绝缘层位于所述栅极远离所述第一绝缘层的一侧；所述层间介质层位于所述第二绝缘层远离所述第一绝缘层的一侧；所述源极和所述漏极位于所述层间介质层远离所述第二绝缘层的一侧，其中，所述多条信号线、所述源极和所述漏极同层设置。
在一些实施例中，所述布线区还包括冗余过孔，所述冗余过孔位于所述第一绝缘层、所述第二绝缘层和所述层间介质层，且贯穿到所述有源层。
在一些实施例中，所述显示基板还包括平坦化层，所述平坦化层位于所述显示区、所述布线区和所述盲孔区，并形成在所述层间介质层远离所述衬底基板的一侧。
在一些实施例中，所述显示基板还包括封装坝区，所述封装坝区位于所述布线区与所述通孔区之间并且环绕所述通孔区，至少一条封装坝设置于所述封装坝区并且环绕所述通孔区，所述至少一条封装 坝位于所述层间介质层的远离所述衬底基板的一侧。
在一些实施例中，所述至少一条封装坝包括第一封装坝和第二封装坝，所述第一封装坝位于所述第二封装坝的远离所述通孔区的一侧，所述第二封装坝的沿垂直于所述衬底基板方向上的厚度大于所述第一封装坝的厚度，所述第二封装坝包括第一部和设置于所述第一部上的第二部，所述第一部与所述平坦层同层设置。
在一些实施例中，所述显示基板还包括第一隔离区和第二隔离柱区，所述第一隔离区位于所述布线区与所述封装坝区之间，所述第二隔离区位于所述通孔区与所述封装坝区之间，所述显示基板还包括至少一个第一隔离柱，其形成在所述层间介质层远离所述衬底基板的一侧并位于所述第一隔离区，所述第一隔离柱环绕所述第一封装坝设置，所述第一隔离柱的侧壁设置有凹槽，所述显示基板还包括至少一个第二隔离柱，其形成在所述层间介质层远离所述衬底基板的一侧并位于所述第二隔离区，所述第二隔离柱环绕所述通孔区设置，所述第二隔离柱的侧壁设置有凹槽，所述第一隔离柱、所述第二隔离柱和所述多条信号线同层设置。
在一些实施例中，所述显示基板还包括位于所述第二隔离区的第一膜层和第二膜层，所述第一膜层环绕所述通孔区，所述第二隔离柱在所述衬底基板上的正投影位于所述第一膜层在所述衬底基板上的正投影中；所述第二膜层环绕所述通孔区，所述第二隔离柱在所述衬底基板上的正投影位于所述第二膜层在所述衬底基板上的正投影中，所述第一膜层与所述栅极同层设置，所述第一隔离柱和所述第二隔离柱均包括在所述层间介质层的远离所述衬底一侧的第一金属层、第二金属层及第三金属层，所述第二金属层在所述层间介质层上的正投影的外边界位于所述第一金属层、所述第三金属层在所述层间介质层上的正投影的外边界内侧，以在所述隔离柱的侧壁形成所述凹槽，所述第一金属层和所述第三金属层为钛层，所述第二金属层为铝层。
在一些实施例中，所述显示基板还包括位于所述有机发光二极管上的封装层，其中，所述有机发光二极管位于所述显示区，并包括依次形成在所述平坦层上的阳极、像素界定部、有机功能层和阴极， 所述封装层包括依次层叠设置的第一无机封装薄膜层、有机封装薄膜层和第二无机封装薄膜层，所述第一无机封装薄膜层和所述第二无机封装薄膜层封装位于所述第二隔离区、所述封装坝区、所述第一隔离区、所述布线区、所述显示区和所述盲孔区；所述有机封装薄膜层位于所述封装坝区、所述第一隔离区、所述布线区、所述显示区和所述盲孔区，所述封装层透光，所述第一封装坝包括位于所述层间介质层上的第三部以及所述第三部上的第一隔垫部，所述第二封装坝还包括位于所述第二部上的第二隔垫部，所述第一封装坝的第三部和第一隔垫部、所述第二封装坝的第二部和第二隔垫部、与所述像素界定部同层设置。
根据本公开的一个方面，提供了一种显示装置，其包括以上所述的显示基板，所述显示装置还包括：至少一个第一传感器，其分别对应所述至少一个通孔区位于所述显示基板的远离驱动电路层的一侧；至少一个第二传感器，其分别对应所述至少一个盲孔区位于所述显示基板的与所述至少一个第一传感器相同的一侧。
在一些实施例中，所述至少一个第一传感器包括摄像头，所述至少一个第二传感器包括红外传感器、接近光传感器、泛光照明器、环境光传感器中的至少一种。
根据本公开的一个方面，提供了一种显示基板的制备方法，所述显示基板包括显示区、布线区、至少一个通孔区和至少一个盲孔区，所述布线区围绕所述至少一个通孔区和所述至少一个盲孔区，所述显示区围绕所述布线区，所述方法包括：提供一衬底基板；在所述衬底基板上形成驱动电路层，所述驱动电路层包括位于所述显示区、所述布线区和所述至少一个盲孔区的层间介质层，所述布线区包括在所述层间介质层上围绕所述通孔区和所述盲孔区设置的多条信号线，并且所述多条信号线不遮挡所述通孔区和所述盲孔区，所述显示基板在所述盲孔区透光,其中，所述多条信号线以及所述驱动电路层中的薄膜晶体管的源极和漏极通过同一构图工艺形成。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1a为根据本公开实施例的显示基板的俯视图；
图1b为根据本公开实施例的一种显示基板的整体电路架构示意图；
图2a为图1a中的显示基板在通孔区和盲孔区的放大图；
图2b为根据本公开实施例的显示基板在通孔区和盲孔区的放大图；
图2c为根据本公开实施例的显示基板在通孔区和盲孔区的放大图；
图3为图2a的沿A-A’的剖面图；
图4为显示基板切割通孔区之前的剖视图；
图5为根据本公开实施例的通孔区和盲孔区的布线图；
图6为图4的虚线框B内盲孔的剖视图；
图7为根据本公开实施例的显示基板的显示区的剖视图；
图8为根据本公开实施例的显示基板的显示区的剖视图；
图9为根据本公开实施例的图4中的第一阻隔区的放大图；
图10为根据本公开实施例的图4中的第二阻隔区的放大图；
图11为根据本公开实施例的布线区的放大图；
图12为根据本公开实施例的冗余像素结构的剖视图；
图13为根据本公开实施例的冗余像素结构的剖视图；
图14为根据本公开的实施例的显示基板的制备方法流程图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
显示屏内开孔包括通孔(Punch Hole)和盲孔(Transparent Hole)两种。通孔设计的优点为开孔处无膜层遮挡光学器件，适合摄像头等 透过率要求高的元件。在盲孔处，实际开孔处还保留有透明膜层，透过率低于无膜层的通孔，但高于有机发光二极管(Organic Light-Emitting Diode，OLED)显示屏的正常显示区域，通常用于透过率要求稍低的元件。
通孔设计需要在通孔周边增加封装结构以确保产品的可靠性，这会增大边框；而盲孔设计不需封装结构，比较容易获得窄边框。目前，发明人发现，相关产品仅存在通孔和盲孔中的一种。若采用通孔，则通孔仅用来放置摄像头，其余光学传感器需放置于边框，占用边框尺寸。若采用盲孔，由于透过率损失，造成摄像头成像质量稍差。
根据本公开的一个方面，提供了一种显示基板。如图1a和图2a所示，该显示基板包括显示区10a、布线区10d、至少一个通孔区10b和至少一个盲孔区10c。布线区10d围绕至少一个通孔区10b和至少一个盲孔区10c，显示区10a围绕布线区10d。如图1a所示，该显示基板包括两个通孔区和一个盲孔区，并且该盲孔区设置于所述两个通孔区之间。也可以根据需要以其他方式来布置通孔区和盲孔区，例如盲孔区不设置在通孔区之间，而在两个相邻的通孔区之外设置盲孔区。通孔区10b内设置有通孔，盲孔区10c内设置有盲孔，盲孔和通孔的形状可以为圆形、矩形、或者其他规则或不规则形状。如图2b所示，两个通孔区10b中的通孔的形状为圆形，两个通孔区10b之间的盲孔区10c中的盲孔为两个尺寸不同的矩形拼接形成的类似奶瓶的形状；如图2c所示为相邻的一个大通孔区10b1和一个小通孔区10b2的布置，该大通孔区10b1为对矩形的直角进行圆倒角后的类似胶囊的形状，该小通孔区10b2为圆形。
通孔和盲孔的尺寸可以根据需要设置，如图1a和图2a所示，通孔或盲孔为圆形时，其直径可在2mm-4mm范围内。如图2b所示，圆形通孔的直径可在2mm-4mm范围内，不规则形状的盲孔沿长度和宽度方向的尺寸需根据需要而与圆形通孔的尺寸配合。如图2c所示，胶囊形通孔的长度可在9mm-10mm范围内，宽度可为4mm；圆形通孔的直径可为4mm。胶囊形通孔10b1的左边部分可以对应放置摄像头，胶囊型通孔10b1的右边部分可以对应放置传感器，即对应图2b所示 的盲孔区10c的位置。大通孔10b1和小通孔10b2之间的间距要保证10b1的封装坝和10b2的封装坝之间的间距满足一定要求，使得该区域的有机封装薄膜层不至于太薄。
本公开以图1a和图2a所示的通孔区和盲孔区为例来进行说明。
图1b为一种显示基板的整体电路架构的示意图。例如，如图1b所示，1001表示显示基板的整体外框线；显示基板包括有效显示区(即像素阵列区)10a以及位于有效显示区10a周边的周边区域，该有效显示区包括阵列排布的像素单元1002；该周边区域包括移位寄存器单元1003，多个级联的移位寄存器单元1003组成栅极驱动电路，用于向显示基板1001的有效显示区10a的阵列排布的像素单元1002提供例如逐行移位的栅极扫描信号；该周边区域还包括发光控制单元1004，多个级联的发光控制单元1004组成发光控制阵列，用于向显示面板1001的有效显示区10a中的阵列排布的像素单元1002提供例如逐行移位的发光控制信号。
如图1b所示，与数据驱动芯片IC连接的数据线D1-DN(N为大于1的整数)纵向穿过有效显示区10a，以为阵列排布的像素单元1002提供数据信号；与移位寄存器单元1003连接的GOA信号线G1-GM(M为大于1的整数)横穿有效显示区10a，以为阵列排布的像素单元提供栅极扫描信号，与发光控制单元1004连接的EOA信号线E1-EM(M为大于1的整数)横穿有效显示区10a以为阵列排布的像素单元提供发光控制信号。例如，各个像素单元1002可以包括本领域内的具有7T1C、8T2C或4T1C等电路结构的像素电路和发光元件，像素电路在通过数据线传输的数据信号和通过栅线传输的栅极扫描信号和发光控制信号的控制下工作，以驱动发光元件发光从而实现显示等操作。该发光元件例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)。
如图3和图4所示，该显示基板包括衬底基板100和驱动电路层200。驱动电路层200形成在衬底基板100上，其包括位于显示区10a、布线区10d和盲孔区10c的层间介质层。衬底基板100可包括衬底101以及设置于衬底101上的缓冲层102，并且衬底基板100可 以为其他复合衬底基板。所述衬底基板为柔性基板，所述驱动电路层设置于所述缓冲层上。如图5所示，布线区10d包括在层间介质层上围绕通孔区10b和盲孔区10c设置的多条信号线，多条信号线不遮挡通孔区10b和盲孔区10c，并且显示基板在盲孔区10c透光。
由于通孔区10b中的通孔的光透光率最高，可用于摄像头等要求光透过率高的元件；由于盲孔区10c中的盲孔的光透过率低，可用于红外传感器、接近光传感器、泛光照明器、环境光传感器等光透过率较低的元件。由于盲孔无需设置封装结构，相比于通孔设计，有利于提高显示区的占比以及实现窄边框；而通孔设计，可以提高摄像头的成像质量。如图3所示，可以将摄像头等要求光透过率高的元件104正对通孔设置在显示基板的远离驱动电路层的一侧，并且可以延伸进入通孔中；可以将红外传感器、接近光传感器、泛光照明器、环境光传感器等光透过率较低的元件105正对盲孔设置在显示基板的一侧，并且光透过率高的元件104和光透过率较低的元件105设置在显示基板的同侧。
为了防止布线遮挡进入通孔和盲孔的光线，如图5和2a所示，在本公开中，布线区10d中的多条信号线围绕通孔区10b和盲孔区10c设置，而不遮挡通孔区10b和盲孔区10c。如图4所示，布线区10d中的布线2也包括类似第一隔离柱1c和第二隔离柱1e的三层金属结构，两者不同之处在于不需对布线2进行蚀刻形成第一隔离柱1c和第二隔离柱1e中的第二金属层处的凹槽。并且在布线区10d所在区域，分别与显示区的栅极205和第二极板231对应形成同层的金属跳线2d，以对跨层的信号线进行连接。布线区10d中的信号线可包括发光控制(EOA)信号线2a、源极信号线2b和栅极驱动(GOA)信号线2c等。如图5所示，细实线均表示源极信号线2b,即数据线，短虚线表示GOA信号线2c,点划线表示EOA信号线2a,总体上EOA信号线2a和GOA信号线2c彼此平行且沿两个通孔中心的连线平行的方向(第二方向)在显示基板上延伸，而在通孔区和盲孔区处，EOA信号线和GOA信号线环绕其中的通孔和盲孔设置来避免遮挡进入盲孔和通孔的光线；总体上源极信号线2b沿与EOA信号线2a和GOA信号 线2c垂直的方向(第一方向)在显示基板上延伸，而仅在通孔区和盲孔区处，源极信号线环绕其中的通孔和盲孔设置来避免遮挡进入盲孔和通孔的光线。如图5所示，在通孔区，EOA信号线2a、源极信号线2b和GOA信号线2c均位于过渡区10e的远离通孔的一侧；在盲孔区，由于未设置过渡区10e，EOA信号线2a、源极信号线2b和GOA信号线2c均位于盲孔区的周围。如图1a所示，多条信号线2包括在层间介质层203上的第四金属层、第五金属层及第六金属层，并且第四金属层、第五金属层第六金属层分别与第一金属层306、第二金属层307及所第三金属层308同层设置。
具体地，如图2a所示，布线区10d还设置有冗余像素结构208，冗余像素结构208与EOA信号线和数据线连接，还与GOA信号线连接(图中未示出)，冗余像素结构208的具体结构如图12或13所示。具体地，在一些实施例中，布线区还包括冗余过孔209，冗余过孔在层间介质层打孔时形成，该过孔露出有源层，冗余过孔可以位于除冗余像素结构和信号线之外的布线区，一般位于冗余像素结构和信号线之间，其空间无法再设置冗余像素结构，此时可以设置冗余过孔，冗余过孔的大小可以根据空间大小设置，数量也可以不限制，其目的是为了平衡布线区和显示区过孔密度的差异，保证TFT特性均一。
具体地，在一些实施例中，驱动电路层在位于布线区10d、显示区10a和盲孔区10c、在远离衬底基板100的一侧依次设置有第一绝缘层201、第二绝缘层202和层间介质层203。如图4所示，在盲孔区10c处的B区域示出了盲孔区10c。如图6所示，B区域包括依次设置的第一绝缘层201、第二绝缘层202和层间介质层203。布线区10d和显示区10a具有与盲孔区10c相同的第一绝缘层201、第二绝缘层202和层间介质层203，此处不加赘述。
在一些实施例中，驱动电路层200还包括位于显示区10a的薄膜晶体管。该薄膜晶体管可为顶栅型，包括有源层、栅极、源极和漏极。如图7为显示区10a的剖视图，薄膜晶体管的有源层204位于衬底基板100上，第一绝缘层201位于有源层204上；栅极205位于第一绝缘层201上，所述第二绝缘层位于栅极205上；源极210和漏极 211位于层间介质层203上，并分别位于栅极205的相对两侧，该源极210和漏极211可分别通过过孔(例如：金属过孔)与有源层204的相对两侧接触。应当理解的是，此薄膜晶体管也可为底栅型。多条信号线、源极210和漏极211同层设置。
如图7所示，电容结构可包括第一极板230和第二极板231，此第一极板230与栅极205同层设置，第二极板231位于第二栅绝缘层202与层间介质层203之间，并与第一极板230相对设置。
栅极205和第一极板230、第二极板231的材料可以包括金属材料或者合金材料，例如包括钼、铝及钛等。源极210和漏极211可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Al/Ti/Al)等。
在一些实施例中，如图4所示，该显示基板还包括平坦化层206，该平坦化层可位于显示区10a、布线区10d和盲孔区10c，并形成在层间介质层203上。该平坦化层206透光。平坦化层206可由氮化硅、氧化硅等材料制成。
在一些实施例中，如图4所示，该显示面板还包括过渡区10e。过渡区10e包括位于布线区10d与通孔区10b之间并且环绕通孔区10b的封装坝区10e2。至少一条封装坝设置于封装坝区10e2中并且环绕通孔区10b位于层间介质层103的远离衬底基板100的一侧。该至少一条封装坝包括第一封装坝1a和第二封装坝1b，所述第一封装坝1a位于所述第二封装坝1b的远离所述通孔区10b的一侧，所述第二封装坝1b的沿垂直于所述衬底基板100方向上的厚度大于所述第一封装坝1a的厚度，所述第二封装坝1b包括第一部303和设置于所述第一部上的第二部304，所述第一部303与所述平坦层206同层设置。
在一些实施例中，如图4所示，该过渡区10e还包括第一隔离区10e1，所述第一隔离区10e1位于所述布线区10d与所述封装坝区10e2之间。所述显示基板还包括至少一个第一隔离柱1c，其形成在所述层间介质层206远离所述衬底基板100的一侧并位于所述第一隔 离区10e1中，所述第一隔离柱1c环绕所述第一封装坝1a设置，所述第一隔离柱1c的侧壁设置有凹槽。至少一个第一隔离柱1c可以隔断有机发光材料以避免水氧侵入发光器件。
在一些实施例中，如图4所示，该过渡区10e还包括第二隔离区10e3，所述第二隔离区10e3位于所述通孔区10b与所述封装坝区10e2之间。所述显示基板还包括至少一个第二隔离柱1e，其形成在所述层间介质层203远离所述衬底基板100的一侧并位于所述第二隔离区10e3中，所述第二隔离柱1e环绕所述通孔区10b设置，所述第二隔离柱1e的侧壁设置有凹槽，以隔断有机发光材料以避免水氧侵入发光器件。
如图4所示，还标示出了用于对通孔进行切割的切割线，通孔的切割线至显示区10a之间区域构成通孔的边框。该边框包括过渡区10e和布线区10d，通常在400um-1mm范围内。通孔和盲孔的尺寸越大，其周围所需的绕线越多，通常通孔之间或通孔和盲孔之间的距离需要满足设置绕线和隔离柱、和/或封装坝的要求。
如图8所示为图4中第一隔离区10e1的放大图，如图9所示为图4中第二隔离区10e3的放大图，所述第一隔离柱1c和所述第二隔离柱1e均包括在所述层间介质层203上的第一金属层306、第二金属层307及第三金属层306，所述第二金属层307在所述层间介质层203上的正投影的外边界位于所述第一金属层306、所述第三金属层308在所述层间介质层203上的正投影的外边界内侧，以在所述隔离柱的侧壁形成所述凹槽，所述第一金属层306和所述第三金属层308为钛层，所述第二金属层307为铝层。并且，图8中的第一隔离柱1c之间具有第一间隔1d，图9中的第二隔离柱之间具有第二间隔1f。
图9与图8的区别在于对应第二隔离柱1e还设置有第一膜层233和第二膜层234。第一膜层233和第二膜层234均位于第二隔离区10e3，所述第一膜层233环绕所述通孔区10b，所述第二隔离柱1e在所述衬底基板100上的正投影位于所述第一膜层233在所述衬底基板100上的正投影中；所述第二膜层234环绕所述通孔区10b，所述第二隔离柱1e在所述衬底基板100上的正投影位于所述第二膜 层234在所述衬底基板上的正投影中。所述第一膜层233与所述第一栅极同层设置，所述第二膜层234与所述第二极板231同层设置。第一膜层233和第二膜层234可由分别与栅极和第二极板231对应的金属制成，用于抬高第二隔离柱1e，还能缓解衬底基板产生裂纹。
如图4所示，所述第一隔离柱1c、所述第二隔离柱1e和所述多条信号线同层设置。
在一些实施例中，如图7所示，该显示基板还包括显示器件和位于所述显示器件上的封装层118。所述显示器件位于所述显示区，并包括依次形成在所述平坦层206上的第一电极212、像素界定部213、有机功能层214和第二电极215。具体地，有机发光二极管包括第一电极212，有机功能层214和第二电极215，第一电极212可以为阳极，第二电极215可以为阴极。像素界定部213和第二电极215之间还设置有支撑部232，支撑部232可与像素界定部213同层且采用相同材料制成。封装层118包括依次层叠设置的第一无机封装薄膜层118a、有机封装薄膜层118b和第二无机封装薄膜层118c。如图4所示，所述第一无机封装薄膜层118a和所述第二无机封装薄膜层118c封装位于所述第二隔离区10e3、所述封装坝区10e2、所述第一隔离区10e1、所述布线区10d、所述显示区10a和所述盲孔区10c。所述有机封装薄膜层118b位于所述第一隔离区10e1、所述布线区10d、所述显示区10a和所述盲孔区10c，所述封装层118透光。
在一些实施例中，如图8所示，第一电极212还可通过转接电极133与漏极211电性连接。当第一电极212通过转接电极133与漏极211电性连接时，该平坦化层206可为双层结构，具体可包括依次形成的第一平坦化膜(PLN1)层206a及第二平坦化膜(PLN2)层206b，此外，在第一平坦化膜层116a与层间介质层103之间还可形成钝化膜(PVX)层134，该钝化膜层134可由氧化硅、氮化硅或者氮氧化硅等材料形成；该钝化膜层134覆盖源极110、漏极111；而转接电极133形成在第一平坦化膜层116a与第二平坦化膜层116b之间，并依次通过第一平坦化膜层116a及钝化膜层134上的过孔(例如金属过孔)与漏极111电性连接；而第一电极112可通过第二平坦化膜层 116b上的过孔(例如金属过孔)与转接电极133电性连接。
在一些实施例中，如图4所示，所述第一封装坝1a包括位于所述层间介质层203上的第三部301以及所述第三部上的第一隔垫部302，所述第二封装坝1b还包括位于所述第二部304上的第二隔垫部305，所述第一封装坝1a的第三部301和第一隔垫部302、所述第二封装坝1b的第二部304和第二隔垫部305、与所述像素界定部213同层设置。
如图4所示和图6所示，盲孔区10c中的膜层结构包括衬底基板100、第一绝缘层201、第二绝缘层202、层间介质层203、平坦层206和封装层118。也可以对该盲孔区10c中的多个膜层进行蚀刻以保留部分上述膜层结构，例如，盲孔区10c中的膜层可以包括第一绝缘层201、第二绝缘层202、层间介质层203、平坦层206和封装层118中的一层或多层，如仅包括一绝缘层201、第二绝缘层202和层间介质层203，或者仅包括第一绝缘层201、第二绝缘层202、层间介质层203和平坦层206。通常，盲孔区10c保留图4中示出的各层，以保持显示基板厚度不产生大的变化，避免采用贴合工艺贴合各层时在各层间产生贴合气泡。光沿着光线入射方向穿过各膜层从而到达盲孔对应的传感器105。这样，为了能够具有一定的光透过率，就要求衬底基板100、第一绝缘层201、第二绝缘层202、层间介质层203、平坦层206和封装层118均由透明材料制成，例如衬底基板100可由聚酰亚胺等有机材料制成并且可以为包括衬底、阻挡层和缓冲层等的复合衬底，第一绝缘层201、第二绝缘层202、层间介质层203可由氧化硅、氮氧化硅等制成。平坦层206可采用有机材料制作而成，例如：光刻胶、丙烯酸基聚合物、硅基聚合物等材料。封装层118的第一无机封装薄膜层118a、第二无机封装薄膜层118c用于防止水、氧从显示功能的显示侧及通孔区10b进入到显示区10a的显示器件中；该第一无机封装薄膜层118a和第二无机封装薄膜层118c可采用氮化硅、氧化硅等无机材料制作而成。有机封装薄膜层118b用于实现平坦化作用，以便于第二无机封装薄膜层118c层的制作，此有机封装薄膜层118b可采用丙烯酸基聚合物、硅基聚合物等材料制作而成。
根据本公开的另一方面，还提供了一种显示装置，该显示装置包括上述实施例的显示基板以及与用于驱动该显示面板的驱动电路。
在一些实施例中，该显示装置还包括至少一个第一传感器104，其分别正对着通孔区10b中的通孔设置并且位于所述显示基板的远离驱动电路层的一侧，并可延伸进入通孔中；至少一个第二传感器105，其分别正对着至少一个盲孔区10c中的盲孔设置并且与至少一个第一传感器104相同地位于显示基板的同一侧，如图3所示。至少一个第一传感器104例如包括摄像头，至少一个第二传感器105例如包括红外传感器、接近光传感器、泛光照明器、环境光传感器。相比于传统只进行通孔(放置摄像头)或通孔设计结合边框传感器布置，既保证了显示装置实现传感器功能的质量，又利于实现窄边框；相比于传统只进行盲孔或盲孔结合边框传感器布置，更有利于摄像头的成像质量又利于实现窄边框。
根据本公开的另一方面，还提供了一种显示基板的制备方法，如图14所示，包括以下步骤：S110，提供一衬底基板；S120，在衬底基板上形成驱动电路层。驱动电路层包括位于显示区、布线区和盲孔区的层间介质层。布线区包括在层间介质层上围绕通孔区和盲孔区设置的多条信号线，并且所述多条信号线不遮挡所述通孔区和所述盲孔区，所述显示基板在所述盲孔区透光。如图4所示，可以采用激光切割或者机械冲压的方式，切割掉通孔区10b处的显示基板，以得到具有通孔的显示基板。
应当理解的是，本公开实施例的提供的上述制作方法应该具备与本公开实施例提供的显示基板具有相同的特点和优点，所以，本公开实施例的提供的上述制作方法的特点和优点可以参照上文描述的显示基板的特点和优点，在此不再赘述。
在一些实施例中,所述至少一个通孔区可形成为包括两个通孔区，所述至少一个盲孔区形成为包括一个盲孔区，并且将该盲孔区设置于所述两个通孔区之间，所述通孔区形成为圆形或胶囊形，所述盲孔区形成为矩形或宽度不同的矩形沿长度方向的拼接形状。
在一些实施例中，在衬底基板上在所述显示区形成所述驱动电 路层进一步包括：在所述衬底基板上形成有源层；在所述有源层的远离所述衬底基板的一侧形成第一绝缘层；在所述第一绝缘层的远离所述有源层的一侧形成栅极；在所述栅极的远离所述第一绝缘层的一侧形成第二绝缘层；在所述第二绝缘层的远离所述栅极的一侧形成层间介质层；在所述层间介质层的远离所述第二绝缘层的一侧形成源极和漏极，其中，所述驱动电路层在所述盲孔区、所述布线区和所述显示区包括所述第一绝缘层、所述第二绝缘层和所述层间介质层，所述多条信号线、所述源极和所述漏极通过同一构图工艺形成。所述多条信号线包括数据线、发光控制信号线和栅极驱动信号线，所述数据线形成为沿第一方向延伸，所述发光控制信号线和所述栅极驱动信号线形成为沿与所述第一方向不同的第二方向延伸，所述数据线包括围绕所述通孔区或所述盲孔区延伸的部分，所述发光控制信号线和所述栅极驱动信号线包括围绕所述通孔区的部分和围绕所述盲孔区的部分。
在一些实施例中，该制备方法还包括在所述驱动电极层的远离所述衬底基板的一侧形成平坦化层，所述平坦化层位于所述显示区、所述布线区和所述盲孔区。
在一些实施例中，所述显示基板还包括封装坝区、第一隔离区和第二隔离区，所述封装坝区位于所述布线区与所述通孔区之间并且环绕所述通孔区，至少一条封装坝设置于所述封装坝区中并且环绕所述通孔区位于所述层间介质层的远离所述衬底基板的一侧，所述至少一条封装坝包括第一封装坝和第二封装坝，所述第一封装坝位于所述第二封装坝的远离所述通孔区的一侧，所述第二封装坝的沿垂直于所述衬底基板方向上的厚度大于所述第一封装坝的厚度，所述第二封装坝包括第一部和设置于所述第一部上的第二部，所述第一部与所述平坦层通过同一构图工艺形成；所述第一隔离区位于所述布线区与所述封装坝区之间，所述显示基板还包括至少一个第一隔离柱，其形成在所述层间介质层远离所述衬底基板的一侧并位于所述第一隔离区，所述第一隔离柱环绕所述第一封装坝设置，所述第一隔离柱的侧壁设置有凹槽；所述第二隔离区位于所述通孔区与所述封装坝区之间，所述显示基板还包括至少一个第二隔离柱，其形成在所述层间介质层远离 所述衬底基板的一侧并位于所述第二隔离区，所述第二隔离柱环绕所述通孔区设置，所述第二隔离柱的侧壁设置有凹槽，所述第一隔离柱、所述第二隔离柱和所述多条信号线通过同一构图工艺形成。
在一些实施例中，该制备方法还包括在所述层间介质层远离所述衬底基板的一侧形成位于所述显示区的有机发光二极管和位于所述布线区的冗余像素结构以及之后形成封装层，其中，所述显示器件位于所述显示区，并依次在所述平坦层上的形成所述显示器件的第一电极(阳极)、像素界定部、有机功能层和第二电极(阴极)，所述冗余像素结构不包括有机发光二极管的阳极。形成所述封装层包括在形成显示器件的衬底基板上依次层叠形成第一无机封装薄膜层、有机封装薄膜层和第二无机封装薄膜层，所述第一无机封装薄膜层和所述第二无机封装薄膜层封装位于所述第二隔离区、所述封装坝区、所述第一隔离区、所述布线区、所述显示区和所述盲孔区；所述有机封装薄膜层位于所述封装坝区、所述第一隔离区、所述布线区、所述显示区和所述盲孔区。
在一些实施例中，所述显示基板的第一封装坝包括位于所述层间介质层的远离所述衬底基板一侧的第三部以及所述第三部的远离所述所述层间介质层一侧的第一隔垫部，所述第二封装坝还包括位于所述第二部的远离所述衬底基板一侧的第二隔垫部，所述第一封装坝的第三部和第一隔垫部、所述第二封装坝的第二部和第二隔垫部、与所述像素界定部通过同一构图工艺形成。
如图4所示，在对通孔区10b处的显示基板切割之前，可按照通常工艺，在布线区10d以及通孔区10b形成与驱动电路层相同的膜层结构作为冗余像素结构(Dummy pixel)。通孔区的冗余像素结构可以和图7或图8所示的像素结构相同，设置冗余像素结构可使得显示基板厚度均匀，并使得切割均匀。当然，也可不设置冗余像素结构。位于布线区的冗余像素结构208可以设置在除信号线走线之外的位置，冗余像素结构与对应行的EOA信号线，GOA信号线是连接的，冗余像素结构与对应列的数据线也是连接的，如有需要也是可以设置为发光的，但是考虑布线区设置的冗余像素结构的数量有限，通常是不 发光的，即图2a示例性示出了布线区10d中的冗余像素结构208，图12示出根据本公开实施例的冗余像素结构208，与显示区10a中的像素结构相比，该冗余像素结构208没有阳极212(避免反光)及对应的连线，在平坦化层206中也没有设置阳极212与漏极211连接的过孔，其他结构与显示区10a中的像素结构完全相同。图13示出根据本公开另一实施例的冗余像素结构208，与显示区10a中的像素结构相比，该冗余像素结构208具有阳极212，但没有阳极212与漏极211之间的开口以避免两者连接，其他结构与显示区10a中的像素结构完全相同。在切割显示基板之后，通孔区10b处的冗余像素结构被去除，仅留下布线区10d的冗余像素结构。如图2b-图2c所示，在未对显示基板切割前，在通孔区10b中的显示基板上还设置有定位标记结构107，以用于切割定位。定位标记结构107可与源漏极层通过同一构图工艺形成。定位标记结构107位置处没有冗余像素结构。
在一些实施例中，如图2a-图2c所示的层结构中，布线区整体可以全部去除像素界定层213，也可以全部保留像素界定层，像素界定层也可以不用设置用于容纳有机发光元件的开口，也可以在布线区靠近显示区的一圈几个像素的区域内保留像素界定层，除此之外布线区全部去除像素界定层。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围

Claims (20)

  1. 一种显示基板，包括显示区、布线区、至少一个通孔区和至少一个盲孔区，所述布线区围绕所述至少一个通孔区和所述至少一个盲孔区，所述显示区围绕所述布线区，其中，
    所述显示基板包括：
    衬底基板；
    驱动电路层，其形成在所述衬底基板上，所述驱动电路层包括位于所述显示区、所述布线区和所述盲孔区的层间介质层，
    其中，所述布线区包括在所述层间介质层上围绕所述通孔区和所述盲孔区设置的多条信号线，并且所述多条信号线不遮挡所述通孔区和所述盲孔区，所述显示基板在所述盲孔区透光。
  2. 根据权利要求1所述的显示基板，其中，所述至少一个通孔区包括两个通孔区，所述至少一个盲孔区包括一个盲孔区，并且该盲孔区设置于所述两个通孔区之间。
  3. 根据权利要求1或2所述的显示基板，其中，所述通孔区为圆形或胶囊形。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述盲孔区为矩形或宽度不同的矩形沿长度方向的拼接形状。
  5. 根据权利要求1至4中任一所述的显示基板，其中，所述多条信号线包括数据线、发光控制信号线和栅极驱动信号线，所述数据线沿第一方向延伸，所述发光控制信号线和所述栅极驱动信号线沿与所述第一方向不同的第二方向延伸。
  6. 根据权利要求5所述的显示基板，其中，所述数据线包括围绕所述通孔区延伸的部分或围绕所述盲孔区延伸的部分。
  7. 根据权利要求5所述的显示基板，其中，所述发光控制信号线和所述栅极驱动信号线包括围绕所述通孔区的部分和围绕所述盲孔区的部分。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述显示区包括有机发光二极管，所述布线区还包括冗余像素结构，所述冗余像素结构不包括有机发光二极管的阳极。
  9. 根据权利要求1至8中任一项所述的显示基板，其中，所述驱动电路层包括位于所述衬底基板上的位于所述布线区、所述显示区和所述盲孔区的第一绝缘层、第二绝缘层和所述层间介质层。
  10. 根据权利要求9所述的显示基板，其中，所述驱动电路层还包括位于所述显示区的薄膜晶体管，所述薄膜晶体管包括有源层、栅极、源极和漏极，其中，
    所述薄膜晶体管的有源层位于所述衬底基板上，所述第一绝缘层位于所述有源层远离所述衬底基板的一侧；
    所述栅极位于所述第一绝缘层远离所述有源层的一侧，所述第二绝缘层位于所述栅极远离所述第一绝缘层的一侧；
    所述层间介质层位于所述第二绝缘层远离所述第一绝缘层的一侧；
    所述源极和所述漏极位于所述层间介质层远离所述第二绝缘层的一侧，
    其中，所述多条信号线、所述源极和所述漏极同层设置。
  11. 根据权利要求10所述的显示基板，其中，所述布线区还包括冗余过孔，所述冗余过孔位于所述第一绝缘层、所述第二绝缘层和所述层间介质层，且贯穿到所述有源层。
  12. 根据权利要求11所述的显示基板，还包括平坦化层，所述 平坦化层位于所述显示区、所述布线区和所述盲孔区，并形成在所述层间介质层远离所述衬底基板的一侧。
  13. 根据权利要求12所述的显示基板，还包括封装坝区，所述封装坝区位于所述布线区与所述通孔区之间并且环绕所述通孔区，至少一条封装坝设置于所述封装坝区并且环绕所述通孔区，所述至少一条封装坝位于所述层间介质层的远离所述衬底基板的一侧。
  14. 根据权利要求13所述的显示基板，其中，所述至少一条封装坝包括第一封装坝和第二封装坝，所述第一封装坝位于所述第二封装坝的远离所述通孔区的一侧，
    所述第二封装坝的沿垂直于所述衬底基板方向上的厚度大于所述第一封装坝的厚度，
    所述第二封装坝包括第一部和设置于所述第一部上的第二部，所述第一部与所述平坦层同层设置。
  15. 根据权利要求14所述的显示基板，还包括第一隔离区和第二隔离柱区，所述第一隔离区位于所述布线区与所述封装坝区之间，所述第二隔离区位于所述通孔区与所述封装坝区之间，
    所述显示基板还包括至少一个第一隔离柱，其形成在所述层间介质层远离所述衬底基板的一侧并位于所述第一隔离区，所述第一隔离柱环绕所述第一封装坝设置，所述第一隔离柱的侧壁设置有凹槽，
    所述显示基板还包括至少一个第二隔离柱，其形成在所述层间介质层远离所述衬底基板的一侧并位于所述第二隔离区，所述第二隔离柱环绕所述通孔区设置，所述第二隔离柱的侧壁设置有凹槽，
    所述第一隔离柱、所述第二隔离柱和所述多条信号线同层设置。
  16. 根据权利要求15所述的显示基板，还包括位于所述第二隔离区的第一膜层和第二膜层，
    所述第一膜层环绕所述通孔区，所述第二隔离柱在所述衬底基 板上的正投影位于所述第一膜层在所述衬底基板上的正投影中；
    所述第二膜层环绕所述通孔区，所述第二隔离柱在所述衬底基板上的正投影位于所述第二膜层在所述衬底基板上的正投影中，
    所述第一膜层与所述栅极同层设置，
    所述第一隔离柱和所述第二隔离柱均包括在所述层间介质层的远离所述衬底一侧的第一金属层、第二金属层及第三金属层，所述第二金属层在所述层间介质层上的正投影的外边界位于所述第一金属层、所述第三金属层在所述层间介质层上的正投影的外边界内侧，以在所述隔离柱的侧壁形成所述凹槽，
    所述第一金属层和所述第三金属层为钛层，所述第二金属层为铝层。
  17. 根据权利要求16所述的显示基板，还包括位于所述有机发光二极管上的封装层，其中，
    所述有机发光二极管位于所述显示区，并包括依次形成在所述平坦层上的阳极、像素界定部、有机功能层和阴极，
    所述封装层包括依次层叠设置的第一无机封装薄膜层、有机封装薄膜层和第二无机封装薄膜层，所述第一无机封装薄膜层和所述第二无机封装薄膜层封装位于所述第二隔离区、所述封装坝区、所述第一隔离区、所述布线区、所述显示区和所述盲孔区；所述有机封装薄膜层位于所述封装坝区、所述第一隔离区、所述布线区、所述显示区和所述盲孔区，所述封装层透光，
    所述第一封装坝包括位于所述层间介质层上的第三部以及所述第三部上的第一隔垫部，所述第二封装坝还包括位于所述第二部上的第二隔垫部，所述第一封装坝的第三部和第一隔垫部、所述第二封装坝的第二部和第二隔垫部、与所述像素界定部同层设置。
  18. 一种显示装置，包括根据权利要求1至17中任一项所述的显示基板，所述显示装置还包括：
    至少一个第一传感器，其分别对应所述至少一个通孔区位于所 述显示基板的远离驱动电路层的一侧；
    至少一个第二传感器，其分别对应所述至少一个盲孔区位于所述显示基板的与所述至少一个第一传感器相同的一侧。
  19. 根据权利要求18所述的显示装置，其中，所述至少一个第一传感器包括摄像头，所述至少一个第二传感器包括红外传感器、接近光传感器、泛光照明器、环境光传感器中的至少一种。
  20. 一种显示基板的制备方法，所述显示基板包括显示区、布线区、至少一个通孔区和至少一个盲孔区，所述布线区围绕所述至少一个通孔区和所述至少一个盲孔区，所述显示区围绕所述布线区，所述方法包括：
    提供一衬底基板；
    在所述衬底基板上形成驱动电路层，所述驱动电路层包括位于所述显示区、所述布线区和所述至少一个盲孔区的层间介质层，
    所述布线区包括在所述层间介质层上围绕所述通孔区和所述盲孔区设置的多条信号线，并且所述多条信号线不遮挡所述通孔区和所述盲孔区，所述显示基板在所述盲孔区透光，
    其中，所述多条信号线以及所述驱动电路层中的薄膜晶体管的源极和漏极通过同一构图工艺形成。
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CN110120990A (zh) * 2018-02-05 2019-08-13 广东欧珀移动通信有限公司 终端显示屏组件及移动终端
CN108847415A (zh) * 2018-06-29 2018-11-20 厦门天马微电子有限公司 一种阵列基板、栅极驱动电路以及显示面板
CN110942752A (zh) * 2018-09-21 2020-03-31 三星显示有限公司 显示面板
CN110890475A (zh) * 2019-11-28 2020-03-17 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置

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