WO2021200563A1 - Semiconductor element and device - Google Patents

Abstract

The purpose of the present technology is to provide a semiconductor element and a device that exhibit excellent pressure resistance. A semiconductor element (100) has: a first semiconductor layer (110); a second semiconductor layer (120); a third semiconductor layer (130); a fourth semiconductor layer (140); a drain electrode (D1) and a source electrode (S1) on the second semiconductor layer (120) or the third semiconductor layer (130); and a gate electrode (G1) on the fourth semiconductor layer (140). The source electrode (S1) is formed on a recessed section (X1). The drain electrode (D1) is formed on a recessed section (X2). The distance (Ld) between a drain electrode contacting region (DC1) and the third semiconductor layer (130) is larger than the distance (Ls) between a source electrode contacting region (SC1) and the third semiconductor layer (130).

Description

Semiconductor devices and equipment

The technical fields of this specification relate to semiconductor devices and devices.

Group III nitride semiconductors represented by GaN have a high dielectric breakdown electric field and a high melting point. Therefore, group III nitride semiconductors are expected as materials for high-power, high-frequency, high-temperature semiconductor devices to replace GaAs-based semiconductors. Therefore, HEMT devices and the like using group III nitride semiconductors have been researched and developed.

For example, Patent Document 1 discloses a technique for simultaneously generating electrons and holes by polarization bonding (see FIG. 4 and the like in Patent Document 1). Further, Patent Document 2 discloses a technique for forming a GaN layer, an AlGaN layer, a GaN layer, and a p-type GaN layer in this order (paragraph [0034] of Patent Document 2). As a result, a technique for raising the energy Ev at the upper end of the valence band of the p-type GaN layer to the Fermi level Ef to generate two-dimensional Hall gas is disclosed.

JP-A-2007-134607 WO2011 / 162243

Semiconductor devices are generally required to have excellent electrical characteristics. Such electrical characteristics include, for example, high withstand voltage, low on-resistance, short response time, responsiveness to large currents, and suppression of leak currents.

The problem to be solved by the technique of the present specification is to provide a semiconductor element and an apparatus having excellent withstand voltage.

The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. A semiconductor layer, a source electrode and a drain electrode on the second semiconductor layer or the third semiconductor layer, a gate electrode on the fourth semiconductor layer, and a gate electrode contact region where the gate electrode and the fourth semiconductor layer come into contact with each other. From the source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer contact, the drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer contact, and the fourth semiconductor layer. It has a first recess and a second recess that reach to the second semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The source electrode is formed on the first recess. The drain electrode is formed on the second recess. The distance between the drain electrode contact region and the third semiconductor layer is larger than the distance between the source electrode contact region and the third semiconductor layer.

In this semiconductor element, the distance between the drain electrode contact region and the third semiconductor layer is larger than the distance between the source electrode contact region and the third semiconductor layer. The electric field generated between the drain electrode contact region and the third semiconductor layer is relaxed. Therefore, this semiconductor device has excellent pressure resistance.

This specification provides at least one semiconductor device and device having excellent electrical characteristics.

It is a top view of the semiconductor element of 1st Embodiment. It is a figure which shows the laminated structure of the semiconductor element of 1st Embodiment. It is a figure which shows the contact area of the electrode of the element functional area of the semiconductor element of 1st Embodiment. It is an enlarged view around the source contact electrode and the drain contact electrode of the semiconductor element of 1st Embodiment. It is a figure (the 1) which shows the cross-sectional structure around the source electrode exposed region of the semiconductor element of 1st Embodiment. It is a figure which shows the cross-sectional structure around the drain electrode exposed region of the semiconductor element of 1st Embodiment. It is a figure which shows the cross-sectional structure around the gate electrode exposed region of the semiconductor element of 1st Embodiment. It is a figure (the 2) which shows the cross-sectional structure around the source electrode exposed region of the semiconductor element of 1st Embodiment. It is a figure which shows the positional relationship between the source electrode contact area and drain electrode contact area of the semiconductor element of 1st Embodiment, and an insulating layer. It is a figure which shows the wiring of the gate electrode of the semiconductor element of 1st Embodiment. It is a figure which shows the wiring of the source electrode of the semiconductor element of 1st Embodiment. It is a figure which shows the laminated structure of the source electrode and drain electrode of the semiconductor element of 1st Embodiment. It is a figure which shows the laminated structure of the gate electrode of the semiconductor element of 1st Embodiment. It is a figure which shows the 2D electron gas and 2D hall gas of the semiconductor element of 1st Embodiment. It is a figure which shows the band structure of the semiconductor element of 1st Embodiment. It is a schematic diagram conceptually showing the electric field when the reverse bias is applied to the gate electrode of the semiconductor element of 1st Embodiment. It is a figure (the 1) for demonstrating the manufacturing method of the semiconductor element of 1st Embodiment. It is a figure (the 2) for demonstrating the manufacturing method of the semiconductor element of 1st Embodiment. It is a figure (the 3) for demonstrating the manufacturing method of the semiconductor element of 1st Embodiment. It is a top view of the semiconductor element of the 2nd Embodiment. It is a figure which shows the laminated structure of the semiconductor element of 3rd Embodiment. It is a figure which shows the periphery of the gate pad electrode of the semiconductor element of 4th Embodiment. It is a figure which shows the cross-sectional structure around the drain electrode exposed region of the semiconductor element of 4th Embodiment. It is a top view of the semiconductor element in the modification of 4th Embodiment. It is an enlarged view around the gate pad electrode in the semiconductor element in the modification of 4th Embodiment. It is a figure which shows the laminated structure of the semiconductor element of 8th Embodiment. It is a figure which shows the electrode formation region of the semiconductor element of 8th Embodiment. It is a figure which shows the electrode formation region of the semiconductor element in the modification of 8th Embodiment. It is a figure (the 1) which shows the laminated structure of the semiconductor element in the modification of 8th Embodiment. It is a figure (the 2) which shows the laminated structure of the semiconductor element in the modification of 8th Embodiment. It is a figure (the 3) which shows the laminated structure of the semiconductor element in the modification of 8th Embodiment. It is a figure which shows the FET when the gate electrode contact area GC1 surrounds the source electrode contact area SC1. It is a figure which shows the FET when the gate electrode contact area GC1 is between the source electrode contact area SC1 and the drain electrode contact area DC1. It is a graph which shows the relationship between the gate voltage and the drain current when 0.1V is applied to the drain electrode of FET. It is a graph which shows the relationship between the gate voltage of FET and drain current. It is a graph which shows the relationship between the drain voltage of FET and the drain current. It is a graph which shows the relationship between the drain voltage and drain current at the time of off in FET. It is a graph which shows the relationship between the drain voltage at the time of off in FET, and the gate current. It is a circuit diagram used for the evaluation of FET. It is a graph which shows the output value in the evaluation of FET. It is a figure which shows the definition of the rise time tr and the fall time tf of FET. It is a table which shows the characteristic of FET. It is a graph which shows the relationship between the junction area of the 2nd undoped GaN layer (third semiconductor layer) and the Mg-doped pGaN layer (the fourth semiconductor layer) in FET, and the withstand voltage of a semiconductor element. It is a graph which shows the relationship between the gate length of FET and the response time. It is a graph which shows the relationship between the junction area and the response time of the 3rd semiconductor layer and the 4th semiconductor layer excluding the polarization superjunction region PSJ1 in FET. It is a graph which shows the relationship between the dislocation density and the junction area in FET. It is a table summarizing the data of FIG. 46. It is a graph which shows the relationship between the dislocation density in FET and the distance between source and drain. It is a table summarizing the data of FIG. 48. It is a graph which shows the relationship between the dislocation density and the response time in FET. It is a table summarizing the data of FIG. It is a graph which shows the relationship between the polarization superjunction length Lpsj and the normalized on-resistance in FET. It is a graph which shows the relationship between the source-drain distance and the normalized on-resistance in FET. It is a table which shows the relationship between the dislocation density in FET and the characteristic of a semiconductor element. It is a table which shows the relationship between the chip size of FET and the current value when a drain voltage Vd is 2V. It is a graph which shows the relationship between the active region area of FET and the current value when a drain voltage Vd is 2V. It is a table which shows the withstand voltage of the FET when the distance Lsd between the polarization superjunction length Lpsj, the source contact electrode S1c and the drain contact electrode D1c in the FET is changed. It is a table which shows the withstand voltage of the FET when the distance Lsd between the polarization superjunction length Lpsj, the source contact electrode S1c and the drain contact electrode D1c in the FET is not changed. It is a graph which shows the relationship between the polarization superjunction length Lpsj in FET, and the withstand voltage of FET. 6 is a graph showing the relationship between the distance between the drain electrode contact region DC1 and the polarized superjunction surface in the FET and the pressure resistance. It is a graph which shows the relationship between the polarization superjunction length Lpsj in FET, and the withstand voltage of a semiconductor element. It is a graph which shows the relationship between the drain voltage of FET and the drain current. It is a graph which shows the relationship between the gate voltage and the drain current when the drain voltage of FET is 0.1V. It is a graph which shows the relationship between the drain voltage and the drain current when the FET is off. It is a graph which shows the relationship between the drain voltage and the gate current when the FET is off. It is a graph which shows the reverse recovery time characteristic of a Schottky barrier diode with a polarization superjunction length Lpsj of 20 μm. It is a graph which shows the forward characteristic of a Schottky barrier diode. It is a graph which shows the reverse characteristic of a Schottky barrier diode. It is a table which shows the pressure resistance of the Schottky barrier diode when the distance Lac between the polarization superjunction length Lpsj, the anode electrode contact region AC1 and the cathode electrode contact region CC1 is changed.

Hereinafter, a specific embodiment will be described by taking a semiconductor element, a manufacturing method thereof, and an apparatus as an example. However, the techniques herein are not limited to these embodiments. In the present specification, the undoped semiconductor layer is a semiconductor layer that is not intentionally doped with impurities. The thickness ratio of each layer in the drawings does not necessarily reflect the actual thickness ratio.

(First Embodiment)
1. 1. Structure of semiconductor element 1-1. Region of Semiconductor Device FIG. 1 is a top view of the semiconductor device 100 of the first embodiment. The semiconductor element 100 is a field effect transistor (FET). As shown in FIG. 1, the semiconductor element 100 has an element functional region FR1, a source electrode exposed region SR1, a drain electrode exposed region DR1, and gate electrode exposed regions GR1 and GR2.

The element functional area FR1 is an area that exerts a function as an element. The device functional region FR1 is a region in which a current actually flows through the semiconductor, as will be described later. The element functional region FR1 is covered with an insulator such as polyimide. Therefore, the semiconductor or metal is not exposed in the element functional region FR1.

The source electrode exposed area SR1 is an area where the source electrode is exposed. The source electrode exposed region SR1 is an region where the pad electrode for electrically connecting to the external electrode is exposed. The source electrode exposed region SR1 has an end portion SR1a, an end portion SR1b, and a central portion SR1c. The end portion SR1a and the end portion SR1b extend in a direction away from the central portion SR1c on the side of the element functional region FR1. The source electrode exposed region SR1 expands as it approaches the element functional region FR1 and the drain electrode exposed region DR1.

The drain electrode exposed area DR1 is an area where the drain electrode is exposed. The drain electrode exposed region DR1 is an region where the pad electrode for electrically connecting to the external electrode is exposed.

The gate electrode exposed areas GR1 and GR2 are areas where the gate electrodes are exposed. The gate electrode exposed regions GR1 and GR2 are regions where the pad electrodes for electrically connecting to the external electrodes are exposed.

The source electrode exposed region SR1, the drain electrode exposed region DR1, and the gate electrode exposed regions GR1 and GR2 are formed on the semiconductor via an insulating layer. Therefore, in the source electrode exposed region SR1, the drain electrode exposed region DR1, and the gate electrode exposed regions GR1 and GR2, the source electrode, the drain electrode, and the gate electrode are not in contact with the semiconductor.

The source electrode exposed region SR1 is arranged so as to face the drain electrode exposed region DR1 with the element functional region FR1 sandwiched between them. The combined region of the source electrode exposed region SR1 and the gate electrode exposed regions GR1 and GR2 is arranged in a band shape. The drain electrode exposed region DR1 is arranged in a band shape.

The gate electrode exposed areas GR1 and GR2 are formed on the side of the source electrode exposed area SR1. The gate electrode exposed regions GR1 and GR2 are arranged so as to face the drain electrode exposed region DR1 with the element functional region FR1 sandwiched between them. A source electrode exposed region SR1 is arranged between the gate electrode exposed region GR1 and the gate electrode exposed region GR2. The gate electrode exposed region GR1 faces the end portion SR1a and the central portion SR1c of the source electrode exposed region SR1. The gate electrode exposed region GR2 faces the end portion SR1b and the center portion SR1c of the source electrode exposed region SR1.

The end SR1a of the source electrode exposed region SR1 is located between the gate electrode exposed region GR1 and the element functional region FR1. The end SR1b of the source electrode exposed region SR1 is located between the gate electrode exposed region GR2 and the element functional region FR1. At the position facing the element functional region FR1, the width of the source electrode exposed region SR1 and the width of the drain electrode exposed region DR1 are substantially equal to each other.

1-2. Element functional area 1-2-1. Cross-sectional structure FIG. 2 is a diagram showing a laminated structure of the semiconductor element 100 of the first embodiment. FIG. 2 is a diagram showing a cross section of II-II of FIG. As shown in FIG. 2, the semiconductor element 100 includes a sapphire substrate Sub1, a buffer layer Bf1, a first semiconductor layer 110, a second semiconductor layer 120, a third semiconductor layer 130, and a fourth semiconductor layer 140. It has a source electrode S1, a drain electrode D1, a gate electrode G1, and a polyimide layer PI1.

The sapphire substrate Sub1 is a support substrate that supports the semiconductor layer. The sapphire substrate Sub1 may be, for example, a growth substrate in which the semiconductor layer is grown from the + c plane. The thickness of the sapphire substrate Sub1 is, for example, 50 μm or more and 500 μm or less.

The buffer layer Bf1 is formed on the sapphire substrate Sub1. The buffer layer Bf1 is, for example, a low temperature GaN buffer layer. The buffer layer Bf1 may be, for example, a low temperature AlN buffer layer. The film thickness of the buffer layer Bf1 is, for example, 20 nm or more and 50 nm or less.

The first semiconductor layer 110 is formed above the buffer layer Bf1. The first semiconductor layer 110 is, for example, a GaN layer. The first semiconductor layer 110 is not intentionally doped with impurities. The film thickness of the first semiconductor layer 110 is, for example, 300 nm or more and 5000 nm or less.

The second semiconductor layer 120 is formed above the first semiconductor layer 110. The second semiconductor layer 120 is in direct contact with the first semiconductor layer 110. The second semiconductor layer 120 is, for example, an AlGaN layer. The Al composition of the second semiconductor layer 120 is, for example, 0.1 or more and 0.5 or less. The bandgap of the second semiconductor layer 120 is larger than the bandgap of the first semiconductor layer 110 and the third semiconductor layer 130. The second semiconductor layer 120 is not intentionally doped with impurities. The film thickness of the second semiconductor layer 120 is, for example, 20 nm or more and 150 nm or less.

The third semiconductor layer 130 is formed above the second semiconductor layer 120. The third semiconductor layer 130 is in direct contact with the second semiconductor layer 120. The third semiconductor layer 130 is, for example, a GaN layer. The third semiconductor layer 130 is not intentionally doped with impurities. The third semiconductor layer 130 is partitioned by being sandwiched between the recess X1 and the recess X2. Further, the third semiconductor layer 130 surrounds the periphery of the recess X1 which is the formation region of the source electrode S1. The film thickness of the third semiconductor layer 130 is, for example, 20 nm or more and 150 nm or less.

The fourth semiconductor layer 140 is formed above the third semiconductor layer 130. The fourth semiconductor layer 140 is in direct contact with the third semiconductor layer 130. The fourth semiconductor layer 140 is, for example, a p-type GaN layer. The fourth semiconductor layer 140 is doped with p-type impurities. The p-type impurity is, for example, Mg. The impurity concentration of the fourth semiconductor layer 140 is, for example, 1 × 10 ¹⁷ cm ^-3 or more and 3 × 10 ²⁰ cm ^-3 or less. The closer to the gate electrode G1, the higher the impurity concentration of the fourth semiconductor layer 140. The film thickness of the fourth semiconductor layer 140 is, for example, 20 nm or more and 150 nm or less.

The source electrode S1 is formed on the second semiconductor layer 120. The source electrode S1 is in direct contact with the second semiconductor layer 120. A recess X1 is formed at the location where the source electrode S1 is formed. The recess X1 reaches from the fourth semiconductor layer 140 to the middle of the second semiconductor layer 120. The second semiconductor layer 120 is exposed at the bottom of the recess X1. The source electrode S1 is formed on the recess X1.

The drain electrode D1 is formed on the second semiconductor layer 120. The drain electrode D1 is in direct contact with the second semiconductor layer 120. A recess X2 is formed at the location where the drain electrode D1 is formed. The recess X2 reaches from the fourth semiconductor layer 140 to the middle of the second semiconductor layer 120. The second semiconductor layer 120 is exposed at the bottom of the recess X2. The drain electrode D1 is formed on the recess X2.

The gate electrode G1 is formed on the fourth semiconductor layer 140. The gate electrode G1 is in direct contact with the fourth semiconductor layer 140.

The polyimide layer PI1 covers the surface of the semiconductor layer. Further, the polyimide layer PI1 covers each electrode of the element functional region FR1.

As described above, the first semiconductor layer 110, the second semiconductor layer 120, the third semiconductor layer 130, and the fourth semiconductor layer 140 are group III nitride semiconductor layers. The first semiconductor layer 110, the second semiconductor layer 120, and the third semiconductor layer 130 are undoped semiconductor layers. The fourth semiconductor layer 140 is a p-type semiconductor layer.

The third semiconductor layer 130 has a recess X3 and a region in contact with the fourth semiconductor layer 140. The recess X3 reaches from the fourth semiconductor layer 140 to the middle of the third semiconductor layer 130. The film thickness of the third semiconductor layer 130 in the recess X3 is thinner than the film thickness of the third semiconductor layer 130 in contact with the fourth semiconductor layer 140.

The recess X1 and the recess X2 are not connected. As will be described later, the recess X1 has a rod-like shape, and the recess X2 has a comb-teeth shape. A third semiconductor layer 130 is arranged between the recess X1 and the recess X2.

1-2-2. Planar structure FIG. 3 is a diagram showing a contact region of an electrode of the element functional region FR1 of the semiconductor element 100 of the first embodiment. FIG. 3 shows a region when the contact region of the electrode in the element functional region FR1 is projected onto the second semiconductor layer 120. The semiconductor element 100 has a source electrode contact region SC1, a drain electrode contact region DC1, and a gate electrode contact region GC1.

The source electrode contact region SC1 is a region in which the source electrode S1 and the second semiconductor layer 120 are in contact with each other. The drain electrode contact region DC1 is a region in which the drain electrode D1 and the second semiconductor layer 120 are in contact with each other. The gate electrode contact region GC1 is a region in which the gate electrode G1 and the fourth semiconductor layer 140 are in contact with each other.

The source electrode contact area SC1 is, for example, the first electrode contact area. The drain electrode contact region DC1 is, for example, a second electrode contact region. The gate electrode contact region GC1 is, for example, a third electrode contact region.

The source electrode contact region SC1, the drain electrode contact region DC1, and the gate electrode contact region GC1 do not overlap each other when projected onto any of the sapphire substrate Sub1, the first semiconductor layer 110, and the second semiconductor layer 120. ..

The source electrode contact region SC1 has a rod-like shape. The gate electrode contact region GC1 surrounds the source electrode contact region SC1 in a non-contact manner. Strictly speaking, the gate electrode contact region GC1 is on the fourth semiconductor layer 140, and the source electrode contact region SC1 is on the second semiconductor layer 120.

The region in which the gate electrode contact region GC1 in which the gate electrode G1 and the fourth semiconductor layer 140 are in contact is projected onto the second semiconductor layer 120 is around the source electrode contact region SC1 in which the source electrode S1 and the second semiconductor layer 120 are in contact. Is surrounded by non-contact. When the gate electrode contact region GC1 and the source electrode contact region SC1 are projected onto the sapphire substrate Sub1 or the first semiconductor layer 110, the gate electrode contact region GC1 surrounds the source electrode contact region SC1 in a non-contact manner.

The drain electrode contact region DC1 has a comb tooth shape. The source electrode contact region SC1 and the gate electrode contact region GC1 are arranged so as to be sandwiched between the comb teeth of the drain electrode contact region DC1. That is, the rod shape of the source electrode contact region SC1 is arranged between the comb tooth shapes of the drain electrode contact region DC1.

The shape of the contact surface where the first semiconductor layer 110 and the second semiconductor layer 120 come into contact is rectangular. The longitudinal direction of the region in which the rod-shaped shape of the source electrode contact region SC1 is projected onto the contact surface is arranged in the direction parallel to the short side of the rectangle. As shown in FIGS. 2 and 3, in the cross section of the source electrode contact region SC1 perpendicular to the longitudinal direction, the source electrode contact region SC1 and the drain electrode contact region DC1 are alternately arranged.

As shown in FIG. 3, the source contact electrode S1c has an arc-shaped portion S1c1 at the tip portion and a rod-shaped portion S1c2 other than the tip portion. The rod-shaped portion S1c2 of the source contact electrode S1c is sandwiched between the arc-shaped portion S1c1 and the arc-shaped portion S1c1.

The drain contact electrode D1c has an arc-shaped portion D1c1 at the tip portion and a rod-shaped portion D1c2 other than the tip portion. The rod-shaped portion D1c2 of the drain contact electrode D1c is not sandwiched between the arc-shaped portion D1c1 and the arc-shaped portion D1c1.

The gate contact electrode G1c has an arc-shaped portion G1c1 at the tip portion and a band-shaped portion G1c2 other than the tip portion. The arc-shaped portion G1c1 of the gate contact electrode G1c is located between the strip-shaped portion G1c2 and the strip-shaped portion G1c2. The arc-shaped portion G1c1 and the strip-shaped portion G1c2 of the gate contact electrode G1c have an annular shape.

As shown in FIG. 1, the number of rod-shaped portions of the source electrode contact region SC1 is one more than the number of comb-shaped rod-shaped portions of the drain electrode contact region DC1. As described above, the electrode contact region located on the outermost side of the semiconductor element 100 is not the drain electrode contact region DC1 but the source electrode contact region SC1.

FIG. 4 is an enlarged view of the periphery of the source contact electrode S1c and the drain contact electrode D1c of the semiconductor element 100 of the first embodiment.

1-2-3. Polarized superjunction region As shown in FIG. 2, the semiconductor device 100 has a polarized superjunction region PSJ1. The polarization superjunction region PSJ1 is a region having a first semiconductor layer 110, a second semiconductor layer 120, and a third semiconductor layer 130, and does not have a fourth semiconductor layer 140. That is, the polarization superjunction region PSJ1 is a region in which the third semiconductor layer 130 is formed and the fourth semiconductor layer 140 is not formed, and is located between the gate electrode contact region GC1 and the drain electrode contact region DC1. Area to do.

As described above, the polarized superjunction region PSJ1 does not have a p-type semiconductor layer. The polarized superjunction region PSJ1 is located in a region sandwiched between the gate electrode contact region GC1 and the drain electrode contact region DC1. The polarization superjunction length Lpsj is the length of the polarization superjunction region PSJ1 in the direction connecting the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1.

1-3. Source electrode exposed region FIG. 5 is a diagram (No. 1) showing a cross-sectional structure around the source electrode exposed region SR1 of the semiconductor element 100 of the first embodiment. FIG. 5 is a diagram showing a VV cross section of FIG. As shown in FIG. 5, the insulating layer IL1 is formed on the first semiconductor layer 110. Then, the source electrode S1 is formed on the insulating layer IL1. Further, a polyimide layer PI1 is formed between the gate wiring electrode G1w of the gate electrode G1 and the source wiring electrode S1w of the source electrode S1. The polyimide layer PI1 insulates the gate electrode G1 and the source electrode S1. In the source electrode exposed region SR1, the source electrode S1 and the semiconductor are not electrically connected.

A groove U1 is formed in the first semiconductor layer 110 along at least a part of the source electrode exposed region SR1. Since the groove U1 is provided, the distance between the first semiconductor layer 110 and the source electrode S1 can be increased. That is, the insulating property between the first semiconductor layer 110 and the source electrode S1 is enhanced.

The source electrode S1 has a source contact electrode S1c, a source wiring electrode S1w, and a source pad electrode S1p. The source contact electrode S1c is in direct contact with the second semiconductor layer 120. The source wiring electrode S1w connects the source contact electrode S1c and the source pad electrode S1p. The source pad electrode S1p is an electrode for electrically connecting to an external power source.

1-4. Drain electrode exposed region FIG. 6 is a diagram showing a cross-sectional structure around a drain electrode exposed region DR1 of the semiconductor element 100 of the first embodiment. FIG. 6 is a diagram showing a VI-VI cross section of FIG. As shown in FIG. 6, the insulating layer IL1 is formed on the first semiconductor layer 110. Then, the drain electrode D1 is formed on the insulating layer IL1. Further, the polyimide layer PI1 fills a gap between the drain electrode D1 and the insulating layer IL1. In the drain electrode exposed region DR1, the drain electrode D1 and the semiconductor are not electrically connected.

A groove U2 is formed in the first semiconductor layer 110 along at least a part of the drain electrode exposed region DR1. Since the groove U2 is provided, the distance between the first semiconductor layer 110 and the drain electrode D1 can be increased. That is, the insulating property between the first semiconductor layer 110 and the drain electrode D1 is enhanced.

The drain electrode D1 has a drain contact electrode D1c, a drain wiring electrode D1w, and a drain pad electrode D1p. The drain contact electrode D1c is in direct contact with the second semiconductor layer 120. The drain wiring electrode D1w connects the drain contact electrode D1c and the drain pad electrode D1p. The drain pad electrode D1p is an electrode for electrically connecting to an external power source.

1-5. Gate electrode exposed region FIG. 7 is a diagram showing a cross-sectional structure around a gate electrode exposed region GR1 of the semiconductor element 100 of the first embodiment. FIG. 7 is a diagram showing a cross section of VII-VII of FIG. As shown in FIG. 7, the insulating layer IL1 is formed on the first semiconductor layer 110. Then, the gate electrode G1 is formed on the insulating layer IL1. In the gate electrode exposed region GR1, the gate electrode G1 and the semiconductor are not electrically connected.

The gate electrode G1 has a gate contact electrode G1c, a gate wiring electrode G1w, and a gate pad electrode G1p. The gate contact electrode G1c is in direct contact with the fourth semiconductor layer 140. The gate wiring electrode G1w connects the gate contact electrode G1c and the gate pad electrode G1p. The gate pad electrode G1p is an electrode for electrically connecting to an external power source.

1-6. Insulating film forming region FIG. 8 is a diagram (No. 2) showing a cross-sectional structure around a source electrode exposed region SR1 of the semiconductor element 100 of the first embodiment. FIG. 8 is a diagram showing a cross section of VIII-VIII of FIG. As shown in FIG. 8, the drain contact electrode D1c of the drain electrode D1 extends toward the source pad electrode S1p. On the extension of the drain contact electrode D1c of the drain electrode D1 extending toward the source pad electrode S1p, the insulating layer IL1 is not in contact with the first semiconductor layer 110 and the second semiconductor layer 120. However, the insulating layer IL1 is formed on the first semiconductor layer 110, and is in contact with the first semiconductor layer 110 at the bottom of the groove U1.

FIG. 9 is a diagram showing the positional relationship between the source electrode contact region SC1 and the drain electrode contact region DC1 of the semiconductor element 100 of the first embodiment and the insulating layer IL1. FIG. 9 is a plan view of the insulating layer IL1, the source electrode contact region SC1 and the drain electrode contact region DC1 extracted.

As shown in FIG. 9, the insulating layer IL1 has a projecting portion IL1a protruding toward the source electrode contact region SC1 and the gate electrode contact region GC1. As shown in FIG. 5, the protruding portion IL1a is located between the gate wiring electrode G1w and the first semiconductor layer 110, and is arranged at a position on the extension of the source electrode contact region SC1 in the longitudinal direction.

As shown in FIGS. 5 and 9, the insulating layer IL1 is in contact with the second semiconductor layer 120 at the position of the protruding portion IL1a. As shown in FIGS. 8 and 9, the insulating layer IL1 is not in contact with the second semiconductor layer 120 at positions other than the protrusion IL1a. As shown in FIG. 5, the protruding portion IL1a of the insulating layer IL1 is in contact with the second semiconductor layer 120, the third semiconductor layer 130, the fourth semiconductor layer 140, the gate contact electrode G1c, and the gate wiring electrode G1w.

1-7. Electrode Wiring Structure FIG. 10 is a diagram showing wiring of the gate electrode G1 of the semiconductor element 100 of the first embodiment. The gate electrode G1 of the gate electrode contact region GC1 is connected to the gate wiring electrode GW2. The gate wiring electrode GW2 is formed in a direction parallel to the longitudinal direction of the source electrode contact region SC1. The gate wiring electrode GW1 is electrically connected to a plurality of gate contact electrodes G1c via the gate wiring electrode GW2. The gate wiring electrode GW1 and the gate wiring electrode GW2 are a part of the gate wiring electrode G1w.

FIG. 11 is a diagram showing the wiring of the source electrode S1 of the semiconductor element 100 of the first embodiment. The source contact electrode S1c is connected to the source wiring electrode SW2. The source wiring electrode SW2 is formed in a direction parallel to the longitudinal direction of the source electrode contact region SC1. The source wiring electrode SW1 is electrically connected to a plurality of source contact electrodes S1c via the source wiring electrode SW2. The source wiring electrode SW1 and the source wiring electrode SW2 are a part of the source wiring electrode S1w.

As shown in FIG. 11, the region where the source wiring electrode S1w of the source electrode S1 is projected onto the second semiconductor layer 120 does not overlap with the region where the drain wiring electrode D1w of the drain electrode D1 is projected onto the second semiconductor layer 120.

As shown in FIGS. 10 and 11, the region where the source wiring electrode SW2 is projected onto the second semiconductor layer 120 overlaps with the region where the gate wiring electrode GW2 is projected onto the second semiconductor layer 120.

The region where the source wiring electrode S1w of the source electrode S1 is projected onto the second semiconductor layer 120 partially overlaps with the region where the gate wiring electrode G1w of the gate electrode G1 is projected onto the second semiconductor layer 120. The region where the drain wiring electrode D1w of the drain electrode D1 is projected onto the second semiconductor layer 120 does not overlap with the region where the gate wiring electrode G1w of the gate electrode G1 is projected onto the second semiconductor layer 120.

1-8. Laminated structure of electrodes 1-8-1. Source electrode and drain electrode The source electrode S1 and the drain electrode D1 are formed on the second semiconductor layer 120 as described above. When the second semiconductor layer 120 is an AlGaN layer, the source electrode S1 and the drain electrode D1 come into contact with the AlGaN layer.

FIG. 12 is a diagram showing a laminated structure of the source electrode S1 and the drain electrode D1 of the semiconductor element 100 of the first embodiment. The source electrode S1 is a first metal layer S1a1, a second metal layer S1a2, a third metal layer S1a3, a fourth metal layer S1a4, a fifth metal layer S1a5, and a sixth metal formed in this order from the side of the second semiconductor layer 120. It has a layer S1a6. There may be another metal layer between the third metal layer S1a3 and the fourth metal layer S1a4.

The first metal layer S1a1 is, for example, V. The second metal layer S1a2 is, for example, Al. The third metal layer S1a3 is, for example, Ti. The fourth metal layer S1a4 is, for example, Ti. The fifth metal layer S1a5 is, for example, Au. The sixth metal layer S1a6 is, for example, Au. The above is an example, and a metal or alloy other than the above may be used.

The film thickness of the first metal layer S1a1 is, for example, 5 nm or more and 60 nm or less. The film thickness of the second metal layer S1a2 is, for example, 20 nm or more and 400 nm or less. The film thickness of the third metal layer S1a3 is, for example, 5 nm or more and 60 nm or less. The film thickness of the fourth metal layer S1a4 is, for example, 5 nm or more and 60 nm or less. The film thickness of the fifth metal layer S1a5 is, for example, 50 nm or more and 400 nm or less. The film thickness of the sixth metal layer S1a6 is, for example, 1000 nm or more and 15000 nm or less. The above is an example, and numerical values other than the above may be used.

The metal layers from the first metal layer S1a1 to the fifth metal layer S1a5 correspond to, for example, the source contact electrode S1c. The sixth metal layer S1a6 corresponds to, for example, the source wiring electrode S1w.

The drain electrode D1 is a first metal layer D1a1, a second metal layer D1a2, a third metal layer D1a3, a fourth metal layer D1a4, a fifth metal layer D1a5, and a sixth metal formed in this order from the side of the second semiconductor layer 120. It has layer D1a6. The type and film thickness of the metal in these metal layers are the same as those of the source electrode S1. Of course, the type and film thickness of the metal in these metal layers may be different from those of the source electrode S1.

1-8-2. Gate electrode FIG. 13 is a diagram showing a laminated structure of the gate electrode G1 of the semiconductor element 100 of the first embodiment. The gate electrode G1 has a first metal layer G1a1, a second metal layer G1a2, a third metal layer G1a3, and a fourth metal layer G1a4 formed in order from the side of the fourth semiconductor layer 140.

The first metal layer G1a1 is, for example, Ni. The second metal layer G1a2 is, for example, Au. The third metal layer G1a3 is, for example, Ni. The fourth metal layer G1a4 is, for example, Au. The above is an example, and a metal or alloy other than the above may be used.

The film thickness of the first metal layer G1a1 is, for example, 5 nm or more and 100 nm or less. The film thickness of the second metal layer G1a2 is, for example, 5 nm or more and 300 nm or less. The film thickness of the third metal layer G1a3 is, for example, 5 nm or more and 100 nm or less. The film thickness of the fourth metal layer G1a4 is, for example, 50 nm or more and 400 nm or less. The above is an example, and numerical values other than the above may be used.

The metal layers from the first metal layer G1a1 to the third metal layer G1a3 correspond to, for example, the gate contact electrode G1c. The fourth metal layer G1a4 corresponds to, for example, the gate wiring electrode G1w. Further, the metal layers from the first metal layer G1a1 to the fourth metal layer G1a4 may correspond to the gate contact electrode G1c, and the gate wiring electrode G1w may be present on the gate contact electrode G1c.

2. Operating Principle of Semiconductor Device 2-1.2 Dimensional Electron Gas and Two-Dimensional Hall Gas FIG. 14 is a diagram showing two-dimensional electron gas and two-dimensional Hall gas of the semiconductor device 100 of the first embodiment. FIG. 15 is a diagram showing a band structure of the semiconductor element 100 of the first embodiment.

As shown in FIG. 14, the first semiconductor layer 110 and the second semiconductor layer 120 are heterojunctioned. As a result, piezo polarization and spontaneous polarization occur, and a positive fixed charge is induced in the second semiconductor layer 120 on the first semiconductor layer 110 side. Further, the second semiconductor layer 120 and the third semiconductor layer 130 are heterojunctioned. As a result, piezo polarization and spontaneous polarization occur, and a negative fixed charge is induced in the second semiconductor layer 120 on the third semiconductor layer 130 side.

As a result, as shown in FIGS. 14 and 15, two-dimensional electron gas (2DEG) is generated inside the first semiconductor layer 110 on the second semiconductor layer 120 side, and the third semiconductor layer on the second semiconductor layer 120 side is generated. Two-dimensional hall gas (2DHG) is generated inside the 130.

Further, the p-type fourth semiconductor layer 140 is in contact with the third semiconductor layer 130. Therefore, the energy at the upper end of the valence band on the second semiconductor layer 120 side of the third semiconductor layer 130 is raised. Therefore, the generation of two-dimensional hall gas (2DHG) is promoted.

In this way, as shown in FIGS. 14 and 15, two-dimensional electron gas (2DEG) and two-dimensional Hall gas (2DHG) are generated at the hetero interface.

2-2. Threshold voltage When the gate voltage applied to the gate electrode G1 is equal to or higher than the threshold voltage Vth, piezo polarization and spontaneous polarization occur as described above. Then, two-dimensional electron gas (2DEG) and two-dimensional whole gas (2DHG) are generated. In this state, a current flows between the source electrode S1 and the drain electrode D1. The threshold voltage Vth is, for example, about −5 V.

When the gate voltage applied to the gate electrode G1 is less than the threshold voltage Vth, piezo polarization and spontaneous polarization do not occur. Therefore, almost no current flows between the source electrode S1 and the drain electrode D1. In reality, a minute leak current flows between the source electrode S1 and the drain electrode D1.

When the gate voltage is less than the threshold voltage Vth, holes are pulled out from the fourth semiconductor layer 140. Therefore, no positive charge is supplied from the gate electrode G1 to the third semiconductor layer 130, and the two-dimensional electron gas (2DEG) and the two-dimensional Hall gas (2DHG) disappear almost at the same time.

The drain current flows in the path of the drain electrode D1, the second semiconductor layer 120, the two-dimensional electron gas (2DEG) of the first semiconductor layer 110, the second semiconductor layer 120, and the source electrode S1. The two-dimensional hall gas (2DHG) is only generated together with the two-dimensional electron gas (2DEG) when the semiconductor element 100 is turned on and off, and is not directly used for passing an electric current through the semiconductor element 100.

3. 3. Electrical Characteristics of Semiconductor Element Here, the relationship between the structure of the semiconductor element 100 and the electrical characteristics of the semiconductor element 100 will be described.

FIG. 16 is a schematic diagram conceptually showing an electric field when a reverse bias is applied to the gate electrode G1 of the semiconductor element 100 of the first embodiment. The horizontal axis of FIG. 16 indicates the position of the semiconductor element 100. The vertical axis of FIG. 16 is an electric field. When the reverse bias is applied, the holes in the semiconductor element 100 are pulled out. Therefore, the two-dimensional electron gas (2DEG) and the two-dimensional Hall gas (2DHG) disappear. Then, the first semiconductor layer 110, the second semiconductor layer 120, and the third semiconductor layer 130 are depleted. As a result, the strength of the electric field becomes uniform over the width direction of the polarization superjunction region PSJ1 in FIG. Here, the area of the electric field shown in FIG. 16 corresponds to the voltage.

Even if a high voltage is applied between the source electrode S1 and the drain electrode D1 of the semiconductor element 100, the electric field can be widely distributed spatially as shown in FIG. 16 by applying a reverse bias to the gate electrode. can. That is, the semiconductor element 100 can suppress the formation of a locally strong electric field. Therefore, the withstand voltage of the semiconductor element 100 is high.

In the present specification, the withstand voltage of the FET refers to the value of the drain voltage Vd at which the drain current Id reaches 1 × 10 ^-4 A when the drain voltage Vd is applied in the off state where the gate voltage Vg is applied at −10 V. say. In the present embodiment, the rated current of the semiconductor element 100 at room temperature is about several A to several tens A. The above drain current Id is a value about 5 orders of magnitude lower than this rated current.

3-1. Polarized superjunction region With the polarized superjunction region PSJ1, the polarized superjunction region PSJ1 can be depleted. Even if a large reverse bias is applied to the gate electrode G1, a uniform electric field distribution is formed over the polarization superjunction region PSJ1. On the other hand, in the conventional FET, a strong electric field is often formed in the vicinity of the gate. Therefore, the electric field strength formed in the vicinity of the gate electrode G1 is sufficiently smaller than that of the conventional FET under the same conditions. As described above, in the semiconductor element 100, the electric field concentration near the gate is relaxed. Therefore, the longer the polarization superjunction length Lpsj, which is the length of the polarization superjunction region PSJ1, the higher the pressure resistance of the semiconductor element 100 tends to be.

On the other hand, when the polarization superjunction length Lpsj is short, the distance between the source electrode S1 and the drain electrode D1 is short. Therefore, the shorter the polarization superjunction length Lpsj, the lower the on-resistance of the semiconductor element 100 tends to be.

3-2. Gate length The gate length Lg is the length of the fourth semiconductor layer 140 in the direction connecting the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1. The shorter the gate length Lg, the shorter the response time tends to be. When the gate length Lg is short, the depletion layer region in the gate length Lg direction is short. Since the depletion layer region becomes narrow, the gate charge capacitance may be small. That is, when the semiconductor element 100 is made to perform the switching operation, the amount of electric charge supplied or discharged from the gate electrode G1 to the depletion layer region can be small. As a result, the switching speed of the semiconductor element 100 is improved.

3-3. Gate width The gate width is the length of the fourth semiconductor layer 140 in the direction orthogonal to the direction connecting the shortest distances from the source electrode contact region SC1 to the drain electrode contact region DC1. That is, the gate width is the length at which the gate electrode contact region GC1 surrounds the source electrode contact region SC1. Since the plurality of source electrode contact regions SC1 are arranged discretely, the gate width is actually the sum of the lengths of the plurality of gate electrode contact regions GC1 surrounding the plurality of source electrode contact regions SC1. ..

The longer the gate width, the larger the region in which the current flows through the semiconductor element 100. Therefore, the longer the gate width, the larger the current value when the drain voltage Vd is 2V. In the first embodiment, in order to increase the gate width, the source electrode contact region SC1 has a rod shape and the drain electrode contact region DC1 has a comb tooth shape.

Since the drain current flows between the source electrode S1 and the drain electrode D1, the idea of lengthening the source width or the drain width can be taken. The drain current is considered to be limited depending on the shorter of the source width and the drain width. The source width is the outer peripheral length of the source electrode contact region SC1. The drain width is the outer peripheral length of the drain electrode contact region DC1. However, the source width or the drain width may be obtained by subtracting the length of the region where the source electrode contact region SC1 and the drain electrode contact region DC1 do not face each other.

3-4. Protruding portion of the insulating layer As shown in FIG. 5, the second semiconductor layer 120 is in contact with the insulating layer IL1 around the protruding portion IL1a of the insulating layer IL1. As shown in FIG. 8, the second semiconductor layer 120 is in contact with the polyimide layer PI1 at a location other than the periphery of the protruding portion IL1a of the insulating layer IL1. The polyimide layer PI1 is suitable for forming a film thicker than the insulating layer IL1. Therefore, the polyimide layer PI1 insulates more regions around the semiconductor layer.

As shown in FIG. 5, in the region directly below the gate wiring electrode G1w, the insulating layer IL1 insulates the semiconductor layer and the surrounding material. As shown in FIG. 8, in the region other than directly under the gate wiring electrode G1w, the polyimide layer PI1 insulates the semiconductor layer and the surrounding material.

Here, it is assumed that the insulating layer IL1 insulates the semiconductor layer and the surrounding materials in a region other than directly under the gate wiring electrode G1w. A high potential is applied to the drain electrode contact region DC1. Therefore, a leak current may be generated from the drain electrode contact region DC1 to the source electrode contact region SC1 or the gate electrode contact region GC1 via the surface of the insulating layer IL1. In the present embodiment, in the region other than directly under the gate wiring electrode G1w, the polyimide layer PI1 insulates the semiconductor layer and the surrounding material, so that the leakage current through the surface of the insulating layer IL1 is suppressed.

As shown in FIG. 5, at the protruding portion IL1a, the first semiconductor layer 110, the second semiconductor layer 120, the third semiconductor layer 130, the fourth semiconductor layer 140, the insulating layer IL1, and the gate wiring are formed from the side of the sapphire substrate Sub. The electrodes G1w are stacked in this order. If the insulating layer IL1 is an oxide, this laminated structure has a MOS structure. The gate voltage for depleting the polarized superjunction region PSJ1 is different between the protruding portion IL1a and the portion where the gate contact electrode G1c and the fourth semiconductor layer 140 are in direct contact with each other.

In the semiconductor element 100 of the first embodiment, the contact point between the second semiconductor layer 120 and the insulating layer IL1 is limited to the periphery of the protruding portion IL1a. Further, a region in which the gate electrode contact region GC1 is projected onto the second semiconductor layer 120 surrounds the source electrode contact region SC1. Therefore, the leakage current is suppressed.

4. Manufacturing method of semiconductor device 4-1. Semiconductor layer forming process As shown in FIG. 17, the buffer layer Bf1, the first semiconductor layer 110, the second semiconductor layer 120, the third semiconductor layer 130, and the fourth semiconductor layer 140 are grown on the sapphire substrate Sub1 in this order. Let me. Therefore, for example, the MOCVD method may be used. Alternatively, other vapor phase growth method, liquid phase growth method, or the like may be used.

4-2. Recessed portion forming step As shown in FIG. 18, recesses X1, X2, and X3 are formed. Therefore, dry etching such as ICP may be used. The etching gas is, for example, a chlorine-based gas such as _{Cl 2} , BCl ₃ , and SICF _4. A photoresist or the like may be used during dry etching. The recess X1 is a region forming the source electrode S1. The recess X2 is a region forming the drain electrode D1. The recess X3 is a region that becomes the polarization superjunction region PSJ1.

The second semiconductor layer 120 is exposed at the bottom of the recess X1 and the recess X2. The third semiconductor layer 130 is exposed at the bottom of the recess X3. Therefore, first, after exposing up to the third semiconductor layer 130, only the regions forming the recesses X1 and X2 may be re-etched to expose the second semiconductor layer 120. Alternatively, two separate steps may be performed. Here, the depths of the recesses X1 and X2 are about the same, but the recesses X1 and X2 are not connected. The recess X1 has a rod-like shape, and the recess X2 has a comb-teeth shape.

Further, in the region outside the element functional region FR1, the groove U1 and the groove U2 are formed to expose the first semiconductor layer 110. As a result, no current path is formed in a region other than the region where the source electrode contact region SC1, the drain electrode contact region DC1, the gate electrode contact region GC1, and the polarization superjunction region PSJ1 exist. That is, the active region of the semiconductor element 100 is limited.

4-3. Insulation layer forming step The insulation layer IL1 is formed on the grooves U1 and U2 of the first semiconductor layer 110. Therefore, for example, the CVD method may be used.

4-4. Electrode forming step As shown in FIG. 19, the source electrode S1, the drain electrode D1 and the gate electrode G1 are formed. Since the source electrode S1 and the drain electrode D1 have the same laminated structure of the electrodes, they may be carried out in the same step. Since the laminated structure of the gate electrode G1 is different from that of the source electrode S1 and the drain electrode D1, it is carried out in a separate step. For the formation of these electrodes, a film forming technique such as sputtering, ALD method, or EB vapor deposition method may be used. By this step, the insulating layer IL1 is arranged between the source electrode S1, the drain electrode D1, the gate electrode G1, and the first semiconductor layer 110.

4-5. Protective layer forming step Next, the surface of the exposed semiconductor layer is covered with polyimide. Polyamic acid, which is a precursor of polyimide, is applied to the exposed portion of the semiconductor. Then, the wafer is heated at 250 ° C. or higher and 500 ° C. or lower to form the polyimide layer PI1.

4-6. Element separation step Then, the semiconductor element 100 is cut out from the wafer, and each independent semiconductor element 100 is manufactured.

4-7. Other Steps Other steps such as a step of forming a wiring electrode or a pad electrode, a heat treatment step, and the like may be appropriately performed. From the above, the semiconductor element 100 is obtained.

5. Effect of the first embodiment 5-1. Source electrode contact area and drain electrode contact area The source electrode contact area SC1 has a rod-like shape. The drain electrode contact region DC1 has a comb tooth shape. The rod-shaped shape of the source electrode contact region SC1 is arranged between the comb teeth of the drain electrode contact region DC1. The path formed by the outer peripheral portion of the source electrode contact region SC1 and the outer peripheral portion of the drain electrode contact region DC1 is long. The current flows through the semiconductor layer in the region sandwiched between the source electrode contact region SC1 and the drain electrode contact region DC1. Therefore, the semiconductor element 100 can carry a large current.

5-2. Gate electrode contact region In the semiconductor element 100, the region in which the gate electrode contact region GC1 in which the gate electrode G1 and the fourth semiconductor layer 140 are in contact is projected onto the second semiconductor layer 120 is the source electrode S1 and the second semiconductor layer 120. The source electrode contact region SC1 in contact with the second semiconductor layer 120 is surrounded by the region projected onto the second semiconductor layer 120 in a non-contact manner. Therefore, the gate electrode contact region GC1 always exists between the drain electrode contact region DC1 in which the drain electrode D1 and the second semiconductor layer 120 are in contact with each other and the source electrode contact region SC1. Therefore, the semiconductor element 100 can suppress the leakage current when it is off.

5-3. Polarized superjunction region The semiconductor device 100 has a polarized superjunction region PSJ1. The presence of the polarized superjunction region PSJ1 makes it possible to widen the depletion region. Therefore, the semiconductor element 100 has high withstand voltage.

5-4. Gate length The semiconductor element 100 has a relatively long gate length Lg. Since the gate length Lg is relatively long, the depletion region can be widened.

6. Modification 6-1. Device The technology of the first embodiment can be applied to a device having a semiconductor element 100. Examples of such a device include a package, a module, a transmitter, a communication device, a power transmission device, and the like.

6-2. Semiconductor layer In the first embodiment, the second semiconductor layer 120 is AlGaN. The second semiconductor layer 120 may be Al _X In _Y Ga _(1-XY) N (X> 0). The first semiconductor layer 110 and the third semiconductor layer 130 may be Al _X In _Y Ga _(1-XY) N (X ≧ 0). However, the bandgap of the first semiconductor layer 110 and the third semiconductor layer 130 is smaller than the bandgap of the second semiconductor layer 120. Further, the compositions of the first semiconductor layer 110 and the third semiconductor layer 130 do not have to be the same.

6-3. Source Electrode Contact Region and Drain Electrode Contact Region In the first embodiment, the source electrode contact region SC1 has a rod shape and the drain electrode contact region DC1 has a comb tooth shape. Instead, the source electrode contact region SC1 may have a comb tooth shape and the drain electrode contact region DC1 may have a rod shape.

Therefore, one of the source electrode contact region SC1 and the drain electrode contact region DC1 has a rod-like shape. The other side of the source electrode contact region SC1 and the drain electrode contact region DC1 has a comb tooth shape. One rod-shaped shape of the source electrode contact region SC1 and the drain electrode contact region DC1 is arranged between the other comb tooth shape of the source electrode contact region SC1 and the drain electrode contact region DC1.

6-4. Shape of Electrode Contact Region The rod-shaped tip of the source electrode contact region SC1 has an arc shape. However, the tip portion is not limited to the arc. The rod-shaped tip portion is an arc-shaped arc-shaped portion. The portion other than the rod-shaped tip portion is a linear rod-shaped portion.

6-5. Source contact electrode and drain contact electrode The source contact electrode S1c and drain contact electrode D1c are in direct contact with the second semiconductor layer 120. This is because the recesses X1 and X2 reach the middle of the second semiconductor layer 120. However, if the bottoms of the recesses X1 and X2 are sufficiently close to the second semiconductor layer 120, the source contact electrode S1c and the drain contact electrode D1c do not need to be in direct contact with the second semiconductor layer 120. In this case, the recesses X1 and X2 reach the middle of the third semiconductor layer 130. The source contact electrode S1c and the drain contact electrode D1c are in contact with the very thin third semiconductor layer 130. The thickness of the very thin portion of the third semiconductor layer 130 is, for example, 10 nm or less. At this time, the third semiconductor layer 130 is thin at the recesses X1 and X2, and thicker at the recesses X1 and X2 except at the recesses X1 and X2. Even in this case, the semiconductor element can pass a sufficiently large current between the source and drain.

Therefore, the source electrode S1 and the drain electrode D1 are formed on the second semiconductor layer 120 or the third semiconductor layer 130. The source electrode contact region SC1 is a region in which the source electrode S1 and the second semiconductor layer 120 or the third semiconductor layer 130 come into contact with each other. The drain electrode contact region DC1 is a region in which the drain electrode D1 and the second semiconductor layer 120 or the third semiconductor layer 130 come into contact with each other.

6-6. Gate electrode contact area The gate electrode contact area GC1 may surround the drain electrode contact area DC1. Even in this case, the leakage current at the time of off is suppressed. In this case, the region in which the gate electrode contact region GC1 is projected onto the second semiconductor layer 120 surrounds the region in which the source electrode contact region SC1 or the drain electrode contact region DC1 is projected onto the second semiconductor layer 120.

6-7. The positional relationship between the wiring electrode source electrode S1 and the drain electrode D1 may be exchanged. In this case, one of the two regions, the region in which the source wiring electrode S1w is projected onto the second semiconductor layer 120 and the region in which the drain wiring electrode D1w is projected on the second semiconductor layer 120, has the gate wiring electrode G1w. There are two regions that partially overlap the region projected on the second semiconductor layer 120, the region where the source wiring electrode S1w is projected on the second semiconductor layer 120 and the region where the drain wiring electrode D1w is projected on the second semiconductor layer 120. The other of them does not overlap with the region where the gate wiring electrode G1w is projected onto the second semiconductor layer 120.

Further, one of two regions, a region in which the source wiring electrode S1w is projected on the second semiconductor layer 120 and a region in which the drain wiring electrode D1w is projected on the second semiconductor layer 120, and the gate wiring electrode G1w are used in the second semiconductor. The distance between the source wiring electrode S1w or the drain wiring electrode D1w and the first semiconductor layer 110 is set between the gate wiring electrode G1w and the first semiconductor layer 110 at a location where the region projected on the layer 120 partially overlaps. Greater than the distance between.

6-8. Protective film The protective film that protects the semiconductor layer may be an insulating layer other than polyimide. The insulating layer may have at least one of an inorganic dielectric film and an organic dielectric film. For example, the insulating _{layer, SiO 2, Si X N Y} , SiON, Al 2 O 3, AlN, AlON, ZrO 2, ZrN, ZrON, Ta 2 O 3, TaN, TaON, HfO 2, HfN 2, HfON, TiO _2. Has one or more of TiN, TiON, and polyimide.

6-9. Combination The above modification examples may be freely combined.

(Second Embodiment)
A second embodiment will be described.

1. 1. Semiconductor element FIG. 20 is a top view of the semiconductor element 200 of the second embodiment. The source electrode contact region SC1 in which the source electrode S1 and the second semiconductor layer 120 are in contact has a rod shape. The drain electrode contact region DC1 in which the drain electrode D1 and the second semiconductor layer 120 are in contact has a comb tooth shape. The rod shape of the source electrode contact region SC1 is arranged between the comb tooth shapes of the drain electrode contact region DC1.

In the semiconductor element 200, the distance Lpsj2 is equal to or greater than the distance Lpsj1. The distance Lpsj1 is the polarization superjunction length in the rod-shaped portion other than the tip portion of the source electrode contact region SC1. The distance Lpsj2 is the polarization superjunction length at the tip of the source electrode contact region SC1.

As described above, the length of the polarization superjunction region PSJ2 in the direction connecting the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1 at the rod-shaped tip portion is the source electrode at the portion other than the rod-shaped tip portion. It is longer than the length of the polarization superjunction region PSJ1 in the direction connecting the shortest distance from the contact region SC1 to the drain electrode contact region DC1.

From the source electrode contact region SC1 at the rod-shaped tip to the length of the polarization superjunction PSJ1 in the direction connecting the shortest distance from the source electrode contact region SC1 to the drain electrode contact region DC1 in the portion other than the rod-shaped tip. The length of the polarization superjunction region PSJ2 in the direction connecting the shortest distance to the drain electrode contact region DC1 is preferably 1.05 or more and 3 or less.

In the semiconductor element 200, the distance Lsd2 is equal to or greater than the distance Lsd1. The distance Lsd1 is the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 in the rod-shaped portion other than the tip portion of the source electrode contact region SC1. The distance Lsd2 is the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 at the tip of the source electrode contact region SC1.

That is, the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 in the rod-shaped tip portion is between the source electrode contact region SC1 and the drain electrode contact region DC1 in the portion other than the rod-shaped tip portion. It is more than a distance.

The rod-shaped tip is an arc-shaped arc. The portion other than the rod-shaped tip portion is a linear rod-shaped portion.

2. Effect of the Second Embodiment The electric field tends to be stronger in the tip portion of the source electrode contact region SC1 of the source electrode S1 than in the rod-shaped portion other than the tip portion. In the semiconductor device 200 of the second embodiment, the length of the polarization superjunction length Lpsj2 of the polarization superjunction region PSJ is increased at the tip portion thereof. Further, for the same reason, the distance Lsd2 is increased. Therefore, the semiconductor element 200 has a higher withstand voltage.

3. 3. Modification 3-1. The source electrode contact region and the drain electrode contact region SC1 may have a comb-shaped shape, and the drain electrode contact region DC1 may have a rod-shaped shape. The comb tooth shape of the source electrode contact region SC1 has a rod shape. Even in that case, the distance between the source electrode contact region SC1 and the drain electrode contact region DC1 in the rod-shaped tip portion is the source electrode contact region SC1 and the drain electrode contact region in the portion other than the rod-shaped tip portion. It is greater than or equal to the distance to DC1.

3-2. Arc-shaped portion The arc-shaped portion has, for example, an arc shape. However, the arcuate portion may have an arcuate shape other than the arc.

3-3. Combination The above modification examples may be freely combined.

(Third Embodiment)
A third embodiment will be described.

1. 1. Semiconductor element FIG. 21 is a diagram showing a laminated structure of the semiconductor element 300 of the third embodiment. The source electrode S1 is formed on the recess X1. The drain electrode D1 is formed on the recess X2.

Here, the distance Ld between the drain electrode contact region DC1 and the third semiconductor layer 130 is larger than the distance Ls between the source electrode contact region SC1 and the third semiconductor layer 130. The distance Ld between the drain electrode contact region DC1 and the third semiconductor layer 130 is, for example, 1 μm or more and 10 μm or less.

Further, when the source electrode contact region SC1, the drain electrode contact region DC1 and the gate electrode contact region GC1 are projected onto the second semiconductor layer 120, the region where the drain electrode contact region DC1 is projected and the gate electrode contact region GC1 are projected. The distance Ldg between the regions is larger than the distance Lsg between the region where the source electrode contact region SC1 is projected and the region where the gate electrode contact region GC1 is projected.

2. Effect of the Third Embodiment When the semiconductor element 300 is operated, the potential difference (voltage) between the drain electrode D1 and the gate electrode G1 is sufficiently larger than the potential difference (voltage) between the source electrode S1 and the gate electrode G1. It can be big. Therefore, in the third embodiment, the distance Ldg between the drain electrode contact region DC1 and the gate electrode contact region GC1 is sufficiently larger than the distance Lsg between the source electrode contact region SC1 and the gate electrode contact region GC1. I'm taking it. Since a potential having a high absolute value is applied to the drain electrode D1, the electric field strength between the drain and the gate is stronger than the electric field strength between the source and the gate. Therefore, the distance Ldg is made sufficiently larger than the distance Lsg.

(Fourth Embodiment)
A fourth embodiment will be described.

1. 1. Semiconductor element FIG. 22 is a diagram showing the periphery of the gate pad electrode of the semiconductor element 400 of the fourth embodiment.

The source electrode S2 has a source contact electrode S2c, a source wiring electrode S2w, and a source pad electrode S2p. The source contact electrode S2c is in direct contact with the second semiconductor layer 120. The source wiring electrode S2w connects the source contact electrode S2c and the source pad electrode S2p. The source pad electrode S2p is an electrode for electrically connecting to an external power source.

The gate electrode G2 has a gate contact electrode G2c, a gate wiring electrode G2w, and a gate pad electrode G2p. The gate contact electrode G2c is in direct contact with the fourth semiconductor layer 140. The gate wiring electrode G2w connects the gate contact electrode G2c and the gate pad electrode G2p. The gate pad electrode G2p is an electrode for electrically connecting to an external power source.

The source wiring electrode S2w has a curved portion S2r that curves in an arc shape at a connection point with the source pad electrode S2p. The gate wiring electrode G2w has a curved portion G2r that is curved in an arc shape at a connection point with the gate pad electrode G2p.

2. Insulation layer FIG. 23 is a diagram showing a cross-sectional structure around a drain electrode exposed region of the semiconductor element 400 of the fourth embodiment. As shown in FIG. 23, the semiconductor element 400 has an insulating layer IL2, an insulating layer IL3, and an insulating layer IL4 in addition to the insulating layer IL1. The insulating layer IL2 is located above the insulating layer IL1. The insulating layer IL3 is located above the insulating layer IL2. The insulating layer IL4 is located above the insulating layer IL3.

The material of the insulating layer IL1 and the insulating layer IL2 is an inorganic dielectric film. The inorganic dielectric film is, for example, SiO ₂ . The material of the insulating layer IL3 and the insulating layer IL4 is an organic dielectric film. The organic dielectric film is, for example, polyimide. It is preferable to form an organic dielectric film on a hard film such as _{SiO 2.}

The insulating layer IL2 and the insulating layer IL3 fill the gap between the insulating layer IL1 and the second semiconductor layer 120. The insulating layer IL2 fills the sides and surface of the semiconductor layer. Further, the insulating layer IL2 fills the contact electrodes of the source electrode S1, the drain electrode D1, and the gate electrode G1. The insulating layer IL4 is the uppermost layer.

3. 3. Effect of Fourth Embodiment The semiconductor element 400 has high withstand voltage. Therefore, a high voltage may be applied to the semiconductor element 400 during use. Even when such a high voltage is applied, the formation of a strong electric field around the curved portion S2r and the curved portion G2r is suppressed. It is also considered that the internal stress in the insulating layer is relaxed.

4. Modification 4-1. Drain electrode Also in the drain electrode, the drain wiring electrode may have a curved portion that curves in an arc shape at a connecting portion with the drain pad electrode.

4-2. Number of Pad Electrodes FIG. 24 is a top view of the semiconductor element in the modified example of the fourth embodiment. As shown in FIG. 24, the gate pad electrode G2p is arranged so as to be sandwiched between the source pad electrode S2p and the source pad electrode S2p. Further, the semiconductor element may have a plurality of source pad electrodes S2p. That is, at least one of the gate electrode G2, the source electrode S2, and the drain electrode D2 may have a plurality of pad electrodes.

FIG. 25 is an enlarged view of the periphery of the gate pad electrode in the semiconductor element in the modified example of the fourth embodiment. As shown in FIG. 25, the curved shape S2i1 is also formed in the connecting portion S2i that connects the source pad electrode S2p and the source pad electrode S2p.

4-3. Shape of Pad Electrode At least one corner of the source pad electrode S2p, the gate pad electrode G2p, and the drain pad electrode may have a curved shape.

4-4. Insulation layer The insulation layer may have at least one of an inorganic dielectric film and an organic dielectric film. For example, the insulating _{layer, SiO 2, Si X N Y} , SiON, Al 2 O 3, AlN, AlON, ZrO 2, ZrN, ZrON, Ta 2 O 3, TaN, TaON, HfO 2, HfN 2, HfON, TiO _2. Has one or more of TiN, TiON, and polyimide.

4-5. Combination The above modification examples may be freely combined.

(Fifth Embodiment)
A fifth embodiment will be described.

1. 1. Semiconductor element The basic structure of the semiconductor element is the same as that of the first embodiment.

The dislocation density in the second semiconductor layer 120 is, for example, 1 × 10 ⁶ cm ⁻² or more and 1 × 10 ¹⁰ cm ⁻² or less. The dislocation density is preferably 5 × 10 ⁹ cm ^-2 or less. The dislocation density in the first semiconductor layer 110 is, for example, 1 × 10 ⁶ cm ⁻² or more and 1 × 10 ¹⁰ cm ⁻² or less. The dislocation density is preferably 5 × 10 ⁹ cm ^-2 or less.

Contact area between the second semiconductor layer 120 and the third semiconductor layer 130 is, per 1μm gate width direction is 10 [mu] m ² or more 200 [mu] m ² or less.

The gate length Lg is 0.1 μm or more and 6 μm or less. Further, the gate length Lg may be 0.3 μm or more and 5 μm or less. Further, the gate length Lg may be 1 μm or more and 4 μm or less.

The contact area and withstand voltage between the second semiconductor layer 120 and the third semiconductor layer 130 are calculated by the following equation (1).
101x-810 ≤ y ≤ 235x + 585 ……… (1)
x: Contact area between the second semiconductor layer and the third semiconductor layer per 1 μm in the gate width direction y: Satisfy the withstand voltage.

2. Electrical Characteristics of Semiconductor Device The rise time (tr) and fall time (tf) of the semiconductor device of the fifth embodiment at 300 V switching are both 3 ns or more and 30 ns or less.

The withstand voltage of the semiconductor element of the fifth embodiment is 1500 V or more and 20000 V or less. Further, the withstand voltage of the semiconductor element may be 3000 V or more and 10000 V or less.

3. 3. Dislocation Density In order to reduce the dislocation density of the semiconductor layer, a method of forming an AlN buffer layer by sputtering, a method of forming an uneven shape on a substrate, a method of forming a thick film of several tens of μm or more by VPE, etc. are used. It is good.

(Sixth Embodiment)
A sixth embodiment will be described.

1. 1. Semiconductor element The basic structure of the semiconductor element is the same as that of the first embodiment.

The polarization superjunction length Lpsj is 1 μm or more and 50 μm or less. The polarization superjunction length Lpsj may be 2 μm or more and 40 μm or less. The polarization superjunction length Lpsj may be 3 μm or more and 30 μm or less.

The gate length Lg is 0.1 μm or more and 6 μm or less. Further, the gate length Lg may be 0.3 μm or more and 5 μm or less. Further, the gate length Lg may be 1 μm or more and 4 μm or less.

2. Electrical Characteristics of Semiconductor Device The rise time (tr) and fall time (tf) of the semiconductor device of the sixth embodiment at 300 V switching are both 3 ns or more and 30 ns or less. The rise time (tr) and fall time (tf) may be 4 ns or more and 20 ns or less. The rise time (tr) and fall time (tf) may be 5 ns or more and 10 ns or less.

The normalized on-resistance of the semiconductor device of the sixth embodiment is 1 mΩ · cm ² or more and 20 mΩ · cm ² or less. The normalized on-resistance, it may be 2 M [Omega · cm ² or more 17mΩ · cm ² or less. The standardized on-resistance may be 3 mΩ · cm ² or more and 15 mΩ · cm ² or less.

(7th Embodiment)
A seventh embodiment will be described.

1. 1. Semiconductor element The basic structure of the semiconductor element is the same as that of the first embodiment.

The active area is 2.2 mm ² or more and 100 mm ² or less. Active region area, may be 2.5 mm ² or more 90 mm ² or less. The active area may be 3 mm ² or more and 80 mm ² or less.

The active region area is an area in which a current substantially flows through the first semiconductor layer 110. The active region area is the area of the source electrode contact region SC1 and the drain electrode contact region DC1 and the outermost source electrode contact region SC1 and the second semiconductor layer 120 from the area of the second semiconductor layer 120 on the third semiconductor layer 130 side. It is the area obtained by subtracting the area of the area sandwiched between the outer peripheral portion of the surface and the outer peripheral portion of the surface.

The gate length Lg is 0.1 μm or more and 6 μm or less. Further, the gate length Lg may be 0.3 μm or more and 5 μm or less. Further, the gate length Lg may be 1 μm or more and 4 μm or less.

The gate width is 300 mm or more and 12000 mm or less. The gate width may be 350 mm or more and 11000 mm or less. The gate width may be 400 mm or more and 10000 mm or less.

The outer peripheral length of the semiconductor element is 13 mm or more and 520 mm or less. The outer peripheral length of the semiconductor element may be 15 mm or more and 500 mm or less. The outer peripheral length of the semiconductor element may be 20 mm or more and 480 mm or less. The outer peripheral length is the sum of the lengths of the four sides of the sapphire substrate Sub1 of the semiconductor element.

2. Electrical Characteristics of Semiconductor Device The rise time (tr) and fall time (tf) of the semiconductor device of the seventh embodiment at 300 V switching are both 3 ns or more and 30 ns or less.

The current value when the drain voltage Vd in the semiconductor element of the seventh embodiment is 2V is 30A or more and 1200A or less. The current value when the drain voltage Vd is 2V is the current value in a region other than the current saturation region in the ON state.

(8th Embodiment)
1. 1. Schottky barrier diode FIG. 26 is a diagram showing a laminated structure of the semiconductor element 500 of the eighth embodiment. The semiconductor element 500 is a Schottky barrier diode. The semiconductor element 500 includes a sapphire substrate Sub2, a buffer layer Bf2, a first semiconductor layer 510, a second semiconductor layer 520, a third semiconductor layer 530, a fourth semiconductor layer 540, a cathode electrode C1, and an anode electrode. It has A1 and.

The buffer layer Bf2 is formed on the sapphire substrate Sub2. The first semiconductor layer 510 is formed on the buffer layer Bf2. The second semiconductor layer 520 is formed on the first semiconductor layer 510. The third semiconductor layer 530 is formed on the second semiconductor layer 520. The fourth semiconductor layer 540 is formed on the third semiconductor layer 530.

The first semiconductor layer 510, the second semiconductor layer 520, the third semiconductor layer 530, and the fourth semiconductor layer 540 are group III nitride semiconductor layers. The bandgap of the second semiconductor layer 520 is larger than the bandgap of the first semiconductor layer 510 and the third semiconductor layer 530. The first semiconductor layer 510, the second semiconductor layer 520, and the third semiconductor layer 530 are undoped semiconductor layers. The fourth semiconductor layer 540 is a p-type semiconductor layer.

The cathode electrode C1 is formed on the second semiconductor layer 520. The recess Y1 reaches from the fourth semiconductor layer 540 to the middle of the second semiconductor layer 520. The cathode electrode C1 is formed on the recess Y1.

The anode electrode A1 is formed on the fourth semiconductor layer 540. The recess Y2 reaches from the fourth semiconductor layer 540 to the middle of the first semiconductor layer 510. The anode electrode A1 is formed from the bottom surface of the recess Y2 to the fourth semiconductor layer 540. Therefore, the anode electrode A1 is in contact with the first semiconductor layer 510, the second semiconductor layer 520, the third semiconductor layer 530, and the fourth semiconductor layer 540. The anode electrode A1 is in contact with the bottom surface and the side surface of the first semiconductor layer 510, the side surface of the second semiconductor layer 520 and the third semiconductor layer 530, and the side surface and the upper surface of the fourth semiconductor layer 540.

FIG. 27 is a diagram showing an electrode forming region of the semiconductor element 500 of the eighth embodiment. As shown in FIG. 27, the semiconductor element 500 includes a cathode electrode contact region CC1 in which the cathode electrode C1 and the second semiconductor layer 520 are in contact with each other, and an anode electrode contact region AC1 in which the anode electrode A1 and the fourth semiconductor layer 540 are in contact with each other. And have.

The cathode electrode contact region CC1 in which the cathode electrode C1 and the second semiconductor layer 520 are in contact has a comb tooth shape. The anode electrode contact region AC1 in which the anode electrode A1 contacts the first semiconductor layer 510 and the fourth semiconductor layer 540 has a rod-like shape. The rod-shaped shape of the region in which the anode electrode contact region AC1 is projected onto the first semiconductor layer 510 is arranged at a position between the comb tooth shapes of the region in which the cathode electrode contact region CC1 is projected on the first semiconductor layer 510.

The polarized superjunction region is a region in which the third semiconductor layer 530 is formed and the fourth semiconductor layer 540 is not formed, and is located between the anode electrode contact region AC1 and the cathode electrode contact region CC1.

2. Withstand voltage In this specification, the withstand voltage of a Schottky barrier diode is the anode voltage Va at which the anode current Ia reaches 1 × 10 ^-4 A when a voltage Va in the opposite direction is applied between the anode electrode A1 and the cathode electrode C1. The value of.

3. 3. Modification 3-1. Shape of Electrode Contact Region The cathode electrode contact region CC1 may have a rod shape, and the anode electrode contact region AC1 may have a comb tooth shape. That is, one of the cathode electrode contact region CC1 and the anode electrode contact region AC1 may have a comb tooth shape, and the other of the cathode electrode contact region CC1 and the anode electrode contact region AC1 may have a rod shape.

FIG. 28 is a diagram showing an electrode forming region of the semiconductor element in the modified example of the eighth embodiment. The cathode electrode contact region CC1 in which the cathode electrode C1 and the second semiconductor layer 520 are in contact has a comb tooth shape. The anode electrode contact region AC1 in which the anode electrode A1 and the first semiconductor layer 510 and the fourth semiconductor layer 540 are in contact has a comb tooth shape. The comb-teeth shape of the region where the cathode electrode contact region CC1 is projected onto the first semiconductor layer 510 is arranged alternately with the comb-teeth shape of the region where the anode electrode contact region AC1 is projected on the first semiconductor layer 510.

One rod-shaped shape of the cathode electrode contact region CC1 and the anode electrode contact region AC1 (including the rod-shaped portion at the tip of the comb-tooth shape) is the other comb-shaped shape of the cathode electrode contact region CC1 and the anode electrode contact region AC1. It suffices if it is placed between them.

3-2. Contact Region of Anode Electrode FIG. 29 is a diagram (No. 1) showing a laminated structure of semiconductor elements 600 in a modified example of the eighth embodiment. The semiconductor element 600 includes a sapphire substrate Sub2, a buffer layer Bf2, a first semiconductor layer 510, a second semiconductor layer 520, a third semiconductor layer 530, a fourth semiconductor layer 540, a cathode electrode C1, and an anode electrode. It has A1 and. The anode electrode A1 is formed on the recess Y3. The recess Y3 reaches from the fourth semiconductor layer 540 to the middle of the second semiconductor layer 520. In the semiconductor element 600, the anode electrode A1 is not in contact with the first semiconductor layer 510.

FIG. 30 is a diagram (No. 2) showing the laminated structure of the semiconductor element 700 in the modified example of the eighth embodiment. The semiconductor element 700 includes a sapphire substrate Sub2, a buffer layer Bf2, a first semiconductor layer 510, a second semiconductor layer 520, a third semiconductor layer 530, a fourth semiconductor layer 540, a cathode electrode C1, and an anode electrode. It has A1 and an insulating layer 750.

The insulating layer 750 covers a part of the second semiconductor layer 520, a side surface of the third semiconductor layer 530, and a part of the fourth semiconductor layer 540. The insulating layer 750 is located between the side surface of the third semiconductor layer 530, the side surface of the fourth semiconductor layer 540, and the anode electrode A1. The anode electrode A1 is in contact with the second semiconductor layer 520 and the fourth semiconductor layer 540, and is not in contact with the third semiconductor layer 530.

As described above, the anode electrode A1 may be in contact with the first semiconductor layer 510 or the second semiconductor layer 520.

3-3. Contact Region of Cathode Electrode FIG. 31 is a diagram (No. 3) showing a laminated structure of semiconductor elements 800 in a modified example of the eighth embodiment. As shown in FIG. 31, the cathode electrode C2 is in contact with the bottom surface and side surface of the first semiconductor layer 510 and the side surface and top surface of the second semiconductor layer 520.

3-4. Polarized super-junction region The length of the polarized super-junction region in the direction connecting the shortest distance from the cathode electrode contact region CC1 to the anode electrode contact region AC1 at the rod-shaped tip is the cathode electrode contact at the portion other than the rod-shaped tip. It is equal to or longer than the length of the polarization superjunction region in the direction connecting the shortest distance from the region CC1 to the anode electrode contact region AC1.

3-5. Distance between the cathode electrode and the third semiconductor layer The distance between the cathode electrode contact region CC1 and the third semiconductor layer 530 is 1 μm or more and 10 μm or less.

3-6. Combination The above modification examples may be freely combined.

(Combination of embodiments)
In some cases, the first to eighth embodiments may be freely combined including modifications.

(Evaluation test)
1. 1. Experiment 1
1-1. Manufacture of FET A FET having a simple structure as shown in FIGS. 32 and 33 was manufactured. FIG. 32 is a diagram showing an FET when the gate electrode contact region GC1 surrounds the source electrode contact region SC1. FIG. 33 is a diagram showing an FET when the gate electrode contact region GC1 is between the source electrode contact region SC1 and the drain electrode contact region DC1. In FIG. 33, the gate electrode contact region GC1 does not surround the source electrode contact region SC1.

As described above, the FET in which the gate electrode contact region GC1 surrounds the source electrode contact region SC1 and the FET in which the gate electrode contact region GC1 does not surround the source electrode contact region SC1 are manufactured. Then, the leakage currents of these FETs were compared.

1-2. Experimental result (leakage current)
FIG. 34 is a graph showing the relationship between the gate voltage and the drain current when 0.1 V is applied to the drain electrode of the FET. The horizontal axis of FIG. 34 is the gate voltage. The vertical axis of FIG. 34 is the drain current.

FIG. 35 is a graph showing the relationship between the gate voltage of the FET and the drain current. The horizontal axis of FIG. 35 is the gate voltage. The vertical axis of FIG. 35 is the drain current. As shown in FIG. 35, when the gate electrode G1 surrounds the source electrode S1, the FET operates when the gate voltage is −5 V or more. Off-leakage current flows even if the gate voltage is less than -5V. The off-leakage current is about 1 × 10 ^-9 A / mm.

As shown in FIG. 35, when the gate electrode G1 does not surround the source electrode S1, the FET operates when the gate voltage is −4.5 V or more. When the gate voltage is less than −4.5 V, an off-leakage current of about ^{1.0 × 10 -6 A / mm flows.} By surrounding the gate electrode G1 around the source electrode S1 in this way, the off-leakage current is reduced by about two orders of magnitude.

FIG. 36 is a graph showing the relationship between the drain voltage of the FET and the drain current. The horizontal axis of FIG. 36 is the drain voltage. The vertical axis of FIG. 36 is the drain current. FIG. 36 shows the drain current of the FET in which the gate electrode G1 surrounds the source electrode S1. FIG. 36 shows the drain current when the gate voltage is changed. As shown in FIG. 36, the larger the gate voltage, the larger the drain current.

FIG. 37 is a graph showing the relationship between the drain voltage and the drain current when the FET is off. The horizontal axis of FIG. 37 is the drain voltage. The vertical axis of FIG. 37 is the drain current. The gate voltage at this time is −10 V. FIG. 37 shows the drain current of the FET in which the gate electrode G1 surrounds the source electrode S1. As shown in FIG. 37, when off, a leakage current of about ^{1 × 10 -9 A / mm flows.} Further, the larger the drain voltage, the slightly larger the drain current.

FIG. 38 is a graph showing the relationship between the off-drain voltage and the gate current in the FET. The horizontal axis of FIG. 38 is the drain voltage. The vertical axis of FIG. 38 is the gate current. The gate voltage at this time is −10 V. FIG. 38 shows the gate current of the FET in which the gate electrode G1 surrounds the source electrode S1. As shown in FIG. 38, when off, a leakage current of about ^{1 × 10 -9 A / mm flows.} Further, the larger the drain voltage, the larger the gate current.

As described above, the leakage current is suppressed in the actually manufactured FET. The current values in FIGS. 35 to 38 are standardized by the gate width.

2. Experiment 2
2-1. Manufacture of FET A FET similar to the semiconductor element 100 of the first embodiment was manufactured. A low-temperature GaN buffer layer, a first undoped GaN layer, an AlGaN layer, a second undoped GaN layer, and an Mg-doped pGaN layer were laminated in this order on a c-plane sapphire substrate by the MOCVD method. The film thicknesses of the low-temperature GaN buffer layer, the first undoped GaN layer, the AlGaN layer, the second undoped GaN layer, and the Mg-doped pGaN layer were 30 nm, 1.0 μm, 47 nm, 80 nm, and 53 nm, respectively. The film formation temperature of the low temperature GaN buffer layer was 530 ° C. The film formation temperature of the first undoped GaN layer, the AlGaN layer, and the second undoped GaN layer was 1100 ° C. The Mg concentration of the Mg-doped pGaN layer ^{was increased from 5.0 × 10 19} cm ^-3 to 2.0 × 10 ²⁰ cm ^-3 to increase the Mg concentration near the surface of the Mg-doped GaN layer.

As a gate electrode, Ni and Au were laminated in order from the semiconductor layer side. As a source electrode and a drain electrode, Ti, Al, Ni, and Au were laminated in this order from the side of the semiconductor layer.

Three types of dislocation densities were used for the semiconductor layer. The dislocation density of the first device was 5.0 × 10 ⁸ cm ^-2. The dislocation density of the second device was 2.3 × 10 ⁹ cm- ² . The dislocation density of the third device was 9.0 × 10 ⁹ cm- ² .

2-2. Evaluation Method FIG. 39 is a circuit diagram used for evaluating the FET. FIG. 40 is a graph showing an output value in the evaluation of FET. The drain voltage Vd was 300V.

FIG. 41 is a diagram showing definitions of a FET rise time tr and a fall time tf. The rise time tr is the time required for the drain voltage Vd to drop from 90% to 10% of the maximum value. The fall time tf is the time required for the drain voltage Vd to rise from 10% to 90% of the maximum value. As shown in FIG. 40, the drain current Id increases as the drain voltage Vd decreases. As shown in FIG. 40, since the drain current Id oscillates in small steps, the drain voltage Vd is used as a reference for the rise time tr and the fall time tf instead of the drain current Id.

2-3. Experimental results (response time)
FIG. 42 is a table showing the characteristics of the FET. In Examples 1-6, the rise time was 22 ns or less. In Comparative Example 1, the rise time was 42 ns. In Example 1-6, the gate length was 4 μm, whereas in Comparative Example 1, the gate length was 8 μm.

FIG. 43 is a graph showing the relationship between the junction area between the second undoped GaN layer (third semiconductor layer) and the Mg-doped pGaN layer (fourth semiconductor layer) in the FET and the withstand voltage of the semiconductor element. The horizontal axis of FIG. 43 is the area of the second undoped GaN layer (third semiconductor layer) per 1 μm in the gate width direction. The vertical axis of FIG. 43 is the withstand voltage of the semiconductor element.

As shown in FIG. 43, the withstand voltage is 1500 V or more in the region where the above equation (1) holds.
101x-810 ≤ y ≤ 235x + 585 ……… (1)
x: Contact area between the second semiconductor layer and the third semiconductor layer per 1 μm in the gate width direction y: Withstand voltage

FIG. 44 is a graph showing the relationship between the gate length of the FET and the response time. The horizontal axis of FIG. 44 is the gate length. The horizontal axis of FIG. 44 is the response time. As shown in FIG. 44, the shorter the gate length, the shorter the response time tends to be. When the gate length is 6 μm or less, the rise time tr and the fall time tf are 30 ns or less. When the gate length is 4 μm or less, the rise time tr and the fall time tf are 20 ns or less.

FIG. 45 is a graph showing the relationship between the junction area and the response time between the third semiconductor layer 130 and the fourth semiconductor layer 140 excluding the polarization superjunction region PSJ1 in the FET. The horizontal axis of FIG. 45 is the bonding area between the third semiconductor layer 130 and the fourth semiconductor layer 140. The vertical axis of FIG. 45 is the response time. As shown in FIG. 45, the smaller the bonding area between the third semiconductor layer 130 and the fourth semiconductor layer 140, the shorter the response time tends to be.

FIG. 46 is a graph showing the relationship between the dislocation density and the junction area in the FET. The horizontal axis of FIG. 46 is the dislocation density. The vertical axis of FIG. 46 is the bonding area between the third semiconductor layer 130 and the fourth semiconductor layer 140. As shown in FIG. 46, it is necessary to increase the bonding area between the third semiconductor layer 130 and the fourth semiconductor layer 140 in order to have a large pressure resistance. Further, the higher the dislocation density, the larger the joint area needs to be taken.

FIG. 47 is a table summarizing the data of FIG. 46.

FIG. 48 is a graph showing the relationship between the dislocation density in the FET and the distance between the source and drain. The horizontal axis of FIG. 48 is the dislocation density. The vertical axis of FIG. 48 is the distance between the source and drain. As shown in FIG. 48, it is necessary to increase the distance between the source and drain in order to have a large pressure resistance. Further, the higher the dislocation density, the larger the distance between the source and drain needs to be.

FIG. 49 is a table summarizing the data of FIG. 48.

FIG. 50 is a graph showing the relationship between the dislocation density and the response time in the FET. The horizontal axis of FIG. 50 is the dislocation density. The vertical axis of FIG. 50 is the response time. As shown in FIG. 50, as the dislocation density is lower, both the rise time tr and the fall time tf tend to be shorter. In particular, the rise time tr is highly effective in improving due to the decrease in dislocation density.

FIG. 51 is a table summarizing the data of FIG. 50. As shown in FIGS. 50 and 51, when the dislocation density is 5 × 10 ⁸ cm ⁻² or less, the rise time tr is 16 ns or less. When the dislocation density is 5 × 10 ⁸ cm ⁻² or less, the fall time tf is 10 ns or less.

2-4. Experimental result (on resistance)
FIG. 52 is a graph showing the relationship between the polarization superjunction length Lpsj and the normalized on-resistance in the FET. The horizontal axis of FIG. 52 is the polarization superjunction length. The vertical axis of FIG. 52 is the normalized on-resistance. As shown in FIG. 52, the longer the polarization superjunction length Lpsj, the higher the normalized on-resistance. Further, when the polarization superjunction length Lpsj is 50 μm or less, the normalized on-resistance is 20 mΩ · cm ² or less. When the polarization superjunction length Lpsj is 2 μm, the normalized on-resistance is about 1 ^{mΩ · cm 2.}

FIG. 53 is a graph showing the relationship between the source-drain distance and the normalized on-resistance in the FET. The horizontal axis of FIG. 53 is the distance between the source and drain. The vertical axis of FIG. 53 is the normalized on-resistance. As shown in FIG. 53, the longer the distance between the source and the drain, the higher the normalized on-resistance. Further, when the distance between the source and drain is 60 μm or less, the normalized on-resistance is 20 mΩ · cm ² or less. When the distance between the source and drain is 11 μm, the normalized on-resistance is about 1 ^{mΩ · cm 2.}

2-5. Experimental results (dislocation density)
FIG. 54 is a table showing the relationship between the dislocation density in the FET and the characteristics of the semiconductor device. As shown in FIG. 54, the lower the dislocation density, the smaller the value of the half width of the X-ray locking curve. Further, the lower the dislocation density, the smaller the sheet resistance. The lower the dislocation density, the higher the mobility of the two-dimensional Hall gas. Sheet resistance is affected by the mobility of the two-dimensional electron gas. Therefore, it is considered that the mobility of the two-dimensional electron gas is increased by lowering the dislocation density and improving the crystallinity. On the other hand, the concentration of the two-dimensional whole gas hardly depends on the dislocation density.

2-6. Experimental results (active area)
FIG. 55 is a table showing the relationship between the chip size of the FET and the current value when the drain voltage Vd is 2V. As shown in FIG. 55, the larger the chip size, the larger the chip outer peripheral length, the chip area, and the active area area. The active region area is the region of the semiconductor in which the current actually flows in the on state. The active region area is between the area of the region where the source electrode and the drain electrode are in contact with the semiconductor layer and the outermost region of the source electrode contact region and the outer peripheral portion of the second semiconductor layer from the area of the element functional region FR1. The area of the area sandwiched between the two and the area minus the area.

Also, the larger the chip size, the larger the gate width. The gate width is the total length of the lines in which the gate electrode G1 surrounds the source electrode S1.

FIG. 56 is a graph showing the relationship between the active region area of the FET and the current value when the drain voltage Vd is 2V. The horizontal axis of FIG. 56 is the active area area. The vertical axis of FIG. 56 is the current value when the drain voltage Vd is 2V. As shown in FIG. 56, when the active region area is 2.2 mm ² or more, the current value when the drain voltage Vd is 2 V is 30 A or more. When the active area is 5.0 mm ² or more, the current value when the drain voltage Vd is 2 V is 100 A or more.

3. 3. Experiment 3
3-1. Manufacture of FET A FET similar to the semiconductor element 200 of the second embodiment was manufactured. The points other than the polarization superjunction length Lpsj are the same as in Experiment 2.

3-2. Experimental results (polarized superjunction length)
FIG. 57 is a table showing the withstand voltage of the FET when the distance Lsd between the polarization superjunction length Lpsj, the source contact electrode S1c and the drain contact electrode D1c in the FET is changed. FIG. 57 shows a case where the minimum value of the polarization superjunction length Lpsj at the tip portion and the minimum value of the polarization superjunction length Lpsj at the portion other than the tip portion are changed.

FIG. 58 is a table showing the withstand voltage of the FET when the polarization superjunction length Lpsj in the FET and the distance Lsd between the source contact electrode S1c and the drain contact electrode D1c are not changed. In FIG. 58, the polarization superjunction length Lpsj at the tip portion and the polarization superjunction length Lpsj at the portion other than the tip portion are the same.

FIG. 59 is a graph showing the relationship between the polarization superjunction length Lpsj in the FET and the withstand voltage of the FET. The horizontal axis of FIG. 59 is the polarization superjunction length Lpsj. The vertical axis of FIG. 59 is the withstand voltage of the FET. As shown in FIG. 59, the withstand voltage of the FET is substantially proportional to the polarization superjunction length Lpsj.

In this way, the withstand voltage of the FET depends on the minimum value of the polarization superjunction length Lpsj.

4. Experiment 4
4-1. Manufacture of FET A FET similar to the semiconductor element 300 of the third embodiment was manufactured. The points other than the distance between the electrode and the semiconductor layer are the same as in Experiment 2.

4-2. Experimental results (distance between electrode and semiconductor layer)
FIG. 60 is a graph showing the relationship between the distance between the drain electrode contact region DC1 and the polarized superjunction surface and the pressure resistance of the FET. The horizontal axis of FIG. 60 is the distance between the drain electrode contact region DC1 and the polarized superjunction surface. The vertical axis of FIG. 60 is the withstand voltage. As shown in FIG. 60, even when the distance between the drain electrode contact region DC1 and the third semiconductor layer 130 is as short as 10 μm or less, the withstand voltage of the semiconductor element is sufficiently high.

FIG. 61 is a graph showing the relationship between the polarization superjunction length Lpsj in the FET and the withstand voltage of the semiconductor element. The horizontal axis of FIG. 61 is the polarization superjunction length Lpsj. The vertical axis of FIG. 61 is the withstand voltage of the semiconductor element. As shown in FIG. 61, the longer the polarization superjunction length Lpsj, the higher the pressure resistance of the semiconductor element. The withstand voltage of the semiconductor element is proportional to the polarization superjunction length Lpsj to some extent.

5. Experiment 5
5-1. Manufacture of FET A FET similar to the semiconductor element 400 of the fourth embodiment was manufactured. The procedure is the same as in Experiment 2 except for the pad electrodes.

5-2. Experimental results (pad electrodes)
FIG. 62 is a graph showing the relationship between the drain voltage and the drain current of the FET. The horizontal axis of FIG. 62 is the drain voltage. The vertical axis of FIG. 62 is the drain current. As shown in FIG. 62, when the gate voltage is increased, the drain current tends to increase. The drain current saturates when the drain voltage is about 15 V or higher.

FIG. 63 is a graph showing the relationship between the gate voltage and the drain current when the drain voltage of the FET is 0.1 V. The horizontal axis of FIG. 63 is the gate voltage. The vertical axis of FIG. 63 is the drain current.

FIG. 64 is a graph showing the relationship between the drain voltage and the drain current when the FET is off. The horizontal axis of FIG. 64 is the drain voltage. The vertical axis of FIG. 64 is the drain current. The gate voltage is -10V.

FIG. 65 is a graph showing the relationship between the drain voltage when the FET is off and the gate current. The horizontal axis of FIG. 65 is the drain voltage. The vertical axis of FIG. 65 is the gate current. The gate voltage is -10V.

The current values in FIGS. 62 to 65 are standardized by the gate width.

6. Experiment 6
6-1. Manufacture of Schottky Barrier Diode A Schottky barrier diode similar to that of the eighth embodiment was manufactured. The laminated structure and manufacturing conditions of the semiconductor layer are the same as in Experiment 1. An element in which the polarization superjunction length Lpsj was changed was manufactured.

6-2. Experimental result (reverse recovery current)
FIG. 66 is a graph showing the reverse recovery time characteristic of a Schottky barrier diode having a polarization superjunction length Lpsj of 20 μm. The horizontal axis of FIG. 66 is time. The vertical axis of FIG. 66 is the anode current. The reverse recovery time was 21.8 ns. The peak value of the reverse recovery current was 5.0 A.

6-3. Experimental results (forward characteristics)
FIG. 67 is a graph showing the forward characteristics of the Schottky barrier diode. The horizontal axis of FIG. 67 is the anode voltage. The vertical axis of FIG. 67 is the anode current. As shown in FIG. 67, the shorter the polarization superjunction length Lpsj, the larger the anode current tends to be. That is, the shorter the polarization superjunction length Lpsj, the smaller the normalized on-resistance tends to be.

6-4. Experimental results (reverse characteristics)
FIG. 68 is a graph showing the reverse characteristics of the Schottky barrier diode. The horizontal axis of FIG. 68 is the cathode voltage. The vertical axis of FIG. 68 is the anode current. As shown in FIG. 68, the shorter the polarization superjunction length Lpsj, the lower the pressure resistance. When the polarization superjunction length Lpsj was 15 μm, 20 μm, 25 μm, 30 μm, and 40 μm, the withstand voltage was about 2000 V, 2600 V, 3000 V, 3000 V, and 3000 V, respectively.

6-5. Experimental results (polarized superjunction length)
FIG. 69 is a table showing the pressure resistance of the Schottky barrier diode when the distance Lac between the polarization superjunction length Lpsj, the anode electrode contact region AC1 and the cathode electrode contact region CC1 is changed. FIG. 69 shows a case where the minimum value of the polarization superjunction length Lpsj at the tip portion and the minimum value of the polarization superjunction length Lpsj at the portion other than the tip portion are changed.

By setting the polarization superjunction length Lpsj and distance Lac of the tip portion to be equal to or greater than the polarization superjunction length Lpsj and distance Lac other than the tip portion, the withstand voltage of the Schottky barrier diode is improved.

(Additional note)
1. 1. 1st
The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. A semiconductor layer, a source electrode and a drain electrode on the second semiconductor layer or the third semiconductor layer, a gate electrode on the fourth semiconductor layer, and a gate electrode contact region where the gate electrode and the fourth semiconductor layer come into contact with each other. It has a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other, and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The region in which the gate electrode contact region is projected onto the second semiconductor layer surrounds the region in which the source electrode contact region or the drain electrode contact region is projected on the second semiconductor layer.

In the semiconductor device of the second aspect, one of the source electrode contact region and the drain electrode contact region has a rod-like shape. The other side of the source electrode contact area and the drain electrode contact area has a comb tooth shape. One rod-shaped shape of the source electrode contact region and the drain electrode contact region is arranged between the other comb tooth shape of the source electrode contact region and the drain electrode contact region.

In the semiconductor element according to the third aspect, the source electrode has a source wiring electrode. The drain electrode has a drain wiring electrode. The region where the source wiring electrode is projected onto the second semiconductor layer does not overlap with the region where the drain wiring electrode is projected onto the second semiconductor layer.

In the semiconductor device according to the fourth aspect, the source electrode has a source wiring electrode. The drain electrode has a drain wiring electrode. The gate electrode has a gate wiring electrode. One of the two regions, the region in which the source wiring electrode is projected on the second semiconductor layer and the region in which the drain wiring electrode is projected on the second semiconductor layer, is a region and a portion in which the gate wiring electrode is projected on the second semiconductor layer. Overlap. The other of the two regions, the region where the source wiring electrode is projected onto the second semiconductor layer and the region where the drain wiring electrode is projected onto the second semiconductor layer, overlaps with the region where the gate wiring electrode is projected onto the second semiconductor layer. It doesn't become.

In the semiconductor element according to the fifth aspect, one of two regions, a region in which the source wiring electrode is projected on the second semiconductor layer and a region in which the drain wiring electrode is projected on the second semiconductor layer, and a gate wiring electrode are provided. Where the region projected onto the second semiconductor layer partially overlaps, the distance between the source wiring electrode or drain wiring electrode and the first semiconductor layer is the distance between the gate wiring electrode and the first semiconductor layer. Greater than.

In the semiconductor element according to the sixth aspect, the first semiconductor layer and the second semiconductor layer are in direct contact with each other. The shape of the contact surface where the first semiconductor layer and the second semiconductor layer come into contact is rectangular. The longitudinal direction of the rod shape is arranged in the direction parallel to the short side of the rectangle.

The device in the seventh aspect has the above-mentioned semiconductor element.

2. Second
The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. A semiconductor layer, a source electrode and a drain electrode on the second semiconductor layer or the third semiconductor layer, a gate electrode on the fourth semiconductor layer, and a gate electrode contact region where the gate electrode and the fourth semiconductor layer come into contact with each other. It has a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other, and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. One of the source electrode contact region and the drain electrode contact region has a rod-like shape. The other side of the source electrode contact area and the drain electrode contact area has a comb tooth shape. One rod-shaped shape of the source electrode contact region and the drain electrode contact region is arranged between the other comb tooth shape of the source electrode contact region and the drain electrode contact region.

In the semiconductor element of the second aspect, the region in which the gate electrode contact region is projected onto the second semiconductor layer surrounds the region in which the source electrode contact region or the drain electrode contact region is projected on the second semiconductor layer.

In the semiconductor element according to the third aspect, the source electrode has a source wiring electrode. The drain electrode has a drain wiring electrode. The region where the source wiring electrode is projected onto the second semiconductor layer does not overlap with the region where the drain wiring electrode is projected onto the second semiconductor layer.

In the semiconductor device according to the fourth aspect, the source electrode has a source wiring electrode. The drain electrode has a drain wiring electrode. The gate electrode has a gate wiring electrode. One of the two regions, the region in which the source wiring electrode is projected on the second semiconductor layer and the region in which the drain wiring electrode is projected on the second semiconductor layer, is a region and a portion in which the gate wiring electrode is projected on the second semiconductor layer. Overlap. The other of the two regions, the region where the source wiring electrode is projected onto the second semiconductor layer and the region where the drain wiring electrode is projected onto the second semiconductor layer, overlaps with the region where the gate wiring electrode is projected onto the second semiconductor layer. It doesn't become.

In the semiconductor element according to the fifth aspect, one of two regions, a region in which the source wiring electrode is projected on the second semiconductor layer and a region in which the drain wiring electrode is projected on the second semiconductor layer, and a gate wiring electrode are provided. Where the region projected onto the second semiconductor layer partially overlaps, the distance between the source wiring electrode or drain wiring electrode and the first semiconductor layer is the distance between the gate wiring electrode and the first semiconductor layer. Greater than.

In the semiconductor element according to the sixth aspect, the first semiconductor layer and the second semiconductor layer are in direct contact with each other. The shape of the contact surface where the first semiconductor layer and the second semiconductor layer come into contact is rectangular. The longitudinal direction of the rod shape is arranged in the direction parallel to the short side of the rectangle.

The device in the seventh aspect has the above-mentioned semiconductor element.

3. 3. Third
The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. A semiconductor layer, a source electrode and a drain electrode on the second semiconductor layer or the third semiconductor layer, a gate electrode on the fourth semiconductor layer, and a gate electrode contact region where the gate electrode and the fourth semiconductor layer come into contact with each other. It has a source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other, and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. One of the source electrode contact region and the drain electrode contact region has a rod-like shape. The other side of the source electrode contact area and the drain electrode contact area has a comb tooth shape. One rod-shaped shape of the source electrode contact region and the drain electrode contact region is arranged between the other comb tooth shape of the source electrode contact region and the drain electrode contact region. This semiconductor device has a polarization superjunction region located between a gate electrode contact region and a drain electrode contact region, which is a region in which a third semiconductor layer is formed and a fourth semiconductor layer is not formed. The length of the polarization superjunction region in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region in the rod-shaped tip portion is from the source electrode contact region to the drain electrode contact region in the portion other than the rod-shaped tip portion. It is longer than the length of the polarization superjunction region in the direction connecting the shortest distances to.

In the semiconductor device of the second aspect, the rod-shaped tip portion is an arc-shaped arc-shaped portion. The portion other than the rod-shaped tip portion is a linear rod-shaped portion.

In the semiconductor element according to the third aspect, the rod-shaped tip portion with respect to the length of the polarized superjunction region in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region in the portion other than the rod-shaped tip portion. The length of the polarization superjunction region in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region is 1.05 or more.

In the semiconductor element according to the fourth aspect, the distance between the source electrode contact region and the drain electrode contact region in the rod-shaped tip portion is the source electrode contact region and the drain electrode contact region in the portion other than the rod-shaped tip portion. It is more than the distance between.

The semiconductor element in the fifth aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. The semiconductor layer, the cathode electrode on the second semiconductor layer, the anode electrode on the fourth semiconductor layer, the cathode electrode contact region where the cathode electrode and the second semiconductor layer contact, the anode electrode and the fourth semiconductor layer. Has an anode electrode contact region, which is in contact with the semiconductor. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The anode electrode is in contact with the second semiconductor layer or the first semiconductor layer. One of the cathode electrode contact region and the anode electrode contact region has a rod-like shape. The other side of the cathode electrode contact area and the anode electrode contact area has a comb tooth shape. One rod-shaped shape of the cathode electrode contact region and the anode electrode contact region is arranged between the other comb tooth shape of the cathode electrode contact region and the anode electrode contact region. This semiconductor device has a polarization superjunction region located between the cathode electrode contact region and the anode electrode contact region, which is a region in which the third semiconductor layer is formed and the fourth semiconductor layer is not formed. The length of the polarization superjunction region in the direction connecting the shortest distance from the cathode electrode contact region to the anode electrode contact region in the rod-shaped tip portion is from the cathode electrode contact region to the anode electrode contact region in the portion other than the rod-shaped tip portion. It is longer than the length of the polarization superjunction region in the direction connecting the shortest distance to.

The semiconductor element in the sixth aspect has a first recess extending from the fourth semiconductor layer to the second semiconductor layer. The cathode electrode is formed on at least the first recess.

In the semiconductor element according to the seventh aspect, the cathode electrode is in contact with the side surface of the first semiconductor layer and the side surface of the second semiconductor layer.

The semiconductor element in the eighth aspect has an anode electrode contact region where the anode electrode and the fourth semiconductor layer contact, and a second recess extending from the fourth semiconductor layer to the first semiconductor layer. The anode electrode is formed on the second recess and is in contact with the first semiconductor layer or the second semiconductor layer.

The semiconductor element in the ninth aspect has an insulating layer between the third semiconductor layer and the fourth semiconductor layer and the anode electrode.

The device according to the tenth aspect has the above-mentioned semiconductor element.

4. Fourth
The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. A semiconductor layer, a source electrode and a drain electrode on the second semiconductor layer or the third semiconductor layer, a gate electrode on the fourth semiconductor layer, and a gate electrode contact region where the gate electrode and the fourth semiconductor layer come into contact with each other. From the source electrode contact region where the source electrode and the second semiconductor layer or the third semiconductor layer contact, the drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer contact, and the fourth semiconductor layer. It has a first recess and a second recess that reach to the second semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The source electrode is formed on the first recess. The drain electrode is formed on the second recess. The distance between the drain electrode contact region and the third semiconductor layer is larger than the distance between the source electrode contact region and the third semiconductor layer.

In the semiconductor element of the second aspect, the distance between the drain electrode contact region and the third semiconductor layer is 10 μm or less.

In the semiconductor element according to the third aspect, when the source electrode contact region, the drain electrode contact region, and the gate electrode contact region are projected onto the second semiconductor layer, the region projected on the drain electrode contact region and the gate electrode contact region are displayed. The distance between the projected regions is greater than the distance between the projected region of the source electrode contact region and the projected region of the gate electrode contact region.

The semiconductor element in the fourth aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. It has a semiconductor layer, a cathode electrode on the second semiconductor layer, an anode electrode on the fourth semiconductor layer, and a cathode electrode contact region where the cathode electrode and the second semiconductor layer come into contact with each other. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The distance between the cathode electrode contact region and the third semiconductor layer is 10 μm or less.

The semiconductor element in the fifth aspect has a first recess extending from the fourth semiconductor layer to the second semiconductor layer. The cathode electrode is formed on at least the first recess.

In the semiconductor element according to the sixth aspect, the cathode electrode is in contact with the side surface of the first semiconductor layer and the side surface of the second semiconductor layer.

The semiconductor element in the seventh aspect has an anode electrode contact region where the anode electrode and the fourth semiconductor layer contact, and a second recess extending from the fourth semiconductor layer to the first semiconductor layer. The anode electrode is formed on the second recess and is in contact with the first semiconductor layer or the second semiconductor layer.

The semiconductor element in the eighth aspect has an insulating layer between the third semiconductor layer and the fourth semiconductor layer and the anode electrode.

The device in the ninth aspect has the above-mentioned semiconductor element.

5. Fifth
The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. It has a semiconductor layer, a source electrode and a drain electrode on the second semiconductor layer or the third semiconductor layer, and a gate electrode on the fourth semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. At least one of the gate electrode, the source electrode, and the drain electrode has a contact electrode, a wiring electrode, and a pad electrode. The wiring electrode connects the contact electrode and the pad electrode. The wiring electrode has a curved portion that curves in an arc shape.

In the semiconductor element of the second aspect, at least one of the gate electrode, the source electrode, and the drain electrode has a plurality of pad electrodes.

In the semiconductor element according to the third aspect, the gate electrode, the source electrode, and the drain electrode have a contact electrode, a wiring electrode, and a pad electrode. This semiconductor element has an insulating layer between the wiring electrode of the gate electrode and the wiring electrode of the source electrode. The insulating layer has a first insulating layer and a second insulating layer above the first insulating layer.

In the semiconductor device according to the fourth aspect, the insulating layer has at least one of an inorganic dielectric film and an organic dielectric film.

In the semiconductor element according to the fifth aspect, the first semiconductor layer and the second semiconductor layer are in direct contact with each other. The shape of the contact surface where the first semiconductor layer and the second semiconductor layer come into contact is rectangular.

The device in the sixth aspect has the above-mentioned semiconductor element.

6. 6th
The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. It has a semiconductor layer, a source electrode and a drain electrode on the second semiconductor layer or the third semiconductor layer, and a gate electrode on the fourth semiconductor layer. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. The dislocation density is 1 × 10 ⁶ cm ^-2 or more and 1 × 10 ¹⁰ cm ^-2 or less. Contact area between the second semiconductor layer and the third semiconductor layer, per 1μm gate width direction is 10 [mu] m ² or more 200 [mu] m ² or less.

In the semiconductor device of the second aspect, the dislocation density is 5 × 10 ⁹ cm ⁻² or less.

In the semiconductor element according to the third aspect, the contact area and the withstand voltage between the second semiconductor layer and the third semiconductor layer are determined by the following equation 101x-810 ≤ y ≤ 235x + 585.
x: Contact area between the second semiconductor layer and the third semiconductor layer per 1 μm in the gate width direction y: Satisfy the withstand voltage.

In the semiconductor element according to the fourth aspect, the gate length, which is the length of the fourth semiconductor layer in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region, is 6 μm or less. Both the rise time and the fall time at 300 V switching are 30 ns or less.

The semiconductor element in the fifth aspect includes the above-mentioned semiconductor element.

7. 7th
The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. The semiconductor layer, the source electrode and drain electrode on the second semiconductor layer or the third semiconductor layer, the gate electrode on the fourth semiconductor layer, and the source electrode and the second semiconductor layer or the third semiconductor layer come into contact with each other. It has a source electrode contact region and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. This semiconductor device has a polarization superjunction region located between a gate electrode contact region and a drain electrode contact region, which is a region in which a third semiconductor layer is formed and a fourth semiconductor layer is not formed. The polarization superjunction length, which is the length of the polarization superjunction region in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region, is 50 μm or less. The gate length, which is the length of the fourth semiconductor layer in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region, is 6 μm or less.

In the semiconductor device of the second aspect, the normalized on-resistance is 20 mΩ · cm ² or less.

In the semiconductor element according to the third aspect, both the rise time and the fall time at 300 V switching are 30 ns or less.

The device in the fourth aspect has the above-mentioned semiconductor element.

8. 8th
The semiconductor element in the first aspect includes a first semiconductor layer, a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth layer above the third semiconductor layer. The semiconductor layer, the source electrode and drain electrode on the second semiconductor layer or the third semiconductor layer, the gate electrode on the fourth semiconductor layer, and the source electrode and the second semiconductor layer or the third semiconductor layer come into contact with each other. It has a source electrode contact region and a drain electrode contact region where the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other. The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer and the third semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are undoped semiconductor layers. The fourth semiconductor layer is a p-type semiconductor layer. From the area of the second semiconductor layer on the third semiconductor layer side, the area of the source electrode contact region and the drain electrode contact region, and the region sandwiched between the outermost source electrode contact region and the outer peripheral portion of the second semiconductor layer. The area of the active area minus the area of is 2.2 mm ² or more.

In the semiconductor element of the second aspect, the gate length, which is the length of the fourth semiconductor layer in the direction connecting the shortest distance from the source electrode contact region to the drain electrode contact region, is 6 μm or less.

In the semiconductor element according to the third aspect, the gate width is 300 mm or more.

In the semiconductor element according to the fourth aspect, the outer peripheral length of the semiconductor element is 13 mm or more.

In the semiconductor device according to the fifth aspect, both the rise time and the fall time are 30 ns or less.

In the semiconductor device according to the sixth aspect, the source electrode has a source pad electrode exposed to the outside of the device. The drain electrode has a drain pad electrode exposed to the outside of the element. The region where the source pad electrode and the drain pad electrode are projected onto the second semiconductor layer does not overlap with the region where the second semiconductor layer is formed.

The semiconductor element in the seventh aspect has the above-mentioned semiconductor element.

100 ... Semiconductor element Sub1 ... Sapphire substrate Bf1 ... Buffer layer 110 ... First semiconductor layer 120 ... Second semiconductor layer 130 ... Third semiconductor layer 140 ... Fourth semiconductor layer S1 ... Source electrode SC1 ... Source electrode contact region D1 ... Drain electrode DC1 ... Drain electrode contact area G1 ... Gate electrode GC1 ... Gate electrode contact area

Claims (9)

1. The first semiconductor layer and
   The second semiconductor layer above the first semiconductor layer and
   The third semiconductor layer above the second semiconductor layer and
   The fourth semiconductor layer above the third semiconductor layer and
   With the source electrode and drain electrode on the second semiconductor layer or the third semiconductor layer,
   With the gate electrode on the fourth semiconductor layer,
   A gate electrode contact region where the gate electrode and the fourth semiconductor layer are in contact with each other,
   A source electrode contact region in which the source electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other.
   A drain electrode contact region in which the drain electrode and the second semiconductor layer or the third semiconductor layer are in contact with each other.
   The first recess and the second recess extending from the fourth semiconductor layer to the second semiconductor layer,
   Have,
   The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are
   It is a group III nitride semiconductor layer.
   The band gap of the second semiconductor layer is
   Larger than the bandgap of the first semiconductor layer and the third semiconductor layer,
   The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are
   It is an undoped semiconductor layer and
   The fourth semiconductor layer is
   It is a p-type semiconductor layer and
   The source electrode is
   It is formed on the first recess and
   The drain electrode is
   It is formed on the second recess and
   The distance between the drain electrode contact region and the third semiconductor layer is
   A semiconductor device including a distance greater than the distance between the source electrode contact region and the third semiconductor layer.
2. In the semiconductor device according to claim 1,
   The distance between the drain electrode contact region and the third semiconductor layer is
   A semiconductor device including being 10 μm or less.
3. In the semiconductor device according to claim 1 or 2.
   When the source electrode contact region, the drain electrode contact region, and the gate electrode contact region are projected onto the second semiconductor layer,
   The distance between the region where the drain electrode contact region is projected and the region where the gate electrode contact region is projected is
   A semiconductor device including a distance larger than a distance between a region projecting the source electrode contact region and a region projecting the gate electrode contact region.
4. The first semiconductor layer and
   The second semiconductor layer above the first semiconductor layer and
   The third semiconductor layer above the second semiconductor layer and
   The fourth semiconductor layer above the third semiconductor layer and
   With the cathode electrode on the second semiconductor layer,
   With the anode electrode on the fourth semiconductor layer,
   A cathode electrode contact region where the cathode electrode and the second semiconductor layer are in contact with each other,
   Have,
   The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are
   It is a group III nitride semiconductor layer.
   The band gap of the second semiconductor layer is
   Larger than the bandgap of the first semiconductor layer and the third semiconductor layer,
   The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are
   It is an undoped semiconductor layer and
   The fourth semiconductor layer is
   It is a p-type semiconductor layer and
   The distance between the cathode electrode contact region and the third semiconductor layer is
   A semiconductor device including being 10 μm or less.
5. In the semiconductor device according to claim 4,
   It has a first recess extending from the fourth semiconductor layer to the second semiconductor layer.
   The cathode electrode is
   A semiconductor device including at least formed on the first recess.
6. In the semiconductor device according to claim 5,
   The cathode electrode is
   A semiconductor element including contact with a side surface of the first semiconductor layer and a side surface of the second semiconductor layer.
7. The semiconductor device according to any one of claims 4 to 6.
   An anode electrode contact region where the anode electrode and the fourth semiconductor layer come into contact with each other.
   A second recess extending from the fourth semiconductor layer to the first semiconductor layer,
   Have,
   The anode electrode is
   A semiconductor element formed on the second recess and including being in contact with the first semiconductor layer or the second semiconductor layer.
8. In the semiconductor device according to claim 7,
   A semiconductor device including an insulating layer between the third semiconductor layer and the fourth semiconductor layer and the anode electrode.
9. The device having the semiconductor element according to any one of claims 1 to 8.

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