WO2021192098A1

WO2021192098A1 - Information processing device, information processing method, and information processing program

Info

Publication number: WO2021192098A1
Application number: PCT/JP2020/013368
Authority: WO
Inventors: 昂輝井川
Original assignee: 三菱電機株式会社
Priority date: 2020-03-25
Filing date: 2020-03-25
Publication date: 2021-09-30
Also published as: JPWO2021192098A1; JP7062142B2; CN115349120A

Abstract

Access control hardware (50) determines whether or not to permit access to a memory region, in units of a reference region size, which is a memory region size used as a basis for determining whether or not to permit access. An access control setting unit (13) sets, in the access control hardware, hardware determination region information that indicates, as a hardware determination region, a memory region of a size equal to n times the reference region size (where n is an integer at least equal to 1), and causes the access control hardware to determine whether or not to permit access to the hardware determination region. An access determination unit (15) determines whether or not to permit access to a memory region that is included in the hardware determination region and that is of a size smaller than the reference region size.

Description

Information processing equipment, information processing methods and information processing programs

This disclosure relates to an information processing device, an information processing method, and an information processing program.

In recent years, with the diversification of functions installed in information processing devices, a configuration for executing multitasking in which a plurality of functions are realized by a plurality of tasks may be adopted. In a multitasking execution environment, a memory protection function may be required to prevent a task from unintentionally accessing a memory area managed by another task.
As a general method for realizing the memory protection function, there is a method of using hardware having a memory protection function independent of the CPU (Central Processing Unit) (hereinafter, access control hardware).
Examples of access control hardware include MPU (Memory Protection Unit) or MMU (Memory Management Unit).
As a specific example of the memory protection function, when MPU is used, the OS (Operating System) defines in advance for each task each task, and the information about the memory area for which access is permitted (hereinafter, HW access right). Information) is set in the control register of the MPU. Then, the MPU monitors whether the memory access of each task violates the memory access right based on the HW access right information set in the control register.

If a memory access violation is detected, the MPU notifies the OS of the memory access violation and causes the OS to perform memory access violation processing for removing the cause of the access violation and returning to the state before the access violation. In this way, the MPU realizes the memory protection function by performing access control for controlling access to the memory area.
In the following, a method of realizing such access control with access control hardware will be referred to as HW memory protection.
For example, Patent Document 1 discloses an HW memory protection technique using an MPU or MMU.

JP 2013-140476A

In HW memory protection using access control hardware, access control can be performed only in units of the reference area size, which is the size of the memory area for which access control is possible, and access control to memory areas smaller than the reference area size cannot be performed. There may be an area size constraint called.

A method of performing access control processing in an OS running on a CPU has also been proposed so as not to be restricted by the area size.
Hereinafter, the method of performing such access control processing by the CPU is referred to as SW memory protection.
While SW memory protection can control access without being restricted by area size, there is a problem that the CPU load is larger than that of HW memory protection.

One of the main purposes of this disclosure is to solve the above problems, and it is an object to realize access control without being restricted by the area size while suppressing the CPU load.

The information processing device according to the present disclosure is
Access control hardware, which is hardware that determines whether or not to allow access to a memory area, is a unit of the reference area size, which is the size of the memory area that is the standard for determining whether or not to allow access.
Hardware judgment area information indicating a memory area having a size n (n is an integer of 1 or more) times the reference area size as a hardware judgment area is set in the access control hardware, and the access control hardware is described. An access control setting unit that determines whether or not to allow access to the hardware determination area,
It has an access determination unit for determining whether or not to allow access to a memory area having a size smaller than the reference area size included in the hardware determination area.

According to the present disclosure, access control can be realized without being restricted by the area size while suppressing the CPU load.

The figure which shows the hardware configuration example of the information processing apparatus which concerns on Embodiment 1. FIG. The figure which shows the functional structure example of the information processing apparatus which concerns on Embodiment 1. FIG. The flowchart which shows the operation example of the information processing apparatus which concerns on Embodiment 1. The flowchart which shows the execution example of the task of the information processing apparatus which concerns on Embodiment 1. The flowchart which shows the example of the access control by the HW memory protection of the information processing apparatus which concerns on Embodiment 1. The flowchart which shows the example of the access control by the SW memory protection of the information processing apparatus which concerns on Embodiment 1. FIG. The figure which shows the example of the shared memory area corresponding to the transmission packet structure which concerns on Embodiment 1. FIG. The figure which shows the example of the access control concerning the packet transmission which concerns on Embodiment 1. FIG. The figure which shows the example of the shared memory area corresponding to the received packet structure which concerns on Embodiment 1. FIG. The figure which shows the example of the access control about the packet reception which concerns on Embodiment 1. FIG. The figure which shows the functional structure example of the information processing apparatus which concerns on Embodiment 2. FIG. The flowchart which shows the operation example of the access determination information generation of the information processing apparatus which concerns on Embodiment 2.

Hereinafter, embodiments will be described with reference to figures. In the following description and drawings of the embodiments, those having the same reference numerals indicate the same parts or corresponding parts.

Embodiment 1.
*** Explanation of configuration ***
FIG. 1 is a diagram showing a hardware configuration example of the information processing device 1 according to the present embodiment.
The information processing device 1 is a computer. The information processing device 1 includes a processor 10, a memory 20, an auxiliary storage device 30, a communication interface 40 (also referred to as communication I / F40), and access control hardware 50 as hardware, and is connected to each other by a signal line. ..

The processor 10 is an IC (Integrated Circuit) that performs processing. The processor 10 is, as a specific example, a CPU.

The memory 20 is a volatile memory that temporarily stores data. As a specific example, the memory 20 is a RAM (Random Access Memory).

The auxiliary storage device 30 is a non-volatile memory for storing data. As a specific example, the auxiliary storage device 30 is a hard disk.
The auxiliary storage device 30 includes SSD (registered trademark, Solid State Drive), SD (registered trademark, Secure Digital) memory card, CF (registered trademark, CompactFlash), NAND flash, flexible disk, optical disk, compact disk, and Blu-ray (registered trademark, Secure Digital) memory card. It may be a portable recording medium such as a registered trademark) disc or a DVD (registered trademark, Digital Versaille Disk).
The auxiliary storage device 30 stores HW access right information and access determination information, which will be described later.
Further, the auxiliary storage device 30 stores a program that realizes the functions of the communication task 11, the general task 12, the access control setting unit 13, the task control unit 14, the access determination unit 15, and the access control unit 16, which will be described later.
The program that realizes the functions of the communication task 11, the general task 12, the access control setting unit 13, the task control unit 14, the access determination unit 15, and the access control unit 16 stored in the auxiliary storage device 30 is loaded by the memory 20. NS. Further, the program is read by the processor 10 and executed.

The OS is also stored in the auxiliary storage device 30. Then, at least a part of the OS is executed by the processor 10.
The processor 10 executes a program that realizes the functions of the communication task 11, the general task 12, the access control setting unit 13, the task control unit 14, the access determination unit 15, and the access control unit 16 while executing at least a part of the OS. Run.
When the processor 10 executes the OS, task management, memory management, file management, communication control, and the like are performed.

Further, at least one of information, data, a signal value, and a variable value indicating the processing results of the communication task 11, the general task 12, the access control setting unit 13, the task control unit 14, the access determination unit 15, and the access control unit 16. Is stored in at least one of the processor 10, the memory 20, the register in the auxiliary storage 30, and the cache memory.

The programs that realize the functions of the communication task 11, the general task 12, the access control setting unit 13, the task control unit 14, the access determination unit 15, and the access control unit 16 are hard disks, SSDs (registered trademarks), and SDs (registered trademarks). It may be stored in a portable recording medium such as a memory card, CF (registered trademark), NAND flash, flexible disk, optical disk, compact disc, Blu-ray (registered trademark) disk, or DVD (registered trademark).
Then, a program that realizes the functions of the communication task 11, the general task 12, the access control setting unit 13, the task control unit 14, the access determination unit 15, and the access control unit 16 may be distributed.

The communication I / F40 is an electronic circuit that executes information communication processing with a connection destination via a signal line. As a specific example, the communication I / F40 is a communication chip for Ethernet (registered trademark) or a NIC (Network Interface Card).

The access control hardware 50 executes access control by HW memory protection.
More specifically, the access control hardware 50 determines whether or not to allow access to the memory area in units of the reference area size, which is the size of the memory area that is the reference for determining whether or not to allow access. Further, the access control hardware 50 notifies the OS of the memory access violation and causes the OS to execute the memory access violation processing when it is determined that the access is not permitted as a result of determining whether the access is permitted or not.
The access control hardware 50 is, as a specific example, an MPU.
In this embodiment, MPU will be used as a specific example of the access control hardware 50.

Note that the "unit" of the access control setting unit 13, the task control unit 14, the access determination unit 15, and the access control unit 16 may be read as "process", "procedure", or "process".

FIG. 2 shows the functional configuration of the information processing device 1 according to the present embodiment.
The information processing device 1 includes a communication task 11, a general task 12, an access control setting unit 13, a task control unit 14, an access determination unit 15, and an access control unit 16.

Communication task 11 sends and receives packets via the communication I / F40.

The general task 12 generates or processes at least a part of the data of the payload part of the packet sent and received by the communication task 11. There may be a plurality of general tasks 12.

The access control setting unit 13 confirms the execution schedule of the communication task 11 or the general task 12, and acquires the HW access right information of the communication task 11 or the general task 12.
The HW access right information is information defined for each task. Further, the HW access right information may be defined for each task execution cycle for tasks that are periodically executed.
The HW access right information includes hardware determination area information indicating a memory area having a size at least n (n is an integer of 1 or more) times the reference area size as a hardware determination area. Further, the HW access right information may include access attributes such as data read or write in addition to the hardware determination area information. That is, the HW access right information is information that defines which memory area and what kind of access attribute the access control hardware 50 is allowed to access.
Then, the access control setting unit 13 sets the HW access right information in the access control hardware 50, and causes the access control hardware 50 to determine whether or not to allow access to the hardware determination area.
Further, the access control setting unit 13 may set HW access right information including hardware determination area information for each timing for a plurality of timings in the access control hardware 50. As a specific example, the access control setting unit 13 may set the HW access right information including the hardware determination area information in the access control hardware 50 for each task switching timing. Then, the access control setting unit 13 may cause the access control hardware 50 to determine whether or not to allow access to the corresponding hardware determination area at each timing.
The process performed by the access control setting unit 13 corresponds to the access control setting process.

The task control unit 14 switches the task to be executed after the access control setting unit 13 completes setting the HW access right information in the access control hardware 50.

Based on the access determination information, the access determination unit 15 determines whether or not to allow access to the memory area having a size smaller than the reference area size included in the hardware determination area.
The access determination information is information defined for each task. Further, the access determination information may be defined for each task execution cycle for the task to be executed periodically.
Further, the access determination information includes software determination area information indicated as a software determination area determined by the access determination unit 15. Further, the access determination information may include access attributes such as data read or write in addition to the software determination area information. That is, the access determination information is information that defines which memory area and what access attribute the access determination unit 15 is allowed to access.
The access determination information according to the present embodiment is information specified at the time of designing the information processing apparatus 1.
The process performed by the access determination unit 15 corresponds to the access determination process.

The access control unit 16 controls access to the memory area based on the permission / rejection determination result of the access determination unit 15.
That is, the access determination unit 15 and the access control unit 16 execute access control by SW memory protection.
The access control setting unit 13, the task control unit 14, the access determination unit 15, and the access control unit 16 may be realized as a part of the functions of the OS.

*** Explanation of operation ***
Next, an operation example of the information processing apparatus 1 according to the present embodiment will be described with reference to the flowchart of FIG.
In the following, in data sharing between communication task 11 and general task 12, as a method of reducing the number of data copies, a reference area corresponding to a packet structure composed of a header, a payload, and a footer is based on the concept of zero copy. An example of preparing a shared memory area of size is used.
In the following example, the communication task 11 accesses the shared memory area. In addition, the general task 12 accesses the payload portion that is smaller than the reference area size.
Therefore, for the access of the communication task 11, the HW access right information and the access determination information are set so that the access is permitted only by the access control by the HW memory protection. Further, for the access of the general task 12, the HW access right information and the access determination information are set so that the access is permitted only by the access control by the SW memory protection.
In the present embodiment, the shared memory area is described as the reference area size so that it becomes clear that the payload portion is smaller than the reference area size, but the shared memory area is not limited to this and is twice the reference area size. It may be an integral multiple of the above.

First, in step S100, the access control setting unit 13 waits until the timing of starting or switching the task arrives. When the timing of starting or switching the task arrives, the process proceeds to step S110.

Next, in step S110, the access control setting unit 13 confirms the task execution schedule from the OS, and then acquires the HW access right information of the task whose execution is to be refrained from starting.

Next, in step S120, the access control setting unit 13 sets the HW access right information in the access control hardware 50. Then, the access control setting unit 13 notifies the task control unit 14 of the completion of the setting.

Next, in step S130, the task control unit 14 starts the task whose execution is to be refrained from next based on the task execution schedule. If there is a task being executed, the task control unit 14 switches the task and starts the next task to be refrained from being executed. Then, the process returns to step S100.

Next, an execution example of the task of the information processing apparatus 1 according to the present embodiment will be described with reference to the flowchart of FIG.

First, in step S200, the task started by the task control unit 14 executes the process. As a specific example, if the started task is the communication task 11, the communication task 11 executes a process related to sending and receiving packets.
Then, when the task reads the data in the memory area or writes the data to the memory area, the process proceeds to step S210.

Next, in step S210, when the task attempts to access the memory area, the process proceeds to step S220. On the other hand, if the task does not attempt to access the memory area, the process proceeds to step S230.

In step S220, the access control hardware 50 executes access control by HW memory protection.
Details of access control by HW memory protection will be described later.

In step S230, the task notifies the access determination unit 15 of the access request to the memory area.
When the access determination unit 15 and the access control unit 16 are realized as a part of the functions of the OS, the task may notify the access request to the memory area by using the API (Application Programming Interface) of the OS.

In step S240, access control by SW memory protection is executed by the access determination unit 15 and the access control unit 16 notified of the access request from the task.
Details of access control by SW memory protection will be described later.

Next, an example of access control by HW memory protection of the information processing apparatus 1 according to the present embodiment will be described with reference to the flowchart of FIG.

First, in step S300, the access control hardware 50 determines whether or not to allow access to the shared memory area by the communication task 11 based on the set HW access right information.

Next, in step S310, if the access control hardware 50 determines whether or not to allow access is permitted, the process proceeds to step S320. On the other hand, if the access control hardware 50 does not allow the access, the process proceeds to step S330.

In step S320, the access control hardware 50 causes the communication task 11 to access the shared memory area.

In step S330, the access control hardware 50 notifies the OS of the memory access violation, and causes the OS to execute the memory access violation processing for removing the cause of the access violation and returning to the state before the access violation.

In this way, if the access tried by the communication task 11 is permitted to the access control hardware 50, the communication task 11 can access the shared memory area. If the communication task 11 unintentionally attempts to access an unauthorized shared memory area, the access control hardware 50 causes the OS to execute memory access violation processing to protect the memory. ..

Next, an example of access control by SW memory protection of the information processing device 1 according to the present embodiment will be described with reference to the flowchart of FIG.

First, in step S400, the access determination unit 15 determines whether or not to allow access to the shared memory area by the general task 12 based on the set access determination information.

Next, in step S410, the access control unit 16 acquires the result of determining whether or not to allow access by the access determination unit 15.

Next, in step S420, the access control unit 16 confirms the result of the access permission / rejection determination by the access determination unit 15. If the result of the access permission / rejection determination by the access determination unit 15 is permission, the process proceeds to step S430. On the other hand, if the result of the access permission / rejection determination by the access determination unit 15 is not permission, the process proceeds to step S440.

Next, in step S430, the access control unit 16 causes the general task 12 to access the shared memory area. As a specific example, the access control unit 16 causes the general task 12 to access the shared memory area via the OS. When the access determination unit 15 and the access control unit 16 are realized as a part of the functions of the OS, the access control unit 16 causes the OS to access the shared memory area in response to a request received from the task by the access determination unit 15. You may.

Next, in step S440, the access control unit 16 notifies the OS of the memory access violation and causes the OS to execute the memory access violation process.

In this way, if the access requested by the general task 12 is permitted to the access determination unit 15, the general task 12 can access the shared memory area. Further, when the general task 12 unintentionally requests access to an unauthorized memory area, the access requested by the general task 12 is not permitted to the access determination unit 15, and the access control unit 16 is set to the OS. The memory is protected by letting the memory access violation process be executed.

Next, an operation example of the information processing apparatus 1 relating to packet transmission according to the present embodiment will be described with reference to FIGS. 7 and 8.
FIG. 7 shows an example of a shared memory area corresponding to the transmission packet structure according to the present embodiment.
The shared memory area of the reference area size shown in FIG. 7 is divided into memory areas smaller than the reference area size such as the header, the areas sd1 and sd2 in the payload, and the footer. Then, it is shown that the entire area of the shared memory area is a hardware determination area to which access control by HW memory protection is applied. Further, sd1 and sd2 are shown to be software determination areas to which access control by SW memory protection is applied.

FIG. 8 shows an example of access control related to packet transmission according to the present embodiment.
An example is used in which the communication task 11 and the general task X and the general task Y, which are the general tasks 12, are executed. In addition, it is assumed that each task is executed in a specified cycle, execution timing, and execution time.
The three rows from the top of the table in FIG. 8 show the cycle, execution timing, and execution task, which indicate the execution schedule of the task, and indicate that the time advances as it advances to the right end.
In addition, the three rows from the bottom of the table in FIG. 8 show the status of access control by HW memory protection and SW memory protection during execution of each task.
Specifically, the communication task 11 is executed at the execution timings from 1 to 3 in the cycle 0. Then, at the timing, the access control setting unit 13 informs the access control hardware 50 of the hardware determination area information in which the shared memory area is used as the hardware determination area, and the access attributes of the read (R) and the write (W). Is set. Then, at the timing, it is shown that the access control by the HW memory protection of the access control hardware 50 allows the read (R) and write (W) access to the shared memory area.
On the other hand, at this timing, it is shown that the software determination area information and the access attribute are not set in the access determination information.
Further, the general task X is executed at the execution timings from 4 to 7 in the cycle 0. Then, at the timing, the software determination area information with sd1 as the software determination area and the access attribute of the write (W) are set in the access determination information. Then, at the execution timing, the access control by the SW memory protection of the access determination unit 15 and the access control unit 16 enables the write (W) access to the area sd1 in the payload of the shared memory area. It is shown.
On the other hand, at this timing, the access control setting unit 13 indicates that the access control hardware 50 is set with hardware determination area information that does not use the shared memory area as the hardware determination area as HW access right information. ing.
Further, the general task Y is executed at the execution timings from 8 to 10 in the cycle 0. Then, at the timing, the software determination area information with sd2 as the software determination area and the access attribute of the write (W) are set in the access determination information. Then, at the execution timing, it is shown that the access control by the SW memory protection of the access determination unit 15 and the access control unit 16 allows the write (W) access to the area sd2 in the payload of the shared memory area. Has been done.
On the other hand, at this timing, the access control setting unit 13 indicates that the access control hardware 50 is set with hardware determination area information that does not use the shared memory area as the hardware determination area as HW access right information. ing.

Further, a series of processing examples related to packet transmission are shown in FIGS. 8 (1) to (3).
Specifically, in (1), the general task X accesses sd1 and writes the data. Next, in (2), the general task Y accesses sd2 and writes the data. Then, in (3), the communication task 11 accesses the shared memory area, writes the data to the header and the footer, then reads the data in the entire shared memory area and transfers it to the communication I / F 40 as a transmission packet.

Next, an operation example of the information processing apparatus 1 relating to packet reception according to the present embodiment will be described with reference to FIGS. 9 and 10. The same configuration or operation as packet transmission will be omitted and the differences will be described.
FIG. 9 shows an example of a shared memory area corresponding to the received packet structure according to the present embodiment.
The shared memory area of the reference area size shown in FIG. 9 is divided into memory areas smaller than the reference area size such as the header, the areas rd1 and rd2 in the payload, and the footer. Then, it is shown that access control by SW memory protection is applied to rd1 and rd2.

FIG. 10 shows an example of access control related to packet reception according to the present embodiment.
Specifically, the communication task 11 is executed at the execution timings from 1 to 3 in the cycle 0. Then, at the timing, the access control setting unit 13 informs the access control hardware 50 of the hardware determination area information in which the shared memory area is used as the hardware determination area, and the access attributes of the read (R) and the write (W). Is set. Then, at the timing, it is shown that the access control by the HW memory protection of the access control hardware 50 allows the read (R) and write (W) access to the shared memory area.
On the other hand, at this timing, it is shown that the software determination area information and the access attribute are not set in the access determination information.
Further, the general task X is executed at the execution timings from 4 to 7 in the cycle 0. Then, at the timing, the software determination area information with rd1 as the software determination area and the access attribute of the read (R) are set in the access determination information. Then, at the timing, it is shown that the access control by the SW memory protection of the access determination unit 15 and the access control unit 16 allows the read (R) access to the area rd1 in the payload of the shared memory area. Has been done.
On the other hand, at this timing, the access control setting unit 13 indicates that the access control hardware 50 is set with hardware determination area information that does not use the shared memory area as the hardware determination area as HW access right information. ing.
Further, the general task Y is executed at the execution timings from 8 to 10 in the cycle 0. Then, at the timing, the software determination area information with rd2 as the software determination area and the access attribute of the read (R) are set in the access determination information. Then, at the timing, it is shown that the access control by the SW memory protection of the access determination unit 15 and the access control unit 16 allows the read (R) access to the area rd2 in the payload of the shared memory area. ing.
On the other hand, at this timing, the access control setting unit 13 indicates that the access control hardware 50 is set with hardware determination area information that does not use the shared memory area as the hardware determination area as HW access right information. ing.

Further, a series of processing examples related to packet reception are shown in FIGS. 10 (1) to (3).
Specifically, in (1), the communication task 11 acquires the received packet from the communication I / F40, accesses the shared memory area, and writes the data. After that, the communication task 11 reads the header and footer data and verifies the validity. Next, in (2), the general task X accesses rd1 and reads the data. Then, in (3), the general task Y accesses rd2 and reads the data.

*** Explanation of the effect of the embodiment ***
As described above, in the present embodiment, in the memory protection environment, the communication task 11 and the general task 12 access the shared memory area and share data by using the shared memory area corresponding to the packet structure. Then, access to the shared memory area, which is the reference area size, is controlled by access control by HW memory protection, and access to the payload portion smaller than the reference area size is controlled by access control by SW memory protection. Therefore, access control is realized without being restricted by the area size associated with HW memory protection. Further, since access control by SW memory protection is used only for a part of the shared memory area, the CPU load can be suppressed.
When only the access control by HW memory protection is used and the data stored in the memory area of the packet structure accessible only by the communication task 11 is shared with the general task 12, an overhead due to data copying occurs.
More specifically, the communication task 11 copies the payload data from the memory area of the packet structure to the memory area to which the general task 12 is allowed access. Then, the general task 12 accesses the memory area to which access is permitted and acquires the copied data so that the data can be shared, but the overhead of the processing time and the memory usage related to the data copy occurs. It ends up. By using the access control according to the present embodiment, the data copy can be avoided, so that the effect of reducing the overhead of the processing time and the memory usage related to the data copy can also be obtained.

Embodiment 2.
In this embodiment, an example in which access determination information is generated even when the information processing apparatus 1 is operating will be described.
In this embodiment, the difference from the first embodiment will be mainly described.
The matters not explained below are the same as those in the first embodiment.

*** Explanation of configuration ***
FIG. 11 shows the functional configuration of the information processing device 1 according to the present embodiment.
In the present embodiment, the information processing device 1 newly includes a determination information generation unit 17.
The determination information generation unit 17 generates access determination information in response to a request for access determination information generation from a task that requests access determination information generation (hereinafter referred to as a request task).
In the generation request, the identifier of the target task (hereinafter, the target task) for which the access determination unit 15 determines the access permission / disapproval and the memory area (hereinafter, the memory area) in which the target task requests the access determination unit 15 to determine the access permission / disapproval. , Request memory area) is included. Further, in the generation request, the execution timing of the target task (hereinafter, request timing) in which the target task requests the access determination unit 15 to determine whether or not to allow access, and the access attribute given to the target task (hereinafter, grant attribute). The requirements for access judgment such as are also included.
The requested memory area is at least a part of the memory area in which the requested task is permitted to access but the target task is not permitted to access by the access control by HW memory protection.
By requesting the generation of access judgment information, the request task can access the request memory area where the target task is not permitted to access by access control by HW memory protection only at the request timing with the grant attribute. do.

*** Explanation of operation ***
Next, an operation example of generating access determination information of the information processing apparatus 1 according to the present embodiment will be described with reference to the flowchart of FIG.

First, in step S500, during the execution of the request task, the request task requests the judgment information generation unit 17 to generate access judgment information. The request for generating access determination information includes access determination requirements such as an identifier of the target task, a request memory area, a request timing, and an assigned attribute.

Next, in step S510, the determination information generation unit 17 confirms the consistency between the access determination requirement included in the access determination information generation request, the HW access right information during the execution of the request task, and the execution schedule of the target task. do.
Specifically, the determination information generation unit 17 confirms whether the request memory area is smaller than the reference area size included in the hardware determination area information of the HW access right information. Further, the determination information generation unit 17 confirms whether the request timing is included in the execution schedule of the target task.

Next, in step S520, the determination information generation unit 17 determines the consistency between the access determination requirement included in the access determination information generation request, the HW access right information during the execution of the request task, and the execution schedule of the target task. do.
Specifically, in the determination information generation unit 17, the request memory area is smaller than the reference area size included in the hardware determination area information of the HW access right information during the execution of the request task, and the request timing is the execution schedule of the target task. If it is confirmed that it is included in, it is judged to be consistent. Then, the process proceeds to step S530.
On the other hand, in the judgment information generation unit 17, the request memory area must not be smaller than the reference area size included in the hardware judgment area information of the HW access right information during the execution of the request task, or the request timing must be included in the execution schedule of the target task. If so, it is determined that there is no consistency. Then, the process proceeds to step S540.

In step S530, the determination information generation unit 17 generates access determination information. Then, the determination information generation unit 17 stores the generated access determination information in the auxiliary storage device 30.
When the access request is notified from the target task, the access determination unit 15 determines whether or not the access of the target task is permitted based on the generated access determination information.

In step S540, the determination information generation unit 17 does not generate access determination information and executes error processing.

*** Explanation of the effect of the embodiment ***
As described above, in the present embodiment, access determination information is newly generated when the task being executed requests the generation of access determination information. Then, using the generated access determination information, the access determination unit 15 determines whether or not to allow access to the memory area having a size smaller than the reference area size. Therefore, even if there is a change in the usage method of the memory area, access control can be realized without being restricted by the area size while suppressing the CPU load. Further, it is not necessary to specify the access determination information in advance at the time of design, and the degree of freedom in design can be increased.

Although the embodiments have been described above, the two embodiments may be combined and implemented.
Alternatively, one of these two embodiments may be partially implemented.
Alternatively, these two embodiments may be partially combined and implemented.
It should be noted that the present invention is not limited to these embodiments, and various changes can be made as needed.

1 information processing device, 10 processor, 11 communication task, 12 general task, 13 access control setting unit, 14 task control unit, 15 access judgment unit, 16 access control unit, 17 judgment information generation unit, 20 memory, 30 auxiliary storage device , 40 communication I / F, 50 access control hardware.

Claims

Access control hardware, which is hardware that determines whether or not to allow access to a memory area, is a unit of the reference area size, which is the size of the memory area that is the standard for determining whether or not to allow access.
Hardware judgment area information indicating a memory area having a size n (n is an integer of 1 or more) times the reference area size as a hardware judgment area is set in the access control hardware, and the access control hardware is described. An access control setting unit that determines whether or not to allow access to the hardware determination area,
An information processing device including an access determination unit that determines whether or not to allow access to a memory area having a size smaller than the reference area size included in the hardware determination area.
The access control setting unit
Hardware judgment area information indicating a hardware judgment area for each timing for a plurality of timings is set in the access control hardware, and access to the hardware judgment area corresponding to the access control hardware is permitted or denied for each timing. The information processing apparatus according to claim 1.
The information processing device further
An identifier of a task for which the access determination unit determines access permission, a memory area for which the task requests the access determination unit to determine access permission, and a determination for access permission for the task to the access determination unit. It has a determination information generation unit that generates access determination information used for determining access permission / rejection of the access determination unit based on the execution timing of the task and the access attribute given to the task.
The access determination unit
The information processing device according to claim 1, wherein the access determination information is used to determine whether or not to allow access to a memory area having a size smaller than the reference area size.
The determination information generation unit
The information processing device according to claim 3, wherein the access determination information is generated when the execution schedule of the task is confirmed and the execution timing of the task matches the execution schedule.
The access control hardware
The information processing device according to claim 1, which is an MPU (Memory Protection Unit).
A computer having access control hardware, which is hardware for determining whether or not to allow access to a memory area, is a unit of the reference area size, which is the size of the memory area that is the standard for determining whether or not to allow access. Hardware judgment area information indicating a memory area having a size n (n is an integer of 1 or more) times as a hardware judgment area is set in the access control hardware, and the access control hardware is sent to the hardware judgment area. Let's judge the access permission of
An information processing method in which the computer determines whether or not to allow access to a memory area having a size smaller than the reference area size included in the hardware determination area.
A computer that has access control hardware, which is hardware that determines whether or not to allow access to a memory area, in units of the reference area size, which is the size of the memory area that is the standard for determining whether or not to allow access.
Hardware judgment area information indicating a memory area having a size n (n is an integer of 1 or more) times the reference area size as a hardware judgment area is set in the access control hardware, and the access control hardware is described. Access control setting processing that determines whether or not to allow access to the hardware determination area,
An information processing program that executes an access determination process for determining whether or not to allow access to a memory area having a size smaller than the reference area size included in the hardware determination area.