WO2021186958A1 - Light-receiving element and control method - Google Patents

Abstract

A light-receiving element (solid state imaging element 11) according to the present disclosure has a pixel array (pixel array unit 21), a first wiring (wiring L1), and a second wiring (wiring L4). The pixel array (pixel array unit 21) has a plurality of light-receiving pixels arranged in a matrix, the plurality of light-receiving pixels including: a light-receiving region (50) that photoelectrically converts incident light to a signal charge; and pairs of first electrodes (P+ semiconductor region 73) and second electrodes (P+ semiconductor region 73) to which are alternatingly applied a voltage that generates, in the light-receiving region, an electric field that time-divides the signal charge and distributes the result to a pair of charge storage electrodes. The first wiring (wiring L1) connects the first electrodes (P+ semiconductor region 73) together in a pair of non-adjacent light-receiving pixels. The second wiring (wiring L4) connects the second electrodes (P+ semiconductor region 73) together in a pair of light-receiving pixels.

Description

Light receiving element and control method

The present disclosure relates to a light receiving element and a control method.

The light receiving element used in the distance measuring system using the indirect ToF (Time of Flight) method includes a pixel array in which a plurality of light receiving pixels are arranged in a matrix. Each light receiving pixel has a light receiving region that photoelectrically converts incident light into a signal charge, and a pair of electrodes that alternately apply a voltage that generates an electric field in the light receiving region that time-divides the signal charge and distributes it to a pair of charge storage electrodes. And. (See, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2011-86904

However, the charge collection efficiency of the light receiving pixel decreases as the miniaturization progresses.

Therefore, in the present disclosure, a light receiving element and a control method capable of increasing the charge collection efficiency are proposed.

According to the present disclosure, a light receiving element is provided. The light receiving element has a pixel array, a first wiring, and a second wiring. The pixel array is a pair of a light receiving region that photoelectrically converts incident light into a signal charge and a pair of voltages that alternately apply a voltage that generates an electric field in the light receiving region that time-divides the signal charge and distributes it to a pair of charge storage electrodes. A plurality of light receiving pixels including the first electrode and the second electrode are arranged in a matrix. The first wiring connects the first electrodes of a pair of non-adjacent light receiving pixels. The second wiring connects the second electrodes of the pair of light receiving pixels to each other.

It is a figure which shows the structural example of the solid-state image sensor which is an example of the light receiving element which concerns on this disclosure. It is a figure which shows the structural example of the pixel which concerns on this disclosure. It is explanatory drawing of the current control method which concerns on this disclosure. It is explanatory drawing of the current control method which concerns on this disclosure. It is explanatory drawing of the voltage application method which concerns on this disclosure. It is explanatory drawing of the voltage application method which concerns on this disclosure. It is explanatory drawing of the voltage application method which concerns on this disclosure. It is a figure which shows the example of the pixel structure which concerns on this disclosure. It is a figure which shows the example of the pixel structure which concerns on this disclosure. It is a figure which shows the example of the pixel structure which concerns on this disclosure. It is a figure which shows the arrangement example of the pixel separation area which concerns on this disclosure. It is a figure which shows the arrangement example of the pixel separation area which concerns on this disclosure. It is a figure which shows the arrangement example of the pixel separation area which concerns on this disclosure. It is explanatory drawing of the pixel drive circuit which concerns on this disclosure. It is explanatory drawing of the pixel drive circuit which concerns on this disclosure. It is explanatory drawing of the pixel drive circuit which concerns on this disclosure. It is explanatory drawing of the pixel drive circuit which concerns on this disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the following embodiments, the same parts are designated by the same reference numerals, so that duplicate description will be omitted.

[1. Configuration example of solid-state image sensor]
The present technology can be applied to, for example, a solid-state image sensor constituting a distance-finding system that measures a distance by an indirect ToF (Time of Flight) method, an image pickup device having such a solid-state image sensor, and the like.

For example, a distance measuring system is an in-vehicle system that is mounted on a vehicle and measures the distance to an object outside the vehicle, or measures the distance to an object such as a user's hand, and the user is based on the measurement result. It can be applied to a system for recognizing gestures. In this case, the result of gesture recognition can be used, for example, for operating a car navigation system.

FIG. 1 is a diagram showing a configuration example of an embodiment of a solid-state image sensor, which is an example of a light receiving element to which the present technology is applied.

The solid-state image sensor 11 shown in FIG. 1 is a back-illuminated CAPD (Current Assisted Photonic Demodulator) sensor, and is provided in an image sensor having a distance measuring function.

The solid-state image sensor 11 has a configuration including a pixel array unit 21 formed on a semiconductor substrate (not shown) and a peripheral circuit unit. The peripheral circuit unit is composed of, for example, a vertical drive unit 22, a column processing unit 23, a horizontal drive unit 24, and a system control unit 25. The peripheral circuit unit may be integrated on the same semiconductor substrate as the pixel array unit 21, or a part or all of the peripheral circuit unit may be formed on a semiconductor substrate different from the pixel array unit 21 so that the pixel array unit 21 may be integrated. It may be integrated with the substrate.

The solid-state image sensor 11 is also provided with a signal processing unit 26 and a data storage unit 27. The signal processing unit 26 and the data storage unit 27 may be mounted on the same substrate as the solid-state image sensor 11, or may be arranged on a substrate different from the solid-state image sensor 11 in the image pickup device. ..

In the pixel array unit 21, light receiving pixels (hereinafter, simply referred to as “pixels”) that generate a signal charge according to the amount of received light and output a signal corresponding to the signal charge are arranged in a row direction and a column direction, that is, a matrix. It has a structure in which it is arranged two-dimensionally. That is, the pixel array unit 21 has a plurality of pixels that perform photoelectric conversion of the incident light and output a signal corresponding to the signal charge obtained as a result.

Here, the row direction means the arrangement direction of the pixels in the pixel row (that is, the horizontal direction), and the column direction means the arrangement direction of the pixels in the pixel row (that is, the vertical direction). That is, the row direction is the horizontal direction in the figure, and the column direction is the vertical direction in the figure.

In the pixel array unit 21, pixel drive lines 28 are wired along the row direction for each pixel row with respect to the matrix-like pixel array, and two vertical signal lines 29 are wired along the column direction in each pixel row. ing. For example, the pixel drive line 28 transmits a drive signal for driving when reading a signal from a pixel. In FIG. 1, the pixel drive line 28 is shown as one wiring, but the wiring is not limited to one. One end of the pixel drive line 28 is connected to the output end corresponding to each line of the vertical drive unit 22.

The vertical drive unit 22 is composed of a shift register, an address decoder, etc., and drives each pixel of the pixel array unit 21 at the same time for all pixels or in line units. That is, the vertical drive unit 22 constitutes a drive unit that controls the operation of each pixel of the pixel array unit 21 together with the system control unit 25 that controls the vertical drive unit 22.

The signal output from each pixel in the pixel row according to the drive control by the vertical drive unit 22 is input to the column processing unit 23 through the vertical signal line 29. The column processing unit 23 performs predetermined signal processing on the signal output from each pixel through the vertical signal line 29, and temporarily holds the pixel signal after the signal processing.

Specifically, the column processing unit 23 performs noise removal processing, AD (Analog to Digital) conversion processing, and the like as signal processing.

The horizontal drive unit 24 is composed of a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel strings of the column processing unit 23. By the selective scanning by the horizontal drive unit 24, the pixel signals processed by the column processing unit 23 for each unit circuit are sequentially output.

The system control unit 25 is composed of a timing generator or the like that generates various timing signals, and the vertical drive unit 22, the column processing unit 23, and the horizontal drive unit 24 are based on the various timing signals generated by the timing generator. Drive control such as.

The signal processing unit 26 has at least an arithmetic processing function, and performs various signal processing such as arithmetic processing based on the pixel signal output from the column processing unit 23. The data storage unit 27 temporarily stores the data required for the signal processing in the signal processing unit 26.

[2. Pixel configuration example]
Next, a configuration example of the pixels provided in the pixel array unit 21 will be described. The pixels provided in the pixel array unit 21 are configured as shown in FIG. 2, for example.

FIG. 2 shows a cross section of one pixel 51 provided in the pixel array unit 21, and the pixel 51 receives light incident on the light receiving region 50 from the outside, particularly infrared light, and performs photoelectric conversion, resulting in the result. A signal corresponding to the obtained signal charge is output.

The pixel 51 has, for example, a silicon substrate, that is, a substrate 61 which is a P-type semiconductor substrate composed of a P-type semiconductor region, and a condensing structure 62 including an on-chip lens 62-1 formed on the substrate 61. There is.

In the drawing of the substrate 61, on the upper surface, that is, the surface of the light receiving region 50 on the side where the light from the outside is incident (hereinafter, also referred to as the incident surface), the light incident from the outside is collected and the light receiving region 50 is collected. A condensing structure 62 is formed so as to be incident inside.

Further, in the pixel 51, an inter-pixel light-shielding portion 63-1 and an inter-pixel light-shielding portion 63-2 for preventing color mixing between adjacent pixels are formed at the end portion of the pixel 51 on the incident surface of the light receiving region 50. Has been done.

Further, on the portion of the light receiving region 50 opposite to the incident surface, wiring for driving a transistor or the like formed in the pixel 51, wiring for reading a signal from the pixel 51, or the like is formed. The wiring layer (not shown) is formed by stacking.

On the surface side of the light receiving region 50 opposite to the incident surface, that is, on the inner portion of the lower surface in the drawing, an oxide film 64, a signal extraction unit 65-1 called a tap (tap), and a signal extraction unit 65-2 is formed.

In this example, an oxide film 64 is formed in the central portion of the pixel 51 in the vicinity of the surface of the light receiving region 50 opposite to the incident surface, and the signal extraction unit 65-1 and the signal extraction are taken out at both ends of the oxide film 64, respectively. Part 65-2 is formed.

Here, the signal extraction unit 65-1 includes an N-type semiconductor region 71-1 and an N-semiconductor region 72-1 and a P-type semiconductor region P + semiconductor region 73-1 and a P-semiconductor region. It has 74-1 and.

That is, the N + semiconductor region 71-1 is formed at a position adjacent to the right side in the figure of the oxide film 64 on the inner surface portion of the surface of the light receiving region 50 opposite to the incident surface. Further, in the figure of the N + semiconductor region 71-1, the N-semiconductor region 72-1 is formed on the upper side so as to cover (enclose) the N + semiconductor region 71-1.

Further, the P + semiconductor region 73-1 is formed at a position adjacent to the right side in the figure of the N + semiconductor region 71-1 in the surface inner portion of the surface of the light receiving region 50 opposite to the incident surface. Further, in the figure of the P + semiconductor region 73-1, the P-semiconductor region 74-1 is formed on the upper side so as to cover (enclose) the P + semiconductor region 73-1.

Although not shown here, more specifically, when the light receiving region 50 is viewed from the direction perpendicular to the plane of the light receiving region 50, the P + semiconductor region 73-1 and the P-semiconductor region 74-1 are centered. As a result, the N + semiconductor region 71-1 and the N-semiconductor region 72-1 are formed so as to surround the P + semiconductor region 73-1 and the P-semiconductor region 74-1.

Similarly, the signal extraction unit 65-2 includes an N-semiconductor region 72-2 having a lower concentration of donor impurities than the N-type semiconductor region 71-2 and the N + semiconductor region 71-2, and a P-type semiconductor region. It has a P-semiconductor region 73-2 and a P-semiconductor region 74-2 having a lower acceptor impurity concentration than the P + semiconductor region 73-2. Here, the donor impurities include, for example, elements belonging to Group 5 in the periodic table of elements such as phosphorus (P) and arsenic (As) with respect to Si. The acceptor impurities include, for example, elements belonging to Group 3 in the periodic table of elements such as boron (B) with respect to Si.

That is, the N + semiconductor region 71-2 is formed at a position adjacent to the left side in the figure of the oxide film 64 on the inner surface portion of the surface of the light receiving region 50 opposite to the incident surface. Further, in the figure of the N + semiconductor region 71-2, the N-semiconductor region 72-2 is formed on the upper side so as to cover (enclose) the N + semiconductor region 71-2.

Further, the P + semiconductor region 73-2 is formed at a position adjacent to the left side in the figure of the N + semiconductor region 71-2 on the inner surface portion of the surface of the light receiving region 50 opposite to the incident surface. Further, in the figure of the P + semiconductor region 73-2, the P-semiconductor region 74-2 is formed on the upper side so as to cover (enclose) the P + semiconductor region 73-2.

Although not shown here, more specifically, when the light receiving region 50 is viewed from the direction perpendicular to the plane of the light receiving region 50, the P + semiconductor region 73-2 and the P-semiconductor region 74-2 are centered. As a result, the N + semiconductor region 71-2 and the N-semiconductor region 72-2 are formed so as to surround the P + semiconductor region 73-2 and the P-semiconductor region 74-2.

Hereinafter, when it is not necessary to distinguish between the signal extraction unit 65-1 and the signal extraction unit 65-2, they are also simply referred to as the signal extraction unit 65.

Further, hereinafter, when it is not necessary to distinguish N + semiconductor region 71-1 and N + semiconductor region 71-2, they are also simply referred to as N + semiconductor region 71, and N-semiconductor region 72-1 and N-semiconductor region 72-2 are referred to as N-semiconductor region 72-1 and N-semiconductor region 72-2. When it is not necessary to make a distinction, it is also simply referred to as an N-semiconductor region 72.

Further, hereinafter, when it is not necessary to distinguish between the P + semiconductor region 73-1 and the P + semiconductor region 73-2, they are also simply referred to as the P + semiconductor region 73, and the P-semiconductor region 74-1 and the P-semiconductor region 74-2 are referred to. When it is not necessary to make a distinction, it is also simply referred to as a P-semiconductor region 74.

Further, in the light receiving region 50, a separation portion 75-1 for separating these regions is formed by an oxide film or the like between the N + semiconductor region 71-1 and the P + semiconductor region 73-1. Similarly, between the N + semiconductor region 71-2 and the P + semiconductor region 73-2, a separation portion 75-2 for separating these regions is formed by an oxide film or the like. Hereinafter, when it is not necessary to distinguish between the separation unit 75-1 and the separation unit 75-2, the separation unit 75-1 and the separation unit 75-2 will be simply referred to as the separation unit 75.

The N + semiconductor region 71 provided in the light receiving region 50 functions as a detection unit for detecting the amount of light incident on the pixel 51 from the outside, that is, the amount of signal carriers generated by the photoelectric conversion by the light receiving region 50. Further, the P + semiconductor region 73 functions as an injection contact portion for injecting a large number of carrier currents into the light receiving region 50, that is, for directly applying a voltage to the light receiving region 50 to generate an electric field in the light receiving region 50.

In the pixel 51, an FD (Floating Diffusion) portion (hereinafter, also referred to as a FD portion A), which is a floating diffusion region (not shown), is directly connected to the N + semiconductor region 71-1, and further, the FD portion A thereof. Is connected to the vertical signal line 29 via an amplification transistor or the like (not shown).

Similarly, another FD section (hereinafter, also referred to as FD section B) different from the FD section A is directly connected to the N + semiconductor region 71-2, and the FD section B is not shown. It is connected to the vertical signal line 29 via an amplification transistor or the like. Here, the FD unit A and the FD unit B are connected to different vertical signal lines 29.

For example, when trying to measure the distance to an object by the indirect ToF method, infrared light is emitted toward the object from an image pickup device provided with a solid-state image sensor 11. Then, when the infrared light is reflected by the object and returned to the image pickup apparatus as reflected light, the light receiving region 50 of the solid-state image sensor 11 receives the incident reflected light (infrared light) and performs photoelectric conversion. ..

At this time, the vertical drive unit 22 drives the pixel 51 and distributes the signal charge obtained by the photoelectric conversion to the FD unit A and the FD unit B. As described above, the pixel 51 is driven not by the vertical drive unit 22, but by a separately provided drive unit, a horizontal drive unit 24, or the like via a vertical signal line 29 or another control line that is long in the vertical direction. You may do so.

Here, in the general indirect ToF method, a predetermined voltage is alternately applied to the pair of P + semiconductor regions 73 provided in one pixel, and the FD section A and the FD section B are obtained by photoelectric conversion. Distribute the signal charge.

For example, at a certain timing, the vertical drive unit 22 applies a voltage to the two P + semiconductor regions 73 via a contact or the like. Specifically, at a certain timing, the vertical drive unit 22 applies a voltage of 1.5 V to the electrode MIX1 connected to the P + semiconductor region 73-1 to the electrode MIX0 connected to the P + semiconductor region 73-2. Apply a voltage of 0V.

Then, an electric field is generated between the two P + semiconductor regions 73 in the light receiving region 50, and a current flows from the P + semiconductor region 73-1 to the P + semiconductor region 73-2. In this case, the holes in the light receiving region 50 move in the direction of the P + semiconductor region 73-2, and the electrons move in the direction of the P + semiconductor region 73-1.

Therefore, in such a state, infrared light (reflected light) from the outside is incident on the light receiving region 50 via the condensing structure 62, and the infrared light is photoelectrically converted in the light receiving region 50 to be positive with electrons. When converted into a pair of holes, the obtained electrons are guided in the direction of the P + semiconductor region 73-1 by the electric field between the P + semiconductor region 73 and move into the N + semiconductor region 71-1.

In this case, the electrons generated by the photoelectric conversion are used as a signal carrier for detecting the amount of infrared light incident on the pixel 51, that is, the signal charge corresponding to the amount of infrared light received.

As a result, the signal charge corresponding to the electrons moving into the N + semiconductor region 71-1 is accumulated in the N + semiconductor region 71-1, and this signal charge is stored in the FD unit A, the amplification transistor, and the vertical. It is detected by the column processing unit 23 via the signal line 29 or the like.

That is, the accumulated charge of the N + semiconductor region 71-1 is transferred to the FD unit A directly connected to the N + semiconductor region 71-1, and the signal corresponding to the signal charge transferred to the FD unit A is an amplification transistor or vertical. It is read out by the column processing unit 23 via the signal line 29. Then, the read signal is subjected to processing such as AD conversion processing in the column processing unit 23, and the pixel signal obtained as a result is supplied to the signal processing unit 26.

This pixel signal is a signal indicating the amount of signal charge corresponding to the electrons detected by the N + semiconductor region 71-1, that is, the amount of signal charge accumulated in the FD unit A. In other words, the pixel signal can be said to be a signal indicating the amount of infrared light received by the pixel 51.

Further, at the next timing, a voltage is applied to the two P + semiconductor regions 73 by the vertical drive unit 22 via a contact or the like so that an electric field in the direction opposite to the electric field previously generated in the light receiving region 50 is generated. NS. Specifically, a voltage of 1.5 V is applied to the electrode MIX0 connected to the P + semiconductor region 73-2, and a voltage of 0 V is applied to the electrode MIX1 connected to the P + semiconductor region 73-1.

As a result, an electric field is generated between the two P + semiconductor regions 73 in the light receiving region 50, and a current flows from the P + semiconductor region 73-2 to the P + semiconductor region 73-1.

In such a state, infrared light (reflected light) from the outside is incident on the light receiving region 50 via the condensing structure 62, and the infrared light is photoelectrically converted in the light receiving region 50 to convert electrons and holes. When converted into a pair, the obtained electrons are guided in the direction of the P + semiconductor region 73-2 by the electric field between the P + semiconductor region 73 and move into the N + semiconductor region 71-2.

As a result, the signal charge corresponding to the electrons moving into the N + semiconductor region 71-2 is accumulated in the N + semiconductor region 71-2, and this signal charge is stored in the FD unit B, the amplification transistor, and the vertical. It is detected by the column processing unit 23 via the signal line 29 or the like.

That is, the accumulated charge of the N + semiconductor region 71-2 is transferred to the FD unit B directly connected to the N + semiconductor region 71-2, and the signal corresponding to the signal charge transferred to the FD unit B is an amplification transistor or vertical. It is read out by the column processing unit 23 via the signal line 29. Then, the read signal is subjected to processing such as AD conversion processing in the column processing unit 23, and the pixel signal obtained as a result is supplied to the signal processing unit 26.

In the above example, the P + semiconductor regions 73-1 and 73-2 are the first electrode and the second electrode to which a voltage of 1.5 V, which is a predetermined voltage, and a voltage of 0 V are alternately applied. Further, the N + semiconductor regions 71-1 and 71-2 serve as charge storage electrodes that detect and store signal charges generated by photoelectric conversion of light incident on the light receiving region 50.

In this way, in the general indirect ToF method, when pixel signals obtained by photoelectric conversion of the same pixel 51 for different periods are obtained, the signal processing unit 26 reaches the object based on those pixel signals. The distance information indicating the distance of is calculated and output to the subsequent stage.

The method of allocating signal carriers to N + semiconductor regions 71 that are different from each other and calculating the distance information based on the signals corresponding to those signal carriers is called the indirect ToF method.

However, as the miniaturization of the pixel 51 progresses, the distance between the signal extraction unit 65-1 and the signal extraction unit 65-2 is reduced, but the length of the light receiving region 50 in the thickness (depth) direction is reduced. Not done.

Therefore, when the pixel 51 is miniaturized, even if a current is passed from the signal extraction unit 65-1 to the signal extraction unit 65-2, the electric field can be sufficiently expanded to the vicinity of the incident surface of light in the light receiving region 50. Can not. As a result, the pixel 51 cannot efficiently guide the photoelectrically converted signal charge to the signal extraction unit 65-1 in the vicinity of the incident surface of the light in the light receiving region 50, and the charge collection efficiency is lowered.

Therefore, in the present disclosure, charge collection is performed by passing a current through the light receiving region 50 between the adjacent pixels 51 or between the pixels 51 separated by one or more pixels to distribute the signal charge to the FD unit A and the FD unit B. Improve efficiency.

[3. Current control method]
3A and 3B are explanatory views of the current control method according to the present disclosure. In FIGS. 3A and 3B, the direction of the current flowing in the light receiving region 50 of the six pixels 51A to 51F arranged in the same row is indicated by an arrow in the light receiving region 50.

Further, in FIGS. 3A and 3B, of the pair of signal extraction units 65-1 and 65-2 in the pixels 51A to 51F, the one in which a positive voltage is applied to the P + semiconductor region 73 is the rectangular dotted line frame A. The side to which a voltage of 0 V or less is applied is shown as a rectangular dotted line frame B.

The signal extraction unit 65-1 becomes the signal extraction unit A when a positive voltage is applied to the P + semiconductor region 73, and becomes the signal extraction unit B when a voltage of 0 V or less is applied. Similarly, the signal extraction unit 65-2 becomes the signal extraction unit A when a positive voltage is applied to the P + semiconductor region 73, and becomes the signal extraction unit B when a voltage of 0 V or less is applied. Become.

Therefore, here, the signal extraction unit 65 to which the positive voltage is applied to the P + semiconductor region 73 at a certain timing is the signal extraction unit A, and the one to which the voltage of 0 V or less is applied to the P + semiconductor region 73. The signal extraction unit 65 is referred to as a signal extraction unit B.

In the current control method according to the present disclosure, as shown in FIG. 3A, at a certain timing, a current is passed from the signal extraction unit A of the pixel 51B to the signal extraction unit B of the pixel 51C, and the signal extraction unit A of the pixel 51D to the pixel 51E. A current is passed through the signal extraction unit B of.

As a result, the signal charges photoelectrically converted in the two pixels 51B and 51C are guided in the direction opposite to the direction of the arrow shown in the light receiving region 50 in the pixels 51B and 51C, and are transferred to the signal extraction unit A of the pixel 51B. .. Further, the signal charges photoelectrically converted in the two pixels 51D and 51E are guided in the direction opposite to the direction of the arrow shown in the light receiving region 50 in the pixels 51D and 51E, and are transferred to the signal extraction unit A of the pixels 51D.

Then, at the next timing, as shown in FIG. 3B, the signal extraction unit A of the pixel 51A goes to the signal extraction unit B of the pixel 51B, the signal extraction unit A of the pixel 51C to the signal extraction unit B of the pixel 51D, and the pixel 51E. A current is passed from the signal extraction unit A of the above to the signal extraction unit B of the pixel 51F.

As a result, the signal charges photoelectrically converted in the two pixels 51A and 51B are guided in the direction opposite to the direction of the arrow shown in the light receiving region 50 in the pixels 51A and 51B, and are transferred to the signal extraction unit A of the pixels 51A. .. Further, the signal charges photoelectrically converted in the two pixels 51C and 51D are guided in the direction opposite to the direction of the arrow shown in the light receiving region 50 in the pixels 51C and 51D, and are transferred to the signal extraction unit A of the pixels 51C. Further, the signal charges photoelectrically converted in the two pixels 51E and 51F are guided in the direction opposite to the direction of the arrow shown in the light receiving region 50 in the pixels 51E and 51F, and are transferred to the signal extraction unit A of the pixels 51E.

As described above, in the current control method according to the present disclosure, by passing a current over two pixels, the current path is extended as compared with the case where a current is passed from the signal extraction unit A to the signal extraction unit B in one pixel. can do. As a result, in the current control method according to the present disclosure, the electric field due to the current can be expanded to the vicinity of the incident surface of the light in the light receiving region 50.

Therefore, according to the current control method according to the present disclosure, the charge collection efficiency is improved by efficiently transferring the photoelectrically converted signal charge in the vicinity of the incident surface of the light in the light receiving region 50 to the signal extraction unit A by the electric field. Can be improved.

In the current control method according to the present disclosure, it is also possible to improve the charge collection efficiency by passing a current through the light receiving region 50 between pixels separated by one pixel or more and further extending the current path.

[4. Current application method]
Next, an example of the voltage application method according to the present disclosure will be described with reference to FIGS. 4 to 6. 4 to 6 are explanatory views of the voltage application method according to the present disclosure. _{4 to 6 show the time t = t 4p + 0} , t _{4p + 1} , t _{4p + 2} , of the pixels in the m (m is a natural number) column among the plurality of pixels arranged in a matrix in the pixel array unit 21. The voltage application state at t _{4p + 3} (p is a natural number) is shown.

Further, in FIGS. 4 to 6, the P + semiconductor region 73 to which a positive voltage (for example, 1.5V) is applied is indicated by a circle surrounding “+”, and the P + semiconductor region to which 0V or a negative voltage is applied is shown. 73 is indicated by a circle surrounding "-". Further, the P + semiconductor region 73 in the high impedance state is indicated by a circle surrounding “x”.

Further, the two pixels surrounded by the broken line frame shown in FIGS. 4 to 6 are pixels to which the signal charges to be photoelectrically converted are added, in other words, pixels that distribute the signal charges to a pair of charge storage electrodes. The hatched pixels are light-shielding pixels.

As shown in FIG. 4, in the voltage application method according to the present disclosure, a predetermined voltage (for example, 1.5 V or 0 V) is alternately applied between the farthest P + semiconductor region 73 in units of two pixels adjacent to each other in the column direction. It is applied and the photoelectrically converted signal charge is added. Further, the P + semiconductor region 73 other than the P + semiconductor region 73 to which a predetermined voltage is applied is brought into a high impedance state.

Specifically, at time t = t _{4p + 0} , a positive voltage is applied to the P + semiconductor region 73 (an example of the first electrode) circled with “+” in the pixels in the first and third rows that are not adjacent to each other. NS. At this time, a negative voltage is applied to the P + semiconductor region 73 (an example of the second electrode) circled “−” in the pixels in the second and fourth rows that are not adjacent to each other.

After that, at time t = t _{4p + 1} , a negative voltage is applied to the P + semiconductor region 73 circled with “−” in the pixels in the first and third rows that are not adjacent to each other. At this time, a positive voltage is applied to the P + semiconductor region 73 circled with “+” in the pixels in the second and fourth rows that are not adjacent to each other.

After that, at time t = t _{4p + 2} , a positive voltage is applied to the P + semiconductor region 73 circled with “+” in the pixels in the first and third rows that are not adjacent to each other. At this time, a negative voltage is applied to the P + semiconductor region 73 circled with “−” in the pixels in the second and fourth rows that are not adjacent to each other.

After that, at time t = t _{4p + 3} , a negative voltage is applied to the P + semiconductor region 73 circled with “−” in the pixels in the first and third rows that are not adjacent to each other. At this time, a positive voltage is applied to the P + semiconductor region 73 circled with “+” in the pixels in the second and fourth rows that are not adjacent to each other.

_Here, A _i, TapA the _{B i,} when the amount of signal charges generated in each pixel in each exposure period B, Tap a, measured charge quantity _a i of b, _{b i} of each _{pixel, A} i, B _It is expressed as follows using i.
a ₁ = A ₁ + A ₂ ,
a ₂ = A ₂ + A ₃ ,
a ₃ = A ₃ + A ₄ ,
・ ・ ・
b ₁ = B ₁
b ₂ = B ₁ + B ₂ ,
b ₃ = A ₂ + A ₃ ,
・ ・ ・

Then, by writing a = {a _i } and A = {A _i }, the above equation can be expressed as a = XA. Here, X = {X _ij } is a constant matrix of N rows and M columns. Note that N and M are the number of rows and the number of columns of the aperture pixel region in the pixel array, respectively. Therefore, the signal charge amount A photoelectrically converted in each pixel is expressed as ^{A = X -1 a.}

Using this equation, it is possible to obtain an approximate value of the true 1-pixel signal charge amount of TapA from the measured signal charge amount photoelectrically converted by two pixels adjacent to each other in the row direction. For TapB, the approximate value of the true one-pixel signal charge amount can be obtained by the same calculation. The distance can be calculated by indirect ToF by using the signals corresponding to the amount of one pixel signal charge of A and B thus obtained.

Further, in the example shown in FIG. 4, pixels that are not adjacent to each other, for example, the P + semiconductor region 73 (an example of the first electrode) in which “+” in the pixels in the first row and the pixels in the third row are circled, and 2 Positive voltage and negative voltage are alternately applied to the P + semiconductor region 73 (an example of the second electrode) circled with “−” in the pixels in the row and the pixels in the fourth row. As a result, for example, at time t = t _{4p + 0} , a current flows between the pixels in the first and second rows adjacent in the column direction, and a current flows between the pixels in the third and fourth rows adjacent in the column direction. It flows.

In this way, a current path is passed between the two pixels adjacent to each other in the column direction by passing a current between the P + semiconductor region 73 circled with "+" and the P + semiconductor region 73 circled with "-". Can be extended to the vicinity of the light incident surface in the light receiving region 50.

As a result, the signal charge transfer electric field in the vicinity of the light incident surface in the light receiving region 50 is strengthened, so that the signal charge photoelectrically converted in the vicinity of the light incident surface can be efficiently transferred to the charge storage electrode.

In the example shown in FIG. 4, the case of adding the signal charges photoelectrically converted by the two pixels adjacent to each other in the column direction has been described, but the combination of the pixels to which the signal charges are added is not limited to two pixels. No. For example, as shown in FIG. 5, a predetermined voltage can be applied to each P + semiconductor region 73 so as to add a signal charge every 1.5 pixels.

Also in the example shown in FIG. 5, for example, the path of the current can be extended to the vicinity of the light incident surface in the light receiving region 50 as compared with the case where the current is passed between the pair of P + semiconductor regions 73 provided in one pixel. As a result, as in the example shown in FIG. 4, the photoelectrically converted signal charge can be efficiently transferred to the charge storage electrode in the vicinity of the light incident surface.

In FIGS. 4 and 5, the P + semiconductor region 73 to which the positive voltage is applied at the same time is provided to the pixels which are not adjacent to each other, and the P + semiconductor region 73 to which the negative voltage is applied at the same time is provided to the pixels which are not adjacent to each other. Indicated.

However, the P + semiconductor region 73, to which a positive voltage is applied at the same time at a certain timing, may be provided in adjacent pixels. Further, the P + semiconductor region 73 to which the negative voltage is applied at the same time at a certain timing may be provided in the adjacent pixels.

For example, as shown in FIG. 6, at time t = t _{4p + 0} , a negative voltage is applied to the P + semiconductor region 73 circled “-” in the pixels in the second and third rows adjacent to each other in the column direction. .. Here, the P + semiconductor region 73 in which the “−” to which the negative voltage is applied is circled is an example of the second electrode having the shortest arrangement interval between the pixels in the second row and the third row.

At this time, a positive voltage is applied to the P + semiconductor region 73 circled with “+” in the pixels of the 0th car and the 1st row, which are a pair of adjacent pixels other than the pixels of the 2nd and 3rd rows. .. Here, the P + semiconductor region 73 in which the “+” to which the positive voltage is applied is circled is an example of the first electrode having the shortest arrangement interval between the pixels in the 0th row and the 1st row.

As a result, a current flows between the pixels in the first row and the pixels in the second row, and a current flows between the pixels in the third row and the pixels in the fourth row, so that the electric field near the light incident surface in the light receiving region 50 is generated. Since it is strengthened, the transfer efficiency of the signal charge can be improved.

After that, at time t = t _{4p + 1} , a positive voltage is applied to the P + semiconductor region 73 circled with “+” in the pixels in the second and third rows adjacent to each other in the column direction. At this time, a negative voltage is applied to the P + semiconductor region 73 circled with “−” in the pixels of the 0th car and the 1st row, which are a pair of adjacent pixels other than the pixels of the 2nd and 3rd rows. As a result, the electric field near the light incident surface in the light receiving region 50 is strengthened as in the case of time t = t _{4p + 0, so that the signal charge transfer efficiency can be improved.}

After that, at time t = t _{4p + 2} , a positive voltage is applied to the P + semiconductor region 73 circled with “+” in the pixels in the first and second rows adjacent to each other in the column direction. At this time, a negative voltage is applied to the P + semiconductor region 73 circled with “-” in the pixels in the third and fourth rows, which are a pair of adjacent pixels other than the pixels in the first and second rows. ..

As a result, the electric current in the vicinity of the light incident surface in the light receiving region 50 is strengthened by the current flowing between the pixels in the second row and the pixels in the third row, so that the signal charge transfer efficiency can be improved.

After that, at time t = t _{4p + 3} , a negative voltage is applied to the P + semiconductor region 73 circled with “−” in the pixels in the first and second rows adjacent to each other in the column direction. At this time, a positive voltage is applied to the P + semiconductor region 73 circled with “+” in the pixels in the third and fourth rows, which are a pair of adjacent pixels other than the pixels in the first and second rows. .. As a result, the electric field near the light incident surface in the light receiving region 50 is strengthened as in the case of time t = t _{4p + 2, so that the signal charge transfer efficiency can be improved.}

As described above, also by the voltage application method shown in FIG. 6, between the two pixels adjacent to each other in the column direction, between the P + semiconductor region 73 circled with “+” and the P + semiconductor region 73 circled with “-”. By passing a current through the light-receiving region 50, the path of the current can be extended to the vicinity of the light incident surface in the light receiving region 50.

As a result, as in the voltage application method shown in FIG. 4, the signal charge transfer electric field in the vicinity of the light incident surface in the light receiving region 50 is strengthened, so that the signal charge photoelectrically converted in the vicinity of the light incident surface is efficiently charged by the charge storage electrode. Can be transferred to.

Further, in the examples shown in FIGS. 4 to 6, the case of adding the signal charges photoelectrically converted by 2 pixels or 1.5 pixels has been described, but the number of pixels to which the signal charges are added may be more than 2 pixels. Often, a predetermined voltage may be applied to each P + semiconductor region 73 so as to add the signal charges photoelectrically converted by the three pixels and the four pixels. That is, the number of pixels for distributing the photoelectrically converted signal charge to the pair of charge storage electrodes may be three or more.

Further, the pixel array unit 21 may have a configuration in which the number of pixels for distributing the photoelectrically converted signal charge to the pair of charge storage electrodes is different for each region in the pixel array unit 21.

Further, in the examples shown in FIGS. 4 to 6, the pixels for distributing the photoelectrically converted signal charges to the pair of charge storage electrodes are pixels arranged along the column direction, but this is an example. The pixels that distribute the photoelectrically converted signal charges to the pair of charge storage electrodes may be, for example, pixels arranged along the row direction. Further, the pixels that distribute the photoelectrically converted signal charges to the pair of charge storage electrodes may be, for example, pixels arranged along an oblique direction.

[5. Pixel structure example]
Next, a structural example of the pixel according to the present disclosure will be described with reference to FIGS. 7A to 7C. 7A to 7C are diagrams showing an example of a pixel structure according to the present disclosure. In FIGS. 7A and 7B, the direction of the current flowing through the light receiving region 50 of the six pixels 51A to 51F arranged in the same row is indicated by an arrow in the light receiving region 50.

Further, in FIGS. 7A to 7C, of the pair of signal extraction units 65-1 and 65-2 in the pixels 51A to 51F, the one in which a positive voltage is applied to the P + semiconductor region 73 is the rectangular dotted line frame A. The side to which a voltage of 0 V or less is applied is shown as a rectangular dotted line frame B.

The signal extraction unit 65-1 becomes the signal extraction unit A when a positive voltage is applied to the P + semiconductor region 73, and becomes the signal extraction unit B when a voltage of 0 V or less is applied. Similarly, the signal extraction unit 65-2 becomes the signal extraction unit A when a positive voltage is applied to the P + semiconductor region 73, and becomes the signal extraction unit B when a voltage of 0 V or less is applied. Become.

Therefore, here, the signal extraction unit 65 to which the positive voltage is applied to the P + semiconductor region 73 at a certain timing is the signal extraction unit A, and the one to which the voltage of 0 V or less is applied to the P + semiconductor region 73. The signal extraction unit 65 is referred to as a signal extraction unit B.

As shown in FIG. 7A, a pixel separation region 101 that optically and electrically separates adjacent light receiving regions is provided between the light receiving regions 50 in each of the pixels 51A to 51F according to the present disclosure. The pixel separation region 101 is, for example, DTI (Deep Trench Isolation), and is formed by embedding an insulator such as _{SiO 2 in a trench formed at a position between pixels 51A and 51F in the light receiving region 50.} NS.

As a result, each of the pixels 51A to 51F can suppress electrical color mixing due to leakage of the photoelectrically converted signal charge to the adjacent pixels 51A to 51F. Further, each of the pixels 51A to 51F can suppress optical color mixing due to leakage of light incident on the light receiving region 50 to adjacent pixels 51A to 51F.

However, the pixel separation region 101 reaches a halfway portion from the surface of the light receiving region 50 facing the light incident surface toward the light incident surface. As a result, each of the pixels 51A to 51F passes through the region near the incident surface of light in the light receiving region 50 when a current is passed from the signal extraction unit A to the signal extraction unit B over two pixels, for example, in the signal extraction unit B. The signal charge can be transferred from the signal to the signal extraction unit A of the adjacent pixel.

Further, as shown in FIG. 7B, the pixel separation region 102 may have a structure that reaches a halfway portion from the light incident surface in the light receiving region 50 toward the surface facing the light incident surface. Even with such a configuration, the pixel separation region 102 can suppress color mixing due to leakage of light and signal charges to adjacent pixels.

However, according to the pixel separation region, when a current is passed from the signal extraction unit A to the signal extraction unit B over two pixels, the signal extraction unit B passes through a region near the surface of the light receiving region 50 facing the incident surface of light. The signal charge can be transferred from the signal to the signal extraction unit A of the adjacent pixel.

Further, as shown in FIG. 7C, the pixel separation region 103 may have a structure that reaches from the light incident surface in the light receiving region 50 to the surface facing the light incident surface. According to the pixel separation region 103, color mixing can be suppressed more reliably than the pixel separation regions 101 and 102 shown in FIGS. 6A and 6B, but the signal charge can be transferred across the plurality of pixels 51A to 51F. Can not.

However, the pixel separation region 103 is suitable for preventing leakage of signal charges from pixels that transfer signal charges across a plurality of pixels 51A to 51F to other pixels. An example of arranging the pixel separation regions 101 and 103 will be described later with reference to FIGS. 8 to 10.

Note that, in FIGS. 7A and 7B, the voltage application method shown in FIG. 4 is adopted, and a signal is transmitted from the signal extraction unit B of one pixel to the signal extraction unit A of the other pixel among the pair of adjacent pixels. Although the case of transferring the electric charge is shown, the voltage application method shown in FIG. 6 can also be adopted.

When the voltage application method shown in FIG. 6 is adopted, the signal extraction unit B of the pixel 51A shown in FIGS. 7A and 7B becomes the signal extraction unit A, the signal extraction unit A of the pixel 51D becomes the signal extraction unit B, and the pixel 51E The signal extraction unit B becomes the signal extraction unit A. Then, the signal charge is transferred from the signal extraction unit B to the signal extraction unit A of the adjacent pixel.

Therefore, when the voltage application method shown in FIG. 6 is adopted, the direction of current flow indicated by the arrow in the pixels 51A, 51D, 51E shown in FIGS. 7A and 7B is opposite to the direction indicated by the arrow shown in FIGS. 7A and 7B. It becomes the direction.

As described above, even when the voltage application method shown in FIG. 6 is adopted, the signal charge can be transferred across a plurality of pixels 51A to 51F (here, 2 pixels), so that the signal charge transfer efficiency can be improved. Can be improved.

[6. Arrangement example of pixel separation area]
Next, an example of arranging the pixel separation region according to the present disclosure will be described with reference to FIGS. 8 to 10. 8 to 10 are diagrams showing an arrangement example of the pixel separation region according to the present disclosure. In FIGS. 8 to 10, the P + semiconductor region 73 to which a positive voltage is applied at a certain timing is indicated by a circle surrounding “+”, and the P + semiconductor region 73 to which 0 V or a negative voltage is applied is indicated by “−”. It is indicated by a circle surrounding it. Further, the P + semiconductor region 73 in the high impedance state is indicated by a circle surrounding “x”.

Further, the two pixels surrounded by the broken line frame shown in FIGS. 8 to 10 are pixels to which the signal charges to be photoelectrically converted are added, in other words, pixels that distribute the signal charges to a pair of charge storage electrodes. The hatched pixels are light-shielding pixels.

Here, among a plurality of pixels arranged in a matrix, for example, a pixel array that transfers signal charges across pixels for each of two pixels adjacent to each other in the column direction (for example, two pixels surrounded by a broken line frame). Let's take an example.

As shown in FIG. 8, the pixel array unit 21 moves from the surface of the light receiving region 50 facing the light incident surface to the light incident surface between the pixels adjacent to each other in the column direction and between the pixels adjacent to each other in the row direction. A pixel separation region 101 that reaches the middle of the direction is provided.

As a result, the pixel array unit 21 improves the charge collection efficiency by transferring the signal charge between the pixels adjacent to each other in the column direction in which the signal charge is transferred through the region near the incident surface of the light in the light receiving region 50. Can be made to.

As shown in FIG. 9, in the pixel array unit 21A, signal charges are transferred between pixels adjacent in the column direction, but signal charges are not transferred between pixels adjacent in the row direction. Therefore, the pixel array unit 21 separates the pixels that are adjacent to each other in the column direction in which the signal charge is transferred from the surface of the light receiving region 50 facing the light incident surface to the middle portion toward the light incident surface. Region 101 is provided. As a result, the pixel array unit 21 can transfer the signal charge through the region near the incident surface of the light in the light receiving region 50 between the pixels adjacent to each other in the column direction in which the signal charge is transferred.

On the other hand, a pixel separation region 103 that penetrates from the light incident surface in the light receiving region 50 to the surface facing the light incident surface is provided between the pixels adjacent to each other in the row direction in which the signal charge is not transferred. As a result, the pixel array unit 21 can prevent the signal charge from leaking to the pixels adjacent to each other in the row direction in which the signal charge is not transferred.

Further, as shown in FIG. 10, the pixel array unit 21B is provided with no pixel separation region between pixels adjacent to each other in the column direction in which the signal charge is transferred, and is in the row direction in which the signal charge is not transferred. Between the adjacent pixels, a pixel separation region 103 that penetrates from the light incident surface in the light receiving region 50 to the surface facing the light incident surface is provided.

As a result, the pixel array unit 21B prevents the signal charge from leaking to the pixels adjacent in the row direction in which the signal charge is not transferred, and between the pixels adjacent in the column direction in which the signal charge is transferred. The charge transfer efficiency of the

In FIGS. 8 to 10, the voltage application method shown in FIG. 4 is adopted, and a positive voltage and a negative voltage are applied to the two farthest P + semiconductor regions 73 among the pair of pixels adjacent in the column direction. Although the case where the signal charge is transferred is shown, the voltage application method shown in FIG. 6 can also be adopted.

When the voltage application method shown in FIG. 6 is adopted, the P + semiconductor region 73 to which the positive voltage is applied, which is circled “+” in the pixels in the third row shown in FIGS. 8 to 10, is circled “−”. It becomes the P + semiconductor region 73 to which the negative voltage surrounded by is applied. Then, the P + semiconductor region 73 to which the negative voltage circled “−” is applied in the pixels of the fourth row shown in FIGS. 8 to 10 is applied with the positive voltage circled “+”. It becomes the semiconductor region 73.

As a result, the signal charge transfer electric field in the vicinity of the light incident surface in the light receiving region 50 is strengthened as in the voltage application method shown in FIG. 4, so that the signal charge photoelectrically converted in the vicinity of the light incident surface is efficiently charged by the charge storage electrode. Can be transferred to.

[7. Pixel drive circuit]
Next, the pixel drive circuit according to the present disclosure will be described with reference to FIGS. 11 to 14. 11 to 14 are explanatory views of a pixel drive circuit according to the present disclosure. Here, a pixel drive circuit that performs the voltage application method shown in FIG. 4 will be described with reference to FIGS. 11 and 12, and a pixel drive that performs the voltage application method shown in FIG. 6 will be described with reference to FIGS. 13 and 14. The circuit will be described.

In FIGS. 11 and 12, among a plurality of pixels arranged in a matrix in the pixel array units 21 and 21C, m (m is a natural number) column to m + 3 columns, 4n (n is a natural number) row to 4n + 3 Pixels up to the row are selectively shown.

Further, in FIGS. 13 and 14, among a plurality of pixels arranged in a matrix in the pixel array units 21D and 21E, pixels from m column to m + 3 columns, 4n (n is a natural number) to 4n + 4 rows. Is selectively shown.

Further, in FIGS. 11 to 14, the P + semiconductor region 73 to which a positive voltage is applied at a certain timing is indicated by a circle surrounding “+”, and the P + semiconductor region 73 to which 0 V or a negative voltage is applied is indicated by “−”. It is indicated by a circle surrounding it. Further, the P + semiconductor region 73 in the high impedance state is indicated by a circle surrounding “x”.

Further, the MIX signal lines 4n, 4n + 1,4n + 2,4n + 3,4n + 4 described below are for applying a voltage of 1.5V or a voltage of 0V described with reference to FIG. 2 to each P + semiconductor region 73, for example. Voltage supply line.

As shown in FIG. 11, the pixel array unit 21 includes a wiring L1 that connects electrodes (P + semiconductor region 73) to which a positive voltage is applied at a certain timing in a pair of pixels that are not adjacent to each other. The wiring L1 is an example of the first wiring, and the electrode connected by the wiring L1 is an example of the first electrode in a pair of light receiving pixels that are not adjacent to each other and are connected by the first wiring.

Further, the pixel array unit 21 includes wirings L2 and L3 for connecting other electrodes (P + semiconductor region 73) that are brought into a high impedance state when a positive voltage is applied to the electrodes by the wiring L1.

Further, the pixel array unit 21 connects other electrodes (P + semiconductor region 73) in a pair of pixels that are not adjacent to each other to which 0 V or a negative voltage is applied when a positive voltage is applied to the electrodes by wiring L1. The wiring L4 is provided. The wiring L4 is an example of the second wiring, and the electrode connected by the wiring L4 is an example of the second electrode in a pair of light receiving pixels that are not adjacent to each other and are connected by the second wiring.

_{The corresponding buffer amplifiers BA 4n} , BA _{4n + 1} , BA _{4n + 2} , and BA _{4n + 3} are connected to the wirings L1, L2, L3, and L4, respectively. The buffer amplifiers BA _4n , BA _{4n + 1} , BA _{4n + 2} , and BA _{4n + 3} can output, for example, switching between a voltage of 1.5V and a voltage of 0V. _{Switches SW 4n} , SW _{4n + 1} , SW _{4n + 2} , and SW _{4n + 3} are connected between the buffer amplifiers BA _4n , BA _{4n + 1} , BA _{4n + 2} , BA _{4n + 3,} and the pixel array unit 21.

Specifically, the switch SW _4n is connected to the buffer amplifier BA _{4n , the MIX signal line 4n is connected to the switch SW 4n} , and the wiring L1 is connected to the MIX signal line 4n. The switch SW _{4n + 1} is connected to the buffer amplifier BA _{4n + 1 , the MIX signal line 4n + 1 is connected to the switch SW 4n + 1} , and the wiring L2 is connected to the MIX signal line 4n + 1.

Further, the switch SW _{4n + 2} is connected to the buffer amplifier BA _{4n + 2 , the MIX signal line 4n + 2 is connected to the switch SW 4n + 2} , and the wiring L3 is connected to the MIX signal line 4n + 2. The switch SW _{4n + 3} is connected to the buffer amplifier BA _{4n + 3 , the MIX signal line 4n + 3 is connected to the switch SW 4n + 3} , and the wiring L4 is connected to the MIX signal line 4n + 3.

The switches SW _4n , SW _{4n + 1} , SW _{4n + 2} , and SW _{4n + 3} are composed of, for example, CMOS (Complementary Metal Oxide Semiconductor) switches provided in the peripheral circuits of the pixel array unit 21. When the switches SW _4n , SW _{4n + 1} , SW _{4n + 2} , and SW _{4n + 3} have a structure in which a sensor board provided with a pixel array unit 21 is laminated on a logic board provided with peripheral circuits, a CMOS switch on the logic board is used. It is composed.

The buffer amplifiers BA _4n , BA _{4n + 1} , BA _{4n + 2} , BA _{4n + 3,} and switches SW _4n , SW _{4n + 1} , SW _{4n + 2} , and SW _{4n + 3} are controlled by, for example, the system control unit 25 and the vertical drive unit 22 (see FIG. 1).

For example, the system control unit 25 and the vertical drive unit 22 _{turn on the switch SW 4n} at a certain timing to output a voltage of 1.5V from the buffer amplifier BA _{4n , turn on the switch SW 4n + 3} , and start from the buffer amplifier BA _{4n + 3.} Output 0V or negative voltage. At this time, the system control unit 25 and the vertical drive unit 22 turn off _{the switch SW 4n + 1} and the switch SW _{4n + 2.}

As a result, the system control unit 25 and the vertical drive unit 22 set the state of the pixel array unit 21 to the state shown in FIG. 11, pass a current between two pixels adjacent to each other in the column direction, and apply an electric field due to the current in the light receiving region 50. The charge collection efficiency can be improved by extending the light to the vicinity of the incident surface.

If the buffer amplifiers BA _4n , BA _{4n + 1} , BA _{4n + 2} , and BA _{4n + 3} are 3-stage buffers that can switch between 1.5V output state, 0V output state, and high impedance state, switches SW _4n , SW _{4n + 1} , and SW _{4n + 2.} , SW _{4n + 3} can be omitted.

In this case, the system control unit 25 and the vertical drive unit 22 set the buffer amplifier BA _4n to the 1.5V output state, the buffer amplifier BA _{4n + 3} to the 0V output state, and the buffer amplifiers BA _{4n + 1} and BA _{4n + 2} at a certain timing, for example. Put it in the impedance state. As a result, the system control unit 25 and the vertical drive unit 22 can change the state of the pixel array unit 21 to the state shown in FIG.

Further, as shown in FIG. 12, the pixel array unit 21C alternately applies a voltage for distributing the signal charge to the pair of charge storage electrodes instead of the _{switches SW 4n} , SW _{4n + 1} , SW _{4n + 2} , and SW _{4n + 3 shown in FIG.} The configuration may include a switch for connecting the pair of first electrodes and the second electrodes to each other.

_{Specifically, instead of the switch SW 4n} shown in FIG. 11, the pixel array unit 21C has switches SWA _{4n, m} , SWA _{4n that connect the first electrode and the buffer amplifier BA 4n} in a pair of light receiving pixels that are not adjacent to each other. _{, M + 2} . The switches SWA _{4n, m} and SWA _{4n, m + 2} are examples of the first switch for connecting the first electrodes to each other.

Further, the pixel array unit 21C includes switches SWB _{4n, m} to SWB _{4n + 2, m} for connecting the electrodes of a pair of light receiving pixels that are not adjacent to each other and the buffer amplifier BA _{4n + 1 , instead of the switch SW 4n + 1} shown in FIG.

Further, the pixel array unit 21C includes switches SWA _{4n + 1, m} to SWA _{4n + 3, m} for connecting the electrodes of a pair of light receiving pixels that are not adjacent to each other and the buffer amplifier BA _{4n + 2 , instead of the switch SW 4n + 2} shown in FIG.

_{Further, instead of the switch SW 4n + 3} shown in FIG. 11, the pixel array unit 21C uses switches SWB _{4n + 1, m} to SWB _{4n + 3, m} for _{connecting the second electrode and the buffer amplifier BA 4n + 3} in a pair of light receiving pixels that are not adjacent to each other. Be prepared. The switches SWB _{4n + 1, m} to SWB _{4n + 3, m} are examples of the second switch for connecting the second electrodes to each other.

In addition, "A" and "B" following the code SW in the code attached to the above switch represent a Tap name (for example, "A" for TapA and "B" for TapB), and "4n" and the like represent. The pixel row number, "m", etc. represent the pixel column number.

Therefore, for example, the switch connected to the TapA of 4n rows and m + 3 columns is the switch SWA _{4n, m + 3} , and the switch connected to the TapB of 4n + 3 rows and m + 3 columns is the switch SWB _{4n + 3, m + 3} .

_{In FIG. 12, the reference numerals are omitted for the switches other than the switches SWA 4n, m + 3} and SWB _{4n + 3, m + 3} provided in the pixels in the m + 3 row, and the switches provided in the pixels in the m + 1 row and the m + 2 row. There is.

Then, the system control unit 25 and the vertical drive unit 22 control, for example, when driving the pixels of the m-row, the switches of the following combinations are turned on / off at the same time.
・ Switch SWA _{4n, m} and switch SWA _{4n + 2, m}
・ Switch SWB _{4n, m} and switch SWB _{4n + 2,m}
・ Switch SWA _{4n + 1, m} and switch SWA _{4n + 3, m}
・ Switch SWB _{4n + 1, m} and switch SWB _{4n + 3, m}

Specifically, as shown in FIG. 12, the system control unit 25 and the vertical drive unit 22 have switches SWA _{4n, m} and SWA _{4n + 2, m connected to the P + semiconductor region 73 circled with “+”. , The switches SWB 4n + 1, m} and SWB _{4n + 3, m} connected to the P + semiconductor region 73 circled “−” are turned on.

At this time, the system control unit 25 and the vertical drive unit 22 are switched switches SWB _{4n, m} , SWA _{4n + 1, m} , SWB _{4n + 2, m} , SWA _{4n + 3, m connected to the P + semiconductor region 73 circled with “x”.} Turn off. Then, the system control unit 25 and the vertical drive unit 22 alternately apply positive voltage and negative voltage to the wiring L1 and the wiring L4.

Further, the system control unit 25 and the vertical drive unit 22 also control the pixels in the m + 1 row to the m + 3 row in the same manner. As a result, the system control unit 25 and the vertical drive unit 22 set the state of the pixel array unit 21C to the state shown in FIG. 12, pass a current between two pixels adjacent to each other in the column direction, and apply an electric field due to the current in the light receiving region 50. The charge collection efficiency can be improved by extending the light to the vicinity of the incident surface.

Further, as shown in FIG. 13, in the pixel array unit 21D, for example, the pixel array unit 21 shown in FIG. 11 is connected to electrodes having the shortest arrangement interval between a pair of vertically adjacent pixels. The configuration is different from.

In the pixel array unit 21D, the electrodes having the shortest arrangement interval between the adjacent pixels of the 4n row and the 4n + 1 row are connected by the wiring L1. The electrodes having the shortest arrangement interval between the adjacent pixels of the 4n + 1 row and the 4n + 2 row are connected by the wiring L2. Electrodes having the shortest arrangement interval between adjacent pixels of 4n + 2 rows and 4n + 3 rows are connected by wiring L3. Electrodes having the shortest arrangement interval between adjacent pixels of 4n + 3 rows and 4n + 4 rows are connected by wiring L4.

In such a configuration, the system control unit 25 and the vertical drive unit 22 are, for example, switches SW _4n , SW _{4n + 2} , SW _{connected to the buffer amplifiers BA 4n} , BA _{4n + 2} , BA _{4n + 4 of 4n line, 4n + 2 line, and 4n + 4 line.} Turn on _{4n + 4.}

At this time, the system control unit 25 and the vertical drive unit 22 turn off the switches SW _{4n + 1} and SW _{4n + 3 connected to the buffer amplifiers BA 4n + 1} and BA _{4n + 3 in the 4n + 1 line and the 4n + 3 line.} Then, the system control unit 25 and the vertical drive unit 22 alternately apply positive voltage and negative voltage to the wiring L1 and the wiring L3.

That is, the system control unit 25 and the vertical drive unit 22 have the arrangement interval between the first electrode having the shortest arrangement interval between adjacent pixels of 4n row and 4n + 1 row and the detached pixels of 4n + 2 row and 4n + 3 row. Positive voltage and negative voltage are alternately applied to the second electrode having the shortest distance. As a result, a current flows between the pixels in the 4n + 1th row and the 4n + 2nd row adjacent in the column direction, and a current flows between the pixels in the 4n + 3rd row and the 4n + 4th row adjacent in the column direction.

In this way, the system control unit 25 and the vertical drive unit 22 set the state of the pixel array unit 21D to the state shown in FIG. 13, pass a current between two pixels adjacent to each other in the column direction, and receive an electric field due to the current in the light receiving region 50. The charge collection efficiency can be improved by extending the light to the vicinity of the incident surface of the light.

Further, as shown in FIG. 14, the pixel array unit 21E has the shortest arrangement interval between a pair of vertically adjacent pixels instead of the _{switches SW 4n} , SW _{4n + 1} , SW _{4n + 2} , and SW _{4n + 3 shown in FIG.} It may be configured to include a switch for connecting the electrodes of the above.

_{Specifically, the pixel array unit 21E is adjacent to the switches SWB 4n-1, m} , SWA _{4n, m} that connect the electrodes having the shortest arrangement interval between the adjacent pixels of the 4n-1 row and the 4n row. _{The switches SWB 4n, m} and SWA _{4n + 1, m} for connecting the electrodes having the shortest arrangement interval between the pixels of the 4n row and the 4n + 1 row are provided.

_{Further, the pixel array unit 21E includes switches SWB 4n + 1, m} , SWA _{4n + 2, m} , and adjacent 4n + 2 rows and 4n + 3 rows, which connect electrodes having the shortest arrangement interval between adjacent pixels of 4n + 1 row and 4n + 2 rows. _{It is provided with switches SWB 4n + 2, m} and SWA _{4n + 3, m} for connecting electrodes having the shortest arrangement interval between pixels. _{Further, the pixel array unit 21E includes switches SWB 4n + 3, m} and SWA _{4n + 4, m} for connecting electrodes having the shortest arrangement interval between adjacent pixels of 4n + 3 rows and 4n + 4 rows.

In addition, "A" and "B" following the code SW in the code attached to the above switch represent a Tap name (for example, "A" for TapA and "B" for TapB), and "4n" and the like represent. The pixel row number, "m", etc. represent the pixel column number. Further, in FIG. 14, the description of the reference numerals is omitted for the switches provided in the pixels of the m + 1 row, the m + 2 row, and the m + 3 row.

Then, the system control unit 25 and the vertical drive unit 22 control, for example, when driving the pixels of the m-row, the switches of the following combinations are turned on / off at the same time.
・ Switch SWB _{4n-1, m} and switch SWA _{4n, m}
・ Switch SWB _{4n, m} and switch SWA _{4n + 1, m}
・ Switch SWB _{4n + 1, m} and switch SWA _{4n + 2, m}
・ Switch SWB _{4n + 2, m} and switch SWA _{4n + 3, m}
・ Switch SWB _{4n + 3, m} and switch SWA _{4n + 4, m}

Specifically, as shown in FIG. 14, the system control unit 25 and the vertical drive unit 22 are switched switches SWB _{4n-1, m} , SWA _{4n, which are connected to the P + semiconductor region 73 circled with “+”.} Turn on _{m , SWB 4n + 3, m} , SWA _{4n + 4, m, and the switches SWB 4n + 1, m} , SWA _{4n + 2, m} connected to the P + semiconductor region 73 circled "-".

At this time, the system control unit 25 and the vertical drive unit 22 are switched switches SWB _{4n, m} , SWA _{4n + 1, m} , SWB _{4n + 2, m} , SWA _{4n + 3, m connected to the P + semiconductor region 73 circled with “x”.} Turn off. Then, the system control unit 25 and the vertical drive unit 22 alternately output positive voltage and negative voltage from _{the 4n line buffer amplifier BA 4n} and the 4n + 2 line buffer amplifier BA _{4n + 2.}

Further, the system control unit 25 and the vertical drive unit 22 also control the pixels in the m + 1 row to the m + 3 row in the same manner. As a result, the system control unit 25 and the vertical drive unit 22 change the state of the pixel array unit 21E to the state shown in FIG. The charge collection efficiency can be improved by passing a current between the pixels of the row) and expanding the electric field due to the current to the vicinity of the incident surface of the light in the light receiving region 50.

In the examples shown in FIGS. 11 to 14, the MIX signal lines 4n, 4n + 1,4n + 2,4n + 3,4n + 4 are arranged in the horizontal (pixel row) direction of the pixel array units 21,21C, 21D, 21E, but vertically. It is also possible to arrange in the (pixel string) direction.

Note that the effects described in this specification are merely examples and are not limited, and other effects may be obtained. Further, in the present specification, the case where the pixel array portion according to the present disclosure is a back-illuminated type has been described as an example, but the pixel array portion according to the present disclosure may be a front-illuminated type.

The present technology can also have the following configurations.
(1)
A light receiving region that photoelectrically converts incident light into a signal charge, and a pair of first electrodes that alternately apply a voltage that generates an electric field that divides the signal charge into a pair of charge storage electrodes and distributes the electric field to the light receiving region. A pixel array in which a plurality of light receiving pixels including the second electrode are arranged in a matrix, and
The first wiring that connects the first electrodes of a pair of non-adjacent light receiving pixels,
A light receiving element having a second wiring for connecting the second electrodes of the pair of light receiving pixels.
(2)
A light receiving region that photoelectrically converts incident light into a signal charge, and a pair of first electrodes that alternately apply a voltage that generates an electric field that divides the signal charge into a pair of charge storage electrodes and distributes the electric field to the light receiving region. A pixel array in which a plurality of light receiving pixels including the second electrode are arranged in a matrix, and
A light receiving element having a control unit for applying the voltage to the first electrode and the second electrode to cause a current to flow in the light receiving region between adjacent light receiving pixels or between light receiving pixels separated by one pixel or more.
(3)
The first switch that connects the first electrodes to each other,
A second switch for connecting the second electrodes to each other is provided.
The control unit
The first electrodes of a pair of non-adjacent light receiving pixels are connected to each other by the first switch, the second electrodes of the pair of light receiving pixels are connected to each other by the second switch, and the first electrode and the second electrode are connected to each other. The light receiving element according to (2) above, wherein the voltages are alternately applied to the electrodes.
(4)
The control unit
The voltage is applied to the first electrode having the shortest arrangement interval between a pair of adjacent light receiving pixels and the second electrode having the shortest arrangement interval between a pair of adjacent light receiving pixels other than the pair of light receiving pixels. The light receiving element according to (2) above.
(5)
The first switch that connects the first electrodes to each other,
A second switch for connecting the second electrodes to each other is provided.
The control unit
The first electrodes having the shortest arrangement interval between a pair of adjacent light receiving pixels are connected to each other by the first switch, and the arrangement interval between a pair of adjacent light receiving pixels other than the pair of light receiving pixels is the shortest. The light receiving element according to (2), wherein the second electrodes are connected to each other by the second switch, and the voltage is alternately applied to the first electrode and the second electrode.
(6)
The light receiving element according to any one of (1) to (5), wherein the number of light receiving pixels for distributing the signal charge to the pair of charge storage electrodes is different for each region in the pixel array.
(7)
The light receiving pixel that distributes the signal charge to the pair of charge storage electrodes is
The light receiving element according to any one of (1) to (6) above, which is a light receiving pixel arranged along a column direction among the light receiving pixels arranged in a matrix.
(8)
The light receiving pixel that distributes the signal charge to the pair of charge storage electrodes is
The light receiving element according to any one of (1) to (6) above, which is a light receiving pixel arranged along the row direction among the light receiving pixels arranged in a matrix.
(9)
The light receiving pixel that distributes the signal charge to the pair of charge storage electrodes is
The light receiving element according to any one of (1) to (6) above, which is a light receiving pixel arranged along an oblique direction among the light receiving pixels arranged in a matrix.
(10)
The light receiving element according to any one of (1) to (9) above, which is provided between the light receiving regions and has a pixel separation region that optically and electrically separates the adjacent light receiving regions.
(11)
The pixel separation area is
The light receiving element according to (10) above, which reaches a halfway portion toward the incident surface from a surface facing the incident surface of light in the light receiving region.
(12)
The pixel separation area is
The light receiving element according to (10) above, which reaches a halfway portion from the incident surface of light in the light receiving region toward the surface facing the incident surface.
(13)
The pixel separation area is
The light receiving element according to (11) or (12), which is provided along a direction orthogonal to the arrangement direction of light receiving pixels that distributes the signal charge to the pair of charge storage electrodes.
(14)
The pixel separation area is
The light receiving light according to (10), which is provided along the arrangement direction of light receiving pixels that reach from the incident surface of light in the light receiving region to the surface facing the incident surface and distribute the signal charge to the pair of charge storage electrodes. element.
(15)
A light receiving region that photoelectrically converts incident light into a signal charge, and a pair of first electrodes that alternately apply a voltage that generates an electric field that divides the signal charge into a pair of charge storage electrodes and distributes the electric field to the light receiving region. This is a method for controlling a pixel array in which a plurality of light receiving pixels including a second electrode are arranged in a matrix.
A control method comprising applying the voltage to the first electrode and the second electrode to cause a current to flow in the light receiving region between adjacent light receiving pixels or between light receiving pixels separated by one pixel or more.

11 solid-state image sensor, 21 pixel array unit, 22 vertical drive unit, 51 pixels, 61 substrate, 62 condensing structure, 71-1, 71-2, 71 N + semiconductor region, 73-1, 73-2, 73 P + semiconductor region

Claims (15)

1. A light receiving region that photoelectrically converts incident light into a signal charge, and a pair of first electrodes that alternately apply a voltage that generates an electric field that divides the signal charge into a pair of charge storage electrodes and distributes the electric field to the light receiving region. A pixel array in which a plurality of light receiving pixels including the second electrode are arranged in a matrix, and
   The first wiring that connects the first electrodes of a pair of non-adjacent light receiving pixels,
   A light receiving element having a second wiring for connecting the second electrodes of the pair of light receiving pixels.
2. A light receiving region that photoelectrically converts incident light into a signal charge, and a pair of first electrodes that alternately apply a voltage that generates an electric field that divides the signal charge into a pair of charge storage electrodes and distributes the electric field to the light receiving region. A pixel array in which a plurality of light receiving pixels including the second electrode are arranged in a matrix, and
   A light receiving element having a control unit for applying the voltage to the first electrode and the second electrode to cause a current to flow in the light receiving region between adjacent light receiving pixels or between light receiving pixels separated by one pixel or more.
3. The first switch that connects the first electrodes to each other,
   A second switch for connecting the second electrodes to each other is provided.
   The control unit
   The first electrodes of a pair of non-adjacent light receiving pixels are connected to each other by the first switch, the second electrodes of the pair of light receiving pixels are connected to each other by the second switch, and the first electrode and the second electrode are connected to each other. The light receiving element according to claim 2, wherein the voltages are alternately applied to the electrodes.
4. The control unit
   The voltage is applied to the first electrode having the shortest arrangement interval between a pair of adjacent light receiving pixels and the second electrode having the shortest arrangement interval between a pair of adjacent light receiving pixels other than the pair of light receiving pixels. The light receiving element according to claim 2, wherein the light receiving elements are alternately applied.
5. The first switch that connects the first electrodes to each other,
   A second switch for connecting the second electrodes to each other is provided.
   The control unit
   The first electrodes having the shortest arrangement interval between a pair of adjacent light receiving pixels are connected to each other by the first switch, and the arrangement interval between a pair of adjacent light receiving pixels other than the pair of light receiving pixels is the shortest. The light receiving element according to claim 2, wherein the second electrodes are connected to each other by the second switch, and the voltage is alternately applied to the first electrode and the second electrode.
6. The light receiving element according to claim 1, wherein the number of light receiving pixels for distributing the signal charge to the pair of charge storage electrodes is different for each region in the pixel array.
7. The light receiving pixel that distributes the signal charge to the pair of charge storage electrodes is
   The light receiving element according to claim 1, which is a light receiving pixel arranged along the column direction among the light receiving pixels arranged in a matrix.
8. The light receiving pixel that distributes the signal charge to the pair of charge storage electrodes is
   The light receiving element according to claim 1, which is a light receiving pixel arranged along the row direction among the light receiving pixels arranged in a matrix.
9. The light receiving pixel that distributes the signal charge to the pair of charge storage electrodes is
   The light receiving element according to claim 1, which is a light receiving pixel arranged along an oblique direction among the light receiving pixels arranged in a matrix.
10. The light receiving element according to claim 1, which is provided between the light receiving regions and has a pixel separation region that optically and electrically separates the adjacent light receiving regions.
11. The pixel separation area is
    The light receiving element according to claim 10, wherein the light receiving element reaches a halfway portion toward the incident surface from a surface facing the incident surface of light in the light receiving region.
12. The pixel separation area is
    The light receiving element according to claim 10, wherein the light receiving surface reaches a halfway portion from the incident surface of light in the light receiving region toward the surface facing the incident surface.
13. The pixel separation area is
    The light receiving element according to claim 11, which is provided along a direction orthogonal to the arrangement direction of the light receiving pixels that distribute the signal charge to the pair of charge storage electrodes.
14. The pixel separation area is
    The light receiving element according to claim 10, which is provided along the arrangement direction of light receiving pixels that reach from the incident surface of light in the light receiving region to the surface facing the incident surface and distribute the signal charge to the pair of charge storage electrodes. ..
15. A light receiving region that photoelectrically converts incident light into a signal charge, and a pair of first electrodes that alternately apply a voltage that generates an electric field that divides the signal charge into a pair of charge storage electrodes and distributes the electric field to the light receiving region. This is a method for controlling a pixel array in which a plurality of light receiving pixels including a second electrode are arranged in a matrix.
    A control method comprising applying the voltage to the first electrode and the second electrode to cause a current to flow in the light receiving region between adjacent light receiving pixels or between light receiving pixels separated by one pixel or more.

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