WO2021184485A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2021184485A1
WO2021184485A1 PCT/CN2020/086171 CN2020086171W WO2021184485A1 WO 2021184485 A1 WO2021184485 A1 WO 2021184485A1 CN 2020086171 W CN2020086171 W CN 2020086171W WO 2021184485 A1 WO2021184485 A1 WO 2021184485A1
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Prior art keywords
branch
metal layer
wiring
clock signal
array substrate
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PCT/CN2020/086171
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English (en)
French (fr)
Inventor
奚苏萍
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Publication of WO2021184485A1 publication Critical patent/WO2021184485A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate

Definitions

  • This application relates to the field of display technology, in particular to an array substrate and a liquid crystal display panel.
  • Gate Driver On Array is to use the Array process in the existing thin film transistor liquid crystal display to fabricate the Gate row scan driving signal circuit on the array substrate to realize the gate progressive scan driving method.
  • the left GOA and the right GOA drive the display panel at the same time.
  • the display specifications of the panel become higher and higher, and the demand for chip voltage becomes larger and larger, which will cause the signal in the GOA to appear large current.
  • Panel heating affects the characteristics of thin film transistors.
  • the usual method is to set each signal (CK or STV or LC) is connected in series with resistors to effectively reduce the large current of the signal, but the resistance of different signal lines will increase the cost of EE.
  • the purpose of the embodiments of the present application is to provide an array substrate and a liquid crystal display panel, which have the beneficial effects of effectively reducing the current of the clock signal and saving costs.
  • an array substrate including:
  • a substrate having a display area and a non-display area
  • a plurality of GOA driving units which are arranged in the non-display area
  • each of the clock signal line structures includes an input trunk line for accessing an external clock signal, and a plurality of branches set to different preset impedances Wiring and the output trunk wiring used to output the clock signal to the corresponding GOA drive unit, and the input trunk wiring and the output trunk wiring
  • the output trunk line is connected to adjust the current value of the corresponding clock signal.
  • the input main wiring and the output main wiring are connected by selectively connecting one or more of the multiple branch wirings, thereby adjusting the current value of the corresponding clock signal;
  • the resistance of the clock signal line junction is set to a value according to requirements, which is convenient to reduce the current value of the clock signal, and can save costs.
  • the multiple branch wirings are ITO wirings.
  • the widths of the multiple branch traces are the same and the lengths are sequentially reduced.
  • the lengths of the multiple branch traces are the same and the widths are sequentially reduced.
  • the lengths and widths of the multiple branch traces are different.
  • a first metal layer, a first insulating layer, and a second metal layer are sequentially provided on the substrate;
  • the first metal layer is formed with the input main wiring, a plurality of branch connection wirings, and the output main wiring, and the second metal layer is formed with a first connection metal block;
  • the first metal layer is electrically connected to the first connecting metal block through a plurality of first via holes opened on the first insulating layer, and the first connecting metal block is connected to the plurality of branches.
  • One of the lines is connected, and the multiple branch connection lines are connected to the multiple branch lines in a one-to-one correspondence.
  • a second insulating layer is further provided on the second metal layer, and a third metal layer is provided on the second insulating layer;
  • the third metal layer forms the plurality of branch wirings, one end of each branch wiring is electrically connected to the output main wiring, and the other end of each branch wiring is arranged A plurality of second via holes on the second insulating layer are electrically connected to the corresponding branch connection wires.
  • a laser area is formed on the second metal layer for performing a laser operation on the laser area so that the first connecting metal block is connected to a required branch. Electric connection.
  • a second connecting metal block is further formed on the second metal layer, and the plurality of branch wirings respectively pass through third via holes opened on the second insulating layer It is electrically connected to the second connecting metal block, and the second connecting metal block is electrically connected to the output main wiring through a fourth via hole opened on the first insulating layer.
  • the present application provides a liquid crystal display panel, which includes an array substrate, and the array substrate includes:
  • a substrate having a display area and a non-display area
  • a plurality of GOA driving units which are arranged in the non-display area
  • a plurality of clock signal line structures which are arranged in the non-display area, and each of the clock signal line structures includes an input trunk line for accessing an external clock signal, and a plurality of branches set to different preset impedances Wiring and the output trunk wiring used to output the clock signal to the corresponding GOA drive unit, and the input trunk wiring and the output trunk wiring
  • the output trunk line is connected to adjust the current value of the corresponding clock signal.
  • the multiple branch wirings are ITO wirings.
  • the widths of the multiple branch traces are the same and the lengths are sequentially reduced.
  • the lengths of the multiple branch wirings are the same and the widths are sequentially reduced.
  • the lengths and widths of the multiple branch wires are different.
  • a first metal layer, a first insulating layer, and a second metal layer are sequentially provided on the substrate;
  • the first metal layer is formed with the input main wiring, a plurality of branch connection wirings, and the output main wiring, and the second metal layer is formed with a first connection metal block;
  • the first metal layer is electrically connected to the first connecting metal block through a plurality of first via holes opened on the first insulating layer, and the first connecting metal block is connected to the plurality of branches.
  • One of the lines is connected, and the multiple branch connection lines are connected to the multiple branch lines in a one-to-one correspondence.
  • a second insulating layer is further provided on the second metal layer, and a third metal layer is provided on the second insulating layer;
  • the third metal layer forms the plurality of branch wirings, one end of each branch wiring is electrically connected to the output main wiring, and the other end of each branch wiring is arranged A plurality of second via holes on the second insulating layer are electrically connected to the corresponding branch connection wires.
  • a laser area is formed on the second metal layer for performing a laser operation on the laser area so that the first connecting metal block is connected to a required branch. Wire electrical connection.
  • a second connecting metal block is further formed on the second metal layer, and the plurality of branch wirings respectively pass through the third vias opened on the second insulating layer.
  • the hole is electrically connected to the second connecting metal block, and the second connecting metal block is electrically connected to the output main wiring through a fourth via hole opened on the first insulating layer.
  • a clock signal line structure is provided in the non-display area, and each clock signal line structure includes an input trunk line for accessing an external clock signal, and a plurality of clock signal line structures are set to different presets.
  • Set impedance branch wiring and output trunk wiring for outputting the clock signal to the corresponding GOA drive unit, and route the input trunk by selectively wiring one or more of the multiple branch wirings
  • the wiring and the output main wiring are connected to adjust the current value of the corresponding clock signal; thus, the resistance of the clock signal wiring junction is set according to requirements, which is convenient for reducing the current value of the clock signal and can save costs.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of another partial structure of an array substrate provided by an embodiment of the application.
  • FIG. 4 is a schematic cross-sectional structure diagram of an array substrate provided by an embodiment of the application.
  • orientation or positional relationship indicated by the terms “inner” and “outer” are based on the orientation or positional relationship shown in the drawings, or are usually placed when the application product is used.
  • the orientation or positional relationship is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the application.
  • first”, “second”, etc. are only used for distinguishing description, and cannot be understood as indicating or implying relative importance.
  • connection should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection.
  • the connection can also be indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • FIG. 1 is a schematic structural diagram of an array substrate in an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of another partial structure of an array substrate provided by an embodiment of the application.
  • the array substrate includes a substrate 10, a plurality of GOA driving units 40, and a plurality of clock signal line structures 30.
  • the substrate 10 is a glass substrate.
  • the substrate 10 has a display area 11 and a non-display area 12; the display area 11 is provided with a plurality of pixel units 20 distributed in an array, and the GOA driving unit 40 is disposed in the non-display area 12 and is used to drive the plurality of pixel units 20 respectively .
  • a plurality of clock signal line structures 30 are arranged in the non-display area 12, and each of the clock signal line structures 30 includes an input trunk line 31 for accessing external clock signals, and a plurality of different preset impedances.
  • the main wiring 31 and the output main wiring 34 are connected to adjust the current value of the corresponding clock signal.
  • the input main wiring and the output main wiring are connected by selectively connecting one or more of the multiple branch wirings, thereby adjusting the current value of the corresponding clock signal;
  • the resistance of the clock signal line junction is set to a value according to requirements, which is convenient to reduce the current value of the clock signal, and can save costs.
  • the substrate 10 is provided with a first metal layer 300, a first insulating layer 50, a second metal layer 80, a second insulating layer 60 and a third metal layer 70.
  • the first metal layer 300 is disposed on the substrate 10, and the first insulating layer 50 is disposed on the first metal layer 300.
  • the second insulating layer 60 is disposed on the second metal layer.
  • the third metal layer 70 is disposed on the second insulating layer.
  • the third metal layer 70 is an ITO metal layer.
  • the third metal layer 70 is formed with the plurality of branch wiring lines 71.
  • the multiple branch traces 71 correspond to ITO traces.
  • the first metal layer 300 is formed with the input main wiring 31, a plurality of branch connection wirings 311, and the output main wiring 32, and the second metal layer 80 is formed with a first connection metal block 81
  • the first metal layer 300 is electrically connected to the first connecting metal block 81 through a plurality of first via holes 101 opened on the first insulating layer 50.
  • the first connecting metal block 81 is connected to one of the plurality of branch connection traces 311 through the first via 101, and the plurality of branch connection traces 311 are connected to the plurality of branch traces 71.
  • the first insulating layer 50 and the second insulating layer 60 are both silicon nitride or silicon dioxide layers.
  • each branch wiring 71 is electrically connected to the output main wiring 31, and the other end of each branch wiring 71 is disposed on the second insulation
  • the plurality of second via holes 102 on the layer 60 are electrically connected to the corresponding branch connection traces.
  • the widths of the multiple branch wires 71 are the same and the lengths are sequentially reduced, so that the resistances of the multiple branch wires 71 are sequentially reduced.
  • the lengths of the multiple branch traces 71 are the same and the widths are sequentially reduced, so that the resistances of the multiple branch traces 71 are sequentially increased.
  • the lengths and widths of the multiple branch traces 71 are not the same. Through the comprehensive configuration of the width and length, the resistances of the multiple branch traces 71 are sequentially reduced or increased sequentially. .
  • the number of branch wires 71 is 8, and the resistances are 100 ohms, 200 ohms, 300 ohms, 400 ohms, 500 ohms, 600 ohms, 700 ohms, and 800 ohms in order.
  • a laser area is formed on the second metal layer 80 for performing a laser operation on the laser area so that the first connecting metal block 81 is connected to the required branch line 311 Electric connection.
  • the 100-ohm branch connection trace is connected to the first connection metal block 81 through the laser carving connection structure 201.
  • the laser engraving connection structure 201 is disconnected, and the corresponding one of the branch connection wires 311 is connected to the first connecting metal block 81 through the laser engraving structure 202.
  • a second connecting metal block 82 is further formed on the second metal layer 80, and the plurality of branch traces 311 respectively pass through the third via holes 103 opened on the second insulating layer 60. It is electrically connected to the second connecting metal block 82, and the second connecting metal block 82 is electrically connected to the output main wiring 34 through a fourth via 104 opened on the first insulating layer 50.
  • An embodiment of the present application also provides a liquid crystal display panel, which includes the array substrate in any of the foregoing embodiments.
  • a clock signal line structure is provided in the non-display area, and each clock signal line structure includes an input trunk line for accessing an external clock signal, and multiple Set the branch traces with different preset impedances and the output main traces for outputting the clock signal to the corresponding GOA drive unit.
  • the input trunk wiring and the output trunk wiring are connected to adjust the current value of the corresponding clock signal; thus, the resistance of the clock signal wiring junction is set to a value according to requirements, which is convenient to reduce the current value of the clock signal. save costs.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种阵列基板及液晶显示面板，其中阵列基板包括：基板（10），其具有显示区域（11）以及非显示区域（12）；多个GOA驱动单元（40），其设置于非显示区域（12）；多个时钟信号线结构（30），其设置于非显示区域（12），每一时钟信号线结构（30）包括一用于接入外部时钟信号的输入主干走线（31）、多条设置为不同预设阻抗的支路走线（71）以及用于将时钟信号输出给对应的GOA驱动单元（40）的输出主干走线（34），通过选择性地将多条支路走线（71）中的一条或多条来将输入主干走线（31）以及输出主干走线（34）接通，从而调整对应时钟信号的电流值。

Description

阵列基板及液晶显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及液晶显示面板。
 背景技术
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器中的Array制程将Gate行扫描驱动信号电路制作在阵列基板上，实现对Gate逐行扫描的驱动方式。
对于GOA产品，通常为双驱产品，即左边GOA和右边GOA同时驱动显示面板。随着面板尺寸越来越大，分辨率越来越高，面板显示规格越来越高，芯片电压的需求越来越大，会造成GOA 中的讯号出现大电流，长时间大电流，会造成面板发热，影响薄膜晶体管的特性，为改善这一现象，通常的做法是在X-board或C-board处每个讯号(CK or STV or LC)上串联电阻，从而有效降低讯号的大电流，但是不同的讯号线挂的电阻会增加EE的成本。
 技术问题
本申请实施例的目的在于提供一种阵列基板及液晶显示面板，具有有效降低时钟信号的电流以及节约成本的有益效果。
 技术解决方案
第一方面，本申请实施例提供了一种阵列基板，包括：
基板，其具有显示区域以及非显示区域；
多个GOA驱动单元，其设置于所述非显示区域；
多个时钟信号线结构，其设置于所述非显示区域，每一所述时钟信号线结构包括一用于接入外部时钟信号的输入主干走线、多条设置为不同预设阻抗的支路走线以及用于将时钟信号输出给对应的GOA驱动单元的输出主干走线，通过选择性地将该多条支路走线中的一条或多条来将所述输入主干走线以及所述输出主干走线接通，从而调整对应时钟信号的电流值。
本申请实施例通过选择性地将该多条支路走线中的一条或多条来将所述输入主干走线以及所述输出主干走线接通，从而调整对应时钟信号的电流值；从而使得该时钟信号线结的电阻为根据需求的设置值，便于降低时钟信号的电流值，可以节约成本。
在本申请所述的阵列基板中，所述多条支路走线为ITO走线。
在本申请所述的阵列基板中，所述多条支路走线的宽度相同且长度依次减小。
在本申请所述的阵列基板中，所述多条支路走线的长度相同且宽度依次减小。
在本申请所述的阵列基板中，所述多条支路走线的长度以及宽度均不相同。
在本申请所述的阵列基板中，所述基板上依次设置有第一金属层、第一绝缘层以及第二金属层；
所述第一金属层上形成有所述输入主干走线、多条支路连接走线以及输出主干走线，所述第二金属层上形成有第一连接金属块；
所述第一金属层通过开设于所述第一绝缘层上的多个第一过孔与所述第一连接金属块电连接，所述第一连接金属块与所述多条支路连接走线中的一条连接，所述多条支路连接走线与所述多条支路走线一一对应地连接。
在本申请所述的阵列基板中，所述第二金属层上还设置有第二绝缘层，所述第二绝缘层上设置有第三金属层；
所述第三金属层形成所述多条支路走线，每一所述支路走线的一端分别与所述输出主干走线电连接，每一所述支路走线的另一端通过设置于所述第二绝缘层上的多个第二过孔与对应所述支路连接走线电连接。
在本申请所述的阵列基板中，所述第二金属层上形成有镭射区，用于在所述镭射区进行镭射操作以使得所述第一连接金属块与所需要的支路连接走线电连接。
在本申请所述的阵列基板中，所述第二金属层上还形成有第二连接金属块，所述多条支路走线分别通过开设于所述第二绝缘层上的第三过孔与所述第二连接金属块电连接，所述第二连接金属块通过开设于所述第一绝缘层上的第四过孔与所述输出主干走线电连接。
第二方面，本申请提供了一种液晶显示面板，其包括阵列基板，所述阵列基板包括：
基板，其具有显示区域以及非显示区域；
多个GOA驱动单元，其设置于所述非显示区域；
多个时钟信号线结构，其设置于所述非显示区域，每一所述时钟信号线结构包括一用于接入外部时钟信号的输入主干走线、多条设置为不同预设阻抗的支路走线以及用于将时钟信号输出给对应的GOA驱动单元的输出主干走线，通过选择性地将该多条支路走线中的一条或多条来将所述输入主干走线以及所述输出主干走线接通，从而调整对应时钟信号的电流值。
在本申请所述的液晶显示面板中，所述多条支路走线为ITO走线。
在本申请所述的液晶显示面板中，所述多条支路走线的宽度相同且长度依次减小。
在本申请所述的液晶显示面板中，所述多条支路走线的长度相同且宽度依次减小。
在本申请所述的液晶显示面板中，所述多条支路走线的长度以及宽度均不相同。
在本申请所述的液晶显示面板中，所述基板上依次设置有第一金属层、第一绝缘层以及第二金属层；
所述第一金属层上形成有所述输入主干走线、多条支路连接走线以及输出主干走线，所述第二金属层上形成有第一连接金属块；
所述第一金属层通过开设于所述第一绝缘层上的多个第一过孔与所述第一连接金属块电连接，所述第一连接金属块与所述多条支路连接走线中的一条连接，所述多条支路连接走线与所述多条支路走线一一对应地连接。
在本申请所述的液晶显示面板中，所述第二金属层上还设置有第二绝缘层，所述第二绝缘层上设置有第三金属层；
所述第三金属层形成所述多条支路走线，每一所述支路走线的一端分别与所述输出主干走线电连接，每一所述支路走线的另一端通过设置于所述第二绝缘层上的多个第二过孔与对应所述支路连接走线电连接。
在本申请所述的液晶显示面板中，所述第二金属层上形成有镭射区，用于在所述镭射区进行镭射操作以使得所述第一连接金属块与所需要的支路连接走线电连接。
在本申请所述的液晶显示面板中，所述第二金属层上还形成有第二连接金属块，所述多条支路走线分别通过开设于所述第二绝缘层上的第三过孔与所述第二连接金属块电连接，所述第二连接金属块通过开设于所述第一绝缘层上的第四过孔与所述输出主干走线电连接。
 有益效果
本申请实施例通过设置个时钟信号线结构，其设置于所述非显示区域，每一所述时钟信号线结构包括一用于接入外部时钟信号的输入主干走线、多条设置为不同预设阻抗的支路走线以及用于将时钟信号输出给对应的GOA驱动单元的输出主干走线，通过选择性地将该多条支路走线中的一条或多条来将所述输入主干走线以及所述输出主干走线接通，从而调整对应时钟信号的电流值；从而使得该时钟信号线结的电阻为根据需求的设置值，便于降低时钟信号的电流值，可以节约成本。
 附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施例提供的阵列基板的结构示意图；
图2为本申请实施例提供的阵列基板的一种局部结构示意图；
图3为本申请实施例提供的阵列基板的另一种局部结构示意图；以及
图4为本申请实施例提供的阵列基板的剖视结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
在本申请的描述中，需要说明的是，术语“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该申请产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
还需要说明的是，除非另有明确的规定和限定，术语“设置”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图1，图2，图3，图1是本申请实施例中的一种阵列基板的结构示意图。图2为本申请实施例提供的阵列基板的一种局部结构示意图。图3为本申请实施例提供的阵列基板的另一种局部结构示意图。结合图1、图2、图3所示，阵列基板包括基板10、多个GOA驱动单元40、多个时钟信号线结构30。
其中，该基板10为玻璃基板。该基板10具有显示区域11以及非显示区域12；显示区域11设置有多个呈阵列分布的像素单元20，该GOA驱动单元40设置于非显示区域12并分别用于驱动该多个像素单元20。多个时钟信号线结构30设置于所述非显示区域12，每一所述时钟信号线结构30包括一用于接入外部时钟信号的输入主干走线31、多条设置为不同预设阻抗的支路走线71以及用于将时钟信号输出给对应的GOA驱动单元40的输出主干走线34，通过选择性地将该多条支路走线71中的一条或多条来将所述输入主干走线31以及所述输出主干走线34接通，从而调整对应时钟信号的电流值。
本申请实施例通过选择性地将该多条支路走线中的一条或多条来将所述输入主干走线以及所述输出主干走线接通，从而调整对应时钟信号的电流值；从而使得该时钟信号线结的电阻为根据需求的设置值，便于降低时钟信号的电流值，可以节约成本。
在一些实施例中，具体地，该基板10上设置有第一金属层300、第一绝缘层50、第二金属层80、第二绝缘层60以及第三金属层70。该第一金属层300设置于该基板10上，该第一绝缘层50设置于该第一金属层300上。该第二绝缘层60设置于该第二金属层上。该第三金属层70设置于该第二绝缘层上。
其中，该第三金属层70为ITO金属层。该第三金属层70形成有该多条支路走线71。多条支路走线71对应为ITO走线。
其中，该第一金属层300上形成有所述输入主干走线31、多条支路连接走线311以及输出主干走线32，所述第二金属层80上形成有第一连接金属块81；所述第一金属层300通过开设于所述第一绝缘层50上的多个第一过孔101与所述第一连接金属块81电连接。具体地，第一连接金属块81通过第一过孔101与所述多条支路连接走线311中的一条连接，多条支路连接走线311与所述多条支路走线71一一对应地连接。
该第一绝缘层50以及该第二绝缘层60均为氮化硅或者二氧化硅层。
在一些实施例中，该每一所述支路走线71的一端分别与所述输出主干走线31电连接，每一所述支路走线71的另一端通过设置于所述第二绝缘层60上的多个第二过孔102与对应所述支路连接走线电连接。
可选地，在一些实施例中，多条支路走线71的宽度相同且长度依次减小，从而使得该多条支路走线71的电阻依次减小。
可选地，在一些实施例中，多条支路走线71的长度相同且宽度依次减小，从而使得该多个支路走线71的电阻依次增大。
可选地，在一些实施例中，多条支路走线71的长度以及宽度均不相同，通过宽度和长度综合配置，使得该多条支路走线71的电阻依次减小或者依次增大。
具体地，该支路走线71的条数为8条，电阻依次为100欧姆、200欧姆、300欧姆、400欧姆、500欧姆、600欧姆、700欧姆以及800欧姆。
请参照图4，其中，在该第二金属层80上形成有镭射区，用于在所述镭射区进行镭射操作以使得所述第一连接金属块81与所需要的支路连接走线311电连接。例如，其中，在默认状态下，该100欧姆的支路连接走线通过镭雕连接结构201与第一连接金属块81连接。当需要调整时，将该将镭雕连接结构201断开，将该支路连接走线311中的对应一条与该第一连接金属块81通过镭雕结构202连接。
在一些实施例中，该第二金属层80上还形成有第二连接金属块82，所述多条支路走线311分别通过开设于所述第二绝缘层60上的第三过孔103与所述第二连接金属块82电连接，所述第二连接金属块82通过开设于所述第一绝缘层50上的第四过孔104与所述输出主干走线34电连接。
本申请实施例还提供了一种液晶显示面板，该液晶显示面板包括上述任意实施例中的阵列基板。
由上可知，本申请实施例通过设置个时钟信号线结构，其设置于所述非显示区域，每一所述时钟信号线结构包括一用于接入外部时钟信号的输入主干走线、多条设置为不同预设阻抗的支路走线以及用于将时钟信号输出给对应的GOA驱动单元的输出主干走线，通过选择性地将该多条支路走线中的一条或多条来将所述输入主干走线以及所述输出主干走线接通，从而调整对应时钟信号的电流值；从而使得该时钟信号线结的电阻为根据需求的设置值，便于降低时钟信号的电流值，可以节约成本。
以上所述仅为本申请的实施例而已，并不用于限制本申请的保护范围，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (18)

  1. 一种阵列基板，其包括：
    基板，其具有显示区域以及非显示区域；
    多个GOA驱动单元，其设置于所述非显示区域；
    多个时钟信号线结构，其设置于所述非显示区域，每一所述时钟信号线结构包括一用于接入外部时钟信号的输入主干走线、多条设置为不同预设阻抗的支路走线以及用于将时钟信号输出给对应的GOA驱动单元的输出主干走线，通过选择性地将该多条支路走线中的一条或多条来将所述输入主干走线以及所述输出主干走线接通，从而调整对应时钟信号的电流值。
  2. 根据权利要求1所述的阵列基板，其中，所述多条支路走线为ITO走线。
  3. 根据权利要求1所述的阵列基板，其中，所述多条支路走线的宽度相同且长度依次减小。
  4. 根据权利要求1所述的阵列基板，其中，所述多条支路走线的长度相同且宽度依次减小。
  5. 根据权利要求1所述的阵列基板，其中，所述多条支路走线的长度以及宽度均不相同。
  6. 根据权利要求1所述的阵列基板，其中，所述基板上依次设置有第一金属层、第一绝缘层以及第二金属层；
    所述第一金属层上形成有所述输入主干走线、多条支路连接走线以及输出主干走线，所述第二金属层上形成有第一连接金属块；
    所述第一金属层通过开设于所述第一绝缘层上的多个第一过孔与所述第一连接金属块电连接，所述第一连接金属块与所述多条支路连接走线中的一条连接，所述多条支路连接走线与所述多条支路走线一一对应地连接。
  7. 根据权利要求6所述的阵列基板，其中，所述第二金属层上还设置有第二绝缘层，所述第二绝缘层上设置有第三金属层；
    所述第三金属层形成所述多条支路走线，每一所述支路走线的一端分别与所述输出主干走线电连接，每一所述支路走线的另一端通过设置于所述第二绝缘层上的多个第二过孔与对应所述支路连接走线电连接。
  8. 根据权利要求6所述的阵列基板，其中，所述第二金属层上形成有镭射区，用于在所述镭射区进行镭射操作以使得所述第一连接金属块与所需要的支路连接走线电连接。
  9. 根据权利要求6所述的阵列基板，其中，所述第二金属层上还形成有第二连接金属块，所述多条支路走线分别通过开设于所述第二绝缘层上的第三过孔与所述第二连接金属块电连接，所述第二连接金属块通过开设于所述第一绝缘层上的第四过孔与所述输出主干走线电连接。
  10. 一种液晶显示面板，其包括阵列基板，所述阵列基板包括：
    基板，其具有显示区域以及非显示区域；
    多个GOA驱动单元，其设置于所述非显示区域；
    多个时钟信号线结构，其设置于所述非显示区域，每一所述时钟信号线结构包括一用于接入外部时钟信号的输入主干走线、多条设置为不同预设阻抗的支路走线以及用于将时钟信号输出给对应的GOA驱动单元的输出主干走线，通过选择性地将该多条支路走线中的一条或多条来将所述输入主干走线以及所述输出主干走线接通，从而调整对应时钟信号的电流值。
  11. 根据权利要求10所述的液晶显示面板，其中，所述多条支路走线为ITO走线。
  12. 根据权利要求10所述的液晶显示面板，其中，所述多条支路走线的宽度相同且长度依次减小。
  13. 根据权利要求10所述的液晶显示面板，其中，所述多条支路走线的长度相同且宽度依次减小。
  14. 根据权利要求10所述的液晶显示面板，其中，所述多条支路走线的长度以及宽度均不相同。
  15. 根据权利要求10所述的液晶显示面板，其中，所述基板上依次设置有第一金属层、第一绝缘层以及第二金属层；
    所述第一金属层上形成有所述输入主干走线、多条支路连接走线以及输出主干走线，所述第二金属层上形成有第一连接金属块；
    所述第一金属层通过开设于所述第一绝缘层上的多个第一过孔与所述第一连接金属块电连接，所述第一连接金属块与所述多条支路连接走线中的一条连接，所述多条支路连接走线与所述多条支路走线一一对应地连接。
  16. 根据权利要求15所述的液晶显示面板，其中，所述第二金属层上还设置有第二绝缘层，所述第二绝缘层上设置有第三金属层；
    所述第三金属层形成所述多条支路走线，每一所述支路走线的一端分别与所述输出主干走线电连接，每一所述支路走线的另一端通过设置于所述第二绝缘层上的多个第二过孔与对应所述支路连接走线电连接。
  17. 根据权利要求15所述的液晶显示面板，其中，所述第二金属层上形成有镭射区，用于在所述镭射区进行镭射操作以使得所述第一连接金属块与所需要的支路连接走线电连接。
  18. 根据权利要求15所述的液晶显示面板，其中，所述第二金属层上还形成有第二连接金属块，所述多条支路走线分别通过开设于所述第二绝缘层上的第三过孔与所述第二连接金属块电连接，所述第二连接金属块通过开设于所述第一绝缘层上的第四过孔与所述输出主干走线电连接。
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