WO2021179342A1 - Circuit d'attaque de grille rapide de tube d'alimentation en gan de haute fiabilité - Google Patents

Circuit d'attaque de grille rapide de tube d'alimentation en gan de haute fiabilité Download PDF

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Publication number
WO2021179342A1
WO2021179342A1 PCT/CN2020/079855 CN2020079855W WO2021179342A1 WO 2021179342 A1 WO2021179342 A1 WO 2021179342A1 CN 2020079855 W CN2020079855 W CN 2020079855W WO 2021179342 A1 WO2021179342 A1 WO 2021179342A1
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Prior art keywords
circuit
output
gate
current
power tube
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PCT/CN2020/079855
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English (en)
Chinese (zh)
Inventor
励晔
黄飞明
赵文遐
贺洁
朱勤为
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无锡硅动力微电子股份有限公司
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Publication of WO2021179342A1 publication Critical patent/WO2021179342A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the invention relates to the field of integrated circuits, in particular to a highly reliable GaN power tube fast gate drive circuit.
  • GaN High Electron Mobility Transistor has high off-state breakdown strength and excellent channel conductivity in the on-state, which is the development trend of high-frequency and high-power density switching power transistors.
  • the breakdown strength of GaN material is 10 times higher than that of Si, which means that compared with Si devices, for a given device size, 10 times the voltage can be applied to GaN devices, due to the specific conduction
  • the resistance Ron is proportional to the length of the drift region of the device required to maintain a given breakdown voltage, so more compact GaN devices have the lowest possible on-resistance.
  • the HEMT electron transfer characteristics of GaN devices have specific on-resistance almost two orders of magnitude lower than that of Si power devices with the same rated voltage. Therefore, GaN devices simultaneously achieve high breakdown voltage and high current levels, that is, high switching frequencies at high power levels.
  • GaN devices themselves also have some shortcomings.
  • the device does not have an avalanche voltage rating, so the gate drive is quite critical.
  • the absolute maximum rated voltage is typically only plus or minus 10V.
  • the gate drive voltage is less than 5V, the dynamic on-resistance performance of the GaN device will deteriorate. .
  • the ultra-fast turn-on speed of GaN devices will lead to poor EMI characteristics.
  • enhancement mode (E-mode) GaN is usually a normally-off device, and its gate turn-on threshold of about 1.5V is also lower than the turn-on threshold of Si devices about 3.5V.
  • the low gate turn-on threshold is easy to use in applications. Misleading. The key point is that whether the expected advantages of low loss, high power density and high reliability can be achieved depends on a gate drive circuit with strong protection characteristics.
  • the purpose of the present invention is to overcome the shortcomings in the prior art and provide a highly reliable GaN power tube fast gate drive circuit, which can improve the EMI performance of the GaN power tube during operation and improve the working reliability.
  • the technical solution adopted in the embodiment of the present invention is:
  • a highly reliable GaN power tube fast gate drive circuit including: drive current adjustment circuit, first MOS switch Q111, turn-off delay circuit, second MOS switch Q113, drive voltage clamp circuit, inverter INV115, Charge pump capacitor C120;
  • the control terminal of the drive current regulating circuit and the input terminal of the inverter INV115 are connected to the input terminal of the gate drive circuit; the input terminal of the gate drive circuit is used to input the control signal On; the output terminal of the inverter INV115 is connected to the first MOS switch The control terminal of Q111 and the input terminal of the turn-off delay circuit; the output terminal of the turn-off delay circuit is connected to the control terminal of the second MOS switch Q113;
  • the driving current regulating circuit outputs two current sources iCp and iDrv, which are respectively connected to node a and node b at both ends of the charge pump capacitor C120; one switch terminal of the first MOS switch Q111 is connected to node a, and the other switch terminal is connected to the reference ground; One switch terminal of the two MOS switch Q113 is connected to node b, and the other switch terminal is connected to the reference ground;
  • One end of the driving voltage clamping circuit is connected to node b, and the other end is connected to the reference ground;
  • the node b is used as the output terminal of the gate drive circuit to output the driving voltage vDrv for driving the GaN power tube.
  • the two current sources iCp and iDrv output by the drive current regulating circuit are controlled by the control signal On; when the control signal On is low, the currents of the two output current sources iCp and iDrv are all zero; when the control signal On is At high level, the output currents of the two current sources iCp and iDrv vary with the drive voltage vDrv output by the gate drive circuit.
  • the input and output of the off-delay circuit are in phase, the output signal Offd of the off-delay circuit is delayed at the rising edge of its input signal off; the output signal of the off-delay circuit is at the falling edge of its input signal off No time delay.
  • the output signal Offd of the off-delay circuit is delayed at the rising edge of the input signal off, and the delay time td is tens of nanoseconds.
  • the driving current adjustment circuit includes: inverter INV1, NMOS transistors N1, N2, PMOS transistors P0, P1, P2, P3, controlled current source IBias1, capacitor C1, resistor Rup, Rdrv;
  • the input terminal of the inverter INV1 and the gate of the PMOS transistor P0 are connected to the input terminal of the drive current regulation circuit; the output terminal of the inverter INV1 is connected to the gate of the NMOS transistor N1, the source of N1 and one end of the capacitor C1 are connected to the reference ground ,
  • the drain of N1 is connected to the other end of the capacitor C1, the gate of the NMOS transistor N2 and the current outflow end of the controlled current source IBias1; the current inflow end of the controlled current source IBias1, the source of the PMOS transistor P1, the source of P0,
  • the source of P2, the source of P3, and one end of the resistor Rup are connected to the power supply voltage terminal; the gate of P1 is connected to the drain of P0, the other end of the resistor Rup, the gate of P2, the gate of P3, and the drain of P1; P1
  • the drain of N2 is connected to the drain of N2; the source of N2 is connected to one
  • the driving voltage clamping circuit is composed of two back-to-back clamping diodes in series; the positive voltage threshold of the driving voltage clamping circuit is set within the safe turn-on voltage range of the GaN power tube driven by the gate driving circuit.
  • the second MOS switch Q113 is composed of two back-to-back NMOS transistors connected in series, and the gates of the two back-to-back NMOS transistors are connected as their control terminals.
  • the first MOS switch Q111 adopts a single NMOS transistor.
  • the advantage of the present invention is that the present invention provides a highly reliable GaN power tube fast gate drive circuit.
  • the opening speed of the GaN power tube is controlled by controlling the rate of change of the driving current, thereby Improve EMI performance; in the turn-on phase of the GaN power tube, precisely control the gate drive voltage of the GaN power tube to improve the reliability of the GaN power tube; in the turn-off phase of the GaN power tube, generate a negative gate drive voltage through the charge pump, which can Quickly turn off the GaN power tube to avoid false triggering and solve the reliability under high-speed switching.
  • Fig. 1 is an electrical schematic diagram of a gate drive circuit according to an embodiment of the present invention.
  • Fig. 2 is a schematic diagram of a driving current adjusting circuit according to an embodiment of the present invention.
  • Fig. 3 is a signal timing diagram of an embodiment of the present invention.
  • the embodiment of the present invention provides a highly reliable GaN power tube fast gate drive circuit (herein referred to as the gate drive circuit), as shown in FIG. 1, including: a drive current adjustment circuit 110, a first MOS switch Q111, and Delay circuit 112, second MOS switch Q113, driving voltage clamping circuit 114, inverter INV115, charge pump capacitor C120;
  • the gate drive circuit including: a drive current adjustment circuit 110, a first MOS switch Q111, and Delay circuit 112, second MOS switch Q113, driving voltage clamping circuit 114, inverter INV115, charge pump capacitor C120;
  • the control terminal of the drive current regulating circuit 110 and the input terminal of the inverter INV115 are connected to the input terminal of the gate drive circuit; the input terminal of the gate drive circuit is used to input the control signal On; the output terminal of the inverter INV115 is connected to the first MOS The control terminal of the switch Q111 and the input terminal of the turn-off delay circuit 112; the output terminal of the turn-off delay circuit 112 is connected to the control terminal of the second MOS switch Q113;
  • the driving current regulating circuit 110 outputs two current sources iCp and iDrv, which are respectively connected to the node a and node b at both ends of the charge pump capacitor C120; one switch terminal of the first MOS switch Q111 is connected to the node a, and the other switch terminal is connected to the reference ground; One switch terminal of the second MOS switch Q113 is connected to node b, and the other switch terminal is connected to the reference ground;
  • One end of the driving voltage clamping circuit 114 is connected to node b, and the other end is connected to the reference ground;
  • Node b is used as the output terminal of the gate drive circuit to output the driving voltage vDrv for driving the GaN power tube;
  • the driving voltage vDrv passes through the driving current adjusting circuit 110, the first MOS switch Q111, the turn-off delay circuit 112, the second MOS switch Q113, the driving voltage clamping circuit 114, the inverter INV115, and the charge pump capacitor. C120 works together;
  • the gate of the GaN power tube Q100 is connected to the driving voltage vDrv output by the gate driving circuit, the drain is connected to the load 101 of the GaN power tube Q100, and the source is connected to the current detection circuit 102 of the GaN power tube Q100;
  • the first MOS switch Q111 adopts a single NMOS tube; the control terminal of the single NMOS tube is its gate;
  • the second MOS switch Q113 is preferably formed by using two back-to-back NMOS transistors in series, and the gates of the two back-to-back NMOS transistors are connected as its control terminal; when the two NMOS transistors of the MOS switch are turned off, the two NMOS transistors are not connected in series. There is a parasitic path.
  • the two diodes shown in Q113 are MOS parasitic diodes; when the gate of the second MOS switch Q113 is low, the two internal NMOS switches are turned off, and both ends of the MOS switch are both positive and negative. Does not constitute a current path;
  • the second MOS switch Q113 using a single NMOS tube is also feasible, but it is not a better solution.
  • the GaN power tube Q100 starts to turn off, when its driving voltage vDrv becomes a negative voltage, the negative voltage will be caused by the parasitic diode in the MOS tube.
  • the limit is around -0.6v;
  • the driving voltage clamping circuit 114 is composed of two back-to-back clamping diodes in series, so the driving voltage clamping circuit 114 can clamp both the positive voltage and the negative voltage, which fully guarantees the reliability of the GaN power tube during switching;
  • the two current sources iCp and iDrv output by the driving current regulating circuit 110 are controlled by the control signal On; when the control signal On is low, the currents of the two output current sources iCp and iDrv are all zero; when the control signal On is high Normally, the output currents of the two current sources iCp and iDrv vary with the drive voltage vDrv output by the gate drive circuit;
  • the first MOS switch Q111 is controlled by the output of the inverter INV115, and the input terminal of the inverter INV115 is connected to the control signal On; when On is low, the output of the inverter INV115 is high, and the first MOS switch Q111 is turned on On; when On is high, the output of the inverter INV115 is low, and the first MOS switch Q111 is turned off;
  • the second MOS switch Q113 is controlled by the off-delay circuit 112.
  • the input and output of the off-delay circuit 112 are in phase.
  • the output signal Offd of the off-delay circuit 112 is delayed at the rising edge of its input signal off, and the delay time td can be tens of nanoseconds;
  • the output signal Offd of the turn-off delay circuit 112 is not delayed at the falling edge of the input signal off;
  • the delay circuit is a relatively mature circuit, and will not be repeated here;
  • the control signal On is at low level.
  • the currents of the two current sources iCp and iDrv output by the driving current regulating circuit 110 are all zero, the first MOS switch Q111 is turned on, and the second MOS switch Q113 is also turned on.
  • the drive voltage vDrv output by the gate drive circuit is zero, and the GaN power tube Q100 is turned off;
  • the inverter INV115 When the control signal On changes from a low level to a high level, the inverter INV115 outputs a low level, the turn-off delay circuit 112 also immediately outputs a low level, the first MOS switch Q111 is immediately turned off, and the second MOS switch Q113 It is also turned off immediately.
  • the two current sources iCp and iDrv output by the drive current regulating circuit 110 respectively charge both ends of the charge pump capacitor C120.
  • the voltages vCp and vDrv at both ends of the charge pump capacitor C120 increase, and the output voltage of the gate drive circuit vDrv starts from zero to increase; when the driving voltage vDrv reaches the turn-on threshold of the GaN power tube Q100, the GaN power tube Q100 is turned on, and the two current sources iCp and iDrv output by the driving current regulating circuit 110 continue to connect to the charge pump capacitor C120.
  • the driving voltage vDrv When the driving voltage vDrv reaches the positive voltage threshold of the driving voltage clamping circuit 114, the voltage vCp and vDrv across the charge pump capacitor C120 continue to increase, and the GaN power tube Q100 is fully turned on; The current of the current source iDrv is absorbed by the driving voltage clamping circuit 114, and the driving voltage vDrv is clamped. Generally, the driving voltage of the GaN power tube is clamped at about 6V, and the voltage vCp of the node a continues to be driven by the current output by the current regulating circuit 110 The source iCp is charged; when the voltage vCp reaches the power supply voltage of the driving current regulating circuit 110, the current of the current source iCp automatically drops to zero.
  • the voltage vCp of the node a at one end of the charge pump capacitor C120 is the power supply voltage of the driving current regulating circuit 110.
  • the voltage vDrv at the node b at the other end of the pump capacitor C120 is about 6V; in this embodiment, when the control signal On changes from a low level to a high level and the GaN power tube Q100 is fully turned on, one end of the charge pump capacitor C120 is required
  • the voltage vCp of node a is higher than the voltage vDrv of node b at the other end;
  • the magnitude of the negative voltage of the driving voltage vDrv depends on the voltage difference across the charge pump capacitor C120 before the control signal On changes from high to low, as well as the capacitance of the charge pump capacitor C120 and the gate junction capacitance of the GaN power tube 100; vDrv
  • the maximum negative voltage of is the negative voltage threshold of the driving voltage clamping circuit 114;
  • the second MOS switch Q113 is also turned on, the driving voltage vDrv is pulled back to the zero level, and the GaN power tube 100 remains in the off state;
  • the driving current adjusting circuit 110 is shown in FIG. 2 and includes: inverter INV1, NMOS transistors N1, N2, PMOS transistors P0, P1, P2, P3, controlled current source IBias1, capacitor C1, resistor Rup, Rdrv;
  • the input terminal of the inverter INV1 and the gate of the PMOS transistor P0 are connected to the input terminal of the drive current regulation circuit; the output terminal of the inverter INV1 is connected to the gate of the NMOS transistor N1, the source of N1 and one end of the capacitor C1 are connected to the reference ground ,
  • the drain of N1 is connected to the other end of the capacitor C1, the gate of the NMOS transistor N2 and the current outflow end of the controlled current source IBias1; the current inflow end of the controlled current source IBias1, the source of the PMOS transistor P1, the source of P0,
  • the source of P2, the source of P3, and one end of the resistor Rup are connected to the power supply voltage terminal; the gate of P1 is connected to the drain of P0, the other end of the resistor Rup, the gate of P2, the gate of P3, and the drain of P1; P1
  • the drain of N2 is connected to the drain of N2; the source of N2 is connected to one
  • P1, P2, P3 constitute a current mirror; the power supply voltage is terminated with the power supply voltage VDD;
  • the inverter INV1 When the control signal On is low, the inverter INV1 outputs a high level. At this time, the PMOS transistor P0 is turned on, the NMOS transistor N1 is turned on, the voltage vGn of the gate of N2 is low, and the gates of P1, P2, and P3 are turned on. The voltage vGp of is at a high level, the driving current regulating MOS tube N2 is turned off, and the current mirrors P1, P2, P3 are turned off;
  • the inverter INV1 When the control signal On is at a high level, the inverter INV1 outputs a low level. At this time, the PMOS transistor P0 is turned off, and the NMOS transistor N1 is turned off. The controlled current source Ibias1 charges the capacitor C1, and the voltage vGn rises. When the voltage vGn is greater than After the driving current adjusts the threshold voltage of the MOS tube N2, N2 is turned on, and the current flowing through N2 passes through the current mirrors P1, P2, and P3 to generate current sources iCp and iDrv;
  • the current rate of change of the current sources iCp and iDrv can be controlled by adjusting the size of the controlled current source Ibias1;
  • the resistance Rdrv can set the current levels of the current sources iCp and iDrv; the resistance Rdrv can also affect the voltage difference between the two ends of the charge pump capacitor C120;
  • the current mirrors P1, P2, P3 can set the current size and ratio of the current sources iCp and iDrv;
  • the input signal Off of the turn-off delay circuit 112 immediately changes from low to high, which also causes the first MOS switch Q111 to be turned on immediately, and the output signal Offd of the turn-off delay circuit 112 is delayed After td time from low to high, the driving voltage vDrv drops from 6V to negative voltage, and then pulls back to zero level after a delay of tens of nanoseconds.

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Abstract

La présente invention concerne un circuit d'attaque de grille rapide de tube d'alimentation en GaN de haute fiabilité, comprenant : une extrémité de commande d'un circuit de réglage de courant d'attaque (110) et une extrémité d'entrée d'un inverseur de phase (INV115) qui sont connectées à une extrémité d'entrée du circuit d'attaque de grille ; l'extrémité d'entrée du circuit d'attaque de grille est utilisée pour entrer un signal de commande de mise sous tension ; une extrémité de sortie de l'inverseur de phase (INV115) est connectée à une extrémité de commande d'un premier commutateur MOS (Q111) et une extrémité d'entrée d'un circuit de retard de mise hors tension (112) ; une extrémité de sortie du circuit de retard de mise hors tension (112) est connectée à une extrémité de commande d'un second commutateur MOS (Q113) ; le circuit de réglage de courant d'attaque (110) délivre deux sources de courant iCp et iDrv qui sont respectivement connectées à un nœud a et à un nœud b au niveau de deux extrémités d'un condensateur de pompe de charge (C120) ; le premier commutateur MOS (Q111) a une extrémité de commutateur connectée au nœud a, et l'autre extrémité de commutateur connectée à une masse de référence ; le second commutateur MOS (Q113) a une extrémité de commutateur connectée au nœud b, et l'autre extrémité de commutateur connectée à la masse de référence ; le nœud b est utilisé comme extrémité de sortie du circuit d'attaque de grille. La fiabilité de travail d'un tube d'alimentation en GaN peut être améliorée.
PCT/CN2020/079855 2020-03-13 2020-03-18 Circuit d'attaque de grille rapide de tube d'alimentation en gan de haute fiabilité WO2021179342A1 (fr)

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CN202010176828.8A CN111224647A (zh) 2020-03-13 2020-03-13 高可靠的GaN功率管快速门极驱动电路
CN202010176828.8 2020-03-13

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CN113972908A (zh) * 2021-12-24 2022-01-25 江苏长晶科技股份有限公司 一种防止误操作的低功耗控制端口
CN114268227A (zh) * 2021-12-15 2022-04-01 苏州汇川控制技术有限公司 功率管驱动电路及系统
CN114614808A (zh) * 2022-03-16 2022-06-10 上海南麟集成电路有限公司 一种功率管驱动电路

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CN116015022A (zh) * 2021-10-22 2023-04-25 深圳英集芯科技股份有限公司 驱动电路和相关的控制芯片电路、电源适配器及电子设备
CN117938140A (zh) * 2024-03-19 2024-04-26 深圳安森德半导体有限公司 功率管防过冲驱动电路及驱动方法

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CN113972908A (zh) * 2021-12-24 2022-01-25 江苏长晶科技股份有限公司 一种防止误操作的低功耗控制端口
CN113972908B (zh) * 2021-12-24 2022-03-29 江苏长晶科技股份有限公司 一种防止误操作的低功耗控制端口
CN114614808A (zh) * 2022-03-16 2022-06-10 上海南麟集成电路有限公司 一种功率管驱动电路
CN114614808B (zh) * 2022-03-16 2022-10-18 上海南麟集成电路有限公司 一种功率管驱动电路

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