WO2021170844A1

WO2021170844A1 - Buffer-memory module and luminous device for a motor vehicle equipped with such a module

Info

Publication number: WO2021170844A1
Application number: PCT/EP2021/054919
Authority: WO
Inventors: Frantz PELISSIER
Original assignee: Valeo Vision
Priority date: 2020-02-28
Filing date: 2021-02-26
Publication date: 2021-09-02
Also published as: FR3107776B1; FR3107776A1

Abstract

The invention proposes a module intended to serve as a buffer memory between a first system generating data at a first rate and a second system consuming data at a second rate. While the module emulates the operation of a buffer memory employing a random-access memory element with two ports (input/output), the proposed module merely uses such a memory element with a single combined input/output port.

Description

Title: BUFFER MEMORY MODULE AND LUMINOUS DEVICE FOR A EQUIPPED MOTOR VEHICLE

OF SUCH A MODULE

[1] [line light-emitting diode, LED, is a semiconductor electronic component capable of emitting light when traversed by an electric current having at least a threshold intensity. Beyond the threshold intensity, the intensity of the electric current is directly related to the light intensity emitted by the diode, thus making it possible to achieve different levels of brightness. In the automotive industry, LED technology is increasingly being used for various light signaling and display solutions. LED arrays are of particular interest in the field of automotive lighting. Matrix light sources can be used for “leveling” type functions, i.e., adjustment of the height of the light beam emitted, according to the attitude of the vehicle and the profile of the road. Other applications include the DBL ("Digital Bending Light") which corresponds to the adjustment of the direction of the emitted light beam, to follow the road in the horizontal plane, the ADB ("Adaptive Driving Beam") which corresponds with an anti-glare function which generates shadow zones in the light beam emitted by a high beam so as not to disturb other road users, but also functions of projection of patterns on the ground using the pixelized light beam .

[2] It is known to use light sources of different types of technologies for the lighting applications mentioned. This is, for example, monolithic technology, according to which a large number of elementary LED-type sources, equivalent to pixels, are etched in a common semiconductor substrate. Electrical connections integrated into the substrate enable the pixels to be activated independently of each other. Another known technology is that of microLEDs, which generates a matrix of LEDs of small dimensions, typically less than 150 μm.

[3] It is particularly interesting to control raster or pixelated light sources using digital images, or using a stream of images. digital, each pixel of an image corresponding to a light setpoint to be produced by at least one elementary light source of the matrix source. The control data stream intended for such a light source can therefore generate a large data set at a high data rate. The display throughput may however be less, insofar as each technology for controlling the electric power supply of light sources and each technology of matrix source generates a different response time when faced with a new setpoint to be achieved. A buffer memory located between a system which emits the light instructions in the form of pixelated images, ie typically a central control module of the motor vehicle, and a light module intended to carry out the instruction in question, generally makes it possible to absorb in a known manner, a difference between the rate of the incoming data stream, and the outgoing data stream. Many regulatory lighting functions all the more require the creation of a default mode: when the input setpoint data is lost, the lighting function must nevertheless be able to be performed. For this purpose, it has been proposed to store each setpoint image entirely received in a dedicated memory area, so that it can be produced when a reception error occurs in a newly received setpoint image.

[4] It has in particular been proposed to use an integrated circuit with at least one on-board random access memory element to perform these buffer memory and setpoint memory functions. The system at the origin of the pixelated instructions writes the instructions by means of an input port towards the memory element, while the luminous device which must carry out the instruction reads a completely received instruction by means of an output port of this memory element . This solution is very expensive, primarily because of the cost of producing two-port RAM type random access memory elements.

[5] The object of the invention is to overcome at least one of the problems posed by the prior art. More specifically, the object of the invention is to provide a buffer memory module which is adapted to meet the aforementioned needs, while having a lower production cost and by having recourse to electronic components less complex than the solutions known in the field. art. [6] According to a first aspect of the invention, a module intended to act as a buffer memory between a first system generating data at a first rate and a second system consuming data at a second rate is provided. The module is remarkable in that it includes:

[7] - an integrated circuit comprising an input memory intended to receive data from the first system, an output memory intended to provide data for the second system, and a control unit,

[8] - an intermediate memory comprising a random access memory element having a single combined read / write port.

[9] The input and output memories each comprise a sequential memory element of FIFO (“First In First Out”) type provided with a state indication with respect to a predetermined intermediate filling level of the element. respective memory. The module's control unit is configured to write data from input memory to intermediate memory, and to write data from intermediate memory to output memory, based on said status indications.

[10] Preferably the first data rate may be greater than the second data rate.

[11] Preferably, the input and output memories can store data units between 8 and 64 bits in size. A unit of data may preferably correspond to a pixel of a digital image. Preferably, the input and output memories can be sized to contain a plurality of pixels, between 2 and 16 pixels.

[12] During a stacking or unstacking operation, at least one data unit is added / removed from the sequential stack. The intermediate memory may preferably have a capacity of several megabytes.

[13] Preferably, the control unit can be configured to realize a state machine comprising three states, in which a first state corresponds to a default mode, a second state corresponds to a data unstacking of the input memory. and their writing in the intermediate memory, and a third state corresponds to a reading of data in the intermediate memory and their stacking in the output memory, the transitions between the states being predetermined by said respective state indications of the input and output memory. In the default mode, no reading or writing of data in the intermediate memory is performed. Intermediate full indicator allows the state machine to unstack and stack data before the input and output memories are full, so that the buffer module always has the ability to unstack and stack simultaneously. data in the intermediate memory.

[14] The input memory can preferably be clocked by a first clock signal having a first frequency, and the state machine can preferably be clocked by a second clock signal having a second frequency, the second frequency being at least twice the first frequency.

[15] Preferably, the status indications can be binary indications. The input memory status indication can preferably be set to 1 if the input memory is full to a predetermined level which is between 50 and 90%, and to 0 otherwise . The output memory status indication can preferably be set to 1 if the input memory is full to a predetermined level which is between 10 and 50%, and to 0 otherwise.

[16] Preferably, the integrated circuit can be a network of in-situ programmable gates of the FPGA type. Alternatively, the integrated circuit can be a circuit dedicated to an application, for example an ASIC type circuit. In these two alternatives, it is particularly economical for the intermediate memory to be an external memory not integrated with the integrated circuit, for example not integrated with the package of the integrated circuit.

[17] The intermediate memory may preferably include at least one element of RAM (“Random Access Memory”), SRAM (“Static Random Access Memory”), SDRAM (“Synchronous Dynamic Random Access Memory”) or DDRAM (“Double Data Rate Synchronous Random Access Memory ”).

[18] Preferably, the intermediate memory can be structured to record at least two separate data sets, and in that the control unit is configured to write data from the intermediate memory to the output memory only if these data correspond to a data set completely stored in the intermediate memory. The two distinct data sets can preferably correspond to two distinct digital images.

[19] According to another aspect of the invention, a lighting device for a motor vehicle is provided. The device comprises a pixelated light source controlled by a flow of images to be projected. The device further includes an input buffer module. The device is remarkable that this module corresponds to a module according to one aspect of the invention.

[20] Preferably, the data to be written to / read from the input and output memories may correspond to pixels of an image, and the intermediate memory may be structured to store the data in full frames.

[21] Preferably, the module is configured so as to maintain a fully received image in the intermediate memory at all times. This is preferably the most recent full image that has been received through input memory.

[22] The control unit can preferably be configured so that, in the event of detection of a fault in the data entry level, the data which corresponds to this complete image is written to the destination. output memory. This allows a lighting device comprising a pixelated light source to be able to perform its lighting function at all times, in particular a low beam function. This makes it possible to ensure regulatory lighting during an isolated fault in the input data. A defect may for example be characterized by the absence of sufficient data to correspond to an entire image and / or the irremediable loss of a packet of an image which is then incomplete, and / or the presence of corrupted data detected at using a means of data verification.

[23] The pixelated light source may preferably comprise a monolithic matrix component, an array of light emitting diodes, LEDs, micro LEDs, or mini LEDs. [24] The pixelated light source may preferably comprise a monolithic source, comprising elementary electroluminescent light sources with semiconductor elements etched in a common substrate and which can be activated independently of each other.

[25] The lighting device may preferably be a signaling or display device for a motor vehicle.

[26] By using the measures proposed by the present invention, it becomes possible to provide a buffer memory module which is adapted to meet the needs of adapting the rates of input and output data streams between two systems. on the one hand, and to be able to store data, for example image data, in contiguous sets on the other hand. This is made possible by maintaining a lower production cost and by resorting to less complex electronic components compared to solutions known in the art. The measurements of the invention use an integrated circuit with low capacity and fast memory elements, of FIFO type, on board. Between an input FIFO and an output FIFO, the data pass through a memory element of RAM type, external to the integrated circuit, as a function of the filling state of the FIFO type memory elements. When the input data stream is interrupted or lost, data previously received and stored in the RAM memory can be relayed to the output FIFO according to a preferred embodiment. While using a single combined I / O RAM memory element, the proposed module emulates the operation of a significantly more expensive dedicated I / O RAM memory element. The use of the proposed module is particularly advantageous in the context of a lighting device for a motor vehicle with a pixelated light source. This type of device is typically driven by a high bit rate data stream, comprising a sequence of instruction images to be produced by the pixelated light source. The achievable display frequency may be lower than the input rate. The device must be able to manage the loss of a light setpoint in order to comply with the regulations in force, which is made possible by using the memory module offered. As this is a device made in mass production, the savings made by using the proposed module are substantial. [27] Other characteristics and advantages of the present invention will be better understood with the aid of the description of the examples and of the drawings, among which:

[28] - [Fig. 1] is an illustration of a memory module according to a preferred embodiment of the invention;

[29] - [Fig. 2] is a state diagram illustrating a state machine which is involved in a preferred embodiment of the invention.

[30] Unless specifically indicated to the contrary, technical characteristics described in detail for a given embodiment may be combined with the technical characteristics described in the context of other embodiments described by way of example and in a non-limiting manner.

[31] The description focuses on those elements of a memory module and a lighting device for a motor vehicle which are necessary for an understanding of the invention. Other elements, which are known to be part of such modules and devices, will not be mentioned or described in detail. For example, the presence and operation of a converter circuit involved in the power supply of a matrix light source, known per se, will not be described in detail. The same goes for optical elements such as lenses for example. Furthermore, electronic circuits producing sequential memories of FIFO (“First In First Out”) type are known per se and these electronic circuits will not be described explicitly.

[32] The illustration of Figure 1 shows a memory module 100 according to a preferred embodiment of the invention. The memory module is intended to act as a buffer memory between a first system 10 generating data at a first rate and a second system 20 consuming data at a second rate.

[33] According to a concrete and non-limiting example of the invention, the first system 10 is a central control unit of a motor vehicle which sends light instructions in the form of digital images to the second system 20. The second system 20 can, according to this example, be a light device with a matrix or pixelated light source. The data relating to the digital images can preferably be received by the proposed module by means of a network interface (not shown), capable of receiving data on a data bus internal to the motor vehicle. For example, the bus can be an Ethernet bus, a Gigabit Multimedia Serial Link, GMSL type bus, or a Low Voltage Differential Signaling, LVDS technology bus, such as an FPD-Link III bus. Each pixel of the digital image can correspond to an elementary light setpoint to be produced by an elementary light source of the pixelated light source. Such a light device is known per se in the art and involves a converter circuit, for example a switching circuit, which is able to supply an electric supply current to each of the elementary light sources, from a current electrical input supplied by a current source internal to the motor vehicle, comprising for example a battery. The average intensity of the electric current supplied to an elementary light source with an electroluminescent semiconductor element is a function of the switching frequency of the converter, and defines the level of luminosity emitted by the elementary light source. The data consumption rate of this second system 20 depends on the power supply technology as well as the light source technology used, and the associated response times. In particular, this data consumption rate may be lower than the input rate provided by the first system 10.

[34] The illustrated module 100 comprises an integrated circuit 110, typically of the FPGA (“Field Programmable Gâte Array”) type comprising an input sequential memory 112 of the FIFO type, intended to receive data from the first system 10. The integrated circuit 110 also includes an output sequential memory 114 intended to provide data for the second system 20, as well as a control unit 116. The input 112 and output 114 memories each include an indicator which provides information F1. , F2 describing their filling level, with respect to a predetermined intermediate filling level (between empty and full). According to a preferred embodiment, the indicators F1, F2 are binary value indicators (0,1). The state indicator F1 of the input memory 112 is for example set to the value 1 if the input memory is full up to a predetermined level which is between 50 and 90%, and to the value 0 otherwise. It is therefore an indicator which is non-zero when the input FIFO is almost full. The state indication F2 of the output memory 114 can preferably be set. the value 1 if the input memory is full to a predetermined level which is between 10 and 50%, and the value 0 otherwise. It is therefore an indicator which is non-zero when the output FIFO is almost empty. The threshold values can preferably be predetermined as a function of the intended application during the calibration of the proposed module. Logic circuits capable of generating the values of indicators F1 respectively F2 are known per se in the art and involve comparators of the state of each cell of the FIFO with a predetermined mask corresponding to the threshold value.

[35] The module 100 further includes an intermediate memory 120. This is a random access memory element, RAM, having a single combined read / write port operably linked to the integrated circuit 10. The control unit 116 is configured to write data from first system 10 and from input memory 112 to intermediate memory 120, and to write data from intermediate memory 129 to output memory 114 at destination of the second system 20, as a function of said state indications F1 and F2.

[36] The input 112 and output 114 memories preferably have a capacity of between 8 and 64 bits per unit of data recorded, and in the example mentioned above, are capable of storing a few, for example 4 or 8 , pixel values of a digital image. The use of on-board memories with limited capacity makes it possible to keep the production cost of the module low. Intermediate memory 120 may preferably have a capacity of several Megabytes, and thus accumulate entire digital images. Unlike the small size data units stored in the input memories 112 respectively output 114, a data unit stored in the intermediate memory 120 can contain a larger number of pixels of a digital image. An action of writing / reading data to / from the intermediate memory 120 generates in such a non-limiting case of the invention the unstacking / stacking of several data units from / to the input / output memories respectively. The intermediate memory is in particular preferably structured so as to be able to record and read there at least two whole digital images. [37] FIG. 2 shows a state transition diagram of a finite automaton produced by the control unit 116 in accordance with a preferred embodiment of the invention, without however limiting the invention to this automaton. finished. In a known manner, the state machine is clocked by a clock signal. In the case of the invention, the clock frequency which rates the changes of state of the state machine is at least twice the clock frequency which rates the inputs / outputs of the input and / or sequential memories. or output. The state denoted 00 corresponds to a default state, in which the control unit 116 orders neither the reading nor the writing of data in the intermediate memory element 116. Even, in the state 00, the control unit orders neither the unstacking of a data unit from the input FIFO memory 112, nor the stacking of a data unit into the output FIFO memory 114.

[38] When the input FIFO memory 112 is almost full (F1 = 1) and the output FIFO memory 114 is not nearly empty (F2 = 0), the control unit switches to the state denoted 10. In state 10, the control unit orders the unstacking of at least one data unit from the input FIFO 112, and writes the corresponding data in the intermediate memory 120. The write address in the intermediate memory is preferably given by the numbering of the pixel in the image which is being read, and of the index of the image when the memory can store several images. By maintaining a pixel and image counter at controller 116 and knowing the number of pixels per image, each piece of data written can thus be uniquely and unambiguously addressed on a subsequent read. Unless the flags F1, F2 change, state 10 is held, and data is written to intermediate memory on each clock stroke.

[39] Starting from state 00, when the input FIFO memory 112 is not nearly full (F1 = 0) and the output FIFO memory 114 is almost empty (F2 = 1), the unit control switch to the state denoted 01. In state 01, the control unit orders the reading of the next pixel (referenced by the addressing as described previously) in the intermediate memory 120, and stacks the corresponding data in the output FIFO 114. Unless the flags change. F1, F2, state 10 is maintained, and data is written in the output FIFO 114 destined for the second system 20 at each clock stroke. [40] In the non-limiting example of FIG. 2, the state machine does not include a state denoted by 11. Starting from state 10, when the flag F2 also switches to the value 1, the control unit switches to state 01. Likewise, starting from state 01, when the flag F1 also switches to the value 1, the control unit switches to state 10. Therefore, when the input FIFO 112 is almost full and the output FIFO 114 is almost empty, the states of unstack / write in intermediate memory 120 and read in intermediate memory 120 / stack are alternated at each clock stroke. The write and read addresses for each step remain available to the control unit 116 according to the principle described above.

[41] It goes without saying that the steps of writing / reading in the intermediate memory 120 can involve sub-steps which are dependent on the RAM technology used to produce this memory 120. Those skilled in the art will know how to adapt the method. described according to these parameters based on this basic knowledge in the art and without requiring any inventive step.

[42] According to a particularly preferred embodiment of the invention, the control unit maintains a specific indication in a memory element not shown, which means that one of the structured memory areas of the intermediate memory 120 has been fully populated with complete data from a digital image. The control unit 116 can be configured to detect loss of input data. Such a loss occurs, for example, when the first system 10 stacks data while the input FIFO 112 is already full. Such a situation can, for example and in a non-limiting manner, be detected at the level of the control unit by checking whether the sequence numbers of the pixels unstacked from the input FIFO are ordered according to a regular and complete sequence, or not. . In such a case, different reaction strategies can be implemented. For example, the memory location / digital image which is being saved to intermediate memory may be overwritten by the next digital image. Alternatively, a part of the image being written can be used, while the erroneous / missing part can be filled by the data which was recorded in the corresponding memory locations, in connection with a previous image. In all cases, the strategy will ensure that the data or setpoint values which will be stacked in the output FIFO 114, intended for the second system 20, correspond to a digital image (eg a complete light matrix setpoint) completely received beforehand. Preferably, the setpoint values which correspond to the last image completely received will be stacked in the output FIFO 114 destined for the second system 20 when the data input coming from the first system 10 is faulty. The fault is cleared when a new complete digital image is received is successfully written to the intermediate memory element 120.

[43] It goes without saying that the embodiments described do not limit the scope of protection of the invention. By resorting to the description which has just been given, other embodiments can be envisaged without departing from the scope of the present invention.

[44] The extent of protection is determined by the claims. |

Claims

[Claim 1] (Module (100) for use as a buffer memory between a first system (10) generating data at a first rate and a second system (20) consuming data at a second rate, characterized in that the module comprises: an integrated circuit (110) including an input memory (112) for receiving data from the first system, an output memory (114) for providing data for the second system, and a control unit

(116), an intermediate memory (120) comprising a random access memory element having a single combined read / write port; wherein the input (112) and output (114) memories each include a FIFO-type sequential memory element with a status indication (F1, F2) with respect to a predetermined intermediate fill level of the respective memory element, and wherein the control unit (116) is configured to write data from the input memory (112) to the intermediate memory (120), and to write data from the memory intermediate (120) to the output memory (114), as a function of said state indications (F1, F2).

[Claim 2] A module according to claim 1, characterized in that the input (112) and output (114) memories store data units between 8 and 64 bits in size.

[Claim 3] Module according to one of claims 1 or 2, characterized in that the control unit (116) is configured to produce a state machine comprising three states, in which a first state (00) corresponds to a default mode , a second state (10) corresponds to an unstacking of data from the input memory (112) and their writing to the intermediate memory (120), and a third state (01) corresponds to a reading of data in the intermediate memory (120) and their stacking in the output memory (114), the transitions between the states being predetermined by said respective state indications (F1, F2) of the input and output memory. [Claim 4] A module according to claim 3, characterized in that the input memory (112) is clocked by a first clock signal having a first frequency, and in that the state machine (116) is clocked by a second clock signal having a second frequency, the second frequency being at least twice the first frequency.

[Claim 5] Module according to one of claims 1 to 4, characterized in that the status indications (F1, F2) are binary indications.

[Claim 6] Module according to one of claims 1 to 5, characterized in that the integrated circuit (110) is a network of in-situ programmable gates of the FPGA type.

[Claim 7] Module according to one of claims 1 to 6, characterized in that the intermediate memory (120) comprises at least one element of RAM, SRAM, SDRAM or DDRAM type.

[Claim 8] Module according to one of claims 1 to 7, characterized in that the intermediate memory (120) is structured to record at least two distinct data sets, and in that the control unit (116) is configured for write data from the intermediate memory (120) to the output memory (114) only if this data corresponds to a set of data completely stored in the intermediate memory.

[Claim 9] A lighting device for a motor vehicle comprising a pixelated light source controlled by a stream of images to be projected, the module further comprising an input buffer memory module, characterized in that the latter corresponds to a module according to one of the preceding claims.

[Claim 10] Device according to claim 9, characterized in that the data intended to be written / read in the input and output memories correspond to pixels of an image, and in that the intermediate memory is structured for store data in full images.

[Claim 11 j Device according to one of claims 9 or 10, characterized in that the pixelated light source comprises a monolithic matrix component, a matrix of light emitting diodes, LEDs, micro LEDs, or mini LEDs. [Claim 12] Device according to one of claims 9 to 11, characterized in that it is a signaling or display device for a motor vehicle.