WO2021168758A1 - 一种基于PCIe的通信方法及装置 - Google Patents

一种基于PCIe的通信方法及装置 Download PDF

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Publication number
WO2021168758A1
WO2021168758A1 PCT/CN2020/077039 CN2020077039W WO2021168758A1 WO 2021168758 A1 WO2021168758 A1 WO 2021168758A1 CN 2020077039 W CN2020077039 W CN 2020077039W WO 2021168758 A1 WO2021168758 A1 WO 2021168758A1
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WIPO (PCT)
Prior art keywords
node
working mode
root complex
communication
identity information
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PCT/CN2020/077039
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English (en)
French (fr)
Inventor
万蕾
朱杰作
王学寰
鲍鹏鑫
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华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20921673.8A priority Critical patent/EP4099637A4/en
Priority to PCT/CN2020/077039 priority patent/WO2021168758A1/zh
Priority to CN202080002612.8A priority patent/CN113647058B/zh
Publication of WO2021168758A1 publication Critical patent/WO2021168758A1/zh
Priority to US17/895,769 priority patent/US20220405229A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric

Definitions

  • This application relates to the field of communication technology, and in particular to a communication method and device based on peripheral component interconnect express (PCIe).
  • PCIe peripheral component interconnect express
  • the main components of the PCIe system include a root complex (Root), a switch, an endpoint, and so on.
  • the root complex is used to manage all buses and all nodes in the PCIe system, and is the communication bridge between nodes in the PCIe system;
  • a PCIe system can include one or more switching nodes, and the switching nodes are data in the PCIe system
  • a switching node can be connected to one or more of the root complex, other switching nodes or end nodes; end nodes are end devices, such as peripherals, etc., used to receive from other nodes or root complexes Body data, or send data to other nodes or root complexes.
  • the configuration space of a node is used to store the function information or address and other information of the node. If the current node is a storage device, other nodes in the PCIe system have no right to read the configuration space of the node. For example, for node 1 of the PCIe system, only the root complex and node 1 have the right to read the configuration space of node 1, while other nodes in the PCIe system except node 1 have no right to read the configuration of node 1 space. This means that only the root complex in the PCIe system can know the function or address of each node.
  • the embodiments of the present application provide a PCIe-based communication method and device, so that the communication between nodes in the PCIe system does not pass through the root complex, thereby reducing the complexity of communication between nodes.
  • an embodiment of the present application provides a PCIe-based communication method, including: the root complex writes the identity information of the second node to the first node, and writes routing table information to the third node, where the first node Is the source node of the first data, the second node is the destination node of the first data, and the third node is the node from the first data to the second node.
  • the method described in the first aspect may be executed by the root complex itself, or may be executed by a chip in the root complex, and so on.
  • the sending node by writing the identity information of the destination node of the data to the sending node (for example, the first node), the sending node can carry the identity information of the destination node of the data when sending data.
  • the routing table information By writing the routing table information to the intermediate node (for example, the third node), the intermediate node can determine the routing path according to the identity information of the destination node and the routing table information when receiving the data, and based on the routing path, the data can be sent to The destination node (for example, the second node).
  • the destination node for example, the second node.
  • the root complex determines that the first node supports the first operating mode; or, determines that all the first nodes support the first operating mode and the second operating mode; where the first operating mode is the relationship between the node and the node
  • the communication between the nodes does not go through the working mode of the root complex, and the second working mode is that the communication between the nodes needs to go through the working mode of the root complex.
  • the communication between nodes can be realized without passing through the root complex, thereby reducing the communication complexity of each node in the PCIe system; the first node supports both the first working mode When the mode supports the second working mode, it can realize that the communication between nodes does not go through the root complex to reduce the communication complexity of each node in the PCIe system, and it can also communicate according to the current communication mode, which is compatible .
  • the root complex when the first node is in the second working mode, the root complex configures a first memory address for the first node, and the first memory address is the local memory space of the first node mapped to the central processing unit The physical address in the running memory corresponding to the (central processing unit, CPU).
  • the first memory address for the first node by configuring the first memory address for the first node, the first node can communicate according to the current communication mode, and the compatibility of the two working modes is realized.
  • the root complex determines that the third node supports the first operating mode; or, determines that the third node supports the first operating mode and the second operating mode; where the first operating mode is between node and node
  • the communication does not go through the working mode of the root complex, and the second working mode is that the communication between nodes needs to go through the working mode of the root complex.
  • the third node when the third node only supports the first working mode, the communication between nodes can be realized without passing through the root complex, thereby reducing the communication complexity of each node in the PCIe system; the third node supports both the first working mode When the mode supports the second working mode, it can realize that the communication between nodes does not go through the root complex, so as to reduce the communication complexity of each node in the PCIe system, and it can also communicate according to the current communication mode, which is compatible .
  • the root complex when the third node is in the second working mode, the root complex configures the second memory address for the third node, and the second memory address is the local memory space of the third node mapped to the corresponding operation of the CPU The physical address in memory.
  • the third node by configuring the second memory address for the third node, the third node can communicate according to the current communication mode, and the compatibility of the two working modes is realized.
  • the root complex writes the identity information of the first node into the first node.
  • the identity information of the first node can be sent to the destination node of the data, so that the destination node can confirm the information of the source node of the data; The received data is verified to determine whether the received data is the data sent to this node.
  • the root complex writes the identity information of the third node into the third node.
  • the identity information of the third node can be sent to the destination node of the data, so that the destination node can confirm the information of the source node of the data; The received data is verified to determine whether the received data is the data sent to this node.
  • the identity information is a bus number, a device number, and a function number (bus, device and function number, BDF), or an identity (ID) number.
  • the identity information can be a unique BDF allocated to the node by the root complex, or a unique ID number re-allocated by the root complex to the node, so that the identity information of each node is unique.
  • an embodiment of the present application provides a PCIe-based communication method, including: a first node determines the identity information of a second node according to information stored in the first node, and sends a first transaction layer packet to the third node (transaction layer packet, TLP), where the second node is the destination node of the first data, and the first TLP includes the first data and the identity information of the second node.
  • a first node determines the identity information of a second node according to information stored in the first node, and sends a first transaction layer packet to the third node (transaction layer packet, TLP), where the second node is the destination node of the first data, and the first TLP includes the first data and the identity information of the second node.
  • TLP transaction layer packet
  • the first node can be an end node or a bridge node
  • the second node can be an end node or a bridge node
  • the third node can be a bridge node.
  • the sending node determines the identity information of the receiving node (for example, the second node) through stored information, and then encapsulates the first data and the identity information of the receiving node and sends them to the intermediate node ( For example, the third node), so that the intermediate node forwards the first data to the receiving node.
  • the intermediate node For example, the third node
  • the communication between the end nodes, the communication between the switching nodes, and the communication between the end nodes and the switching nodes in the PCIe system can be realized without the root complex, and the direct communication between the nodes can be realized. Reduce the complexity of communication between nodes in the PCIe system.
  • the above-mentioned stored information may be configured by the root complex or configured by other network nodes.
  • the first node supports the first working mode
  • the first working mode is a working mode in which the communication between the nodes does not pass through the root complex.
  • the first node supports the first working mode, which can realize that the communication between the nodes does not pass through the root complex, thereby reducing the communication complexity of each node in the PCIe system.
  • the first node supports the first working mode and the second working mode.
  • the first working mode is the working mode in which the communication between the node and the node does not go through the root complex
  • the second working mode is the node and the second working mode.
  • the communication between nodes needs to go through the working mode of the root complex.
  • the first node supports both the first working mode and the second working mode, which can realize the communication between nodes without passing through the root complex, so as to reduce the communication complexity of each node in the PCIe system.
  • the communication can be carried out according to the current communication mode, and the compatibility of the two working modes is realized.
  • the stored information also includes the identity information of the first node.
  • the information stored in the first node includes the identity information of the first node, and the identity information of the first node can be sent to the destination node of the data so that the destination node can confirm the information of the source node of the data; The received data is verified to determine whether the received data is the data sent to this node.
  • the first TLP also includes the identity information of the first node.
  • the first data and the identity information of the first node are encapsulated as the first TLP and sent to the destination node, so that the destination node can confirm the information of the source node of the data.
  • the identity information is BDF, or ID number.
  • the identity information can be a unique BDF allocated by the root complex to the node, or a unique ID number re-allocated by the root complex to the node, so that the identity information of each node is unique.
  • an embodiment of the present application provides a PCIe-based communication device.
  • the device may be a communication device, or a chip or chipset in the communication device.
  • the communication device may be a root complex or a first node. That is to say, the communication device can be a root complex, an end node, or a switching node.
  • the device may include a processing unit.
  • the processing unit may be a processor; the device may also include a transceiver module and a storage module, and the storage module may be a memory; the storage module is used to store instructions, and the processing unit executes all instructions of the storage module.
  • the stored instructions enable the root complex to perform the corresponding functions in the above-mentioned first aspect, or the processing unit executes the instructions stored in the storage module, so that the first node executes the corresponding functions in the above-mentioned second aspect.
  • the processing unit can be a processor, and the transceiver unit can be an input/output interface, a pin or a circuit, etc.; the processing unit executes the instructions stored in the storage module to The root complex is caused to perform the corresponding function in the foregoing first aspect, or the processing unit executes the instruction stored in the storage module, so that the first node performs the corresponding function in the foregoing second aspect.
  • the storage module may be a storage module (for example, register, cache, etc.) in the chip or chipset, or a storage module (for example, read-only memory, random access memory, etc.) located outside the chip or chipset in the network device. Fetch memory, etc.).
  • an embodiment of the present application provides a PCIe-based communication device, which includes a processor, and may also include a communication interface and/or a memory.
  • the communication interface is used to transmit information, and/or messages, and/or data between the device and other devices.
  • the memory is used to store computer-executable instructions.
  • the processor executes the computer-executable instructions stored in the memory, so that the device executes any design or second aspect of the first aspect or the first aspect described above. Or any of the communication methods designed in the second aspect.
  • the embodiments of the present application also provide a computer-readable storage medium.
  • the computer-readable storage medium is used to store computer instructions.
  • the computer instructions run on the computer, the computer executes the first aspect or the first aspect described above. Any possible design, the second aspect, or the communication method of any possible design in the second aspect.
  • this application also provides a computer program product including instructions.
  • the computer program product is used to store computer instructions.
  • the computer instructions run on a computer, the computer executes any one of the first aspect or the first aspect. Possible design, the second aspect, or the communication method of any one of the possible designs of the second aspect.
  • the present application also provides a PCIe system, which includes a first node, a second node, and a third node.
  • the first node is an end node
  • the second node is a switching node
  • the third node is an end node.
  • the first node can perform the corresponding function in the first aspect
  • the second node can perform the corresponding function in the second aspect.
  • a chip provided by an embodiment of the present application.
  • the chip includes at least one processor and a communication interface.
  • the processor is coupled to the memory and is used to read a computer program stored in the memory to execute the first aspect or A communication method designed in any one of the first aspect, the second aspect, or any one of the second aspects.
  • an embodiment of the present application provides a chip, including a communication interface and at least one processor, and the processor runs to execute any possible design, second aspect, or Any one of the possible designed communication methods in the second aspect.
  • FIG. 1 is a schematic diagram of the architecture of a PCIe system provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of the architecture of another PCIe system provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a process for allocating BDF according to an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of a TLP header provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of another TLP head provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of another TLP head provided by an embodiment of the application.
  • FIG. 7 is a schematic structural diagram of another TLP header provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of another TLP header provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of another TLP header provided by an embodiment of the application.
  • FIG. 10 is a schematic flowchart of a PCIe-based communication method provided by an embodiment of this application.
  • FIG. 11 is a schematic flowchart of another PCIe-based communication method provided by an embodiment of the application.
  • FIG. 12 is a schematic flowchart of another PCIe-based communication method provided by an embodiment of this application.
  • FIG. 13 is a schematic structural diagram of a PCIe-based communication device provided by an embodiment of this application.
  • FIG. 14 is a schematic structural diagram of another PCIe-based communication device provided by an embodiment of the application.
  • 15 is a schematic structural diagram of another PCIe-based communication device provided by an embodiment of the application.
  • 16 is a schematic structural diagram of another PCIe-based communication device provided by an embodiment of this application.
  • FIG. 17 is a schematic structural diagram of another TLP header provided by an embodiment of the application.
  • FIG. 18 is a schematic structural diagram of another TLP head provided by an embodiment of the application.
  • a plurality of in the embodiments of the present application refers to two or more than two. In view of this, “a plurality of” may also be understood as “at least two” in the embodiments of the present application. "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, including at least one of A, B, and C, then the included may be A, B, C, A and B, A and C, B and C, or A and B and C.
  • ordinal numbers such as “first” and “second” mentioned in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the order, timing, priority, or importance of multiple objects.
  • PCIe is a high-speed short-distance communication interface, which is widely used in computers, test instruments and other equipment. PCIe can quickly read and write memory and supports large broadband communications. Some car companies have extended its transmission distance and can be used as a large data communication interface for the car intranet.
  • FIG. 1 is a schematic structural diagram of a PCIe system provided by an embodiment of this application.
  • the PCIe system may include a root complex (shown in Figure 1 as the root complex), at least one switching node (Figure 1 includes switching node 1), and at least one end node (Figure 1 includes end node 1 , End node 2 and end node 3).
  • the root complex is responsible for managing all the buses in the PCIe system 100 (shown in thick black lines in FIG. 1), switching nodes, and end nodes. It is the communication bridge between the nodes in the PCIe system 100 and is also in the PCIe system 100. The communication bridge between each node and the CPU.
  • the switching node serves as a bridge connecting one or more of the root complex, other switching nodes, and end nodes, and is a node for data forwarding.
  • the switching node 1 connects the root complex, the end node 1 and the end node 2.
  • An end node is an end device, such as a peripheral device, which is responsible for sending data or receiving data.
  • the interface between the CPU and the root complex is not PCIe, and does not belong to the PCIe system 100.
  • the CPU can establish a connection relationship with the entity where the PCIe system 100 is located (such as computer equipment, vehicles, etc.), or it can be located in the same entity as the PCIe system 100, and is used to receive data sent by each node in the PCIe system 100, and can also The received data is processed, such as format conversion, image rendering, etc.
  • One device (for example, root complex, switch node 1, end node 1, end node 2, or end node 3) in the PCIe system 100 can support up to 8 functions, such as audio, video and other functions.
  • the bridge node is used to connect other devices.
  • each function of the device has its own configuration space, and the configuration space stores the information of the function.
  • the configuration space may be an independent storage unit of the device, for example, the size of the configuration space may be 256k.
  • the root complex has the authority to read and write the configuration space of each device in the PCIe system 100.
  • the root complex can obtain information about the functions supported by the end node 1 by reading the information in the configuration space of the end node 1.
  • the root complex can also complete the initialization and configuration of the end node 1 by writing the configuration space of the end node 1.
  • Devices other than the root complex and their functions can only see information about their configuration space.
  • FIG. 2 is a schematic diagram of another structure of the PCIe system 100.
  • the functions supported by the root complex include host bridge, bridge node 1 and bridge node 2.
  • the host bridge node, bridge node 1 and bridge node 2 pass through the bus ((in bold black in Figure 2).
  • the functions supported by the switching node 1 include the bridge node 3, the bridge node 4, and the bridge node 5, and the bridge node 3, the bridge node 4, and the bridge node 5 establish a connection relationship with each other through a bus.
  • the host bridge node is used to establish a connection relationship with the CPU, the bridge node 1 establishes a connection relationship with the bridge node 3 in the switching node 1 through the bus, the bridge node 2 establishes a connection relationship with the end node 3 through the bus, and the bridge node 4 establishes a connection relationship with the end node 3 through the bus.
  • the end node 1 establishes a connection relationship, and the bridge node 5 establishes a connection relationship with the end node 2 through the bus.
  • the root complex needs to enumerate and traverse the buses, devices, and functions in the devices in the PCIe system 100 to complete the initialization and configuration of each device.
  • Figure 3 a schematic diagram of the process of allocating BDF to the root complex.
  • S2 The root complex discovers bridge node 1 through Bus 0, assigns a bus number, a device number and a function number (bus device and function number, BDF) to bridge node 1, and sets the downstream bus of bridge node 1 to Bus 1.
  • BDF bus device and function number
  • the root complex traverses the nodes connected to Bus 0, first finds bridge node 1, and then traverses the nodes connected to the downstream bus of bridge node 1 according to the depth-first rule, and sets the bus to Bus 1. At the same time, the root complex allocates BDF to bridge node 1.
  • the bus number of the switch node (or bridge node) includes the upstream bus number of the switch node (or bridge node), the downstream bus number of the switch node (or bridge node) and the switch The maximum bus number of the branch where the node (or bridge node) is located.
  • the upstream bus of bridge node 1 is Bus 0, and the downstream bus number of bridge node 1 is Bus 1.
  • the maximum bus number of the branch where bridge node 1 is located cannot be determined. You can temporarily set the maximum bus number of the branch where bridge node 1 is located to 0xFF, and the bus number of bridge node 1 can be 0 , 1, 0xFF.
  • the root complex will write the bus number in the BDF to the switching node (Or bridge node) so that the switching node (or bridge node) performs ID routing according to the bus number.
  • the root complex can write the bus number into the configuration space of the switch node (or bridge node).
  • the root complex can determine the next hop node to forward the data according to the bus number and the bus number of the destination node. For the specific implementation of routing according to the bus number, reference may be made to the prior art, which will not be repeated here.
  • S3 The root complex discovers bridge node 3 through Bus 1, assigns BDF to bridge node 3, and sets the downstream bus of bridge node 3 to Bus 2.
  • the root complex traverses the nodes connected to Bus 1 and finds bridge node 3, and then traverses the nodes connected to the downstream bus of bridge node 3 according to the depth-first rule, and sets the bus to Bus 2. At the same time, the root complex allocates BDF to bridge node 3, where the bus number of bridge node 3 can be 1, 2, 0xFF.
  • S4 The root complex discovers bridge node 4 through Bus 2, assigns BDF to bridge node 4, and sets the downstream bus of bridge node 4 to Bus 3.
  • the root complex traverses the nodes connected to Bus 2, first finds the bridge node 4, and then traverses the nodes connected to the downstream bus of the bridge node 4 according to the depth-first rule, and sets the bus as Bus 3. At the same time, the root complex allocates BDF to the bridge node 4, where the bus number of the bridge node 4 can be 2, 3, 0xFF.
  • S5 The root complex discovers end node 1 through Bus 3, and allocates BDF to end node 1.
  • the root complex traverses the nodes connected to Bus 3 and finds end node 1, and then the root complex allocates BDF to end node 1.
  • the bus number of the end node includes the upstream bus number of the end node (or the function of the end node).
  • the upstream bus of end node 1 is Bus 3, so the bus number of end node 1 can be 3.
  • the root complex will not transfer the end node (or the function of the end node)
  • the BDF is written to the end node (or the function of the end node).
  • the BDF of the end node (or the function of the end node) is managed by the root complex, and the end node (or the function of the end node) does not know its own BDF.
  • the root complex determines that the maximum bus number of the branch where the bridge node 4 is located is 3, and updates the bus number of each node in the branch where the bridge node 4 is located. After the update, the bus number of the bridge node 4 is 2, 3, 3; the bus number of the end node 1 is 3.
  • S6 The root complex discovers bridge node 5 through Bus 2, assigns BDF to bridge node 5, and sets the downstream bus of bridge node 5 to Bus 4.
  • the root complex After the root complex traverses the branch where the bridge node 4 is located, it finds the bridge node 5 through Bus 2, and then traverses the nodes connected to the downstream bus of the bridge node 5 according to the depth-first rule, and sets the bus as Bus 4. At the same time, the root complex allocates BDF to the bridge node 5, where the bus number of the bridge node 5 can be 2, 4, 0xFF.
  • S7 The root complex discovers end node 2 through Bus 4, and allocates BDF to end node 2.
  • the root complex traverses the nodes connected to Bus 4 and finds end node 2, and then the root complex allocates BDF to end node 2, where the bus number of end node 2 can be 4.
  • the root complex determines that the maximum bus number of the branch where the bridge node 5 is located is 4, and updates the bus number of each node in the branch where the bridge node 5 is located. After the update, the bus number of bridge node 1 is 0, 1, 4; the bus number of bridge node 3 is 1, 2, 4; the bus number of bridge node 5 is 2, 4, 4; the bus number of end node 2 is 4.
  • S8 The root complex discovers bridge node 2 through Bus 0, allocates BDF to bridge node 2, and sets the downstream bus with bridge node 2 to Bus 5.
  • the root complex After the root complex traverses the branch where bridge node 1 is located, it finds bridge node 2 through Bus 0, and then traverses the nodes connected to the downstream bus of bridge node 2 according to the depth-first rule, and sets the bus to Bus 5. At the same time, the root complex allocates BDF to bridge node 2, where the bus number of bridge node 2 can be 0, 5, 0xFF.
  • S9 The root complex discovers end node 2 through Bus 5, and allocates BDF to end node 2.
  • the root complex traverses the nodes connected to Bus 5 and finds end node 2, and then the root complex allocates BDF to end node 2, where the bus number of the end node can be 5.
  • the root complex determines that the maximum bus number of the branch where the bridge node 2 is located is 5, and updates the bus number of each node in the branch where the bridge node 2 is located. After the update, the bus number of bridge node 2 is 0, 5, and 5; the bus number of end node 2 is 5.
  • the root complex can allocate BDFs to all nodes in the PCIe system 100, and write the bus number of the switching node (or bridge node) to the switching node (or bridge node) for ID routing.
  • TLP transaction layer packet
  • the PCIe system supports three routing methods for communication: address routing, identity (ID) routing, and implicit routing. Different routing methods have different routing addresses in the TLP header.
  • address routing e.g., address routing
  • ID identity routing
  • implicit routing e.g., implicit routing.
  • Different routing methods have different routing addresses in the TLP header.
  • the length of the TLP header is 12 bytes (Byte)
  • the fields related to the routing mode are Byte8 to Byte11, as shown in Figure 4.
  • the fields related to the routing mode are Byte8 ⁇ Byte15, as shown in Figure 5.
  • Address routing refers to the method of routing based on memory addresses.
  • the memory address is the physical address mapped from the local memory space of the node to the running memory corresponding to the CPU.
  • the memory address includes a 32-bit memory address and a 64-bit memory address.
  • Different memory addresses require different TLP headers. For example, a 32-bit memory address needs to use a TLP header with a length of 12 bytes, and Byte8 to Byte11 in the TLP header are used to indicate a 32-bit memory address, as shown in Figure 6.
  • a 64-bit memory address needs to use a TLP header with a length of 16 bytes.
  • Byte8 ⁇ Byte11 in the TLP header are used to indicate the high 32-bit memory address, and Byte12 ⁇ Byte15 in the TLP header are used to indicate the low 32-bit memory address.
  • Memory address as shown in Figure 7.
  • the memory address of the node in the PCIe system is configured by the root complex and written into the register (for example, bar) of each node.
  • the node in the PCIe system has a local memory space, which is open to the CPU, but the CPU can only directly access the running memory corresponding to the CPU, and cannot directly access the local memory space of the node. Therefore, the root complex can map the local memory space of the node to the running memory corresponding to the CPU to obtain the memory address, so that the root complex can access the local memory space of the node according to the memory address, that is, realize the communication between the root complex and the node .
  • the routing table information of the switching node is the operating memory range corresponding to the CPU, and the operating memory range corresponding to the CPU covers the memory addresses of all nodes connected to the switching node (or bridge node).
  • the memory address of the pendant node is only known by the pendant node itself and the root complex.
  • the mapping relationship between the local memory space of the pendant node and the running memory corresponding to the CPU is also known by the root complex.
  • the switch node (or bridge) Node) is not clear. Therefore, when two nodes pass through a switch node (or bridge node) for data transmission, the switch node (or bridge node) does not know which node to forward the data to, so it needs to pass through the switch node (or bridge node).
  • the communication between the two nodes of the node must pass through the root complex. Therefore, the address routing only supports data sent from the root complex to the node, or data sent from the node to the root complex. For the communication between nodes, it must go through the root complex.
  • ID routing refers to the way of routing according to BDF.
  • the ID routing method includes two TLP headers. For example, a TLP header with a length of 12 bytes can be used, and some bytes in Byte8 to Byte11 in the TLP header are used to indicate the BDF, as shown in FIG. 8. For another example, a TLP header with a length of 16 bytes can be used, and some bytes of Byte8 to Byte11 in the TLP header are used to indicate the BDF, as shown in FIG. 9.
  • the BDF of each node is the BDF configured by the root complex for the node. The BDF of the node is only known by the root complex, and the node itself or other nodes are not.
  • This ID routing method is usually only used for the root complex to send configuration messages to the node, and the node to send configuration response messages to the root complex. Therefore, ID routing only supports communication from the root complex to the node, or communication from the node to the root complex. For the communication between nodes, this ID routing method is not supported.
  • Implicit routing refers to other routing methods that do not use address routing or ID routing.
  • the implicit route is used to send data to the root complex.
  • the TLP sent by the node is sent to by default, and the TLP is forwarded to the root complex by default. Therefore, implicit routing is only used for communication from the node to the root complex.
  • the three routing methods currently supported by the PCIe system cannot communicate directly between end nodes, between switching nodes and switching nodes, and between end nodes and switching nodes. If two nodes want to communicate, they must go through the root complex. The working mechanism that the nodes in the PCIe system must communicate through the root complex will cause the complexity of communication between the nodes in the PCIe system to greatly increase. As shown in Figure 1 or Figure 2, although end node 1 and end node 2 are connected to switch node 1, the two cannot directly communicate through switch node 1. End node 1 must first communicate with the root complex through the root complex In order to find end node 2, or end node 2 must communicate with the root complex first, and then end node 1 can be found through the root complex.
  • end node 1 sends data to end node 2
  • the specific process can be: end node 1 sends the data to switch node 1, switch node 1 sends the data to the root complex, and the root complex then sends the data to switch node 1. The data is sent to end node 2.
  • the embodiments of the present application provide a PCIe-based communication method and device, which are used to prevent the communication between nodes in the PCIe system from passing through the root complex, thereby reducing the complexity of communication between nodes in the PCIe system. .
  • FIG. 10 is a flowchart of a PCIe-based communication method provided by an embodiment of this application.
  • the method can be applied to the PCIe system in the in-vehicle network, especially the in-vehicle network of an autonomous vehicle. Of course, it can also be applied. PCIe system for other devices.
  • this method can be applied to the PCIe system 100 shown in FIG. 1 or FIG. 2.
  • the method will be introduced by taking the method applied to the root complex in the PCIe system 100 as an example.
  • the root complex reads the information stored in the first node.
  • the root complex can read the information stored in the first node when the PCIe system 100 is initialized, and can also read the information stored in the first node when it detects that the first node needs to send the first data.
  • the stored information may be configured by the root complex, or configured by other nodes, or manually configured, etc., which is not limited in the embodiment of the present application.
  • the first data is data sent by the first node to the second node, that is, the first node is the source node of the first data.
  • the first node may be an end node or a function of an end node in the PCIe system 100, or may be a switching node or a function of a switching node in the PCIe system 100.
  • the first node may be the end node 1 or the bridge node 4.
  • the information stored in the first node may be information of the configuration space of the first node.
  • the configuration space of a node can be a section of physical storage address for storing configuration information.
  • the root complex reads the information stored in the first node, and can determine the working mode supported by the first node based on the information.
  • the reserved space of the configuration space of the first node may store indication information, and the indication information is used to indicate the working mode supported by the first node.
  • the root complex can read the reserved space in the configuration space of the first node, so as to determine the working mode supported by the first node according to the read instruction information.
  • the reserved space is an unused storage address in the configuration space.
  • the working mode supported by the first node includes a first working mode and a second working mode.
  • the first working mode is a working mode in which the communication between nodes does not go through the root complex
  • the second working mode is between nodes and nodes. The communication needs to go through the working mode of the root complex.
  • the root complex determines the working mode supported by the first node according to the information stored in the first node. If the root complex determines that the first node only supports the first operating mode, then only execute S1002; if the root complex determines that the first node only supports the second operating mode, execute S1003 ⁇ S1004; if the root complex determines that the first node supports In the first working mode and the second working mode, S1002 to S1004 are executed.
  • the root complex After the root complex determines that the first node supports the first working mode, the root complex writes the identity information of the destination node (for example, referred to as the second node) corresponding to the first node into the first node. Specifically, the root complex may first determine the destination node corresponding to the first node, and then the root complex may write the identity information of the destination node corresponding to the first node into the first node. For example, the root complex may determine the destination node of the first data according to the type of the first data (for example, the video type or the image type, etc.) and the function of each node in the PCIe system 100.
  • the type of the first data for example, the video type or the image type, etc.
  • the first node is the end node 1
  • the type of the first data is the video type
  • the end node 2 is the display
  • the end node 3 is the memory
  • the root complex can determine that the destination node of the first data is the end node 2.
  • the root complex writes the identity information of the second node into the first node, for example, writes the identity information of the second node into the information stored in the first node, or writes the identity information of the second node into the first node , Or write the identity information of the second node into the parameters of the first node, etc.
  • the root complex writes the identity information of the second node into the reserved space of the configuration space of the first node.
  • the second node is the destination node of the first data.
  • the second node may be an end node or a function of an end node in the PCIe system 100, or may be a switching node or a function of a switching node in the PCIe system 100.
  • the identity information of each node in the PCIe system 100 is unique.
  • the identity information of a node is allocated by the root complex.
  • a node's identity information may be the BDF of the node allocated by the root complex, or the ID of the node allocated by the root complex.
  • FIG. 3 For the specific allocation process, refer to the flow shown in FIG. 3, which will not be repeated here.
  • the root complex can write the identity information of each destination node of the multiple destination nodes into the first node.
  • the first node is end node 1
  • the type of first data is video type
  • end node 2 and end node 3 are both displays
  • the root complex determines that both end node 2 and end node 3 can display the first data, so the root The complex determines that both end node 2 and end node 3 are the destination nodes of end node 1.
  • the root complex can write the identity information of the end node 2 and the identity information of the end node 3 into the end node 1.
  • the root complex may write the identity information of the first node into the first node.
  • the first node can encapsulate the first data, the identity information of the first node, and the identity information of the second node into a TLP when sending the first data, so that the TLP can carry the source address so that the destination node can be based on the The source address determines that the sending node of the TLP is the first node.
  • the first node may also determine whether to discard the received TLP according to whether the destination address carried in the received TLP is consistent with the identity information of the first node.
  • the first node determines that the TLP is sent to the first node; if the destination address carried by the TLP is inconsistent with the identity information of the first node, the first node The node determines that the TLP is not sent to the first node, and can discard the TLP.
  • the root complex writes the identity information of the first node into the first node, for example, writes the identity information of the first node into the information stored in the first node, or writes the identity information of the first node into the first node. Variables in nodes, or parameters for writing the identity information of the first node into the first node, etc. For example, the root complex writes the identity information of the first node into the reserved space of the configuration space of the first node.
  • the root complex maps the local memory space of the first node to the running memory corresponding to the CPU, and obtains the first memory address.
  • the first memory address refers to the physical mapping of the local memory space of the first node to the running memory corresponding to the CPU. address.
  • the size of the local memory space of the first node is 2MB
  • the address of the local memory space is 0x0000 ⁇ 0x007F
  • the size of the running memory corresponding to the CPU is 2GB (GigaByte)
  • the address of the running memory is 0x0000 ⁇ 0xFFFF.
  • the address of the local memory space mapped to the running memory corresponding to the CPU is 0x0100 ⁇ 0x017F, that is, the first memory address is 0x0100 ⁇ 0x017F.
  • S1004 The root complex writes the first memory address into the first node.
  • the root complex writes the first memory address to the first node, for example, writes the first memory address to the register of the first node, or writes the first memory address to the information stored in the first node, or writes the first memory address to the information stored in the first node.
  • a memory address is written into the variable in the first node, or the first memory address is written into the parameter in the first node, etc.
  • FIG. 10 may be implemented by a root complex, or a chip in the root complex, or may be implemented by other devices, such as a CPU.
  • the embodiment of the application does not limit this.
  • the root complex writes the identity information of the destination node (for example, the second node) into the sending node (for example, the first node).
  • the sending node sends the first data to the destination node
  • the first data and the identity information of the destination node may be encapsulated as a TLP and sent to the intermediate node (for example, the third node).
  • the intermediate node can determine the destination address of the TLP by decapsulating the received TLP, so that the TLP can be forwarded without going through the root complex according to the destination address of the TLP.
  • the communication between the end nodes, the communication between the switching nodes, and the communication between the end nodes and the switching nodes in the PCIe system can be realized without the root complex, and the direct communication between the nodes can be realized, which can reduce The complexity of communication between nodes in the PCIe system.
  • the root complex writes the identity information of the destination node into the first node, and allocates the first memory address to the first node, so that the first node supports both the first working mode and the second working mode. Compatibility of various working modes. When two nodes communicate, you can choose a data transmission link that passes through the root complex, or you can choose a data transmission link that does not pass through the root complex, thereby realizing the redundant backup of the data transmission link in the PCIe system and improving This improves the stability of data transmission in the PCIe system. For example, if the root complex fails, the node can choose to communicate directly with other nodes without going through the data transmission link of the root complex.
  • the root complex can write the identity information of the destination node corresponding to the node in the PCIe system to the node, so that the intermediate node can determine the destination address of the received TLP.
  • this embodiment of the present application provides another PCIe-based communication method. Through this method, the intermediate node can perform the TLP on the TLP according to the destination address of the received TLP without going through the root complex. Forwarding to achieve direct communication between nodes.
  • FIG. 11 is a flowchart of a PCIe-based communication method provided by an embodiment of this application. The method can be applied to the PCIe system in the in-car network, especially the in-vehicle network of an autonomous vehicle.
  • PCIe system for other devices.
  • this method can be applied to the PCIe system 100 shown in FIG. 1 or FIG. 2.
  • the method will be introduced by taking the method applied to the root complex in the PCIe system 100 as an example.
  • the root complex reads the information stored in the third node.
  • the root complex can read the information stored in the third node when the PCIe system 100 is initialized, or it can read the information stored in the third node when the third node needs to forward the first data. This embodiment of the application does not limit this.
  • the third node is the node experienced by the first data to the destination node.
  • the third node may be a switching node or a function in a switching node in the PCIe system 100.
  • the third node may be the bridge node 4 or the switching node 1.
  • the information stored in the third node may be information of the configuration space of the third node.
  • the root complex reads the information stored in the third node, and can determine the working mode supported by the third node based on the stored information.
  • the reserved space of the configuration space of the third node may store indication information, and the indication information is used to indicate the working mode supported by the third node. Then the root complex can read the reserved space of the configuration space of the third node, so as to determine the working mode supported by the third node according to the read instruction information.
  • the reserved space is the unused storage address in the configuration space
  • the working mode supported by the third node includes the first working mode and the second working mode
  • the first working mode is that the communication between the node and the node does not go through the root compound
  • the second working mode is the working mode in which the communication between nodes needs to go through the root complex.
  • the third node supporting the first working mode includes the third node supporting only the first working mode, or the third node supporting the first working mode and the second working mode.
  • the root complex may allocate a second memory address to the third node, and write the second memory address to the third node.
  • the second memory address refers to a physical address mapped from the local memory space of the first node to the running memory corresponding to the CPU.
  • the root complex maps the local memory space of the third node to the running memory corresponding to the CPU to obtain the second memory address.
  • the root complex writes the second memory address to the third node, for example, writes the second memory address to the register of the third node, or writes the second memory address to the information stored in the third node, or writes the second memory address to the information stored in the third node. 2.
  • the memory address is written into the variable in the third node, or the second memory address is written into the parameter in the third node, etc.
  • the root complex when it is determined that the third node supports the first working mode, the root complex writes the identity information of the destination node corresponding to the third node into the third node.
  • the root complex may determine the destination node corresponding to the third node according to the function of each node in the PCIe system 100, and then the root complex writes the identity information of the destination node corresponding to the third node into the third node. If it is determined that there are multiple destination nodes corresponding to the third node, the root complex can write the identity information of each of the multiple destination nodes into the third node.
  • the root complex writes the identity information of the destination node corresponding to the third node into the third node, for example, writes the identity information of the destination node corresponding to the third node into the information stored in the third node, or The identity information of the destination node corresponding to the node is written into the variable in the third node, or the identity information of the destination node corresponding to the third node is written into the parameter of the third node, etc.
  • the root complex writes the identity information of the destination node corresponding to the third node into the reserved space of the configuration space of the third node.
  • the root complex when it is determined that the third node supports the first working mode, the root complex writes the identity information of the third node into the third node.
  • the third node can carry the identity information of the third node in the sent or forwarded TLP, so that the destination node determines that the sending node of the TLP is the third node according to the source address.
  • the third node may also determine whether to discard the received TLP according to whether the destination address carried by the received TLP is consistent with the identity information of the third node.
  • the root complex writes the identity information of the third node into the third node, for example, writes the identity information of the third node into the information stored in the third node, or writes the identity information of the third node into the third node. Variables in the node, or parameters for writing the identity information of the third node into the third node, etc. For example, the root complex writes the identity information of the third node into the reserved space of the configuration space of the third node.
  • the root complex determines the working mode supported by the third node according to the information stored in the third node. If the root complex determines that the third node supports the first working mode, S1102 to S1103 are executed; if the root complex determines that the third node does not support the first working mode, the process ends.
  • the root complex can determine the routing table information of the third node according to the identity information or functions of each node in the PCIe system 100.
  • the routing table information includes the identity information of the second node and the identity information of the next hop node to the second node.
  • the routing table information of the third node may be the bus number of the third node.
  • the third node determines the next hop node of the TLP according to the bus number of the third node and the bus number of the destination node. For example, if the bus number of the destination node is greater than the largest bus number in the branch where the third node is located, the third node discards the TLP.
  • the third node determines that the next hop node of the TLP is the third node's The node attached to the downstream bus.
  • the routing table information of the third node can be a range of ID numbers, which covers the IDs of all nodes linked to the third node No. For example, the root complex assigns identity information to each node in order according to the depth-first principle.
  • the third node can determine the next hop node of the TLP according to whether the ID number of the destination node is within the ID range. For example, if the ID number of the destination node is not within the ID range, the third node discards the TLP; if the ID number of the destination node is within the ID range, the third node determines that the next hop node of the TLP is the third node. The node attached to the node.
  • the routing table information of the third node may include the ID number of at least one node linked to the third node, and the The ID number of at least one destination node corresponding to each node, and the ID number of the next hop node that reaches at least one destination node.
  • the node hanging under bridge node 4 is end node 1
  • the destination node corresponding to end node 1 includes end node 2 and end node 3.
  • the hop node is bridge node 5, and the next hop node for data from bridge node 4 to end node 3 is bridge node 3.
  • the routing table information of the bridge node 4 includes the ID number of the end node 1, the ID number of the end node 2, the ID number of the bridge node 5, the ID number of the end node 3, and the ID number of the bridge node 3.
  • S1103 The root complex writes routing table information to the third node.
  • the root complex writes the routing table information to the third node, for example, it writes the routing table information to the information stored in the third node, or it writes the routing table information to the variables in the third node, or the routing table information Write the parameters in the third node, etc.
  • the root complex writes routing table information into the reserved space of the configuration space of the third node.
  • process shown in FIG. 11 can be realized by the root complex, or by the chip in the root complex, or by other devices, such as by the third node.
  • the embodiment of the application does not limit this.
  • the third node determines that it supports the first working mode; the third node sends broadcast signals to other nodes in the PCIe system 100 to obtain other nodes.
  • the root complex writes routing table information into the intermediate node (for example, the third node), so that the intermediate node can use the routing table information without going through the root complex according to the destination address in the received TLP and the routing table information.
  • the received TLP is forwarded in an individual manner. In this way, the communication between the end nodes, the communication between the switching nodes, and the communication between the end nodes and the switching nodes in the PCIe system can be realized without the root complex, and the direct communication between the nodes can be realized, which can reduce The complexity of communication between nodes in the PCIe system.
  • the root complex can traverse all nodes in the PCIe system 100 according to the principle of depth first, and assign identity information to all nodes according to the process shown in FIG. 3; for the PCIe system 100 that supports the first working mode, or Each node of at least one node that supports the first working mode and the second working mode writes the identity information of the node and the identity information of the at least one destination node corresponding to the node; and then according to the PCIe system 100 Identify the identity information of all nodes, determine the routing table information of the bridge node, and write the routing table information into the bridge node.
  • the root complex writes the identity information of the destination node to the sending node, and writes routing table information to the intermediate node. According to the identity information of the destination node and the routing table information, the inter-node can be realized. Communication without going through the root complex.
  • the embodiment of the present application provides another PCIe-based communication method, which can realize direct communication between nodes.
  • FIG. 12 is a flowchart of a PCIe-based communication method provided by an embodiment of this application. The method can be applied to the PCIe system in the in-car network, especially the in-vehicle network of an autonomous vehicle. Of course, it can also be applied. PCIe system for other devices.
  • this method can be applied to the PCIe system 100 shown in FIG. 1 or FIG. 2.
  • the method will be introduced by taking the first node as the end node 1, the second node as the end node 2, the third node as the bridge node 4, and the fourth node as the bridge node 5 as an example.
  • S1201 The first node determines the identity information of the second node.
  • the first node may determine the identity information of the second node according to the information stored in the first node.
  • the stored information is configuration information, or variables, or parameters.
  • the first node may determine the identity information of the second node according to the reserved space of the configuration space of the first node.
  • the second node is the destination node of the first data, the first node supports the first working mode, or the first node supports the first working mode and the second working mode.
  • the first working mode is a working mode in which the communication between nodes does not pass through the root complex
  • the second working mode is a working mode in which the communication between nodes needs to pass through the root complex.
  • the first node When the first node supports the second working mode, the first node stores the memory address allocated by the root complex. For example, the memory address is stored in the register of the first node.
  • S1202 The first node sends a TLP to the third node, and the third node receives the TLP.
  • the TLP may include the first data and the identity information of the second node.
  • the TLP may include the first data, the identity information of the first node, and the identity information of the second node.
  • the first node may determine the identity information of the first node according to the information stored in the first node, and then encapsulate the identity information of the first node, the first data, and the identity information of the second node into the TLP together.
  • the identity information as BDF as an example, if the length of the TLP header of the TLP is 12 bytes, Byte8 ⁇ Byte11 in the TLP header can be used to indicate the BDF of the first node and the BDF of the second node, as shown in Figure 17.
  • S1203 The third node determines the first routing table information.
  • the third node may determine the first routing table information according to the information stored in the third node.
  • the stored information is configuration information, or variables, or parameters.
  • the third node may determine the first routing table information according to the reserved space of the configuration space of the third node.
  • the first routing table information may include the identity information of the second node and the identity information of the fourth node. Wherein, the third node supports the first working mode, or the third node supports the first working mode and the second working mode.
  • the third node When the third node supports the second working mode, the third node stores the memory address allocated by the root complex. For example, the memory address is stored in the register of the third node.
  • S1204 The third node determines the first routing path according to the first routing table information.
  • the third node may determine the first routing path according to the first routing table information and the identity information of the second node, and the first routing path is used to indicate that the next hop node of the TLP is the fourth node.
  • S1205 The third node sends a TLP to the fourth node, and the fourth node receives the TLP.
  • the TLP may include the first data, the identity information of the first node, and the identity information of the second node.
  • the TLP may include the first data, the identity information of the third node, and the identity information of the second node.
  • the third node may determine the identity information of the third node according to the information stored in the third node, and then encapsulate the identity information of the third node into the TLP.
  • S1206 The fourth node determines the second routing table information.
  • the fourth node may determine the first routing table information according to the information stored in the fourth node.
  • the stored information is configuration information, or variables, or parameters.
  • the fourth node may determine the second routing table information according to the reserved space of the configuration space of the fourth node.
  • the second routing table information may include the identity information of the second node.
  • the fourth node When the fourth node supports the second working mode, the fourth node stores the memory address allocated by the root complex. For example, the memory address is stored in the register of the fourth node.
  • the fourth node determines the second routing path according to the second routing table information.
  • the fourth node may determine the second routing path according to the second routing table information and the identity information of the second node, where the second routing path is used to indicate that the next hop node of the TLP is the second node.
  • S1208 The fourth node sends a TLP to the second node, and the second node receives the TLP.
  • the TLP may include the first data, the identity information of the first node, and the identity information of the second node.
  • the TLP may include the first data, the identity information of the third node, and the identity information of the second node.
  • the TLP may include the first data, the identity information of the fourth node, and the identity information of the second node.
  • the fourth node may determine the identity information of the fourth node according to the information stored in the fourth node, and then encapsulate the identity information of the fourth node into the TLP.
  • the second node After receiving the TLP, the second node decapsulates the TLP to obtain the first data sent by the first node.
  • the sending node determines the identity information of the receiving node (for example, the second node) through stored information, and then encapsulates the first data and the identity information of the receiving node together and sends them to the intermediate node (For example, the third node), so that the intermediate node forwards the first data to the receiving node.
  • the communication between the end nodes, the communication between the switching nodes, and the communication between the end nodes and the switching nodes in the PCIe system can be realized without the root complex, and the direct communication between the nodes can be realized, which can reduce The complexity of communication between nodes in the PCIe system.
  • an embodiment of the present application provides a PCIe-based communication device.
  • the structure diagram of the device may be as shown in FIG. 13, and includes a processing unit 1301.
  • the communication device 1300 can be specifically used to implement the method executed by the root complex in the embodiment of FIG. 10 and FIG. Perform part of the related method function.
  • the processing unit 1301 is configured to write the identity information of the second node into the first node, and write the routing table information into the third node.
  • the first node is the source node of the first data
  • the second node is the source node of the first data.
  • the destination node, and the third node is the node through which the first data goes to the second node.
  • the processing unit 1301 is further configured to determine that the first node supports the first operating mode; or, determine that the first node supports the first operating mode and the second operating mode; wherein, the first operating mode is The communication between the nodes does not go through the working mode of the root complex, and the second working mode is that the communication between the nodes needs to go through the working mode of the root complex.
  • the processing unit 1301 is further configured to configure a first memory address for the first node when the first node is in the second working mode, where the first memory address is the local memory space of the first node Mapped to the physical address in the running memory corresponding to the CPU.
  • the processing unit 1301 is further configured to determine that the third node supports the first operating mode; or, determine that the third node supports the first operating mode and the second operating mode; wherein, the first operating mode is The communication between the nodes does not go through the working mode of the root complex, and the second working mode is that the communication between the nodes needs to go through the working mode of the root complex.
  • the processing unit 1301 is further configured to configure a second memory address for the third node when the third node is in the second working mode, and the second memory address is the local memory space mapping of the third node To the physical address in the running memory corresponding to the CPU.
  • the processing unit 1301 is further configured to write the identity information of the first node into the first node.
  • the processing unit 1301 is further configured to write the identity information of the third node into the third node.
  • the identity information is a BDF, or an ID number.
  • the division of modules in the embodiments of this application is illustrative, and it is only a logical function division. In actual implementation, there may be other division methods.
  • the functional modules in the various embodiments of this application can be integrated into one process. In the device, it can also exist alone physically, or two or more modules can be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It can be understood that the function or implementation of each module in the embodiment of the present application may further refer to the related description of the method embodiment.
  • the communication device 1400 may be as shown in FIG. 14, and the device 1400 may be an end node or a chip in an end node.
  • the apparatus 1400 may include a processor 1401.
  • the processing unit 1301 may be a processor 1401.
  • the device 1400 may further include a transceiver 1402 and a memory 1403.
  • the processor 1401 may be a CPU or a digital processing unit.
  • the transceiver 1402 may be a communication interface, an interface circuit such as a transceiver circuit, etc., or a transceiver chip.
  • the device 1400 further includes: a memory 1403, configured to store a program executed by the processor 1401.
  • the memory 1403 may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., and may also be a volatile memory, such as random access memory (random access memory). -access memory, RAM).
  • the memory 1403 is any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.
  • the processor 1401 is configured to execute the program code stored in the memory 1403, and is specifically configured to execute the actions of the above-mentioned processing unit 1301, which will not be repeated in this application.
  • the embodiment of the present application does not limit the specific connection medium between the transceiver 1402, the processor 1401, and the memory 1403.
  • the memory 1403, the processor 1401, and the transceiver 1402 are connected by a bus 1404.
  • the bus is represented by a thick line in FIG. , Is not limited.
  • the bus 1404 can be divided into an address bus, a data bus, a control bus, and so on. For ease of representation, only one thick line is used in FIG. 14, but it does not mean that there is only one bus or one type of bus.
  • the embodiment of the present application provides a PCIe-based communication device 1500.
  • the structure of the device 1500 may be as shown in FIG. 15, including a processing unit 1501 and a transceiver unit 1502.
  • the communication device 1500 can implement the method executed by the first node in the embodiment of FIG. Part.
  • the processing unit 1501 is configured to determine the identity information of the second node according to the information stored in the first node, and the second node is the destination node of the first data; the transceiver unit 1502 is configured to send the first node to the third node.
  • TLP the first TLP includes the first data and the identity information of the second node.
  • the first node supports the first working mode
  • the first working mode is a working mode in which the communication between the node and the node does not pass through the root complex.
  • the first node supports the first working mode and the second working mode
  • the first working mode is the working mode in which the communication between the nodes does not go through the root complex
  • the second working mode is the node The communication with the node needs to go through the working mode of the root complex.
  • the stored information further includes the identity information of the first node.
  • the first TLP further includes the identity information of the first node.
  • the identity information is a BDF, or an ID number.
  • the division of modules in the embodiments of this application is illustrative, and it is only a logical function division. In actual implementation, there may be other division methods.
  • the functional modules in the various embodiments of this application can be integrated into one process. In the device, it can also exist alone physically, or two or more modules can be integrated into one module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It can be understood that the function or implementation of each module in the embodiment of the present application may further refer to the related description of the method embodiment.
  • the communication device 1600 may be as shown in FIG. 16, and the device 1600 may be an end node or a chip in an end node, or may be a switching node or a chip in a switching node.
  • the apparatus 1600 may include a processor 1601, a transceiver 1602, and a memory 1603.
  • the processing unit 1501 may be a processor 1601.
  • the transceiver unit 1502 may be a transceiver 1602.
  • the processor 1601 may be a CPU or a digital processing unit.
  • the transceiver 1602 may be a communication interface, an interface circuit such as a transceiver circuit, etc., or a transceiver chip.
  • the device 1600 further includes: a memory 1603, configured to store a program executed by the processor 1601.
  • the memory 1603 may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., and may also be a volatile memory, such as a random access memory (random access memory). -access memory, RAM).
  • the memory 1603 is any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.
  • the processor 1601 is configured to execute the program code stored in the memory 1603, and is specifically configured to execute the actions of the aforementioned processing unit 1501, which will not be repeated in this application.
  • the transceiver 1602 is specifically configured to perform the actions of the above-mentioned transceiver unit 1502, which will not be repeated in this application.
  • connection medium between the foregoing transceiver 1602, the processor 1601, and the memory 1603 is not limited in the embodiment of the present application.
  • the memory 1603, the processor 1601, and the transceiver 1602 are connected by a bus 1604.
  • the bus is represented by a thick line in FIG. 16, and the connection modes between other components are merely illustrative. , Is not limited.
  • the bus 1604 can be divided into an address bus, a data bus, a control bus, and so on. For ease of representation, only one thick line is used in FIG. 16, but it does not mean that there is only one bus or one type of bus.
  • the embodiments of the present application also provide a computer-readable storage medium for storing computer software instructions required to execute the above-mentioned processor, which contains a program required to execute the above-mentioned processor.
  • this application can be provided as methods, systems, or computer program products. Therefore, this application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

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Abstract

一种基于PCIe的通信方法及装置，包括：根复合体将第二节点的身份信息写入第一节点，将路由表信息写入第三节点，第一节点为第一数据的源节点，第二节点为第一数据的目的节点，第三节点为第一数据到第二节点所经历的节点。通过将数据的目的节点的身份信息写入发送节点，发送节点在发送数据时就可以携带该数据的目的节点的身份信息。通过将路由表信息写入中间节点，中间节点在接收到该数据时可以根据目的节点的身份信息以及路由表信息，确定路由路径，并基于该路由路径将数据转发给目的节点。这样就可以使得PCIe系统中节点之间的通信不经过根复合体，实现节点之间的直接通信，从而可以降低PCIe系统中各节点之间的通信复杂度。

Description

一种基于PCIe的通信方法及装置 技术领域
本申请涉及通信技术领域，尤其涉及一种基于外围组件互连传递(peripheral component interconnect express，PCIe)的通信方法及装置。
背景技术
PCIe系统的主要组成单元包括根复合体(root complex，Root)、交换节点(switch)以及端节点(endpoint)等。其中，根复合体用于管理PCIe系统中的所有总线和所有节点，是PCIe系统中节点与节点之间通信的桥梁；一个PCIe系统可以包括一个或多个交换节点，交换节点是PCIe系统中数据的转发节点，一个交换节点可以连接根复合体、其他交换节点或端节点中的一种或多种；端节点为端设备，例如外围设备(peripheral)等，用于接收来自其他节点或根复合体的数据，或向其他节点或根复合体发送数据。
在PCIe系统中，只有根复合体以及节点(例如端节点或交换节点)自身有权限读取该节点的配置空间，其中，一个节点的配置空间用于存储该节点的功能信息或地址等信息，如该当前节点是存储设备，PCIe系统中的其他节点均无权读取该节点的配置空间。例如对于PCIe系统的节点1来说，只有根复合体以及节点1有权限读取节点1的配置空间，而对于PCIe系统中除了节点1之外的其他节点，均无权读取节点1的配置空间。这意味着，在PCIe系统中只有根复合体能够知道各节点的功能或地址等信息。因此，端节点与端节点之间、交换节点与交换节点之间、以及端节点与交换节点之间无法实现直接通信，必须经过根复合体。由于PCIe系统中节点与节点之间的通信必须经过根复合体，这样会大幅度提升节点与节点之间的通信复杂度。
发明内容
本申请实施例提供一种基于PCIe的通信方法及装置，用以使得PCIe系统中的节点与节点之间的通信不经过根复合体，从而可以降低节点与节点之间的通信复杂度。
第一方面，本申请实施例提供一种基于PCIe的通信方法，包括：根复合体将第二节点的身份信息写入第一节点，将路由表信息写入第三节点，其中，第一节点为第一数据的源节点，第二节点为第一数据的目的节点，第三节点为第一数据到第二节点所经历的节点。
在一种可能的设计中，第一方面所述的方法可以由根复合体自身执行，或者可以由根复合体中的芯片执行等。
在本申请实施例中，通过将数据的目的节点的身份信息写入发送节点(例如第一节点)，发送节点在发送数据时就可以携带该数据的目的节点的身份信息。通过将路由表信息写入中间节点(例如第三节点)，中间节点在接收到该数据时可以根据目的节点的身份信息以及路由表信息，确定路由路径，并基于该路由路径可以将数据发送给目的节点(例如第二节点)。这样就可以使得PCIe系统中的端节点之间的通信、交换节点之间的通信、以及端节点与交换节点之间的通信等可以不经过根复合体，实现节点之间的直接通信，从而可以降低PCIe系统中各节点之间的通信复杂度。
在一种可能的设计中，根复合体确定第一节点支持第一工作模式；或者，确定所第一节点支持第一工作模式和第二工作模式；其中，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。在上述设计，第一节点仅支持第一工作模式时，可以实现节点与节点之间的通信不经过根复合体，从而降低PCIe系统中各节点的通信复杂度；第一节点既支持第一工作模式又支持第二工作模式时，既可以实现节点与节点之间的通信不经过根复合体，以降低PCIe系统中各节点的通信复杂度，也可以根据目前的通信方式进行通信，具有兼容性。
在一种可能的设计中，在第一节点处于第二工作模式时，根复合体为第一节点配置第一内存地址，该第一内存地址为第一节点的本地内存空间映射到中央处理器(central processing unit，CPU)对应的运行内存中的物理地址。在上述设计中，通过为第一节点配置第一内存地址，可以使得第一节点按照目前的通信方式进行通信，实现了两种工作模式的兼容。
在一种可能的设计中，根复合体确定第三节点支持第一工作模式；或者，确定第三节点支持第一工作模式和第二工作模式；其中，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。在上述设计，第三节点仅支持第一工作模式时，可以实现节点与节点之间的通信不经过根复合体，从而降低PCIe系统中各节点的通信复杂度；第三节点既支持第一工作模式又支持第二工作模式时，既可以实现节点与节点之间的通信不经过根复合体，以降低PCIe系统中各节点的通信复杂度，也可以按照目前的通信方式进行通信，具有兼容性。
在一种可能的设计中，在第三节点处于第二工作模式时，根复合体为第三节点配置第二内存地址，第二内存地址为第三节点的本地内存空间映射到CPU对应的运行内存中的物理地址。在上述设计中，通过为第三节点配置第二内存地址，可以使得第三节点按照目前的通信方式进行通信，实现了两种工作模式的兼容。
在一种可能的设计中，根复合体将第一节点的身份信息写入第一节点。在上述设计中，通过将第一节点的身份信息写入第一节点，可以将第一节点的身份信息发送给数据的目的节点，以便目的节点确认该数据的源节点的信息；还可以对接收到的数据进行验证，以确定接收到的数据是否为发送给本节点的数据。
在一种可能的设计中，根复合体将第三节点的身份信息写入第三节点。在上述设计中，通过将第三节点的身份信息写入第三节点，可以将第三节点的身份信息发送给数据的目的节点，以便目的节点确认该数据的源节点的信息；还可以对接收到的数据进行验证，以确定接收到的数据是否为发送给本节点的数据。
在一种可能的设计中，该身份信息是总线号、设备号和功能号(bus、device and function number，BDF)，或者是身份标识(identity，ID)号。在上述设计中，身份信息可以是根复合体为节点分配的唯一的BDF，或是根复合体重新为节点分配的唯一的ID号，以使各节点的身份信息具有唯一性。
第二方面，本申请实施例提供一种基于PCIe的通信方法，包括：第一节点根据第一节点中存储的信息，确定第二节点的身份信息，并向第三节点发送第一事务层包(transaction layer packet，TLP)，其中第二节点为第一数据的目的节点，第一TLP包括第一数据和第二节点的身份信息。
一种可能的设计中，第一节点可以是端节点、也可以是桥节点，第二节点可以是端节 点、也可以是桥节点，第三节点可以是桥节点。
本申请实施例中，发送节点(例如第一节点)通过存储的信息确定接收节点(例如第二节点)的身份信息，然后将第一数据和接收节点的身份信息一起封装后发送给中间节点(例如第三节点)，以使中间节点将第一数据转发给接收节点。这样就可以使得PCIe系统中的端节点之间的通信，交换节点之间的通信，以及端节点与交换节点之间的通信等可以不经过根复合体，实现节点之间的直接通信，从而可以降低PCIe系统中各节点之间的通信复杂度。
在一种可能的设计中，上述存储的信息可以是由根复合体配置的，或者其它网络节点配置的。
在一种可能的设计中，第一节点支持第一工作模式，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式。在上述设计中，第一节点支持第一工作模式，可以实现节点与节点之间的通信不经过根复合体，从而降低PCIe系统中各节点的通信复杂度。
在一种可能的设计中，第一节点支持第一工作模式和第二工作模式，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。在上述设计中，第一节点既支持第一工作模式又支持第二工作模式，既可以实现节点与节点之间的通信不经过根复合体，以降低PCIe系统中各节点的通信复杂度，也可以按照目前的通信方式进行通信，实现了两种工作模式的兼容。
在一种可能的设计中，存储的信息还包括第一节点的身份信息。在上述设计中，第一节点中存储的信息包括第一节点的身份信息，可以将第一节点的身份信息发送给数据的目的节点，以便目的节点确认该数据的源节点的信息；还可以对接收到的数据进行验证，以确定接收到的数据是否为发送给本节点的数据。
在一种可能的设计中，第一TLP还包括第一节点的身份信息。在上述设计中，将第一数据和第一节点的身份信息封装为第一TLP发送给目的节点，可以使得目的节点确认该数据的源节点的信息。
在一种可能的设计中，身份信息是BDF，或者是ID号。在上述设计中，身份信息可以是根复合体为节点分配的唯一的BDF，或是根复合体重新为节点分配的唯一的ID号，以使各节点的身份信息具有唯一性。
第三方面，本申请实施例提供一种基于PCIe的通信装置，该装置可以是通信设备，也可以是通信设备内的芯片或芯片组，其中，通信设备可以为根复合体或第一节点中的任一个，也就是说该通信设备可以是根复合体也可以是端节点还可以是交换节点。该装置可以包括处理单元。当该装置是通信设备时，该处理单元可以是处理器；该装置还可以包括收发模块和存储模块，该存储模块可以是存储器；该存储模块用于存储指令，该处理单元执行该存储模块所存储的指令，以使根复合体执行上述第一方面中相应的功能，或者，该处理单元执行该存储模块所存储的指令，以使第一节点执行上述第二方面中相应的功能。当该装置是通信设备内的芯片或芯片组时，该处理单元可以是处理器，该收发单元可以是输入/输出接口、管脚或电路等；该处理单元执行存储模块所存储的指令，以使根复合体执行上述第一方面中相应的功能，或者，该处理单元执行存储模块所存储的指令，以使第一节点执行上述第二方面中相应的功能。该存储模块可以是该芯片或芯片组内的存储模块(例如，寄存器、缓存等)，也可以是该网络设备内的位于该芯片或芯片组外部的存储模块(例如，只读存储器、随机存取存储器等)。
第四方面，本申请实施例提供一种基于PCIe的通信装置，包括：处理器，还可以包括通信接口和/或存储器。通信接口用于该装置与其他装置之间传输信息、和/或消息、和/或数据。该存储器用于存储计算机执行指令，当该装置运行时，该处理器执行该存储器存储的该计算机执行指令，以使该装置执行如上述第一方面或第一方面中任一设计、第二方面或第二方面中任一设计的通信方法。
第五方面，本申请实施例还提供一种计算机可读存储介质，计算机可读存储介质用于存储计算机指令，当计算机指令在计算机上运行时，使得计算机执行上述第一方面或第一方面中任意一种可能的设计、第二方面或第二方面中任意一种可能的设计的通信方法。
第六方面，本申请还提供一种包括指令的计算机程序产品，计算机程序产品用于存储计算机指令，当计算机指令在计算机上运行时，使得计算机执行上述第一方面或第一方面中任意一种可能的设计、第二方面或第二方面中任意一种可能的设计的通信方法。
第七方面，本申请还提供一种PCIe系统，该系统包括第一节点、第二节点、第三节点，例如，第一节点为端节点，第二节点为交换节点，第三节点为端节点，其中，第一节点可以执行上述第一方面中相应的功能，第二节点可以执行上述第二方面中相应的功能。
第八方面，本申请实施例提供的一种芯片，芯片包括至少一个处理器和通信接口，处理器与存储器耦合，用于读取存储器中存储的计算机程序以执行本申请实施例第一方面或第一方面中任一设计、第二方面或第二方面中任一设计的通信方法。
第九方面，本申请实施例提供一种芯片，包括通信接口和至少一个处理器，处理器运行以执行本申请实施例第一方面或第一方面中任意一种可能的设计、第二方面或第二方面中任意一种可能的设计的通信方法。
附图说明
图1为本申请实施例提供的一种PCIe系统的架构示意图；
图2为本申请实施例提供的另一种PCIe系统的架构示意图；
图3为本申请实施例提供的一种分配BDF的流程示意图；
图4为本申请实施例提供的一种TLP头的结构示意图；
图5为本申请实施例提供的另一种TLP头的结构示意图；
图6为本申请实施例提供的另一种TLP头的结构示意图；
图7为本申请实施例提供的另一种TLP头的结构示意图；
图8为本申请实施例提供的另一种TLP头的结构示意图；
图9为本申请实施例提供的另一种TLP头的结构示意图；
图10为本申请实施例提供的一种基于PCIe的通信方法的流程示意图；
图11为本申请实施例提供的另一种基于PCIe的通信方法的流程示意图；
图12为本申请实施例提供的另一种基于PCIe的通信方法的流程示意图；
图13为本申请实施例提供的一种基于PCIe的通信装置的结构示意图；
图14为本申请实施例提供的另一种基于PCIe的通信装置的结构示意图；
图15为本申请实施例提供的另一种基于PCIe的通信装置的结构示意图；
图16为本申请实施例提供的另一种基于PCIe的通信装置的结构示意图；
图17为本申请实施例提供的另一种TLP头的结构示意图；
图18为本申请实施例提供的另一种TLP头的结构示意图。
具体实施方式
为了使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施例作进一步地详细描述。
需要说明的是，本申请实施例中“多个”是指两个或两个以上，鉴于此，本申请实施例中也可以将“多个”理解为“至少两个”。“至少一个”，可理解为一个或多个，例如理解为一个、两个或更多个。例如，包括至少一个，是指包括一个、两个或更多个，而且不限制包括的是哪几个，例如，包括A、B和C中的至少一个，那么包括的可以是A、B、C、A和B、A和C、B和C、或A和B和C。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，字符“/”，如无特殊说明，一般表示前后关联对象是一种“或”的关系。
除非有相反的说明，本申请实施例提及“第一”、“第二”等序数词用于对多个对象进行区分，不用于限定多个对象的顺序、时序、优先级或者重要程度。
为便于技术人员理解，下面先结合附图对申请实施例所涉及的PCIe系统进行说明。
PCIe是一种高速短距离通信接口，广泛应用于计算机、测试仪器等设备中。PCIe可以快速读写内存，支持大宽带通信，一些车企将其传输距离加长，可以作为车内网大数据量通信接口。请参见图1，为本申请实施例提供的PCIe系统的一种结构示意图。如图1所示，PCIe系统可以包括一个根复合体(图1示出为根复合体)、至少一个交换节点(图1包括交换节点1)和至少一个端节点(图1中包括端节点1、端节点2以及端节点3)。
其中，根复合体负责管理PCIe系统100中的所有总线(图1中以粗黑色连线示出)、交换节点和端节点，是PCIe系统100中各节点间通信的桥梁，也是PCIe系统100中各节点与CPU通信的桥梁。交换节点作为桥梁连接根复合体、其他交换节点、以及端节点中的一种或多种，是数据转发的节点，例如，交换节点1连接根复合体、端节点1以及端节点2。端节点为端设备，如外围设备等，负责发送数据或者接收数据。
需要说明的是，CPU与根复合体之间的接口不是PCIe，不属于PCIe系统100。该CPU可以与PCIe系统100所在的实体(例如计算机设备，车辆等)建立连接关系，也可以与PCIe系统100位于同一个实体中，用于接收PCIe系统100中各节点发送的数据，还可以对接收到的数据进行处理，例如进行格式转换、图像渲染等。
PCIe系统100中一个设备(例如根复合体、交换节点1、端节点1、端节点2或端节点3)最多可以支持8个功能(function)，例如音频、视频等功能。其中，桥节点用于连接其它设备。在一个设备支持多个功能时，该设备的每个功能有自己的配置空间，配置空间存储着该功能的信息。该配置空间可以是设备的一段独立的存储单元，例如配置空间的大小可以是256k。根复合体有读写PCIe系统100中各设备配置空间的权限。例如，根复合体可以通过读取端节点1的配置空间中的信息，获取端节点1所支持的功能的信息。再例如，根复合体还可以通过写端节点1的配置空间，完成对该端节点1的初始化和配置。除根复合体之外的其他设备以及设备的功能只能看到自己配置空间的信息。
请参见图2，为PCIe系统100的另一种结构示意图。如图所示，根复合体所支持的功 能包括主桥节点(host bridge)、桥节点1和桥节点2，主桥节点、桥节点1和桥节点2通过总线((图2中以粗黑色连线示出))互相建立连接关系。交换节点1所支持的功能包括桥节点3、桥节点4和桥节点5，桥节点3、桥节点4和桥节点5通过总线互相建立连接关系。其中，主桥节点用于与CPU建立连接关系，桥节点1通过总线与交换节点1中的桥节点3建立连接关系，桥节点2通过总线与端节点3建立连接关系，桥节点4通过总线与端节点1建立连接关系，桥节点5通过总线与端节点2建立连接关系。
在PCIe系统100初始化时，根复合体需要对PCIe系统100中的总线、设备以及设备中的功能进行枚举遍历，以完成对各设备的初始化和配置。请参见图3，为根复合体分配BDF的流程示意图。
S1：根复合体将与主桥节点连接的总线设为Bus 0。
S2：根复合体通过Bus 0，发现桥节点1，为桥节点1分配总线号、设备号和功能号(bus device and function number，BDF)，并将桥节点1的下游总线设为Bus 1。
根复合体遍历与Bus 0连接的节点，首先发现桥节点1，然后按照深度优先规则遍历桥节点1的下游总线所连接的节点，并将该总线设为Bus 1。同时根复合体为桥节点1分配BDF。对于交换节点(或桥节点)而言，交换节点(或桥节点)的总线号包括该交换节点(或桥节点)的上游总线号，该交换节点(或桥节点)的下游总线号和该交换节点(或桥节点)所在分支的最大总线号。桥节点1的上游总线为Bus 0，桥节点1的下游总线号为Bus 1。由于桥节点1所在分支还未遍历完，桥节点1所在分支的最大总线号还不能确定，可以先将桥节点1所在分支的最大总线号暂时设为0xFF，桥节点1的总线号可以为0，1，0xFF。
需要注意的是，对于一个交换节点(或桥节点)而言，在为该交换节点(或桥节点)分配完BDF后，根复合体会将BDF中的总线号(bus number)写入该交换节点(或桥节点)，以便交换节点(或桥节点)根据该总线号进行ID路由。例如，根复合体可以将总线号写入该交换节点(或桥节点)的配置空间。再例如，该交换节点(或桥节点)接收到数据后，根复合体可以根据总线号以及目的节点的总线号，确定转发该数据的下一跳节点。根据总线号进行路由的具体实施方式可以参考现有技术，在此不再赘述。
S3：根复合体通过Bus 1，发现桥节点3，为桥节点3分配BDF，并将桥节点3的下游总线设为Bus 2。
根复合体遍历与Bus 1连接的节点，发现桥节点3，然后按照深度优先规则遍历桥节点3的下游总线所连接的节点，并将该总线设为Bus 2。同时根复合体为桥节点3分配BDF，其中，桥节点3的总线号可以为1，2，0xFF。
S4：根复合体通过Bus 2，发现桥节点4，为桥节点4分配BDF，并将桥节点4的下游总线设为Bus 3。
根复合体遍历与Bus 2连接的节点，首先发现桥节点4，然后按照深度优先规则遍历桥节点4的下游总线所连接的节点，并将该总线设为Bus 3。同时根复合体为桥节点4分配BDF，其中，桥节点4的总线号可以为2，3，0xFF。
S5：根复合体通过Bus 3，发现端节点1，并为端节点1分配BDF。
根复合体遍历与Bus 3连接的节点，发现端节点1，然后根复合体为端节点1分配BDF。对于端节点(或端节点的功能)而言，端节点(或端节点的功能)的总线号包括该端节点(或端节点的功能)的上游总线号。端节点1的上游总线为Bus 3，故端节点1的总线号 可以为3。
需要说明的是，对于端节点(或端节点的功能)而言，在为该端节点(或端节点的功能)分配完BDF后，根复合体不会将端节点(或端节点的功能)的BDF写入该端节点(或端节点的功能)。端节点(或端节点的功能)的BDF由根复合体管理，该端节点(或端节点的功能)并不知道自身的BDF。
至此，桥节点4所在分支遍历完毕。根复合体确定桥节点4所在分支的最大总线号为3，并更新桥节点4所在分支中各节点的总线号。在更新后，桥节点4的总线号为2，3，3；端节点1的总线号为3。
S6：根复合体通过Bus 2，发现桥节点5，为桥节点5分配BDF，并将桥节点5的下游总线设为Bus 4。
根复合体遍历完桥节点4所在的分支后，通过Bus 2，发现桥节点5，然后按照深度优先规则遍历桥节点5的下游总线所连接的节点，并将该总线设为Bus 4。同时根复合体为桥节点5分配BDF，其中，桥节点5的总线号可以为2，4，0xFF。
S7：根复合体通过Bus 4，发现端节点2，并为端节点2分配BDF。
根复合体遍历与Bus 4连接的节点，发现端节点2，然后根复合体为端节点2分配BDF，其中，端节点2的总线号可以为4。
至此，桥节点5所在分支遍历完毕，根复合体确定桥节点5所在分支的最大总线号为4，并更新桥节点5所在分支中各节点的总线号。在更新后，桥节点1的总线号为0，1，4；桥节点3的总线号为1，2，4；桥节点5的总线号为2，4，4；端节点2的总线号为4。
S8：根复合体通过Bus 0，发现桥节点2，为桥节点2分配BDF，并将与桥节点2的下游总线设为Bus 5。
根复合体遍历完桥节点1所在的分支后，通过Bus 0，发现桥节点2，然后按照深度优先规则遍历桥节点2的下游总线所连接的节点，并将该总线设为Bus 5。同时根复合体为桥节点2分配BDF，其中，桥节点2的总线号可以为0，5，0xFF。
S9：根复合体通过Bus 5，发现端节点2，并为端节点2分配BDF。
根复合体遍历与Bus 5连接的节点，发现端节点2，然后根复合体为端节点2分配BDF，其中，端节点的总线号可以为5。
至此，桥节点2所在分支遍历完毕。根复合体确定桥节点2所在分支的最大总线号为5，并更新桥节点2所在分支中各节点的总线号。在更新后，桥节点2的总线号为0，5，5；端节点2的总线号为5。
通过图3所示的流程，根复合体可以为PCIe系统100中的所有节点分配BDF，并将交换节点(或桥节点)的总线号写入该交换节点(或桥节点)以进行ID路由。
在PCIe系统中，各节点之间通过PCIe接口传输数据，PCIe协议中将用于传输数据的数据包称为事务层包(transaction layer packet，TLP)。PCIe系统支持三种路由方式进行通信：地址路由，身份标识(identity，ID)路由以及隐式路由。不同路由方式，TLP头(TLP Header)中填写的路由地址不同。在TLP头的长度为12字节(Byte)时，与路由方式相关的字段为Byte8～Byte11，如图4所示。在TLP头的长度为16字节时，与路由方式相关的字段为Byte8～Byte15，如图5所示。
下面分别对PCIe系统支持的三种路由方式进行介绍。
1)地址路由是指，根据内存地址进行路由的方式。该内存地址是节点的本地内存空 间映射到CPU对应的运行内存中的物理地址。其中，内存地址包括32位的内存地址和64位的内存地址。不同的内存地址需要使用不同的TLP头。例如，32位的内存地址需要使用长度为12字节的TLP头，TLP头中的Byte8～Byte11用于指示32位的内存地址，如图6所示。再例如，64位的内存地址需要使用长度为16字节的TLP头，TLP头中的Byte8～Byte11用于指示高32位的内存地址，TLP头中的Byte12～Byte15用于指示低32位的内存地址，如图7所示。
PCIe系统中节点的内存地址是由根复合体配置的，并写入各节点的寄存器(例如bar)中。PCIe系统中的节点本身有本地内存空间，该本地内存空间是开放给CPU的，但是CPU只能直接访问CPU对应的运行内存，不能直接访问节点的本地内存空间。因此，根复合体可以将节点本地内存空间映射到CPU对应的运行内存，得到内存地址，从而根复合体可以根据该内存地址访问节点的本地内存空间，即实现根复合体与节点之间的通信。
在采用地址路由时，交换节点(或桥节点)的路由表信息为CPU对应的运行内存范围，该CPU对应的运行内存范围覆盖该交换节点(或桥节点)下挂的所有节点的内存地址，而下挂节点的内存地址只有下挂节点自身以及根复合体知道，下挂节点的本地内存空间与CPU对应的运行内存间之间的映射关系也只有根复合体知道，该交换节点(或桥节点)并不清楚。因此，当两个节点之间经过交换节点(或桥节点)进行数据传输时，该交换节点(或桥节点)并不清楚将数据转发给下挂的哪个节点，所以需经过交换节点(或桥节点)的两个节点之间通信必须经过根复合体。因此，该地址路由只支持数据由根复合体发送到节点，或者数据由节点发送到根复合体。而对于节点与节点之间的通信，必须经过根复合体。
2)ID路由是指，根据BDF进行路由的方式。ID路由方式包括两种TLP头。例如，可以使用长度为12字节的TLP头，TLP头中的Byte8～Byte11中的部分字节用于指示BDF，如图8所示。再例如，可以使用长度为16字节的TLP头，TLP头中的Byte8～Byte11中的部分字节用于指示BDF，图9所示。各节点的BDF是由根复合体为节点配置的BDF，节点的BDF只有根复合体知道，节点本身或其他节点是不知道的。该ID路由方式通常仅用于根复合体向节点发送配置消息，以及节点向根复合体发送配置响应消息。因此，ID路由只支持从根复合体到节点的通信，或者从节点到根复合体的通信。而对于节点与节点之间的通信，该ID路由方式并不支持。
3)隐式路由是指，不使用地址路由或ID路由的其他路由方式。该隐式路由用于向根复合体发送数据，节点发送的TLP是默认发送给，默认将该TLP转发给根复合体。因此，隐式路由仅用于从节点到根复合体的通信。
目前PCIe系统所支持的三种路由方式，端节点与端节点之间、交换节点与交换节点之间、以及端节点与交换节点之间，均不能直接通信。如果两个节点要进行通信，则必须经过根复合体。PCIe系统中节点之间必须通过根复合体通信的工作机制，会导致PCIe系统中节点与节点之间的通信复杂度大幅度提升。如图1或图2中，虽然端节点1与端节点2连接在交换节点1上，但两者是不能直接通过交换节点1通信的，端节点1必须先同根复合体通信，经根复合体才能找到端节点2，或者端节点2必须先同根复合体通信，经根复合体才能找到端节点1。例如，端节点1向端节点2发送数据，具体过程可以是：端节点1将数据发送给交换节点1，交换节点1将该数据发送给根复合体，根复合体再通过交 换节点1将该数据发送给端节点2。
鉴于此，本申请实施例提供一种基于PCIe的通信方法及装置，用于使得PCIe系统中节点与节点间的通信不经过根复合体，从而能降低PCIe系统中各节点之间的通信复杂度。
请参见图10，为本申请实施例提供的一种基于PCIe的通信方法的流程图，该方法可以应用于车内网中的PCIe系统，特别是自动驾驶汽车的车内网，当然也可以应用于其他设备的PCIe系统。例如，该方法可以应用于图1或图2所示的PCIe系统100。下面以将该方法应用于PCIe系统100中的根复合体为例，对该方法进行介绍。
S1001：根复合体读取第一节点中存储的信息。
在具体实施时，根复合体可以在PCIe系统100初始化时读取第一节点中存储的信息，也可以在检测到第一节点有发送第一数据的需求时读取第一节点中存储的信息。该存储的信息可以是由根复合体配置的，或者由其他节点配置的，或者由人工配置的等，本申请实施例对此不作限定。
其中，第一数据为第一节点发送给第二节点的数据，即第一节点是该第一数据的源节点。该第一节点可以是PCIe系统100中的端节点或端节点的功能，也可以是PCIe系统100中的交换节点或交换节点中的功能。例如，第一节点可以是端节点1，也可以是桥节点4。第一节点中存储的信息可以是第一节点的配置空间的信息。一个节点的配置空间可以为一段物理存储地址，用于存储配置信息。
根复合体读取第一节点中存储的信息，根据该信息可以确定第一节点所支持的工作模式。例如，第一节点的配置空间的预留空间可以存储指示信息，该指示信息用于指示第一节点所支持的工作模式。则根复合体可以读取第一节点的配置空间中的预留空间，从而根据读取的指示信息确定第一节点支持的工作模式。其中，预留空间为配置空间中未使用的存储地址。第一节点所支持的工作模式包括第一工作模式和第二工作模式，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。
进一步地，根复合体根据第一节点中存储的信息确定第一节点支持的工作模式。如果根复合体确定第一节点仅支持第一工作模式，则仅执行S1002；如果根复合体确定第一节点仅支持第二工作模式，则执行S1003～S1004；如果根复合体确定第一节点支持第一工作模式和第二工作模式，则执行S1002～S1004。
S1002：在确定第一节点支持第一工作模式时，根复合体将第二节点的身份信息写入第一节点。
根复合体在确定第一节点支持第一工作模式后，根复合体将第一节点对应的目的节点(例如称为第二节点)的身份信息写入第一节点。具体地，根复合体可以先确定第一节点对应的目的节点，然后根复合体可以将第一节点对应的目的节点的身份信息写入第一节点。例如，根复合体可以根据第一数据的类型(例如视频类型或图像类型等)以及PCIe系统100中各节点的功能，来确定第一数据的目的节点。例如，第一节点是端节点1，第一数据的类型是视频类型，端节点2为显示器，端节点3为存储器，根复合体可以确定第一数据的目的节点为端节点2。根复合体将第二节点的身份信息写入第一节点，例如是将第二节点的身份信息写入第一节点中存储的信息，或者是将第二节点的身份信息写入第一节点中的变量，或者是将第二节点的身份信息写入第一节点中的参数等。例如，根复合体将第二节点的身份信息写入第一节点的配置空间的预留空间。
其中，第二节点是第一数据的目的节点。第二节点可以是PCIe系统100中的端节点或端节点的功能，也可以是PCIe系统100中的交换节点或交换节点中的功能。PCIe系统100中每个节点的身份信息具有唯一性。节点的身份信息是由根复合体分配的，例如一个节点身份信息可以是根复合体分配的该节点的BDF，或者是根复合体分配的该节点的ID等。具体分配过程可以参考图3所示的流程，在此不再赘述。
在具体实施时，如果根复合体确定第一节点对应的目的节点有多个，则根复合体可以将这多个目的节点中的每个目的节点的身份信息皆写入第一节点。例如，第一节点是端节点1，第一数据的类型是视频类型，端节点2和端节点3皆为显示器，根复合体确定端节点2和端节点3均可以显示第一数据，因此根复合体确定端节点2和端节点3均为端节点1的目的节点。则根复合体可以将端节点2的身份信息以及端节点3的身份信息均写入端节点1。
在一种可能的实施方式中，根复合体可以将第一节点的身份信息写入第一节点。这样，第一节点可以在发送第一数据时，将第一数据、第一节点的身份信息以及第二节点的身份信息一起封装为TLP，这样TLP就可以携带源地址，可以使得目的节点根据该源地址确定TLP的发送节点为第一节点。第一节点还可以根据接收到的TLP中携带的目的地址与第一节点的身份信息是否一致，确定是否丢弃该接收到的TLP。例如，如果TLP携带的目的地址与第一节点的身份信息一致，则第一节点确定该TLP是发送给第一节点的；如果TLP携带的目的地址与第一节点的身份信息不一致，则第一节点确定该TLP不是发送给第一节点的，可以丢弃该TLP。
其中，根复合体将第一节点的身份信息写入第一节点，例如是将第一节点的身份信息写入第一节点中存储的信息，或者是将第一节点的身份信息写入第一节点中的变量，或者是将第一节点的身份信息写入第一节点中的参数等。例如，根复合体将第一节点的身份信息写入第一节点的配置空间的预留空间。
S1003：在确定第一节点支持第二工作模式时，根复合体为第一节点分配第一内存地址。
根复合体将第一节点的本地内存空间映射到CPU对应的运行内存中，得到第一内存地址，该第一内存地址是指第一节点的本地内存空间映射到CPU对应的运行内存中的物理地址。例如，第一节点的本地内存空间的大小为2MB，本地内存空间的地址为0x0000～0x007F，CPU对应的运行内存的大小为2GB(GigaByte)，运行内存的地址为0x0000～0xFFFF，第一节点的本地内存空间映射到CPU对应的运行内存的地址为0x0100～0x017F，即第一内存地址为0x0100～0x017F。
S1004：根复合体将第一内存地址写入第一节点。
根复合体将第一内存地址写入第一节点，例如是将第一内存地址写入第一节点的寄存器，或者是将第一内存地址写入第一节点中存储的信息，或者是将第一内存地址写入第一节点中的变量，或者是将第一内存地址写入第一节点中的参数等。
需要说明的是，图10所示的流程可以是由根复合体实现的，也可以是由根复合体中的芯片实现的，还可以由其他设备实现的，例如由CPU实现等。本申请实施例对此不作限定。
在本申请实施例中，根复合体将目的节点(例如第二节点)的身份信息写入发送节点 (例如第一节点)。当发送节点向目的节点发送第一数据时，可以将第一数据与目的节点的身份信息一起封装为TLP发送给中间节点(例如第三节点)。中间节点可以通过解封接收到的TLP来确定该TLP的目的地址，从而可以根据该TLP的目的地址以不经过根复合体的方式进行转发。这样就可以使得PCIe系统中的端节点之间的通信，交换节点之间的通信，以及端节点与交换节点之间的通信等不经过根复合体，实现节点之间的直接通信，从而可以降低PCIe系统中各节点之间的通信复杂度。
进一步地，根复合体通过将目的节点的身份信息写入第一节点，又为第一节点分配第一内存地址，使得第一节点既支持第一工作模式又支持第二工作模式，实现了两种工作模式的兼容。当两个节点进行通信时，可以选择经过根复合体的数据传输链路，也可以选择不经过根复合体的数据传输链路，从而实现了PCIe系统中数据传输链路的冗余备份，提高了PCIe系统中数据传输的稳定性。例如，若根复合体发生故障，节点可以选择不经过根复合体的数据传输链路与其它节点进行直接通信。
通过图10所示的流程，根复合体可以将PCIe系统中节点对应的目的节点的身份信息写入该节点，以使得中间节点可以确定接收到的TLP的目的地址。为了实现节点之间的直接通信，本申请实施例提供另一种基于PCIe的通信方法，通过该方法，中间节点可以根据接收到的TLP的目的地址按照不经过根复合体的方式对该TLP进行转发，以实现节点之间的直接通信。请参见图11，为本申请实施例提供的一种基于PCIe的通信方法的流程图，该方法可以应用于车内网中的PCIe系统，特别是自动驾驶汽车的车内网，当然也可以应用于其他设备的PCIe系统。例如，该方法可以应用于图1或图2所示的PCIe系统100。下面以将该方法应用于PCIe系统100中的根复合体为例，对该方法进行介绍。
S1101：根复合体读取第三节点中存储的信息。
在具体实施时，根复合体可以是PCIe系统100初始化时读取第三节点中存储的信息，也可以在检测到第三节点有转发第一数据的需求时读取第三节点中存储的信息，本申请实施例对此不作限定。
其中，第三节点是第一数据到目的节点所经历的节点。该第三节点可以是PCIe系统100中交换节点或交换节点中的功能。例如，第三节点可以是桥节点4，也可以是交换节点1。第三节点中存储的信息可以是第三节点的配置空间的信息。
根复合体读取第三节点中存储的信息，根据该存储的信息可以确定第三节点所支持的工作模式。例如，第三节点的配置空间的预留空间可以存储指示信息，该指示信息用于指示第三节点所支持的工作模式。则根复合体可以读取第三节点的配置空间的预留空间，从而根据读取的指示信息确定第三节点支持的工作模式。其中，预留空间为配置空间中未使用的存储地址，第三节点所支持的工作模式包括第一工作模式和第二工作模式，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。
其中，第三节点支持第一工作模式包括第三节点仅支持第一工作模式，或第三节点支持第一工作模式和第二工作模式。
在第三节点支持第一工作模式和第二工作模式时，根复合体可以为第三节点分配第二内存地址，并将第二内存地址写入第三节点。该第二内存地址是指第一节点的本地内存空间映射到CPU对应的运行内存中的物理地址。例如，根复合体将第三节点的本地内存空间 映射到CPU对应的运行内存中，得到第二内存地址。根复合体将第二内存地址写入第三节点，例如是将第二内存地址写入第三节点的寄存器，或者是将第二内存地址写入第三节点中存储的信息，或者是将第二内存地址写入第三节点中的变量，或者是将第二内存地址写入第三节点中的参数等。
在一种可能的实施方式中，在确定第三节点支持第一工作模式时，根复合体将第三节点对应的目的节点的身份信息写入第三节点。例如，根复合体可以根据PCIe系统100中各节点的功能，确定第三节点对应的目的节点，然后根复合体将第三节点对应的目的节点的身份信息写入第三节点。如果确定第三节点对应目的节点有多个，则根复合体可以将这多个目的节点中的每一个目的节点的身份信息皆写入第三节点。其中，根复合体将第三节点对应的目的节点的身份信息写入第三节点，例如是将第三节点对应的目的节点的身份信息写入第三节点中存储的信息，或者是将第三节点对应的目的节点的身份信息写入第三节点中的变量，或者是将第三节点对应的目的节点的身份信息写入第三节点中的参数等。例如，根复合体将第三节点对应的目的节点的身份信息写入第三节点的配置空间的预留空间。
在另一种可能的实施方式中，在确定第三节点支持第一工作模式时，根复合体将第三节点的身份信息写入第三节点。这样，第三节点可以在发送或转发的TLP中携带第三节点的身份信息，以使目的节点根据该源地址确定TLP的发送节点为第三节点。第三节点还可以根据接收到的TLP携带的目的地址与第三节点的身份信息是否一致，确定是否丢弃该接收到的TLP。例如，如果接收到的TLP携带的目的地址与第三节点的身份信息一致，则确定该接收到的TLP是发送给第三节点的；如果该接收到的TLP携带的目的地址与第三节点的身份信息不一致，则确定该接收到的TLP不是发送给第三节点的，并丢弃该接收到的TLP。其中，根复合体将第三节点的身份信息写入第三节点，例如是将第三节点的身份信息写入第三节点中存储的信息，或者是将第三节点的身份信息写入第三节点中的变量，或者是将第三节点的身份信息写入第三节点中的参数等。例如，根复合体将第三节点的身份信息写入第三节点的配置空间的预留空间。
进一步地，根复合体根据第三节点中存储的信息确定第三节点支持的工作模式。如果根复合体确定第三节点支持第一工作模式，则执行S1102～S1103；如果根复合体确定第三节点不支持第一工作模式，则流程结束。
S1102：在确定第三节点支持第一工作模式时，根复合体确定路由表信息。
根复合体可以根据PCIe系统100中各节点的身份信息、或功能等信息，确定第三节点的路由表信息。该路由表信息包括第二节点的身份信息，以及到达第二节点的下一跳节点的身份信息。
如果根复合体为各节点分配的身份信息为BDF，则第三节点的路由表信息可以是第三节点的总线号。第三节点接收到TLP后，根据第三节点的总线号以及目的节点的总线号，确定该TLP的下一跳节点。例如，目的节点的总线号大于第三节点所在分支中的最大总线号，则第三节点丢弃该TLP。再例如，目的节点的总线号大于或等于第三节点的下游总线号，且小于或等于第三节点所在分支中的最大总线号，则第三节点确定TLP的下一跳节点为第三节点的下游总线所下挂的节点。
如果根复合体为各节点顺序分配身份信息，且分配的身份信息为ID号，则第三节点的路由表信息可以是ID号范围，该ID号范围覆盖第三节点下挂的所有节点的ID号。例如，根复合体按照深度优先原则为各节点顺序分配身份信息。第三节点接收到TLP后，可 以根据目的节点的ID号是否在该ID范围内，确定该TLP的下一跳节点。例如，如果目的节点的ID号不在该ID范围内，则第三节点丢弃该TLP；如果目的节点的ID号在该ID范围内，则第三节点确定该TLP的下一跳节点为该第三节点下挂的节点。
如果根复合体为各节点随机分配身份信息，且分配的身份信息为ID号，则第三节点的路由表信息可以包括第三节点下挂的至少一个节点的ID号，该至少一个节点中的每个节点对应的至少一个目的节点的ID号，以及到达至少一个目的节点的下一跳节点的ID号。以中间节点为桥节点4为例，桥节点4下挂的节点为端节点1，端节点1对应的目的节点包括端节点2和端节点3，数据从桥节点4到达端节点2的下一跳节点为桥节点5，数据从桥节点4达到端节点3的下一跳节点为桥节点3。桥节点4的路由表信息包括端节点1的ID号，端节点2的ID号，桥节点5的ID号，端节点3的ID号以及桥节点3的ID号。
S1103：根复合体将路由表信息写入第三节点。
根复合体将路由表信息写入第三节点，例如是将路由表信息写入第三节点中存储的信息，或者是将路由表信息写入第三节点中的变量，或者是将路由表信息写入第三节点中的参数等。例如，根复合体将路由表信息写入第三节点的配置空间的预留空间。
需要说明的是，图11所示的流程可以是由根复合体实现的，也可以是由根复合体中的芯片实现的，还可以由其他设备实现的，例如由第三节点实现等。本申请实施例对此不作限定。
举例而言，在根复合体为PCIe系统100中的节点分配完身份信息后，第三节点确定自身支持第一工作模式；第三节点向PCIe系统100中的其他节点发送广播信号，以获取其他节点的身份信息、或功能等信息；然后第三节点基于其他节点的身份信息、或功能等信息，建立路由表信息。
本申请上述实施例中，根复合体通过将路由表信息写入中间节点(例如第三节点)，这样中间节点可以根据接收到的TLP中的目的地址以及该路由表信息，采用不经过根复合体的方式转发该接收到的TLP。这样就可以使得PCIe系统中的端节点之间的通信，交换节点之间的通信，以及端节点与交换节点之间的通信等不经过根复合体，实现节点之间的直接通信，从而可以降低PCIe系统中各节点之间的通信复杂度。
需要说明的是，根复合体可以按照深度优先原则，遍历PCIe系统100中的所有节点，并为所有节点按照图3所示的流程分配身份信息；针对PCIe系统100中支持第一工作模式、或支持第一工作模式和第二工作模式的至少一个节点中的每个节点，将该节点的身份信息以及该节点对应的至少一个目的节点的身份信息写入该节点；然后根据PCIe系统100中的所有节点的身份信息，确定桥节点的路由表信息，并将该路由表信息写入桥节点。
通过上述图10以及图11所示的流程，根复合体将目的节点的身份信息写入发送节点，将路由表信息写入中间节点，根据目的节点的身份信息以及路由表信息可以实现节点之间不经过根复合体的通信。在进行数据传输时，本申请实施例提供另一种基于PCIe的通信方法，该方法可以实现节点之间的直接通信。请参见图12，为本申请实施例提供的一种基于PCIe的通信方法的流程图，该方法可以应用于车内网中的PCIe系统，特别是自动驾驶汽车的车内网，当然也可以应用于其他设备的PCIe系统。例如，该方法可以应用于图1或图2所示的PCIe系统100。下面以第一节点为端节点1，第二节点为端节点2，第三节点为桥节点4，第四节点为桥节点5为例，对该方法进行介绍。
S1201：第一节点确定第二节点的身份信息。
在确定向第二节点发送第一数据时，第一节点可以根据第一节点中存储的信息，确定第二节点的身份信息。存储的信息是配置信息，或者是变量，或者是参数等。例如，第一节点可以根据第一节点的配置空间的预留空间，确定第二节点的身份信息。其中，第二节点为第一数据的目的节点，第一节点支持第一工作模式，或者第一节点支持第一工作模式和第二工作模式。其中，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。
在第一节点支持第二工作模式时，第一节点存储有根复合体分配的内存地址。例如，第一节点的寄存器中存储有该内存地址。
S1202：第一节点向第三节点发送TLP，第三节点接收到该TLP。
其中，该TLP可以包括第一数据和第二节点的身份信息。
在一种可能的实施方式中，该TLP可以包括第一数据、第一节点的身份信息和第二节点的身份信息。例如，第一节点可以根据第一节点中存储的信息，确定第一节点的身份信息，然后将第一节点的身份信息、第一数据以及第二节点的身份信息一起封装到TLP中。以身份信息为BDF为例，如果该TLP的TLP头的长度为12字节，则可以使用TLP头中的Byte8～Byte11来用于指示第一节点的BDF以及第二节点的BDF，如图17所示；如果该TLP的TLP头的长度为16字节，则可以使用TLP头中的Byte8～Byte11来用于指示第一节点的BDF以及第二节点的BDF，如图18所示。
S1203：第三节点确定第一路由表信息。
第三节点在接收到该TLP后，可以根据第三节点中存储的信息，确定第一路由表信息。存储的信息是配置信息，或者是变量，或者是参数等。例如，第三节点可以根据第三节点的配置空间的预留空间，确定第一路由表信息。例如，第一路由表信息可以包括第二节点的身份信息以及第四节点的身份信息。其中，第三节点支持第一工作模式，或者第三节点支持第一工作模式和第二工作模式。
在第三节点支持第二工作模式时，第三节点存储有根复合体分配的内存地址。例如，第三节点的寄存器中存储有该内存地址。
S1204：第三节点根据第一路由表信息确定第一路由路径。
第三节点可以根据第一路由表信息以及第二节点的身份信息，确定第一路由路径，该第一路由路径用于指示TLP的下一跳节点为第四节点。
S1205：第三节点向第四节点发送TLP，第四节点接收该TLP。
在一种可能的实施方式中，该TLP可以包括第一数据、第一节点的身份信息以及第二节点的身份信息。
在另一种可能的实施方式中，该TLP可以包括第一数据、第三节点的身份信息以及第二节点的身份信息。例如，第三节点可以根据第三节点中存储的信息，确定第三节点的身份信息，然后将第三节点的身份信息封装到该TLP中。
S1206：第四节点确定第二路由表信息。
第四节点在接收到该TLP后，可以根据第四节点中存储的信息，确定第一路由表信息。存储的信息是配置信息，或者是变量，或者是参数等。例如，第四节点可以根据第四节点的配置空间的预留空间，确定第二路由表信息。例如，第二路由表信息可以包括第二节点的身份信息。其中，第四节点支持第一工作模式，或者第四节点支持第一工作模式和第二工作模式。
在第四节点支持第二工作模式时，第四节点存储有根复合体分配的内存地址。例如，第四节点的寄存器中存储有该内存地址。
S1207：第四节点根据第二路由表信息确定第二路由路径。
第四节点可以根据第二路由表信息以及第二节点的身份信息，确定第二路由路径，该第二路由路径用于指示TLP的下一跳节点为第二节点。
S1208：第四节点向第二节点发送TLP，第二节点接收该TLP。
在一种可能的实施方式中，该TLP可以包括第一数据、第一节点的身份信息以及第二节点的身份信息。
在另一种可能的实施方式中，该TLP可以包括第一数据、第三节点的身份信息以及第二节点的身份信息。
在另一种可能的实施方式中，该TLP可以包括第一数据、第四节点的身份信息以及第二节点的身份信息。例如，第四节点可以根据第四节点中存储的信息，确定第四节点的身份信息，然后将第四节点的身份信息封装到该TLP中。
S1209：第二节点获取第一数据。
第二节点接收到TLP后，对该TLP进行解封装，得到第一节点发送的第一数据。
本申请上述实施例中，发送节点(例如第一节点)通过存储的信息确定接收节点(例如第二节点)的身份信息，然后将第一数据和接收节点的身份信息一起封装后发送给中间节点(例如第三节点)，以使中间节点将第一数据转发给接收节点。这样就可以使得PCIe系统中的端节点之间的通信，交换节点之间的通信，以及端节点与交换节点之间的通信等不经过根复合体，实现节点之间的直接通信，从而可以降低PCIe系统中各节点之间的通信复杂度。
基于相同的技术构思，本申请实施例提供一种基于PCIe的通信装置。该装置的结构图可以如图13所示，包括处理单元1301。
通信装置1300具体可以用于实现图10、图11的实施例中根复合体执行的方法，该装置1300可以是根复合体本身，也可以是根复合体中的芯片或芯片组或芯片中用于执行相关方法功能的一部分。其中，处理单元1301，用于将第二节点的身份信息写入第一节点，将路由表信息写入第三节点，第一节点为第一数据的源节点，第二节点为第一数据的目的节点，第三节点为该第一数据到第二节点所经历的节点。
在一种可能的实施方式中，处理单元1301，进一步用于确定第一节点支持第一工作模式；或者，确定第一节点支持第一工作模式和第二工作模式；其中，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。
在一种可能的实施方式中，处理单元1301，进一步用于在第一节点处于第二工作模式时，为第一节点配置第一内存地址，该第一内存地址为第一节点的本地内存空间映射到CPU对应的运行内存中的物理地址。
在一种可能的实施方式中，处理单元1301，进一步用于确定第三节点支持第一工作模式；或者，确定第三节点支持第一工作模式和第二工作模式；其中，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。
在一种可能的实施方式中，处理单元1301，进一步用于在第三节点处于第二工作模式时，为第三节点配置第二内存地址，第二内存地址为第三节点的本地内存空间映射到CPU对应的运行内存中的物理地址。
在一种可能的实施方式中，处理单元1301，进一步用于将第一节点的身份信息写入第一节点。
在一种可能的实施方式中，处理单元1301，进一步用于将第三节点的身份信息写入第三节点。
在一种可能的实施方式中，身份信息是BDF，或者是ID号。
本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，另外，在本申请各个实施例中的各功能模块可以集成在一个处理器中，也可以是单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。可以理解的是，本申请实施例中各个模块的功能或者实现可以进一步参考方法实施例的相关描述。
在一种可能的实施方式中，通信装置1400可以如图14所示，该装置1400可以是端节点或者端节点中的芯片。该装置1400可以包括处理器1401。其中，处理单元1301可以为处理器1401。可选地，该装置1400还可以包括收发器1402，存储器1403。
处理器1401，可以是一个CPU，或者为数字处理单元等。收发器1402可以是通信接口、也可以为接口电路如收发电路等、也可以为收发芯片等。该装置1400还包括：存储器1403，用于存储处理器1401执行的程序。存储器1403可以是非易失性存储器，比如硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等，还可以是易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)。存储器1403是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。
处理器1401用于执行存储器1403存储的程序代码，具体用于执行上述处理单元1301的动作，本申请在此不再赘述。
本申请实施例中不限定上述收发器1402、处理器1401以及存储器1403之间的具体连接介质。本申请实施例在图14中以存储器1403、处理器1401以及收发器1402之间通过总线1404连接，总线在图14中以粗线表示，其他部件之间的连接方式，仅是进行示意性说明，并不引以为限。总线1404可以分为地址总线、数据总线、控制总线等。为便于表示，图14中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
基于与方法实施例的同一技术构思，本申请实施例提供一种基于PCIe的通信装置1500。该装置1500的结构可以如图15所示，包括处理单元1501以及收发单元1502。
通信装置1500可以实现图12的实施例中第一节点执行的方法，该装置1500可以是第一节点本身，也可以是第一节点中的芯片或芯片组或芯片中用于执行相关方法功能的一部分。其中，处理单元1501，用于根据第一节点中存储的信息，确定第二节点的身份信息，该第二节点为第一数据的目的节点；收发单元1502，用于向第三节点发送第一TLP，第一TLP包括第一数据和第二节点的身份信息。
在一种可能的实施方式中，第一节点支持第一工作模式，第一工作模式为节点与节点之间的通信不经过根复合体的工作模式。
在一种可能的实施方式中，第一节点支持第一工作模式和第二工作模式，第一工作模 式为节点与节点之间的通信不经过根复合体的工作模式，第二工作模式为节点与节点之间的通信需经过根复合体的工作模式。
在一种可能的实施方式中，该存储的信息还包括第一节点的身份信息。
在一种可能的实施方式中，该第一TLP还包括第一节点的身份信息。
在一种可能的实施方式中，该身份信息是BDF，或者是ID号。
本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，另外，在本申请各个实施例中的各功能模块可以集成在一个处理器中，也可以是单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。可以理解的是，本申请实施例中各个模块的功能或者实现可以进一步参考方法实施例的相关描述。
在一种可能的实施方式中，通信装置1600可以如图16所示，该装置1600可以是端节点或端节点中的芯片，或者可以是交换节点或交换节点中的芯片。该装置1600可以包括处理器1601，还可以包括收发器1602，存储器1603。其中，处理单元1501可以为处理器1601。收发单元1502可以为收发器1602。
处理器1601，可以是一个CPU，或者为数字处理单元等。收发器1602可以是通信接口、也可以为接口电路如收发电路等、也可以为收发芯片等。该装置1600还包括：存储器1603，用于存储处理器1601执行的程序。存储器1603可以是非易失性存储器，比如硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等，还可以是易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)。存储器1603是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。
处理器1601用于执行存储器1603存储的程序代码，具体用于执行上述处理单元1501的动作，本申请在此不再赘述。收发器1602具体用于执行上述收发单元1502的动作，本申请在此不再赘述。
本申请实施例中不限定上述收发器1602、处理器1601以及存储器1603之间的具体连接介质。本申请实施例在图16中以存储器1603、处理器1601以及收发器1602之间通过总线1604连接，总线在图16中以粗线表示，其他部件之间的连接方式，仅是进行示意性说明，并不引以为限。总线1604可以分为地址总线、数据总线、控制总线等。为便于表示，图16中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
本申请实施例还提供了一种计算机可读存储介质，用于存储为执行上述处理器所需执行的计算机软件指令，其包含用于执行上述处理器所需执行的程序。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生 一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (30)

  1. 一种基于外围组件互连传递PCIe的通信方法，其特征在于，所述方法包括：
    将第二节点的身份信息写入第一节点，所述第一节点为第一数据的源节点，所述第二节点为所述第一数据的目的节点；
    将路由表信息写入第三节点，所述第三节点为所述第一数据到所述第二节点所经历的节点。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    确定所述第一节点支持第一工作模式；或者，
    确定所述第一节点支持第一工作模式和第二工作模式；
    其中，所述第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，所述第二工作模式为节点与节点之间的通信需经过所述根复合体的工作模式。
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    在所述第一节点处于所述第二工作模式时，为所述第一节点配置第一内存地址，所述第一内存地址为所述第一节点的本地内存空间映射到中央处理器CPU对应的运行内存中的物理地址。
  4. 根据权利要求1～3中任意一项所述的方法，其特征在于，所述方法还包括：
    确定所述第三节点支持第一工作模式；或者，
    确定所述第三节点支持第一工作模式和第二工作模式；
    其中，所述第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，所述第二工作模式为节点与节点之间的通信需经过所述根复合体的工作模式。
  5. 根据权利要求4所述的方法，其特征在于，所述方法还包括：
    在所述第三节点处于所述第二工作模式时，为所述第三节点配置第二内存地址，所述第二内存地址为所述第三节点的本地内存空间映射到中央处理器CPU对应的运行内存中的物理地址。
  6. 根据权利要求1～5中任意一项所述的方法，其特征在于，所述方法还包括：
    将所述第一节点的身份信息写入所述第一节点。
  7. 根据权利要求1～6中任意一项所述的方法，其特征在于，所述方法还包括：
    将所述第三节点的身份信息写入所述第三节点。
  8. 根据权利要求1～7中任意一项所述的方法，其特征在于，所述身份信息是总线号、设备号和功能号BDF，或者是身份标识ID号。
  9. 一种基于外围组件互连传递PCIe的通信方法，其特征在于，所述方法包括：
    第一节点根据所述第一节点中存储的信息，确定第二节点的身份信息，所述第二节点为第一数据的目的节点；
    所述第一节点向第三节点发送第一事务层包TLP，所述第一TLP包括所述第一数据和所述第二节点的身份信息。
  10. 根据权利要求9所述的方法，其特征在于，所述第一节点支持第一工作模式，所述第一工作模式为节点与节点之间的通信不经过根复合体的工作模式。
  11. 根据权利要求9所述的方法，其特征在于，所述第一节点支持第一工作模式和第 二工作模式，所述第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，所述第二工作模式为节点与节点之间的通信需经过所述根复合体的工作模式。
  12. 根据权利要求9～11任意一项所述的方法，其特征在于，所述存储的信息还包括所述第一节点的身份信息。
  13. 根据权利要求12所述的方法，其特征在于，所述第一TLP还包括所述第一节点的身份信息。
  14. 根据权利要求9～13中任意一项所述的方法，其特征在于，所述身份信息是总线号、设备号和功能号BDF，或者是身份标识ID号。
  15. 一种基于外围组件互连传递PCIe的通信装置，其特征在于，包括：
    处理单元：用于将第二节点的身份信息写入第一节点，所述第一节点为第一数据的源节点，所述第二节点为所述第一数据的目的节点；将路由表信息写入第三节点，所述第三节点为所述第一数据到所述第二节点所经历的节点。
  16. 根据权利要求15所述的装置，其特征在于，所述处理单元，进一步用于：
    确定所述第一节点支持第一工作模式；或者，
    确定所述第一节点支持第一工作模式和第二工作模式；
    其中，所述第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，所述第二工作模式为节点与节点之间的通信需经过所述根复合体的工作模式。
  17. 根据权利要求16所述的装置，其特征在于，所述处理单元，进一步用于：
    在所述第一节点处于所述第二工作模式时，为所述第一节点配置第一内存地址，所述第一内存地址为所述第一节点的本地内存空间映射到中央处理器CPU对应的运行内存中的物理地址。
  18. 根据权利要求15～17中任意一项所述的装置，其特征在于，所述处理单元，进一步用于：
    确定所述第三节点支持第一工作模式；或者，
    确定所述第三节点支持第一工作模式和第二工作模式；
    其中，所述第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，所述第二工作模式为节点与节点之间的通信需经过所述根复合体的工作模式。
  19. 根据权利要求18所述的装置，其特征在于，所述处理单元，进一步用于：
    在所述第三节点处于所述第二工作模式时，为所述第三节点配置第二内存地址，所述第二内存地址为所述第三节点的本地内存空间映射到中央处理器CPU对应的运行内存中的物理地址。
  20. 根据权利要求15～19中任意一项所述的装置，其特征在于，所述处理单元，进一步用于：
    将所述第一节点的身份信息写入所述第一节点。
  21. 根据权利要求15～20中任意一项所述的装置，其特征在于，所述处理单元，进一步用于：
    将所述第三节点的身份信息写入所述第三节点。
  22. 根据权利要求15～21中任意一项所述的装置，其特征在于，所述身份信息是总线号、设备号和功能号BDF，或者是身份标识ID号。
  23. 一种基于外围组件互连传递PCIe的通信装置，其特征在于，包括：
    处理单元，用于根据第一节点中存储的信息，确定第二节点的身份信息，所述第二节点为第一数据的目的节点；
    收发单元，用于向第三节点发送第一事务层包TLP，所述第一TLP包括所述第一数据和所述第二节点的身份信息。
  24. 根据权利要求23所述的装置，其特征在于，所述第一节点支持第一工作模式，所述第一工作模式为节点与节点之间的通信不经过根复合体的工作模式。
  25. 根据权利要求23所述的装置，其特征在于，所述第一节点支持第一工作模式和第二工作模式，所述第一工作模式为节点与节点之间的通信不经过根复合体的工作模式，所述第二工作模式为节点与节点之间的通信需经过所述根复合体的工作模式。
  26. 根据权利要求23～25任意一项所述的装置，其特征在于，所述存储的信息还包括所述第一节点的身份信息。
  27. 根据权利要求26所述的装置，其特征在于，所述第一TLP还包括所述第一节点的身份信息。
  28. 根据权利要求23～27中任意一项所述的装置，其特征在于，所述身份信息是总线号、设备号和功能号BDF，或者是身份标识ID号。
  29. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储程序或指令，所述程序或所述指令在被一个或多个处理器读取并执行时可实现权利要求1～8或权利要求9～14中任一项所述的方法。
  30. 一种计算机程序产品，其特征在于，当所述计算机程序产品运行时，执行权利要求1～8中任一项所述的方法，或者，执行权利要求9～14中任一项所述的方法。
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