WO2021159582A1 - 一种多轴驱控系统 - Google Patents

一种多轴驱控系统 Download PDF

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Publication number
WO2021159582A1
WO2021159582A1 PCT/CN2020/079824 CN2020079824W WO2021159582A1 WO 2021159582 A1 WO2021159582 A1 WO 2021159582A1 CN 2020079824 W CN2020079824 W CN 2020079824W WO 2021159582 A1 WO2021159582 A1 WO 2021159582A1
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Prior art keywords
address
drive control
module
pin
optocoupler
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PCT/CN2020/079824
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English (en)
French (fr)
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赵勇军
付德光
阳安
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浙江禾川科技股份有限公司
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Publication of WO2021159582A1 publication Critical patent/WO2021159582A1/zh

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B25—HAND TOOLS; PORTABLE POWER-DRIVEN TOOLS; MANIPULATORS
    • B25J—MANIPULATORS; CHAMBERS PROVIDED WITH MANIPULATION DEVICES
    • B25J9/00—Programme-controlled manipulators
    • B25J9/16—Programme controls
    • B25J9/1602—Programme controls characterised by the control system, structure, architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • This application relates to the technical field of industrial robots, in particular to a multi-axis drive control system.
  • Industrial robots are multi-joint manipulators or multi-degree-of-freedom mechanical devices oriented to the industrial field, which significantly improves the efficiency of industrial production.
  • the multi-axis drive control system composed of single-module servo drives has space, high cost, cumbersome wiring, unstable signals and easy interference, etc. Disadvantages, the corresponding multi-axis drive and control integrated machine can effectively solve these problems, and it has been very popular since it came out.
  • the multi-axis drive integrated machine is composed of a drive control module and multiple inverter modules, and one inverter module is used to control one inverter axis.
  • the data exchange between the drive control module and each inverter module often adopts the RS232 mode.
  • the number of drive shafts required in different applications is different, so the setting of the communication address of the multi-axis drive-control integrated machine is more flexible.
  • several communication address setting methods commonly used in the market are as follows: (1) Using dial code Set the communication address of each module in the switch mode; (2) Set the communication address of each module by means of resistance pull-up and pull-down; (3) Set the communication address of each module separately through software.
  • each module needs to be manually addressed, which not only wastes manpower, is inefficient, and is also prone to errors. If the DIP switch is used to set the communication address of each module, workers need to manually set different hardware addresses for each module after the multi-axis drive-control integrated machine is assembled. If the number of modules is large, the DIP switches are expensive and waste man-hours.
  • the purpose of this application is to provide a multi-axis drive and control system to solve the problems of inconvenient and error-prone addressing of the modules of the multi-axis drive and control integrated machine in the prior art.
  • the present application provides a multi-axis drive control system, including a drive control module and a plurality of inverter modules cascaded with the drive control module;
  • the drive control module includes a first address input port and a first address output port
  • the inverter module includes a second address input port and a second address output port
  • the first address output port of the drive control module is connected to the second address input port of the first inverter module in each of the inverter modules.
  • each inverter module has two The two are connected in series, and the second address output port of the former inverter module is connected with the second address input port of the latter inverter module;
  • the drive control module is used to generate an initial address and send it to the first inverter module; each of the inverter modules is used to calculate a communication address received from a local address input port according to a preset calculation rule to obtain a local communication Address, and send the local communication address to the next inverter module.
  • the drive control module generates the initial address and sends it to the first inverter module, specifically:
  • the first processor of the drive control module generates the initial address and outputs it to the first inverter module through the first address output port.
  • the drive control module specifically includes an initial address generation circuit and a first processor
  • the input terminal of the first processor is connected to the first address input port, and the output terminal of the initial address generating circuit is connected to the first address output port.
  • the first address input port is connected to a second address output port of an end inverter module in each inverter module;
  • the first processor is further configured to perform address verification of each inverter module according to the communication address of the end inverter module and the number of the inverter modules.
  • the drive control module further includes a first optocoupler provided between the first address input interface and the first processor.
  • the inverter module specifically includes a calculator circuit and a second processor
  • the input terminal of the calculator circuit is connected to the second address input interface, and the output terminal of the calculator circuit is respectively connected to the input terminal of the second processor and the first address input interface. Two address output interface connection.
  • the inverter module further includes a second optocoupler provided between the second address input interface and the calculator circuit, and a second optocoupler provided between the output terminal of the calculator circuit and the second The third optocoupler between the address output interface.
  • the positive input terminal of the second optocoupler is connected to the first power source, the negative input terminal of the second optocoupler is connected to the second address input interface, and the positive output terminal of the second optocoupler Respectively connected to the first pull-up resistor and the input terminal of the second processor, and the negative output terminal of the second optocoupler is grounded;
  • the positive input end of the third optocoupler is connected to the second power source, the negative input end of the third optocoupler is connected to the output end of the second processor, and the positive output end of the third optocoupler is connected to the
  • the second pull-up resistor is connected to the second address output port, and the negative output terminal of the third optocoupler is grounded.
  • the calculator circuit is specifically an adder or a subtractor, an FPGA or a CPLD.
  • the drive control module is also communicatively connected with each of the inverter modules through an RS485 communication port.
  • the multi-axis drive control system includes a drive control module and a plurality of inverter modules cascaded with the drive control module, wherein the drive control module includes a first address input port and a first address output port, and the inverter module It includes a second address input port and a second address output port; the first address output port of the drive control module is connected to the second address input port of the first inverter module in each inverter module.
  • the inverter modules are connected in series in pairs, and the second address output port of the previous inverter module is connected to the second address input port of the next inverter module; the drive control module is used to generate the initial address and send it to the first inverter module; Each inverter module is used to calculate the communication address received from the local address input port according to the preset calculation rules to obtain the local communication address, and send the local communication address to the next inverter module, so that the drive control module and each After the inverter module is connected, it can realize automatic addressing from the drive control module to each inverter module according to the connection sequence, the communication address and initial address of each module, the installation position of the module in the multi-axis drive control system, and the preset calculation rules Associated, there is no need for manual addressing by workers, which avoids the time-consuming and error-prone problems of manual addressing.
  • FIG. 1 is a schematic structural diagram of a multi-axis drive control system provided by an embodiment of the application
  • Figure 2 is a wiring diagram of the address output port and the address input port provided by an embodiment of the application
  • FIG. 3 is a circuit diagram of an initial address generating circuit provided by an embodiment of the application.
  • FIG. 4 is a circuit diagram of an address verification circuit of a drive control module provided by an embodiment of the application.
  • Fig. 5 is a circuit diagram of an inverter module provided by an embodiment of the application.
  • the core of this application is to provide a multi-axis drive and control system, which is used to solve the problems of inconvenient and error-prone addressing of each module of a multi-axis drive and control integrated machine in the prior art.
  • Fig. 1 is a schematic structural diagram of a multi-axis drive control system provided by an embodiment of the application
  • Fig. 2 is a wiring diagram of an address output port and an address input port provided by an embodiment of the application.
  • the multi-axis drive control system provided by the embodiment of the present application includes a drive control module and a plurality of inverter modules cascaded with the drive control module;
  • the drive control module includes a first address input port B and a first address output port A
  • the inversion module includes a second address input port Y and a second address output port X;
  • the first address output port A of the drive control module is connected to the second address input port Y of the first inverter module in each inverter module. Starting from the first inverter module, each inverter module is connected in series in pairs, and the previous one The second address output port X of the inverter module is connected to the second address input port Y of the next inverter module;
  • the drive control module is used to generate the initial address and send it to the first inverter module; each inverter module is used to calculate the communication address received from the local address input port according to the preset calculation rules to obtain the local communication address and communicate with the local The address is sent to the next inverter module.
  • the first address output port A of the drive control module is connected to the second address input port Y of the inverter module 1
  • the second address output port X of the inverter module 2 is connected to the inverter module.
  • 3's second address input port Y is connected, and so on.
  • the initial address is generated by the drive control module, and each inverter module can complete its own addressing in turn based on the initial address.
  • the drive control module can determine the address of each inverter module according to the number of inverter modules and the preset calculation rules on each inverter module. After each module has been addressed, the drive control module is based on the address of each inverter module and Each inverter module communicates.
  • the drive control module and each inverter module can be connected and communicated one by one through RS232. In order to reduce the number of wiring and improve communication efficiency, the drive control module and each inverter module are connected through RS485 communication ports.
  • the drive control module can be installed at the leftmost starting position, and the inverter modules can be stacked and assembled on the right side of the drive control module.
  • the RS485 communication port passes through the PCB board, respectively.
  • the 485+/485- of each module are connected together, the first address output port A of the drive control module is connected to the second address input port Y of the inverter module 1 through the power strip on the PCB, and the following inverter modules are by analogy
  • the second address output port X of the end inverter module n can return to the first address input port B of the drive control module through a signal line.
  • the drive control module includes a first processor U4, a human-computer interaction interface (including a display screen, keys, etc.), etc., for receiving the input initial address and controlling the first address output port A to send the initial address.
  • the first processor U4 usually adopts an ARM processor.
  • the initial address may be generated by the first processor U4 and output to the inverter module 1 through the first address output port A.
  • the drive control module may further include an initial address generating circuit, and the input terminal of the first processor U4 is connected to the first address input port B, and the output terminal of the initial address generating circuit is connected to the first address output port A.
  • the second address output port X of the end inverter module n is connected to the first address input port B of the drive control module, and the communication address of the end inverter module n is sent to the drive control module, and the first processor U4
  • the communication address of the terminal inverter module n and the number of inverter modules are verified against the address of each inverter module to realize the automatic verification of the address of the multi-axis drive control system after each module is addressed.
  • the preset calculation rule on each inverter module can be cumulatively 1. For example, if the initial address set on the drive control module is 0, the address of inverter module 1 is 1, the address of inverter module 2 is 2, and so on.
  • the preset calculation rules on each inverter module can also be cumulatively minus 1, or other calculation methods, which will not be repeated here.
  • the multi-axis drive control system includes a drive control module and a plurality of inverter modules cascaded with the drive control module.
  • the drive control module includes a first address input port and a first address output port.
  • the module includes a second address input port and a second address output port; the first address output port of the drive control module is connected to the second address input port of the first inverter module in each inverter module, starting from the first inverter module, Each inverter module is connected in series in pairs, and the second address output port of the previous inverter module is connected to the second address input port of the next inverter module;
  • the drive control module is used to generate the initial address and send it to the first inverter module ;
  • Each inverter module is used to calculate the communication address received from the local address input port according to the preset calculation rules to obtain the local communication address, and send the local communication address to the next inverter module, so that the drive control module and After each inverter module is connected, it can realize automatic addressing from the drive
  • Fig. 3 is a circuit diagram of an initial address generation circuit provided by an embodiment of the application
  • Fig. 4 is a circuit diagram of an address verification circuit of a drive control module provided by an embodiment of the present application.
  • the embodiment of the present application provides a specific circuit implementation scheme of the drive control module.
  • the embodiments of the present application and the following embodiments are all described with a calculation method in which the number of address digits is four and each module accumulates 1.
  • the initial address generation circuit consists of four pull-down resistors R13, R14, R15, R16.
  • the first end of each pull-down resistor is grounded, and the second end of each pull-down resistor is connected to the drive
  • the first address output ports AA0_OUT, A1_OUT, A2_OUT, and A3_OUT of the control module are connected.
  • the specific wiring method is: 1 pin of pull-down resistor R13 is connected to GND, pin 2 is connected to port signal A0_OUT; pin 1 of pull-down resistor R14 is connected to GND, pin 2 is connected to port signal A1_OUT; pin 1 of pull-down resistor R15 is connected to GND, and pin 2 is connected Port signal A2_OUT; pin 1 of the pull-down resistor R16 is connected to GND, pin 2 is connected to port signal A3_OUT.
  • the initial address generating circuit causes the first address output port A to output a low-level signal to the ground by default, as the initial address 0000.
  • the drive control module further includes a first optocoupler U2 arranged between the first address input interface and the first processor U4.
  • the first address input port B (A0_IN, A1_IN, A2_IN, A3_IN) of the drive control module is connected to the negative input end of the four first optocouplers U2, and the positive input end of each first optocoupler U2 is The +5V power supply is connected, and the positive output end of each first optocoupler U2 is respectively connected to the four pull-up resistors R21, R24, R22, R27 and the first processor U4.
  • the input end of the first optocoupler U2 further includes current limiting resistors R25, R28, R30, R32 and voltage dividing resistors R26, R29, R31, R33.
  • the second end of the first processor U4 also includes pull-up resistors R39 and R38 and a power decoupling capacitor C1.
  • the SDA port and SCL port of the first processor U4 are connected to the EPROM U13's SDA port and SCL through the pull-up resistors R39 and R38. port.
  • the specific wiring method of the address verification circuit of the drive control module is: pin 2 of the current-limiting resistor R25 is connected to the power supply 5V, pin 1 is connected to the pin 7 of the first optocoupler U2 and pin 2 of the voltage divider resistor R26; the current-limiting resistor R28 Pin 2 is connected to the power supply 5V, pin 1 is connected to pin 5 of the first optocoupler U2 and pin 2 of the voltage divider resistor R29; pin 2 of the current limiting resistor R30 is connected to the power supply 5V, pin 1 is connected to pin 3 of the first photocoupler U2 and pin Pin 2 of the voltage resistor R31; Pin 2 of the current limiting resistor R32 is connected to the power supply 5V, Pin 1 is connected to pin 1 of the first optocoupler U2 and pin 2 of the voltage divider resistor R33; Pin 8 of the first photocoupler U2 is connected to the voltage divider resistor Pin 1 of R26 is connected to A0_IN; Pin 6 of the first optocoupler U2 is
  • the signal level of the second address output port X of the end inverter module n is the signal level of the first address input port B of the drive control module, and the four-bit address signal passes through the drive control module
  • the output of the first optocoupler U2 is sent to the pins AD0, AD1, AD2, AD3 of the first processor U4, the first processor U4 reads the pin level, the identification value is n, and determines the address number of the inverter module Is n, and then the data is written into EPROM U13 through pins SDA and SCL.
  • the drive control module is used as the main communication to communicate with the inverter module of each address. After confirming that the communication address of each inverter module is available, the information of the successful connection of the system is displayed on the display screen.
  • Fig. 5 is a circuit diagram of an inverter module provided by an embodiment of the application.
  • the inverter module specifically includes a calculator circuit and a second processor U3;
  • the input end of the calculator circuit is connected to the second address input interface, and the output end of the calculator circuit is respectively connected to the input end of the second processor U3 and the second address output interface.
  • the inverter module also includes a second optocoupler U5 arranged between the second address input interface and the calculator circuit, and a second optocoupler U5 arranged between the output terminal of the calculator circuit and the second address output interface.
  • the third optocoupler U6 is also included in the inverter module.
  • the positive input end of the second optocoupler U5 is connected to the first power supply +5V
  • the negative input end of the second optocoupler U5 is connected to the second address input interface
  • the positive output end of the second optocoupler U5 is respectively Connect with the first pull-up resistors R314, R315, R317, R1 and the input terminal of the second processor U3, and the negative output terminal of the second optocoupler U5 is grounded;
  • the positive input end of the third optocoupler U6 is connected to the second power supply +3.3V
  • the negative input end of the third optocoupler U6 is connected to the output end of the second processor U3
  • the positive output end of the third optocoupler U6 is connected to the second power supply respectively.
  • Two pull-up resistors R3, R10, R11, R12 are connected to the second address output port X, and the negative output terminal of the third optocoupler U6 is grounded.
  • the input end of the second optocoupler U5 also includes current limiting resistors R19, R4, R6, R8 and voltage dividing resistors R18, R5, R7, R9.
  • the input end of the third optocoupler U6 also includes current limiting resistors R17, R20, R23, and R2.
  • the second end of the second processor U3 is also connected to the EPROM U38 through pull-up resistors R37 and R36, and the second end of the second processor U3 also includes a power decoupling capacitor C16.
  • the calculator circuit can use an adder U1 or a subtractor, an FPGA or a CPLD.
  • the calculation rule of accumulating 1 is taken as an example, so the calculator circuit can adopt the adder U1.
  • pin 2 of the current limiting resistor R19 is connected to the power supply 5V, pin 1 is connected to the pin 7 of the second optocoupler U5 and pin 2 of the voltage divider resistor R18; pin 2 of the current limiting resistor R4 is connected to the power supply+ 5V, pin 1 is connected to pin 5 of the second optocoupler U5 and pin 2 of the voltage dividing resistor R5; pin 2 of the current limiting resistor R6 is connected to the power supply +5V, pin 1 is connected to pin 3 of the second photocoupler U5 and voltage dividing resistor R7 Pin 2 of the current limiting resistor R8 is connected to the power supply +5V, pin 1 is connected to pin 1 of the second optocoupler U5 and pin 2 of the voltage divider resistor R9; pin 8 of the second photocoupler U5 is connected to the voltage divider resistor R18 Pin 1 and port signal A0_IN; Pin 6 of the second optocoupler U5 is connected to pin 1 of the
  • the 16 and 5 pins of the adder U1 are connected to +3.3V power supply, the 6, 7, 8, 10, 15 of the adder U1 are connected to GND; the 9 pins of the adder U1 are connected to pin 1 of R34, and the pin 2 of resistor R34 is connected to GND;
  • Pin 14 of the adder U1 is connected to pin 6 of the third optocoupler U6 and pin 1 of the second processor U3; pin 13 of the adder U1 is connected to pin 4 of the third photocoupler U6 and pin 2 of the second processor U3 ; Pin 12 of the adder U1 is connected to pin 2 of the third optocoupler U6 and pin 3 of the second processor U3; pin 11 of the adder U1 is connected to pin 8 of the third photocoupler U6 and pin 4 of the second processor U3 ;
  • Pin 5 of the second processor U3 is connected to pin 1 of the pull-up resistor R37 and pin 5 of EPROM U38; pin 6 of the second processor U3 is connected to pin 1 of the pull-up resistor R36 and pin 6 of EPROM U38; the pull-up resistor R37 Pin 2 of the power supply and pin 2 of the pull-up resistor R36 are connected to +3.3V power supply and pin 1 of the power decoupling capacitor C98 and pin 8 of EPROM U38; Pin 2 of the power decoupling capacitor C98 is connected to GND; Pin 1, 2, of EPROM U38 Connect pins 3, 4, and 7 to GND;
  • the 2 pin of the voltage divider resistor R17 is connected to the voltage divider resistor R20, the pin 2 is connected to the voltage divider resistor R23, and the pin 2 of the voltage divider resistor R2 is connected to +3.3V;
  • the 1 pin of the voltage divider resistor R17 is connected to the third optocoupler U6 Pin 5;
  • pin 1 of the voltage divider resistor R20 is connected to pin 3 of the third optocoupler U6;
  • pin 1 of the voltage divider resistor R23 is connected to pin 1 of the third photocoupler U6;
  • pin 1 of the voltage divider resistor R2 is connected to the third photocoupler U6 The 7 feet;
  • Pin 1 of the second pull-up resistor R3 is connected to the second pull-up resistor R10.
  • Pin 1 of the second pull-up resistor R11 is connected to the pin 1 of the second pull-up resistor R12.
  • Pin 1 is connected to the +5V power supply;
  • the second pull-up resistor R3 Pin 2 of the third optocoupler U6 is connected to pin 12 of the port signal A0_OUT;
  • pin 2 of the second pull-up resistor R10 is connected to pin 14 of the third photocoupler U6 to the port signal A1_OUT;
  • pin 2 of the second pull-up resistor R11 is connected Pin 16 of the third optocoupler U6 is connected to the port signal A2_OUT;
  • Pin 2 of the second pull-up resistor R12 is connected to the pin 10 of the third photocoupler U6 to the port signal A3_OUT; Pins 11, 13, 15, and 9 of the third photocoupler U6 Connect to GND.
  • the second address input port Y of the inverter module 1 receives four low-level signals 0000 from the first address output port A of the drive control module, so that the fourth address of the inverter module 1
  • the second optocoupler U5 is turned on, and pins 10, 12, 14, and 16 of the second optocoupler U5 output low-level signals, corresponding to the A0, A1, A2, and A3 signals of the second processor U3.
  • the digital quantity is replaced by 0000; (the following are all digital quantities for the convenience of introduction).
  • the Cin of the adder U1 is connected to 3.3V as a high-level signal to realize the automatic accumulation function, then the output level of the pin of the adder U1 of the inverter module 1 is S0, S1, S2, and the output of S3 is 0001.
  • the inverter module The ARM of 1 reads the pin levels AD0, AD1, AD2, and AD3 as 0001; the second processor U3 of the inverter module 1 recognizes it as 1, and then sets the local communication address to 1, and then passes this data through the pin SDA And SCL are written into EPROM U38; at the same time, the level signal is transmitted to the second address output port X of the inverter module 1 through the third optocoupler U6, and the level of the second address output port X is 0001, this signal will pass through the row Plug and transmit to the second address input port Y of the inverter module 2, that is, the signal corresponding to the second address input port Y of the inverter module 2 is 0001, then the second optocoupler U5 output pin 10 of the inverter module 2 , 12, 14, 16 output is 0001, the corresponding adder U1 pin A0, A1, A2, A3 level is expressed as 0001, at this time the adder U1Cin is high, add 1 on the basis of 0001, then the adder U
  • the second processor U3 of the inverter module 2 reads the pin levels AD0, AD1, AD2, and AD3 as 0010, which is identified as 2; then set the local The communication address is 2, and then this data is written into EPROM U38 through the pins SDA and SCL; at the same time, the level signal is transmitted to the second address output port X of the inverter module 2 through the third optocoupler U6, and the second address is output
  • the level of port X is 0010 respectively, this signal will be transmitted to port Y of the next inverter module 3 through the power strip...and so on, to complete the addressing of the communication addresses of all inverter modules.

Abstract

一种多轴驱控系统，包括驱控模块和与驱控模块级联的多个逆变模块，由驱控模块生成初始地址发送至首个逆变模块；各逆变模块按预设计算规则对自本地的地址输入端口接收的通讯地址进行计算后得到本地通讯地址，并将本地通讯地址发送至下一个逆变模块。该驱控系统实现了从驱控模块到各逆变模块按照连接顺序自动定址，避免了人工定址耗时长、易于出错的问题。

Description

一种多轴驱控系统
本申请要求于2020年2月12日提交中国专利局、申请号为202010088488.3、发明名称为“一种多轴驱控系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及工业机器人技术领域，特别是涉及一种多轴驱控系统。
背景技术
工业机器人是面向工业领域的多关节机械手或多自由度的机器装置，显著的提高了工业生产的效率。而工业机器人灵活度和仿生度越高需要的伺服电机的数量就会越多，单模块伺服驱动器组成的多轴驱控系统有着占空间、成本较高、接线繁琐、信号不稳定易受干扰等缺点，相应的多轴驱控一体机可有效的解决这些问题，自问世以来颇为受欢迎。
多轴驱动一体机由驱控模块和多个逆变模块组成，一个逆变模块用于控制一个逆变轴。驱控模块和各逆变模块之间的数据交换常采用RS232模式。在不同的应用场合所需要的驱动轴数各不相同，因此多轴驱控一体机通讯地址的设定较为灵活，目前市场上常用的几种通讯地址设定方式如下：(1)采用拨码开关方式设置每个模块通讯地址；(2)采用电阻上下拉的方式设置每个模块通讯地址；(3)通过软件单独设置每个模块通讯地址。
然而，基于上述通讯地址的设定方式，均需要人工对各个模块进行定址，不仅浪费人力、效率低下，还容易出错。如若采用拨码开关方式设置每个模块通讯地址，需要在多轴驱控一体机组装完成后，由工人手工分别对每一个模块设置不同的硬件地址，模块数量多拨码开关成本高，浪费工时，容易出错；若采用电阻上下拉的方式设置每个模块通讯地址，则对每个模块，均需要通过识别芯片引脚电平设置不同的地址，会导致地址重复，每个模块通讯地址完全固定，不能改变，灵活度不高；若通过软件单独设置每个模块通讯地址，在多轴驱控一体机组装完成后，通过USB分别连接每个模块，用电脑操作后台程序给每个模块逐个设置不同的通讯地址，人 工耗时长，易出错。
发明内容
本申请的目的是提供一种多轴驱控系统，用于解决现有技术中多轴驱控一体机各模块定址不便、易出错的问题。
为解决上述技术问题，本申请提供一种多轴驱控系统，包括驱控模块和与所述驱控模块级联的多个逆变模块；
其中，所述驱控模块包括第一地址输入端口和第一地址输出端口，所述逆变模块包括第二地址输入端口和第二地址输出端口；
所述驱控模块的第一地址输出端口与各所述逆变模块中的首个逆变模块的第二地址输入端口连接，自所述首个逆变模块起，各所述逆变模块两两串接，且前一所述逆变模块的第二地址输出端口与后一所述逆变模块的第二地址输入端口连接；
所述驱控模块用于生成初始地址发送至所述首个逆变模块；各所述逆变模块用于按预设计算规则对自本地的地址输入端口接收的通讯地址进行计算后得到本地通讯地址，并将所述本地通讯地址发送至下一个所述逆变模块。
可选的，所述驱控模块生成所述初始地址发送至所述首个逆变模块，具体为：
所述驱控模块的第一处理器生成所述初始地址并通过所述第一地址输出端口输出至所述首个逆变模块。
可选的，所述驱控模块具体包括初始地址生成电路和第一处理器；
其中，所述第一处理器的输入端与所述第一地址输入端口连接，所述初始地址生成电路的输出端与所述第一地址输出端口连接。
可选的，所述第一地址输入端口与各所述逆变模块中的末端逆变模块的第二地址输出端口连接；
所述第一处理器还用于根据所述末端逆变模块的通讯地址及所述逆变模块的数量进行对各所述逆变模块的地址校验。
可选的，所述驱控模块还包括设于所述第一地址输入接口和所述第一 处理器之间的第一光耦。
可选的，所述逆变模块具体包括计算器电路和第二处理器；
在一个所述逆变模块中，所述计算器电路的输入端与所述第二地址输入接口连接，所述计算器电路的输出端分别与所述第二处理器的输入端和所述第二地址输出接口连接。
可选的，所述逆变模块还包括设于所述第二地址输入接口和所述计算器电路之间的第二光耦，以及设于所述计算器电路的输出端和所述第二地址输出接口之间的第三光耦。
可选的，所述第二光耦的正极输入端与第一电源连接，所述第二光耦的负极输入端与所述第二地址输入接口连接，所述第二光耦的正极输出端分别与第一上拉电阻和所述第二处理器的输入端连接，所述第二光耦的负极输出端接地；
所述第三光耦的正极输入端与第二电源连接，所述第三光耦的负极输入端与所述第二处理器的输出端连接，所述第三光耦的正极输出端分别与第二上拉电阻和所述第二地址输出端口连接，所述第三光耦的负极输出端接地。
可选的，所述计算器电路具体为加法器或减法器或FPGA或CPLD。
可选的，所述驱控模块还与各所述逆变模块之间通过RS485通信端口通信连接。
本申请所提供的多轴驱控系统，包括驱控模块和与驱控模块级联的多个逆变模块，其中，驱控模块包括第一地址输入端口和第一地址输出端口，逆变模块包括第二地址输入端口和第二地址输出端口；驱控模块的第一地址输出端口与各逆变模块中的首个逆变模块的第二地址输入端口连接，自首个逆变模块起，各逆变模块两两串接，且前一逆变模块的第二地址输出端口与后一逆变模块的第二地址输入端口连接；驱控模块用于生成初始地址发送至首个逆变模块；各逆变模块用于按预设计算规则对自本地的地址输入端口接收的通讯地址进行计算后得到本地通讯地址，并将本地通讯地址发送至下一个逆变模块，从而在驱控模块与各逆变模块连接后，可以实现从驱控模块到各逆变模块按照连接顺序自动定址，各模块的通讯地址与 初始地址、该模块在多轴驱控系统中的安装位置以及预设的计算规则关联，无需工人手动定址，避免了人工定址耗时长、易于出错的问题。
附图说明
为了更清楚的说明本申请实施例或现有技术的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种多轴驱控系统的结构示意图；
图2为本申请实施例提供的地址输出端口和地址输入端口的接线图；
图3为本申请实施例提供的一种初始地址生成电路的电路图；
图4为本申请实施例提供的一种驱控模块的地址校验电路的电路图；
图5为本申请实施例提供的一种逆变模块的电路图。
具体实施方式
本申请的核心是提供一种多轴驱控系统，用于解决现有技术中多轴驱控一体机各模块定址不便、易出错的问题。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1为本申请实施例提供的一种多轴驱控系统的结构示意图；图2为本申请实施例提供的地址输出端口和地址输入端口的接线图。
如图1所示，本申请实施例提供的多轴驱控系统包括驱控模块和与驱控模块级联的多个逆变模块；
其中，驱控模块包括第一地址输入端口B和第一地址输出端口A，逆 变模块包括第二地址输入端口Y和第二地址输出端口X；
驱控模块的第一地址输出端口A与各逆变模块中的首个逆变模块的第二地址输入端口Y连接，自首个逆变模块起，各逆变模块两两串接，且前一逆变模块的第二地址输出端口X与后一逆变模块的第二地址输入端口Y连接；
驱控模块用于生成初始地址发送至首个逆变模块；各逆变模块用于按预设计算规则对自本地的地址输入端口接收的通讯地址进行计算后得到本地通讯地址，并将本地通讯地址发送至下一个逆变模块。
在具体实施中，如图1所示，驱控模块的第一地址输出端口A与逆变模块1的第二地址输入端口Y连接，逆变模块2的第二地址输出端口X与逆变模块3的第二地址输入端口Y连接，以此类推。如图2所示，以各模块的通讯地址为四位为例，在相邻的两个模块间，地址输出端口(A/X)的地址线A0_OUT、A1_OUT、A2_OUT、A3_OUT和地址输入端口(B/Y)的地址线A0_IN、A1_IN、A2_IN、A3_IN一一连接，地址输出端口(A/X)的GND与地址输入端口(B/Y)的GND均接地。可以理解的是，若通讯地址为四位，逆变模块的数量不能超过15个。若需要连接更多的逆变模块，可扩展通讯地址的位数。
因此，驱控模块和各逆变模块在通过地址输出端口和地址输入端口串接后，由驱控模块产生初始地址，各逆变模块就可以在初始地址的基础上依次完成自身的定址。而驱控模块根据逆变模块的数量和各逆变模块上的预设计算规则即可确定各逆变模块的地址，在各模块均完成定址后，驱控模块按照各逆变模块的地址与各逆变模块进行通信。驱控模块与各逆变模块之间可以采用RS232的方式一一连接通信，而为了减少布线数量、提高通讯效率，驱控模块与各逆变模块之间通过RS485通信端口通信连接。
如图1所示，在PCB板上，可将驱控模块安装在最左侧的起始位置，将逆变模块在驱控模块右侧依次累加放置组装，RS485通信端口通过PCB板，分别把各模块的485+/485-连接在一起，驱控模块的第一地址输出端口A通过PCB上的排插连接逆变模块1的第二地址输入端口Y，后边的逆变模块以此类推级联，末端逆变模块n的第二地址输出端口X可通过信号线 返回驱控模块的第一地址输入端口B。
驱控模块包括第一处理器U4、人机交互接口(包括显示屏、按键等)等，用于接收输入的初始地址并控制第一地址输出端口A发送初始地址。其中，第一处理器U4通常采用ARM处理器。可以由第一处理器U4生成初始地址并通过第一地址输出端口A输出至逆变模块1。驱控模块还可以进一步包括初始地址生成电路，则第一处理器U4的输入端与第一地址输入端口B连接，初始地址生成电路的输出端与第一地址输出端口A连接。进一步的，末端逆变模块n的第二地址输出端口X与驱控模块的第一地址输入端口B连接，将末端逆变模块n的通讯地址发送至驱控模块，由第一处理器U4根据末端逆变模块n的通讯地址及逆变模块的数量进行对各逆变模块的地址校验，实现多轴驱控系统在各模块定址后的地址自动校验。
各逆变模块上的预设计算规则可以为累加1，如驱控模块上设定初始地址为0，则逆变模块1的地址为1，逆变模块2的地址为2，以此类推。各逆变模块上的预设计算规则也可以为累减1，或其他计算方式，在此不一一赘述。
本申请实施例提供的多轴驱控系统，包括驱控模块和与驱控模块级联的多个逆变模块，其中，驱控模块包括第一地址输入端口和第一地址输出端口，逆变模块包括第二地址输入端口和第二地址输出端口；驱控模块的第一地址输出端口与各逆变模块中的首个逆变模块的第二地址输入端口连接，自首个逆变模块起，各逆变模块两两串接，且前一逆变模块的第二地址输出端口与后一逆变模块的第二地址输入端口连接；驱控模块用于生成初始地址发送至首个逆变模块；各逆变模块用于按预设计算规则对自本地的地址输入端口接收的通讯地址进行计算后得到本地通讯地址，并将本地通讯地址发送至下一个逆变模块，从而在驱控模块与各逆变模块连接后，可以实现从驱控模块到各逆变模块按照连接顺序自动定址，各模块的通讯地址与初始地址、该模块在多轴驱控系统中的安装位置以及预设的计算规则关联，无需工人手动定址，避免了人工定址耗时长、易于出错的问题。
图3为本申请实施例提供的一种初始地址生成电路的电路图；图4为 本申请实施例提供的一种驱控模块的地址校验电路的电路图。
在上述实施例的基础上，本申请实施例提供驱控模块的具体电路实现方案。为方便统一说明，本申请实施例和下述实施例均以地址位数为四位、各模块累加1的计算方式来说明。
如图3所示，在驱控模块上，初始地址生成电路由四个下拉电阻R13、R14、R15、R16组成，各下拉电阻的第一端均接地，各下拉电阻的第二端分别与驱控模块的第一地址输出端口AA0_OUT、A1_OUT、A2_OUT、A3_OUT连接。具体的接线方式为：下拉电阻R13的1脚接GND，2脚接端口信号A0_OUT；下拉电阻R14的1脚接GND,2脚接端口信号A1_OUT；下拉电阻R15的1脚接GND,2脚接端口信号A2_OUT；下拉电阻R16的1脚接GND,2脚接端口信号A3_OUT。初始地址生成电路使第一地址输出端口A对地默认输出低电平信号，作为初始地址0000。
为保证输入输出的隔离，驱控模块还包括设于第一地址输入接口和第一处理器U4之间的第一光耦U2。
如图4所示，驱控模块的第一地址输入端口B(A0_IN、A1_IN、A2_IN、A3_IN)与四个第一光耦U2的负极输入端连接，各第一光耦U2的正极输入端均连接+5V电源，各第一光耦U2的正极输出端分别与四个上拉电阻R21、R24、R22、R27和第一处理器U4连接。此外，第一光耦U2的输入端还包括限流电阻R25、R28、R30、R32和分压电阻R26、R29、R31、R33。第一处理器U4的第二端还包括上拉电阻R39、R38和电源退耦电容C1，第一处理器U4的SDA端口、SCL端口通过上拉电阻R39、R38连接EPROM U13的SDA端口、SCL端口。
驱控模块的地址校验电路的具体接线方式为：限流电阻R25的2脚接电源5V，1脚接第一光耦U2的7脚和分压电阻R26的2脚；限流电阻R28的2脚接电源5V，1脚接第一光耦U2的5脚和分压电阻R29的2脚；限流电阻R30的2脚接电源5V，1脚接第一光耦U2的3脚和分压电阻R31的2脚；限流电阻R32的2脚接电源5V，1脚接第一光耦U2的1脚和分压电阻R33的2脚；第一光耦U2的8脚接分压电阻R26的1脚后接A0_IN；第一光耦U2的6脚接分压电阻R29的1脚后接A_IN；第一光耦U2的4 脚接分压电阻R31的1脚后接A2_IN；第一光耦U2的2脚接分压电阻R33的1脚后接A3_IN；上拉电阻R21的2脚接上拉电阻R24的2脚接上拉电阻R22的2脚接上拉电阻R27的2脚后接+3.3V电源；上拉电阻R21的1脚接第一光耦U2的10脚和第一处理器U4的1脚(AD0)；上拉电阻R22的1脚接第一光耦U2的12脚和第一处理器U4的2脚(AD1)；上拉电阻R24的1脚接第一光耦U2的14脚和第一处理器U4的3脚(AD2)；上拉电阻R27的1脚接第一光耦U2的16脚和第一处理器U4的4脚(AD3)；第一光耦U2的9、11、13、15脚接GND；第一处理器U4的5脚接上拉电阻R39的1脚和EPROM U13的5脚；第一处理器U4的6脚接上拉电阻R38的1脚和EPROM U13的6脚；上拉电阻R38的2脚和上拉电阻R39的2脚接+3.3V电源和电源退耦电容C1的1脚和EPROM U13的8脚；电源退耦电容C1的2脚接GND；EPROM U13的1、2、3、4、7脚接GND。
基于图4所示电路，末端逆变模块n的第二地址输出端口X的信号的电平即为驱控模块的第一地址输入端口B的信号的电平，四位地址信号通过驱控模块的第一光耦U2输出，送到第一处理器U4的引脚AD0、AD1、AD2、AD3，第一处理器U4读取引脚电平，识别数值为n，确定逆变模块的地址数为n，而后将该数据通过引脚SDA、SCL写入EPROM U13。而后驱控模块作为主通信和每个地址的逆变模块进行一次通信，确认各逆变模块的通讯地址均可用后，在显示屏上显示系统连接成功的信息。
图5为本申请实施例提供的一种逆变模块的电路图。
如图5所示，在本申请实施例提供的多轴驱控系统中，逆变模块具体包括计算器电路和第二处理器U3；
在一个逆变模块中，计算器电路的输入端与第二地址输入接口连接，计算器电路的输出端分别与第二处理器U3的输入端和第二地址输出接口连接。
为保证输入输出的隔离，逆变模块还包括设于第二地址输入接口和计算器电路之间的第二光耦U5，以及设于计算器电路的输出端和第二地址输出接口之间的第三光耦U6。
如图5所示，第二光耦U5的正极输入端与第一电源+5V连接，第二光耦U5的负极输入端与第二地址输入接口连接，第二光耦U5的正极输出端分别与第一上拉电阻R314、R315、R317、R1和第二处理器U3的输入端连接，第二光耦U5的负极输出端接地；
第三光耦U6的正极输入端与第二电源+3.3V连接，第三光耦U6的负极输入端与第二处理器U3的输出端连接，第三光耦U6的正极输出端分别与第二上拉电阻R3、R10、R11、R12和第二地址输出端口X连接，第三光耦U6的负极输出端接地。
此外，第二光耦U5的输入端还包括限流电阻R19、R4、R6、R8和分压电阻R18、R5、R7、R9。第三光耦U6的输入端还包括限流电阻R17、R20、R23、R2。第二处理器U3的第二端还通过上拉电阻R37、R36与EPROM U38连接，第二处理器U3的第二端还包括电源退耦电容C16。
计算器电路可以采用加法器U1或减法器或FPGA或CPLD。本申请实施例中以累加1的计算规则为例，故计算器电路可采用加法器U1。
逆变模块的具体接线方式为：限流电阻R19的2脚接电源5V，1脚接第二光耦U5的7脚和分压电阻R18的2脚；限流电阻R4的2脚接电源+5V，1脚接第二光耦U5的5脚和分压电阻R5的2脚；限流电阻R6的2脚接电源+5V，1脚接第二光耦U5的3脚和分压电阻R7的2脚；限流电阻R8的2脚接电源+5V，1脚接第二光耦U5的1脚和分压电阻R9的2脚；第二光耦U5的8脚接分压电阻R18的1脚和端口信号A0_IN；第二光耦U5的6脚接分压电阻R5的1脚和端口信号A1_IN；第二光耦U5的4脚接分压电阻R7的1脚和端口信号A2_IN；第二光耦U5的2脚接分压电阻R9的1脚和端口信号A3_IN；第一上拉电阻R314的2脚接第一上拉电阻R315的2脚接第一上拉电阻R317的2脚接第一上拉电阻R1的2脚后接+3.3V电源；第一上拉电阻R314的1脚接第二光耦U5的10脚和加法器U1的1脚；第一上拉电阻R315的1脚接第二光耦U5的12脚和加法器U1的2脚；第一上拉电阻R317的1脚接第二光耦U5的14脚和加法器U1的3脚；第一上拉电阻R1的1脚接第二光耦U5的16脚和加法器U1的4脚；
加法器U1的16、5脚接+3.3V电源，加法器U1的6、7、8、10、15接GND；加法器U1的9脚接R34的1脚，电阻R34的2脚接GND；
加法器U1的14脚接第三光耦U6的6脚和第二处理器U3的1脚；加法器U1的13脚接第三光耦U6的4脚和第二处理器U3你的2脚；加法器U1的12脚接第三光耦U6的2脚和第二处理器U3的3脚；加法器U1的11脚接第三光耦U6的8脚和第二处理器U3的4脚；
第二处理器U3的5脚接上拉电阻R37的1脚和EPROM U38的5脚；第二处理器U3的6脚接上拉电阻R36的1脚和EPROM U38的6脚；上拉电阻R37的2脚和上拉电阻R36的2脚接+3.3V电源和电源退耦电容C98的1脚和EPROM U38的8脚；电源退耦电容C98的2脚接GND；EPROM U38的1、2、3、4、7脚接GND；
分压电阻R17的2脚接分压电阻R20的2脚接分压电阻R23的2脚接分压电阻R2的2脚接+3.3V；分压电阻R17的1脚接第三光耦U6的5脚；分压电阻R20的1脚接第三光耦U6的3脚；分压电阻R23的1脚接第三光耦U6的1脚；分压电阻R2的1脚接第三光耦U6的7脚；
第二上拉电阻R3的1脚接第二上拉电阻R10的1脚接第二上拉电阻R11的1脚接第二上拉电阻R12的1脚接+5V电源；第二上拉电阻R3的2脚接第三光耦U6的12脚接端口信号A0_OUT；第二上拉电阻R10的2脚接第三光耦U6的14脚接端口信号A1_OUT；第二上拉电阻R11的2脚接第三光耦U6的16脚接端口信号A2_OUT；第二上拉电阻R12的2脚接第三光耦U6的10脚接端口信号A3_OUT；第三光耦U6的11、13、15、9脚接GND。
基于图5所示的逆变模块的电路，逆变模块1的第二地址输入端口Y接收来自驱控模块的第一地址输出端口A的四个低电平信0000，使逆变模块1的四路第二光耦U5导通，第二光耦U5的10、12、14、16脚输出低电平信号，对应第二处理器U3的A0、A1、A2、A3信号为低电平，用数字量代替就是0000；(以下为方便介绍均用数字量表示)。加法器U1的Cin接3.3V为高电平信号实现自动累加功能，则逆变模块1的加法器U1的引脚输出电平为S0、S1、S2、S3输出为0001，此时逆变模块1的ARM通 过读取引脚电平AD0、AD1、AD2、AD3为0001；逆变模块1的第二处理器U3识别为1，则设置本地通讯地址为1，然后把这个数据通过引脚SDA和SCL写入到EPROM U38中；同时电平信号通过第三光耦U6传输到逆变模块1的第二地址输出端口X，第二地址输出端口X的电平为0001，此信号会通过排插传输到逆变模块2的第二地址输入端口Y，即逆变模块2的第二地址输入端口Y的信号对应电平为0001，那么逆变模块2的第二光耦U5输出引脚10、12、14、16输出为0001，对应加法器U1引脚A0、A1、A2、A3电平表示为0001，此时加法器U1Cin为高电平，在0001基础上加1，则加法器U1的引脚S0、S1、S2、S3输出为0010,此时逆变模块2的第二处理器U3通过读取引脚电平AD0、AD1、AD2、AD3为0010,识别为2；则设置本地通讯地址为2，然后把这个数据通过引脚SDA和SCL写入到EPROM U38中；同时电平信号通过第三光耦U6传输到逆变模块2的第二地址输出端口X，第二地址输出端口X电平分别为0010，此信号会通过排插传输到下一个逆变模块3的端口Y……以此类推，完成所有逆变模块的通讯地址的定址。
以上对本申请所提供的一种多轴驱控系统进行了详细介绍。说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一 个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。

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  1. 一种多轴驱控系统，其特征在于，包括驱控模块和与所述驱控模块级联的多个逆变模块；
    其中，所述驱控模块包括第一地址输入端口和第一地址输出端口，所述逆变模块包括第二地址输入端口和第二地址输出端口；
    所述驱控模块的第一地址输出端口与各所述逆变模块中的首个逆变模块的第二地址输入端口连接，自所述首个逆变模块起，各所述逆变模块两两串接，且前一所述逆变模块的第二地址输出端口与后一所述逆变模块的第二地址输入端口连接；
    所述驱控模块用于生成初始地址发送至所述首个逆变模块；各所述逆变模块用于按预设计算规则对自本地的地址输入端口接收的通讯地址进行计算后得到本地通讯地址，并将所述本地通讯地址发送至下一个所述逆变模块。
  2. 根据权利要求1所述的多轴驱控系统，其特征在于，所述驱控模块生成所述初始地址发送至所述首个逆变模块，具体为：
    所述驱控模块的第一处理器生成所述初始地址并通过所述第一地址输出端口输出至所述首个逆变模块。
  3. 根据权利要求1所述的多轴驱控系统，其特征在于，所述驱控模块具体包括初始地址生成电路和第一处理器；
    其中，所述第一处理器的输入端与所述第一地址输入端口连接，所述初始地址生成电路的输出端与所述第一地址输出端口连接。
  4. 根据权利要求2或3任意一项所述的多轴驱控系统，其特征在于，所述第一地址输入端口与各所述逆变模块中的末端逆变模块的第二地址输出端口连接；
    所述第一处理器还用于根据所述末端逆变模块的通讯地址及所述逆变模块的数量进行对各所述逆变模块的地址校验。
  5. 根据权利要求4所述的多轴驱控系统，其特征在于，所述驱控模块还包括设于所述第一地址输入接口和所述第一处理器之间的第一光耦。
  6. 根据权利要求1所述的多轴驱控系统，其特征在于，所述逆变模块 具体包括计算器电路和第二处理器；
    在一个所述逆变模块中，所述计算器电路的输入端与所述第二地址输入接口连接，所述计算器电路的输出端分别与所述第二处理器的输入端和所述第二地址输出接口连接。
  7. 根据权利要求6所述的多轴驱控系统，其特征在于，所述逆变模块还包括设于所述第二地址输入接口和所述计算器电路之间的第二光耦，以及设于所述计算器电路的输出端和所述第二地址输出接口之间的第三光耦。
  8. 根据权利要求7所述的多轴驱控系统，其特征在于，所述第二光耦的正极输入端与第一电源连接，所述第二光耦的负极输入端与所述第二地址输入接口连接，所述第二光耦的正极输出端分别与第一上拉电阻和所述第二处理器的输入端连接，所述第二光耦的负极输出端接地；
    所述第三光耦的正极输入端与第二电源连接，所述第三光耦的负极输入端与所述第二处理器的输出端连接，所述第三光耦的正极输出端分别与第二上拉电阻和所述第二地址输出端口连接，所述第三光耦的负极输出端接地。
  9. 根据权利要求6所述的多轴驱控系统，其特征在于，所述计算器电路具体为加法器或减法器或FPGA或CPLD。
  10. 根据权利要求1所述的多轴驱控系统，其特征在于，所述驱控模块还与各所述逆变模块之间通过RS485通信端口通信连接。
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