WO2021159243A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021159243A1
WO2021159243A1 PCT/CN2020/074646 CN2020074646W WO2021159243A1 WO 2021159243 A1 WO2021159243 A1 WO 2021159243A1 CN 2020074646 W CN2020074646 W CN 2020074646W WO 2021159243 A1 WO2021159243 A1 WO 2021159243A1
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Prior art keywords
substrate
layer
reflection
reflection layer
active layer
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PCT/CN2020/074646
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English (en)
French (fr)
Inventor
贾宜訸
丁向前
宋勇志
庞妍
张小祥
韩皓
杨连捷
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000103.1A priority Critical patent/CN113519061B/zh
Priority to PCT/CN2020/074646 priority patent/WO2021159243A1/zh
Publication of WO2021159243A1 publication Critical patent/WO2021159243A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device.
  • an array substrate includes a substrate, a thin film transistor, and a first anti-reflection layer.
  • the thin film transistor is arranged on the substrate, the thin film transistor includes an active layer, a source and a drain; the source and the drain are arranged on the active layer away from the substrate One side; the source and the drain include a contact portion that is in contact with the active layer and a non-contact portion that is not in contact with the active layer.
  • the first anti-reflective layer is located on a side of the source and the drain close to the substrate; the first anti-reflective layer and at least one of the source and the drain are not
  • the contact portion is in contact, and the orthographic projection of the first anti-reflection layer on the substrate at least partially overlaps with the orthographic projection of the non-contact portion on the substrate.
  • the orthographic projection of the first anti-reflection layer on the substrate and the orthographic projection of the active layer on the substrate have no or substantially no overlap.
  • the first anti-reflection layer is located on a side of the active layer close to the substrate, and the active layer is in contact with the first anti-reflection layer; the first anti-reflection layer
  • the orthographic projection on the substrate covers the orthographic projection of the active layer, the source electrode and the drain electrode on the substrate.
  • the thickness of the first anti-reflection layer ranges from 500 nm to 600 nm; the refractive index of the first anti-reflection layer ranges from 2.2 to 2.3.
  • the material of the first anti-reflection layer includes metal oxide.
  • the material of the first anti-reflection layer includes at least one of molybdenum oxide and zinc oxide.
  • the array substrate further includes data lines.
  • the data line is electrically connected to the source of the thin film transistor and is arranged in the same layer; the first anti-reflection layer is in contact with the data line, and the orthographic projection of the first anti-reflection layer on the substrate Cover the orthographic projection of the data line on the substrate.
  • the thin film transistor further includes a gate located on a side of the active layer close to the substrate; the array substrate further includes a gate located between the gate and the active layer. Gate insulation layer between layers.
  • the thin film transistor further includes a gate, a gate insulating layer, and an interlayer dielectric layer.
  • the gate is located on the side of the active layer away from the substrate; the gate insulating layer is located between the gate and the active layer; the interlayer dielectric layer is located on the gate Between the electrode and the source electrode and the drain electrode.
  • the first anti-reflection layer is located between the interlayer dielectric layer and the source electrode and the drain; the gate insulating layer, the interlayer dielectric layer and the first anti-reflection layer are provided There are at least two contact holes, and the source electrode and the drain electrode are respectively in electrical contact with the active layer through the at least two contact holes; the orthographic projection of the first anti-reflection layer on the substrate , Covering the orthographic projection of the source electrode and the drain electrode, excluding the part at the at least two contact holes, on the substrate.
  • the array substrate further includes a second anti-reflection layer.
  • the second anti-reflection layer is located on the side of the gate close to the substrate; the gate is in contact with the second anti-reflection layer, and the second anti-reflection layer is on the substrate
  • the orthographic projection covers the orthographic projection of the grid on the substrate.
  • the array substrate further includes gate lines.
  • the gate line is electrically connected to the gate of the thin film transistor and arranged in the same layer; the second anti-reflection layer is in contact with the gate line, and the orthographic projection of the second anti-reflection layer on the substrate Cover the orthographic projection of the grid line on the substrate.
  • a display device in another aspect, includes the array substrate, the counter substrate, and the backlight module as described in some of the above embodiments.
  • the counter substrate is disposed opposite to the array substrate, and the backlight module is disposed on a side of the counter substrate away from the array substrate.
  • a method for preparing an array substrate includes: providing a substrate, and forming an active layer of a thin film transistor on the substrate; and forming the active layer on a side of the active layer away from the substrate.
  • the source electrode and the drain electrode of the thin film transistor; the source electrode and the drain electrode include a contact portion contacting the active layer and a non-contact portion not contacting the active layer.
  • the preparation method further includes: before forming the source electrode and the drain electrode, forming a first anti-reflection layer on the substrate; the first anti-reflection layer and the source electrode and the drain electrode The non-contact part of at least one of them is in contact, and the orthographic projection of the first anti-reflection layer on the substrate at least partially overlaps the orthographic projection of the non-contact part on the substrate.
  • forming the active layer, the first anti-reflection layer, the source electrode, and the drain electrode on the substrate includes: forming the active layer on the substrate Layer; deposit the material to be formed into the first anti-reflective layer on the substrate to form a first anti-reflective film; remove the part of the first anti-reflective film that covers or roughly covers the active layer, so that it passes through the The orthographic projection of the first anti-reflection film on the substrate in the removal process does not overlap or substantially does not overlap with the active layer; it is formed on the side of the first anti-reflection film that has undergone the above removal process away from the substrate The source and the drain.
  • forming the active layer, the first anti-reflection layer, the source electrode, and the drain electrode on the substrate includes: depositing a semiconductor material on the substrate to form A semiconductor film; a first photoresist material is coated on the side of the semiconductor film away from the substrate to form a first photoresist film; a first mask is used to remove the first photoresist film to be formed The area outside the active layer is formed as a first photoresist layer that shields the area where the active layer is to be formed; using the first photoresist layer as a mask, the semiconductor thin film is etched to form the active layer Layer; deposit the material to be formed into the first anti-reflection layer on the side of the active layer away from the substrate to form a first anti-reflection film; coat the side of the first anti-reflection film away from the substrate Cover the second photoresist material to form a second photoresist film; using the first mask to remove the second photoresist film in the active layer area, the first anti-reflection
  • forming the first anti-reflection layer, the active layer, the source electrode, and the drain electrode on the substrate includes: depositing the first layer to be formed on the substrate The material of the anti-reflection layer forms a first anti-reflection film; the active layer is formed on the side of the first anti-reflection film away from the substrate; and the active layer is formed on the side of the active layer away from the substrate Depositing the materials to be formed into the source electrode and the drain electrode to form a conductive film; patterning the conductive film and the first anti-reflection film to form the source electrode, the drain electrode and the first anti-reflection layer, and The orthographic projection of the first anti-reflection layer on the substrate covers the orthographic projection of the active layer, the source electrode and the drain electrode on the substrate.
  • forming the first anti-reflection layer, the active layer, the source electrode, and the drain electrode on the substrate includes: depositing the first layer to be formed on the substrate The material of the anti-reflection layer forms a first anti-reflection film; a semiconductor material is deposited on the side of the first anti-reflection film away from the substrate to form a semiconductor film; the semiconductor film is patterned by using a first mask , Forming the active layer; depositing the material to be formed with source and drain electrodes on the side of the active layer away from the substrate to form a conductive film; using a second mask to etch the conductive film And the first anti-reflection film to obtain the source electrode, the drain electrode and the first anti-reflection layer.
  • FIG. 1 is a top view of an array substrate according to some embodiments
  • FIG. 2 is a cross-sectional view of the array substrate in FIG. 1 along B-B';
  • FIG. 3 is a structural diagram of an array substrate according to some embodiments.
  • FIG. 4 is another structural diagram of an array substrate according to some embodiments.
  • FIG. 5 is another structural diagram of an array substrate according to some embodiments.
  • Fig. 6 is a cross-sectional view of the array substrate in Fig. 1 taken along C-C';
  • FIG. 7 is another top view of an array substrate according to some embodiments.
  • Fig. 8 is a cross-sectional view of the array substrate in Fig. 7 along D-D';
  • FIG. 9 is another structural diagram of an array substrate according to some embodiments.
  • FIG. 10 is another structural diagram of an array substrate according to some embodiments.
  • FIG. 11 is another structural diagram of an array substrate according to some embodiments.
  • FIG. 12 is another structural diagram of an array substrate according to some embodiments.
  • FIG. 13 is still another top view of an array substrate according to some embodiments.
  • Fig. 14 is a cross-sectional view of the array substrate in Fig. 13 taken along E-E';
  • FIG. 15 is a structural diagram of a display device according to some embodiments.
  • FIG. 16 is a preparation flow chart of the array substrate according to some embodiments.
  • FIG. 17 is a manufacturing process diagram of the array substrate according to some embodiments.
  • FIG. 18 is another preparation flow chart of the array substrate according to some embodiments.
  • FIG. 19 is a diagram of another manufacturing process of the array substrate according to some embodiments.
  • FIG. 20 is another preparation flow chart of the array substrate according to some embodiments.
  • FIG. 21 is a diagram of still another manufacturing process of the array substrate according to some embodiments.
  • FIG. 22 is another preparation flow chart of the array substrate according to some embodiments.
  • FIG. 23 is a diagram of still another manufacturing process of the array substrate according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • the display device includes an array substrate, an opposite substrate, and a backlight module.
  • the counter substrate and the array substrate are disposed oppositely, and the backlight module is disposed on a side of the counter substrate away from the array substrate.
  • the light emitted by the backlight module passes through the opposite substrate to the array substrate, and exits from the side of the array substrate away from the opposite substrate.
  • part of the structure in the array substrate has high light reflection performance, when the ambient light enters the display device from the side of the array substrate away from the opposite substrate, the ambient light is reflected on the array substrate, and the reflection The light is emitted from the side of the array substrate away from the opposite substrate, so that the display device in the dark state will display bright spots, which reduces the display effect of the display device in the dark state.
  • the array substrate 1 includes: a substrate 10, a thin film transistor (TFT for short), and One anti-reflective layer 11.
  • TFT thin film transistor
  • the array substrate 1 has a display area A and a peripheral area S, and the peripheral area S is located on at least one side of the display area A.
  • a plurality of sub-pixels P are arranged in the display area A. As shown in FIG. 1, a plurality of sub-pixels P may be arranged in an array.
  • the sub-pixels P arranged in a row along the horizontal direction X are called sub-pixels in the same row, and the sub-pixels in the same row may be electrically connected to a gate line 21.
  • the sub-pixels P arranged in a row along the vertical direction Y are called sub-pixels in the same column, and the sub-pixels in the same column may be electrically connected to one data line 15.
  • the TFT is disposed on the substrate 10, and the TFT includes an active layer 12, a source 13 and a drain 14 disposed on the side of the active layer 12 away from the substrate 10.
  • the source electrode 13 and the drain electrode 14 include a contact portion T1 that is in contact with the active layer 12 and a non-contact portion T2 that is not in contact with the active layer 12.
  • the first anti-reflection layer 11 is located on the side of the source 13 and the drain 14 close to the substrate 10.
  • the first anti-reflection layer 11 is in contact with the non-contact portion T2 of at least one of the source electrode 13 and the drain electrode 14, and the orthographic projection of the first anti-reflection layer 11 on the substrate 10 is in line with the non-contact portion T2.
  • the orthographic projections on the bottom 10 overlap at least partially.
  • the first anti-reflection layer 11 is in contact with the non-contact portion T2 of at least one of the source electrode 13 and the drain electrode 14, which may be that the non-contact portion T2 in the drain electrode 14 is in contact with the first anti-reflection layer 11.
  • the non-contact portion T2 in the source electrode 13 may be in contact with the first anti-reflection layer 11 (as shown in FIG. 3), and it may be the non-contact portion T2 and the drain electrode 14 in the source electrode 13
  • the non-contact portions T2 in the middle are all in contact with the first anti-reflection layer 11 (as shown in FIG. 4).
  • the first anti-reflection layer 11 is used to reduce the amount of light that is reflected in the light incident to the inside.
  • the ambient light enters the interior of the array substrate 1 from the substrate 10, and after passing through the first anti-reflection layer 11, the amount of reflected light in the ambient light is reduced, reducing at least the amount of ambient light in the source 13 and drain 14
  • One of the non-contact parts T2 has a reflective reflectivity on the surface on the side close to the substrate 10, so as to avoid the problem that ambient light is reflected inside the array substrate 1 and emitted from the substrate 10, which affects the dark state display effect.
  • ambient light enters the inside of the array substrate 1 from the substrate 10, due to the non-contact portion T2 of at least one of the source 13 and the drain 14 and the first anti-reflection layer 11 Therefore, the ambient light directed to the source 13 and the drain 14 will first pass through the first anti-reflection layer 11.
  • the reflected light of the non-contact portion T2 near the substrate 10 side surface is reduced, reducing the ambient light on the non-contact portion T2 near the substrate 10 side surface of at least one of the source 13 and the drain 14 Reflective reflectivity, so as to prevent ambient light from being reflected on the non-contact part T2 of at least one of the source 13 and the drain 14 on the surface close to the substrate 10.
  • the reflected light exits the substrate 10 and affects The problem of the dark state display effect can improve the dark state display effect of the display device.
  • the orthographic projection of the first anti-reflection layer 11 on the substrate 10 and the orthographic projection of the active layer 12 on the substrate 10 have no or substantially no overlap. In this way, the contact portion T1 of the source electrode 13 and the drain electrode 14 which is in contact with the active layer 12 has no contact or substantially no contact with the first anti-reflection layer 11. At this time, the source electrode 13 and the drain electrode 14 are in contact with the active layer 12 The signal transmission therebetween will not be affected by the first anti-reflection layer 11.
  • the first anti-reflection layer 11 is located on the side of the active layer 12 close to the substrate 11, and the active layer 12 is in contact with the first anti-reflection layer 11.
  • the orthographic projection of the first anti-reflection layer 11 on the substrate 10 covers the orthographic projection of the active layer 12, the source electrode 13 and the drain electrode 14 on the substrate 10.
  • the first anti-reflection layer 11 can reduce the amount of light reflected from the ambient light emitted from the substrate 10 to the active layer 12, the source electrode 13 and the drain electrode 14, and reduce the amount of ambient light on the active layer 12.
  • the ambient light enters the array substrate 1 from the substrate 10 and passes through the first anti-reflection layer 11. A part of the light will be reflected on the surface of the first anti-reflection layer 11, and another part of the light will pass through the first anti-reflection layer. 11. Reflection occurs on the contact surface of the first anti-reflection layer 11 and the non-contact portion T2 of at least one of the source 13 and the drain 14, and the two kinds of reflected reflected light can occur during the transmission process.
  • the interference cancels, so that the reflected light reflected by the ambient light on the surface of the non-contact portion T2 of at least one of the source 13 and the drain 14 near the substrate 10 is eliminated, thereby avoiding the reflected ambient light from the substrate 10
  • the thickness of the first anti-reflection layer 11 ranges from 500 nm to 600 nm, and the refractive index of the first anti-reflection layer 11 ranges from 2.2 to 2.3. In this way, the reflectance of the ambient light incident on the array substrate 1 can be greatly reduced.
  • the material of the first anti-reflection layer 11 includes metal oxide.
  • the material of the first anti-reflection layer 11 includes at least one of molybdenum oxide (MoO x ) and zinc oxide (ZnO x ).
  • molybdenum oxide is translucent, and zinc oxide is transparent.
  • the material of the first anti-reflection layer 11 includes molybdenum oxide, at least a part of the ambient light incident on the first anti-reflection layer 11 can be absorbed by the first anti-reflection layer 11, reducing the transmittance of the ambient light. Overrate.
  • the array substrate 1 further includes a data line 15.
  • the data line 15 is electrically connected to the source electrode 14 of the TFT, and is arranged in the same layer.
  • the first anti-reflection layer 11 is in contact with the data line 15, and the orthographic projection of the first anti-reflection layer 11 on the substrate 10 covers the orthographic projection of the data line 15 on the substrate 10.
  • the material of the data line 15 and the source electrode 14 of the TFT can be the same.
  • the data line 15 and the source electrode 14 of the TFT can be formed synchronously in the process.
  • the data line 15 and the source electrode 14 of the TFT may be an integral structure.
  • the first anti-reflection layer 11 is located on the side of the data line 15 close to the substrate 10. Since the first anti-reflection layer 11 is in contact with the data line 15, and the orthographic projection of the first anti-reflection layer 11 on the substrate 10 covers the orthographic projection of the data line 15 on the substrate 10, the first anti-reflection layer 11 will Anti-reflection of the ambient light incident on the data line 15 from the substrate 10 reduces the reflectivity of the ambient light reflected on the data line 15 and prevents the ambient light from being emitted from the substrate 10 after being reflected on the data line 15. The problem that affects the dark state display effect.
  • the TFT further includes a gate 16.
  • the gate 16 is located on the side of the active layer 12 close to the substrate 10.
  • the array substrate 1 further includes a gate insulating layer 17 located between the gate electrode 16 and the active layer 12.
  • the gate electrode 16 is made of the same material as the source electrode 13 and the drain electrode 14.
  • the gate insulating layer 17 covers the substrate 10.
  • the gate electrode 16 is located on the side of the active layer 12 away from the substrate 10.
  • the array substrate 1 further includes a gate insulating layer 17 between the gate electrode 16 and the active layer 12 and an interlayer dielectric layer 18 between the gate electrode 16 and the source electrode 13 and the drain electrode 14.
  • the first anti-reflection layer 11 is located between the interlayer dielectric layer 18 and the source 13 and the drain 14.
  • At least two contact holes 19 are provided in the gate insulating layer 17, the interlayer dielectric layer 18, and the first anti-reflection layer 11, and the source electrode 13 and the drain electrode 14 are in electrical contact with the active layer 12 through the at least two contact holes 19, respectively.
  • the orthographic projection of the first anti-reflection layer 11 on the substrate 10 covers the orthographic projection of the source electrode 13 and the drain electrode 14, excluding the portions at the at least two contact holes 19 on the substrate 10.
  • the interlayer dielectric layer 18 and the gate insulating layer 17 both cover the substrate 10.
  • the at least two contact holes 19 provided in the gate insulating layer 17, the interlayer dielectric layer 18, and the first anti-reflection layer 11 pass through the gate insulating layer 17, the interlayer dielectric in a direction perpendicular to the substrate 10.
  • the layer 18 and the first anti-reflection layer 11 expose the active layer 12 located in the area of the contact hole 19, and the source electrode 13 and the drain electrode 14 are in contact with the active layer 12 through the contact hole 19.
  • the material for forming the first anti-reflection layer 11 is deposited on the surface of the interlayer dielectric layer 18 to form the first anti-reflection film, and then the contact hole 19 is formed, and then the material for forming the source electrode 13 and the drain electrode 14 is deposited, The conductive film is formed, and the first anti-reflection film and the conductive film are etched through a mask to form the source 13, drain 14 and the first anti-reflection layer 11, thereby reducing the number of masks and saving production costs.
  • the array substrate 1 further includes a light shielding layer 25 provided on the side of the active layer 12 close to the substrate 10.
  • the orthographic projection of the light shielding layer 25 on the substrate 10 at least covers the orthographic projection of the active layer 12 on the substrate 10.
  • a buffer layer 26 is provided between the light shielding layer 25 and the active layer 12.
  • the source electrode 13 or the drain electrode 14 is electrically connected to the light shielding layer 25 through a first via 41 provided on the interlayer dielectric layer 18, the gate insulating layer 17 and the buffer layer 26 along a direction perpendicular to the substrate 10.
  • the light-shielding layer 25 can prevent ambient light from irradiating the active layer 12 and prevent the threshold voltage of the TFT from shifting.
  • the light-shielding layer 25 may be conductive, so that the light-shielding layer 25 is electrically connected to the source electrode 13 or the drain electrode 14, so that the light-shielding layer 25 can generate a stable voltage and avoid the floating gate effect, thereby improving the working stability of the TFT.
  • the array substrate 1 further includes a second anti-reflection layer 20.
  • the second anti-reflection layer 20 is located on the side of the gate 16 close to the substrate 10.
  • the gate 16 is in contact with the second anti-reflection layer 20, and the orthographic projection of the second anti-reflection layer 20 on the substrate 10 covers the orthographic projection of the gate 16 on the substrate 10.
  • the material of the second anti-reflection layer 20 may be the same as the material of the first anti-reflection layer 10.
  • both materials may include at least one of metal oxides such as molybdenum oxide and zinc oxide; for example, both materials may be molybdenum oxide.
  • the orthographic projection of the second anti-reflection layer 20 on the substrate 10 covers the orthographic projection of the gate 16 on the substrate 10.
  • Anti-reflection of the ambient light reduces the reflectivity of the ambient light.
  • the reflectivity of the ambient light is reduced from about 55% to about 6%, so as to prevent the ambient light from being reflected on the grid 16 from being emitted from the substrate 10 and affecting the darkness. The problem of state display effect.
  • the array substrate 1 further includes gate lines 21.
  • the gate line 21 is electrically connected to the gate 16 of the TFT.
  • the gate line 21 and the gate electrode 16 are arranged in the same layer.
  • the second anti-reflection layer 20 is in contact with the gate line 21, and the orthographic projection of the second anti-reflection layer 20 on the substrate 10 covers the orthographic projection of the gate line 21 on the substrate 10.
  • the gate line 21 and the gate electrode 16 are made of the same material, and the gate line 21 and the gate electrode 16 can be formed synchronously in the process.
  • the gate line 21 and the gate 16 of the TFT may be an integral structure.
  • the second anti-reflection layer 20 is located on the side of the gate line 21 close to the substrate 10.
  • the second anti-reflection layer 20 is in contact with the gate line 21, and the orthographic projection of the second anti-reflection layer 20 on the substrate 10 covers the orthographic projection of the gate line 21 on the substrate 10. Therefore, the second anti-reflection layer 20
  • the ambient light incident from the substrate 10 to the gate line 21 will be anti-reflection to avoid the problem that the ambient light is emitted from the substrate 10 after being reflected on the gate line 21 and affects the dark state display effect.
  • the array substrate 1 further includes a first electrode 22 and a second electrode 23 arranged opposite to the first electrode 22.
  • the first electrode 22 and the second electrode 23 are made of the same material.
  • transparent conductive materials including ITO (Indium Tin Oxide) can be used.
  • the second electrode 23 is located on the side of the source 13 and the drain 14 close to the substrate 10, and the first electrode 22 is located on the side of the source 13 and the drain 14 away from the substrate 10.
  • the first electrode 22 has a plurality of slits, and the structure of the second electrode 23 is block-shaped.
  • the second electrode 23 and the gate electrode 16 of the TFT are arranged in the same layer and insulated from each other.
  • a passivation layer 24 is provided between the first electrode 22 and the source electrode 13 and the drain electrode 14.
  • the passivation layer 24 may be a single-layer or multi-layer structure.
  • the material of the passivation layer 24 may be an inorganic material including silicon nitride (Si x N y ) or silicon oxide (SiO x ).
  • the second electrode 23 may be formed on the substrate 10 through processes such as film formation, exposure, development, and etching.
  • the gate 16 is formed on the substrate 10 through processes such as film formation, exposure, development, and etching.
  • the gate 16 and the second electrode 23 are located in the same layer.
  • the first electrode 22 is formed through processes such as film formation, exposure, development, and etching.
  • the passivation layer 24 is provided with a second via 42 which is perpendicular to the substrate 10. Passing through the passivation layer 24 in the direction of, exposing the drain electrode 14, and the first electrode 22 covers the second via hole 42 and is electrically connected to the drain electrode 14.
  • a third via 43 is provided in the passivation layer 24 and the gate insulating layer 17, and the third The via hole 43 penetrates the passivation layer 24 and the gate insulating layer 17 in a direction perpendicular to the substrate 10, exposing the drain electrode 14 and the second electrode 23.
  • the array substrate 1 further includes a third via hole 43.
  • the first conductive pattern 31 and the first conductive pattern 31 cover at least the third via hole 43 and contact the drain 14 and the second electrode 23 to electrically connect the second electrode 23 and the drain 14.
  • the first conductive pattern 31 and the first electrode 22 have the same layer and the same material and are insulated from each other.
  • the first electrode 22 when the first electrode 22 is a common electrode, the first electrode 22 can be provided separately, and one first electrode 22 corresponds to one sub-pixel (as shown in FIG. 13). Alternatively, the first electrodes 22 in at least two sub-pixels in the same row of sub-pixels may be connected as an integral structure (not shown in the figure).
  • the array substrate 1 further includes a common electrode line 28.
  • the common electrode line 28 and the gate electrode 16 have the same layer and the same material.
  • the common electrode line 28 is electrically connected to the common electrode.
  • the common electrodes in the same row of sub-pixels are electrically connected to the same common electrode line 28.
  • the common electrode line 28 is located on the side of the second electrode 23 away from the substrate, and the common electrode line 28 is in contact with the second electrode 23.
  • the first electrode 22 is a common electrode, the first electrode 22 is disposed on the fourth pass of the passivation layer 24 and the gate insulating layer 17 along the direction perpendicular to the substrate 10.
  • the hole 44 is electrically connected to the common electrode line 28.
  • the array substrate 1 further includes a plurality of second conductive patterns 32 arranged at intervals.
  • any adjacent second conductive patterns 32 are at least separated by two sub-pixels.
  • a common electrode is electrically connected to a common electrode line 28 electrically connected to a row of common electrodes adjacent to the common electrode through the second conductive pattern 32.
  • the second conductive pattern 32 can make the two adjacent rows of sub-pixels The electrical signals of the common electrodes are nearly equal, so the voltage drop of each common electrode can be reduced.
  • An embodiment of the present disclosure also provides a display device 100.
  • the display device 100 includes the array substrate 1 provided by any one of the above-mentioned embodiments.
  • the display device 100 further includes an opposite substrate 2 and a backlight module 3.
  • the counter substrate 2 is disposed opposite to the array substrate 1, and the backlight module 3 is disposed on a side of the counter substrate 2 away from the array substrate 1.
  • the display device 100 further includes a liquid crystal layer 4 disposed between the array substrate 1 and the counter substrate 2.
  • the liquid crystal molecules located in the liquid crystal layer 4 can be located on the first electrode 22.
  • the deflection occurs under the action of the electric field formed with the second electrode 23.
  • the first anti-reflection layer 11 in the array substrate 1 can reduce the amount of light reflected in the ambient light and reduce the array substrate. 1
  • the reflectivity of the internal reflection so as to avoid the problem that the ambient light is emitted from the side of the array substrate 1 away from the opposite substrate 2 after being reflected inside the array substrate 1 and affects the dark state display effect.
  • the above-mentioned display device 100 may be any device that displays images whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display for the image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or portable computers GPS receivers/navigators,
  • an embodiment of the present disclosure provides a method for manufacturing an array substrate 1, including:
  • a substrate 10 is provided, and an active layer 12 of TFT is formed on the substrate 10.
  • the substrate 10 plays a supporting role, which can enable various subsequent layers (for example, the active layer 12, the first anti-reflection layer 11, etc.) to have higher stability and reliability.
  • various subsequent layers for example, the active layer 12, the first anti-reflection layer 11, etc.
  • the gate 16 and the gate insulating layer 17 on the side of the gate 16 away from the substrate 10 have been formed on the substrate 10.
  • the source electrode 13 and the drain electrode 14 include a contact portion T1 that is in contact with the active layer 12 and a non-contact portion T2 that is not in contact with the active layer 12.
  • gate insulation is sequentially formed along a direction perpendicular to the substrate 10.
  • the layer 17, the gate 16 and the interlayer dielectric layer 18, and the source electrode 13 and the drain electrode 14 are formed on the side of the interlayer dielectric layer 18 away from the substrate 10.
  • the preparation method of the array substrate 1 further includes:
  • a first anti-reflection layer 11 is formed on the substrate 10.
  • the first anti-reflection layer 11 is in contact with the non-contact portion T2 of at least one of the source electrode 13 and the drain electrode 14, and the orthographic projection of the first anti-reflection layer 11 on the substrate 10 is in contact with the non-contact portion T2.
  • the orthographic projections on the substrate 10 at least partially overlap.
  • the first anti-reflection layer 11 is formed between the source electrode 13 and the drain electrode 14 and the gate insulating layer 17.
  • the first anti-reflection layer 11 is formed between the source electrode 13 and the drain electrode 14 and the interlayer dielectric layer 18.
  • the first anti-reflection layer 11 is used to reduce the amount of light that is reflected in the light incident to the inside thereof. In this way, the ambient light enters the interior of the array substrate 1 from the substrate 10, and after passing through the first anti-reflection layer 11, the amount of reflected light in the ambient light is reduced, reducing at least the amount of ambient light in the source 13 and drain 14
  • One of the non-contact parts T2 has a reflective reflectivity on the surface on the side close to the substrate 10, so as to avoid the problem that ambient light is reflected inside the array substrate 1 and emitted from the substrate 10, which affects the dark state display effect.
  • forming the active layer 12, the first anti-reflection layer 11, the source electrode 13, and the drain electrode 14 on the substrate 10, as shown in FIG. 16, includes the following steps:
  • an active layer 12 is formed on the substrate 10.
  • the material of the first anti-reflection layer 11 to be formed is deposited on the substrate 10 to form the first anti-reflection film 101.
  • the material of the first anti-reflection layer 11 includes metal oxide, such as MoO x and the like.
  • a patterning process may be used to remove the part of the first anti-reflection film 101 covering or substantially covering the active layer 12.
  • a photoresist layer is formed on the side of the first anti-reflection film 101 away from the substrate 10; then the photoresist layer is exposed and developed to obtain a patterned photoresist layer.
  • the adhesive layer exposes the surface of the part of the first anti-reflection film 101 that covers or roughly covers the active layer 12; finally, the patterned photoresist layer is used to etch the first anti-reflection film 101 to remove the first anti-reflection film.
  • the thin film 101 covers or substantially covers the part of the active layer 12.
  • the source 13 and the drain 14 are formed on the side of the first anti-reflection film 101 far away from the substrate 10 after the above-mentioned removal process.
  • some specific preparation steps for preparing the active layer 12, the first anti-reflection layer 11, the source electrode 13, and the drain electrode 14 are exemplarily introduced below.
  • the same mask is used to prepare the first anti-reflection layer 11 and the active layer 12, that is, the mask for preparing the active layer 12 is used, which simplifies the preparation process and saves production costs. .
  • forming the active layer 12, the first anti-reflection layer 11, the source electrode 13, and the drain electrode 14 on the substrate 10, as shown in FIG. 18, includes the following steps:
  • a semiconductor material is deposited on the substrate 10 to form a semiconductor thin film 102.
  • the semiconductor material includes amorphous silicon (a-Si) or polycrystalline silicon (p-Si).
  • a first photoresist material is coated on the side of the semiconductor film 102 away from the substrate 10 to form a first photoresist film 501.
  • a first mask is used to remove parts of the first photoresist film 501 except for the area where the active layer 12 is to be formed, and form a first mask that shields the area where the active layer 12 is to be formed.
  • Photoresist layer 51 is used to remove parts of the first photoresist film 501 except for the area where the active layer 12 is to be formed, and form a first mask that shields the area where the active layer 12 is to be formed.
  • the first mask includes a plurality of first opening regions.
  • the first opening area corresponds to an area on the substrate 10 excluding the area where the active layer 12 is to be formed.
  • the first photoresist material is a negative photoresist, the first opening area corresponds to the area on the substrate 10 where the active layer 12 is to be formed.
  • the semiconductor thin film 102 is etched to form the active layer 12.
  • dry etching may be used when etching the semiconductor thin film 102.
  • the material for forming the first anti-reflection layer 11 is deposited on the side of the active layer 12 away from the substrate 10 to form the first anti-reflection film 101.
  • a second photoresist material is coated on the side of the first anti-reflection film 101 away from the substrate 10 to form a second photoresist film 502.
  • the first mask is used to remove the second photoresist film 502 in the area of the active layer 12, and an exposed active layer is formed on the side of the first anti-reflection film 101 away from the substrate 10. 12.
  • the second photoresist layer 52 wherein, the second photoresist material and the first photoresist material have opposite properties.
  • the first opening area of the first mask corresponds to the substrate 10 to be formed In the area outside the area of the active layer 12, the part of the second photoresist film 502 located in the area where the active layer 12 is to be formed is removed, and the second photoresist layer 52 is obtained.
  • the first opening area of the first mask corresponds to the area on the substrate 10 where the active layer 12 is to be formed .
  • the part of the second photoresist film 502 located in the region where the active layer 12 is to be formed is removed, and the second photoresist layer 52 is obtained.
  • the initial orthographic projection of the first anti-reflection layer 111 on the substrate 10 and the orthographic projection of the active layer 12 on the substrate 10 have no or substantially no overlap.
  • the source electrode 13 and the drain electrode 14 may be made of metal materials including copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), and tungsten (W).
  • Cu copper
  • Al aluminum
  • Mo molybdenum
  • Ti titanium
  • Cr chromium
  • W tungsten
  • the second mask is used to etch the conductive film 103 and the initial first anti-reflection layer 111 to form the source electrode 13, the drain electrode 14, and the first anti-reflection layer 11.
  • wet etching may be used when etching the conductive film 103 and the initial first anti-reflection layer 111.
  • the second mask includes a plurality of second opening regions.
  • the second opening area corresponds to the area on the substrate 10 except the area where the source electrode 13 and the drain electrode 14 are to be formed.
  • the second opening area corresponds to the area on the substrate 10 where the source electrode 13 and the drain electrode 14 are to be formed.
  • the channel region of the active layer 12 is exposed. Since the material of the active layer 12 contains silicon, dry etching is used, so the etching is The etching solution used to etch the initial first anti-reflection layer 111 has little effect on the exposed part of the active layer 12 and can be ignored.
  • forming the first anti-reflection layer 11, the active layer 12, the source electrode 13, and the drain electrode 14 on the substrate 10, as shown in FIG. 20, includes the following steps:
  • a material for forming the first anti-reflection layer 11 is deposited on the substrate 10 to form a first anti-reflection film 101.
  • an active layer 12 is formed on the side of the first anti-reflection film 101 away from the substrate 10.
  • S203 deposit the material to be formed with the source electrode 13 and the drain electrode 14 on the side of the active layer 12 away from the substrate 10 to form a conductive film 103.
  • the conductive film 103 and the first anti-reflection film 101 are patterned to form the source electrode 13, the drain electrode 14, and the first anti-reflection layer 11, and the first anti-reflection layer 11 is formed on the substrate 10.
  • the upper orthographic projection covers the orthographic projection of the active layer 12, the source electrode 13 and the drain electrode 14 on the substrate 10.
  • the conductive film 103 and the first subtraction film on the substrate 10 except for the regions where the source electrode 13 and the drain electrode 14 are to be formed The first anti-reflection film 101 outside the area of the reflective layer 11 obtains the source electrode 13, the drain electrode 14, and the first anti-reflection layer 11.
  • some specific preparation steps for preparing the first anti-reflection layer 11, the active layer 12, the source electrode 13, and the drain electrode 14 are exemplarily introduced below.
  • the same mask is used for preparing the first anti-reflection layer 11 and preparing the source and drain metal layers (including the source 13 and the drain 14), that is, the mask for preparing the source and drain metal layers is used. Therefore, the preparation process is simplified and the production cost is saved.
  • forming the first anti-reflection layer 11, the active layer 12, the source electrode 13 and the drain electrode 14 on the substrate, as shown in FIG. 22, includes the following steps:
  • a material for forming the first anti-reflection layer 11 is deposited on the substrate 10 to form a first anti-reflection film 101.
  • a semiconductor material is deposited on the side of the first anti-reflection film 101 away from the substrate 10 to form a semiconductor film 102.
  • a first mask is used to pattern the semiconductor thin film 102 to form the active layer 12.
  • the material to be formed with the source electrode 13 and the drain electrode 14 is deposited on the side of the active layer 12 away from the substrate 10 to form a conductive film 103.
  • a second mask is used to etch the conductive film 103 and the first anti-reflection film 101 to obtain the source electrode 13, the drain electrode 14 and the first anti-reflection layer 11.
  • the same mask plate can be used as the source electrode 13 and the drain electrode 14, and there is no need to add an additional mask plate for forming the first anti-reflection layer 11. Can reduce production costs and reduce production processes.

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Abstract

一种阵列基板及其制备方法、显示装置，其中，阵列基板包括衬底、薄膜晶体管、以及第一减反射层；薄膜晶体管设置于衬底上；薄膜晶体管包括有源层、源极和漏极，源极和漏极设置于有源层远离衬底一侧；源极和漏极包括与有源层接触的接触部分和不与有源层接触的非接触部分；第一减反射层位于源极和漏极靠近衬底的一侧；第一减反射层与源极和漏极中的至少一者的非接触部分接触，且第一减反射层在衬底上正投影，与该非接触部分在衬底上的正投影至少部分重叠。

Description

阵列基板及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
近年来，随着显示技术的进步，用户观感体验的要求越来越高，显示装置也趋向窄边框设计，显示装置的视觉效果也越来越重要。
发明内容
一方面，提供一种阵列基板。所述阵列基板包括衬底、薄膜晶体管和第一减反射层。其中，所述薄膜晶体管设置于所述衬底上，所述薄膜晶体管包括有源层、源极和漏极；所述源极和所述漏极设置于所述有源层远离所述衬底的一侧；所述源极和所述漏极包括与所述有源层接触的接触部分和不与所述有源层接触的非接触部分。所述第一减反射层位于所述源极和所述漏极靠近所述衬底的一侧；所述第一减反射层与所述源极和所述漏极中的至少一者的非接触部分接触，且所述第一减反射层在所述衬底上正投影，与该非接触部分在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述第一减反射层在所述衬底上的正投影与所述有源层在所述衬底上的正投影无重叠或者大致无重叠。
在一些实施例中，所述第一减反射层位于所述有源层靠近所述衬底的一侧，所述有源层与所述第一减反射层接触；所述第一减反射层在所述衬底上的正投影覆盖所述有源层、所述源极和所述漏极在所述衬底上的正投影。
在一些实施例中，所述第一减反射层的厚度H、所述第一减反射层的折射率η、以及入射至所述第一减反射层上的环境光的波长λ之间的关系为2×η×H＝λ/2。
在一些实施例中，所述第一减反射层的厚度的取值范围为500nm～600nm；所述第一减反射层的折射率的取值范围为2.2～2.3。
在一些实施例中，所述第一减反射层的材料包括金属氧化物。
在一些实施例中，所述第一减反射层的材料包括氧化钼和氧化锌中的至少一者。
在一些实施例中，所述阵列基板还包括数据线。所述数据线与所述薄膜晶体管的源极电连接且同层设置；所述第一减反射层与所述数据线接触，且所述第一减反射层在所述衬底上的正投影覆盖所述数据线在所述衬底上的正 投影。
在一些实施例中，所述薄膜晶体管还包括栅极，所述栅极位于所述有源层靠近所述衬底的一侧；所述阵列基板还包括位于所述栅极与所述有源层之间的栅绝缘层。
在一些实施例中，所述薄膜晶体管还包括栅极、栅绝缘层、层间介质层。其中，所述栅极位于所述有源层远离所述衬底的一侧；所述栅绝缘层位于所述栅极与所述有源层之间；所述层间介质层位于所述栅极与所述源极和所述漏极之间。所述第一减反射层位于所述层间介质层与所述源极和所述漏极之间；所述栅极绝缘层、所述层间介质层和所述第一减反射层中设置有至少两个接触孔，所述源极和所述漏极分别通过所述至少两个接触孔与所述有源层电接触；所述第一减反射层在所述衬底上的正投影，覆盖所述源极和所述漏极中，除处于所述至少两个接触孔处的部分以外的部分在所述衬底上的正投影。
在一些实施例中，所述阵列基板还包括第二减反射层。所述第二减反射层位于所述栅极靠近所述衬底的一侧；所述栅极与所述第二减反射层接触，且所述第二减反射层在所述衬底上的正投影覆盖所述栅极在所述衬底上的正投影。
在一些实施例中，所述阵列基板还包括栅线。所述栅线与所述薄膜晶体管的栅极电连接且同层设置；所述第二减反射层与所述栅线接触，且所述第二减反射层在所述衬底上的正投影覆盖所述栅线在所述衬底上的正投影。
另一方面，提供一种显示装置，所述显示装置包括：如上述一些实施例所述的阵列基板、对置基板、以及背光模组。所述对置基板与所述阵列基板相对设置，所述背光模组设置于所述对置基板远离所述阵列基板的一侧。
又一方面，提供一种阵列基板的制备方法，包括：提供衬底，在所述衬底上形成薄膜晶体管的有源层；在所述有源层远离所述衬底的一侧形成所述薄膜晶体管的源极和漏极；所述源极和所述漏极包括与所述有源层接触的接触部分和不与所述有源层接触的非接触部分。
所述制备方法还包括：在形成所述源极和所述漏极之前，在所述衬底上形成第一减反射层；所述第一减反射层与所述源极和所述漏极中的至少一者的非接触部分接触，且所述第一减反射层在所述衬底上的正投影，与该非接触部分在所述衬底上的正投影至少部分重叠。
在一些实施例中，在所述衬底上形成所述有源层、所述第一减反射层、所述源极和所述漏极，包括：在所述衬底上形成所述有源层；在所述衬底上 沉积待形成第一减反射层的材料，形成第一减反射薄膜；去除所述第一减反射薄膜中覆盖或者大致覆盖所述有源层的部分，使经过该去除工序的第一减反射薄膜在所述衬底上的正投影与所述有源层无重叠或者大致无重叠；在经过上述去除工序的第一减反射薄膜远离所述衬底的一侧形成所述源极和所述漏极。
在一些实施例中，在所述衬底上形成所述有源层、所述第一减反射层、所述源极和所述漏极，包括：在所述衬底上沉积半导体材料，形成半导体薄膜；在所述半导体薄膜远离所述衬底的一侧涂覆第一光阻材料，形成第一光阻薄膜；采用第一掩膜板，去除所述第一光阻薄膜中除待形成有源层的区域之外的部分，形成遮挡待形成有源层的区域的第一光阻层；以所述第一光阻层为掩膜，刻蚀所述半导体薄膜，形成所述有源层；在所述有源层远离所述衬底的一侧沉积待形成第一减反射层的材料，形成第一减反射薄膜；在所述第一减反射薄膜远离所述衬底一侧涂覆第二光阻材料，形成第二光阻薄膜；采用所述第一掩膜板，去除所述有源层的区域中的所述第二光阻薄膜，在所述第一减反射薄膜远离所述衬底的一侧形成暴露所述有源层的第二光阻层；所述第二光阻材料与所述第一光阻材料性质相反；以所述第二光阻层为掩膜，刻蚀所述第一减反射薄膜，去除所述第一减反射薄膜中覆盖或者大致覆盖所述有源层的部分，得到初始第一减反射层；在所述初始第一减反射层远离所述衬底的一侧沉积待形成源极和漏极的材料，形成导电薄膜；采用第二掩膜板，刻蚀所述导电薄膜和所述初始第一减反射层，形成所述源极、所述漏极、以及所述第一减反射层。
在一些实施例中，在所述衬底上形成所述第一减反射层、所述有源层、所述源极和所述漏极，包括：在所述衬底上沉积待形成第一减反射层的材料，形成第一减反射薄膜；在所述第一减反射薄膜远离所述衬底的一侧形成所述有源层；在所述有源层远离所述衬底的一侧沉积待形成源极和漏极的材料，形成导电薄膜；图案化所述导电薄膜和所述第一减反射薄膜，形成所述源极、所述漏极和所述第一减反射层，并使所述第一减反射层在所述衬底上的正投影覆盖所述有源层、所述源极和所述漏极在所述衬底上的正投影。
在一些实施例中，在所述衬底上形成所述第一减反射层、所述有源层、所述源极和所述漏极，包括：在所述衬底上沉积待形成第一减反射层的材料，形成第一减反射薄膜；在所述第一减反射薄膜远离所述衬底的一侧沉积半导体材料，形成半导体薄膜；采用第一掩膜板，图案化所述半导体薄膜，形成所述有源层；在所述有源层远离所述衬底的一侧沉积待形成源极和漏极的材 料，形成导电薄膜；采用第二掩膜板，刻蚀所述导电薄膜和所述第一减反射薄膜，得到所述源极、所述漏极和所述第一减反射层。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的阵列基板的一种俯视图；
图2为图1中的阵列基板沿B-B’的剖视图；
图3为根据一些实施例的阵列基板的一种结构图；
图4为根据一些实施例的阵列基板的另一种结构图；
图5为根据一些实施例的阵列基板的又一种结构图；
图6为图1中的阵列基板沿C-C’的剖视图；
图7为根据一些实施例的阵列基板的另一种俯视图；
图8为图7中的阵列基板沿D-D’的剖视图；
图9为根据一些实施例的阵列基板的又一种结构图；
图10为根据一些实施例的阵列基板的又一种结构图；
图11为根据一些实施例的阵列基板的又一种结构图；
图12为根据一些实施例的阵列基板的又一种结构图；
图13为根据一些实施例的阵列基板的又一种俯视图；
图14为图13中的阵列基板沿E-E’的剖视图；
图15为根据一些实施例的显示装置的结构图；
图16为根据一些实施例的阵列基板的一种制备流程图；
图17为根据一些实施例的阵列基板的一种制备过程图；
图18为根据一些实施例的阵列基板的另一种制备流程图；
图19为根据一些实施例的阵列基板的另一种制备过程图；
图20为根据一些实施例的阵列基板的又一种制备流程图；
图21为根据一些实施例的阵列基板的又一种制备过程图；
图22为根据一些实施例的阵列基板的又一种制备流程图；
图23为根据一些实施例的阵列基板的又一种制备过程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
在相关技术中，显示装置包括阵列基板、对置基板和背光模组。其中，对置基板与阵列基板相对设置，背光模组设置于对置基板远离阵列基板的一侧。
可以理解的是，背光模组发出的光，经由对置基板，射向阵列基板，并从阵列基板远离对置基板的一侧出射。但是，由于阵列基板中的部分结构具 有较高的光反射性能，因此，在环境光从阵列基板远离对置基板的一侧进入显示装置的过程中，环境光在阵列基板上发生反射，且反射光从阵列基板远离对置基板的一侧出射，使得处于暗态的显示装置会显示亮点，导致显示装置的暗态显示效果降低。
在上述现状的基础上，本公开的一些实施例提供一种阵列基板1，如图1和图2所示，阵列基板1包括：衬底10、薄膜晶体管(Thin Film Transistor，简称TFT)、第一减反射层11。
其中，阵列基板1具有显示区A和周边区S，周边区S位于显示区A的至少一侧。显示区A内设置有多个亚像素P。如图1所示，多个亚像素P可以呈阵列排布，沿水平方向X排列成一排的亚像素P称为同一行亚像素，同一行亚像素可以与一根栅线21电连接。沿竖直方向Y排列成一排的亚像素P称为同一列亚像素，同一列亚像素可以与一根数据线15电连接。
如图1和图2所示，TFT设置于衬底10上，TFT包括有源层12、设置于有源层12远离衬底10一侧的源极13和漏极14。
源极13和漏极14包括与有源层12接触的接触部分T1和不与有源层12接触的非接触部分T2。
第一减反射层11位于源极13和漏极14靠近衬底10的一侧。
第一减反射层11与源极13和漏极14中的至少一者的非接触部分T2接触，且第一减反射层11在衬底10上的正投影，与该非接触部分T2在衬底10上的正投影至少部分重叠。
需要说明的是，第一减反射层11与源极13和漏极14中的至少一者的非接触部分T2接触，可以是漏极14中的非接触部分T2与第一减反射层11接触(如图2所示)，可以是源极13中的非接触部分T2与第一减反射层11接触(如图3所示)，可以是源极13中的非接触部分T2和漏极14中的非接触部分T2均与第一减反射层11接触(如图4所示)。
在此基础上，第一减反射层11用于减少入射至其内部的光线中，发生反射的光线的量。这样，环境光由衬底10进入阵列基板1内部，经过第一减反射层11后，环境光中发生反射的光线的量被减少，降低了环境光在源极13和漏极14中的至少一者的非接触部分T2靠近衬底10一侧的表面上发生反射的反射率，从而避免环境光在阵列基板1内部发生反射后，从衬底10出射，影响暗态显示效果的问题。
因此，本公开的实施例提供的阵列基板1，环境光从衬底10进入阵列基板1内部，由于源极13和漏极14中的至少一者的非接触部分T2与第一减反 射层11接触，因此，射向源极13和漏极14的环境光先会经过第一减反射层11，在第一减反射层11的作用下，在源极13和漏极14中的至少一者的非接触部分T2靠近衬底10的一侧表面的反射光被减弱，降低了环境光在源极13和漏极14中的至少一者的非接触部分T2靠近衬底10一侧的表面上发生反射的反射率，从而避免环境光在源极13和漏极14中的至少一者的非接触部分T2靠近衬底10一侧的表面上发生反射的反射光，从衬底10出射，影响暗态显示效果的问题，可以提高显示装置的暗态显示效果。
在一些实施例中，第一减反射层11在衬底10上的正投影与有源层12在衬底10上的正投影无重叠或者大致无重叠。这样，源极13和漏极14中与有源层12接触的接触部分T1与第一减反射层11无接触或者大致无接触，此时，源极13和漏极14与有源层12之间的信号传输不会受到第一减反射层11的影响。
在一些实施例中，如图5所示，第一减反射层11位于有源层12靠近衬底11的一侧，有源层12与第一减反射层11接触。
第一减反射层11在衬底10上的正投影覆盖有源层12、源极13和漏极14在衬底10上的正投影。
可以理解的是，第一减反射层11可以减少由衬底10射向有源层12、源极13和漏极14的环境光中发生反射的光线的量，减弱环境光在有源层12、源极13和漏极14发生反射的反射率，避免环境光在射向源极13和漏极14的过程中，在源极13和漏极14的表面发生反射，从衬底10出射，影响暗态显示效果的问题。
在此基础上，在一些实施例中，第一减反射层11的厚度H、第一减反射层11的折射率η、以及入射至第一减反射层11上的环境光的波长λ之间的关系为2×η×H＝λ/2。
需要说明的是，根据布拉格公式2×n×d×sinθ＝λ/2，其中，n为反射级数，θ为入射光和反射光与反射面的夹角，d为相邻两个反射面的间距，且n取1，sinθ取1。在此基础上，当环境光在第一减反射层11靠近衬底10一侧的表面、以及减反射层11与源极13和漏极14中的至少一者的非接触部分T2的接触面上发生反射时，这两个反射面的间距d等于第一减反射层11的光学厚度(η×H)，即d＝η×H，此时，2×η×H＝λ/2。
在此情况下，环境光由衬底10进入阵列基板1内部，经过第一减反射层11，一部分光会在第一减反射层11表面发生反射，另一部分光会透过第一减反射层11，在第一减反射层11与源极13和漏极14中的至少一者的非接触部 分T2的接触面上发生反射，这两种反射出射的反射光会在传输过程中，可以发生干涉相消，使得环境光在源极13和漏极14中的至少一者的非接触部分T2靠近衬底10一侧的表面上发生反射的反射光被消除，从而避免反射的环境光从衬底10一侧出射，影响暗态显示效果的问题。
在一些实施例中，第一减反射层11的厚度的取值范围为500nm～600nm，第一减反射层11的折射率的取值范围为2.2～2.3。这样，能够较大程度地减少入射至阵列基板1中的环境光的反射率。
在一些实施例中，第一减反射层11的材料包括金属氧化物。
可以理解的是，金属氧化物电阻相对较大，近似绝缘。
示例性地，第一减反射层11的材料包括氧化钼(MoO x)和氧化锌(ZnO x)中的至少一者。
其中，氧化钼呈半透明，氧化锌呈透明。在此情况下，当第一减反射层11的材料包括氧化钼时，入射至第一减反射层11的环境光的至少一部分，可以被第一减反射层11吸收，降低了环境光的透过率。
在一些实施例中，如图1和图6所示，阵列基板1还包括数据线15。
数据线15与TFT的源极14电连接，且同层设置。
第一减反射层11与数据线15接触，且第一减反射层11在衬底10上的正投影覆盖数据线15在衬底10上的正投影。
其中，数据线15和TFT的源极14的材料可以相同，在此情况下，工艺上数据线15与TFT的源极14可以同步形成。数据线15与TFT的源极14可以为一体结构。
可以理解的是，第一减反射层11位于数据线15靠近衬底10的一侧。由于第一减反射层11与数据线15接触，且第一减反射层11在衬底10上的正投影覆盖数据线15在衬底10上的正投影，因此，第一减反射层11会对从衬底10入射至数据线15的环境光进行减反射，减弱了环境光在数据线15上发生反射的反射率，避免了环境光在数据线15上发生反射后从衬底10出射，影响暗态显示效果的问题。
在此基础上，在一些实施例中，如图1和图6所示，TFT还包括栅极16。栅极16位于有源层12靠近衬底10的一侧。
如图7所示，阵列基板1还包括位于栅极16与有源层12之间的栅绝缘层17。
其中，栅极16与源极13和漏极14同材料。栅绝缘层17覆盖衬底10。
在另一些实施例中，如图7和图8所示，栅极16位于有源层12远离衬 底10的一侧。
阵列基板1还包括位于栅极16与有源层12之间的栅绝缘层17、以及位于栅极16与源极13和漏极14之间的层间介质层18。
第一减反射层11位于层间介质层18与源极13和漏极14之间。
栅绝缘层17、层间介质层18和第一减反射层11中设置有至少两个接触孔19，源极13和漏极14分别通过至少两个接触孔19与有源层12电接触。
第一减反射层11在衬底10上的正投影，覆盖源极13和漏极14中，除处于至少两个接触孔19处的部分以外的部分在衬底10上的正投影。
其中，层间介质层18和栅绝缘层17均覆盖衬底10。
需要说明的是，栅绝缘层17、层间介质层18和第一减反射层11中设置的至少两个接触孔19，沿垂直于衬底10的方向穿过栅绝缘层17、层间介质层18和第一减反射层11，露出位于接触孔19区域内的有源层12，源极13和漏极14通过接触孔19，与有源层12接触。
在工艺上，在层间介质层18表面沉积待形成第一减反射层11的材料，形成第一减反射薄膜，之后形成接触孔19，之后沉积待形成源极13和漏极14的材料，形成导电薄膜，通过一个掩膜板，刻蚀第一减反射薄膜和导电薄膜，形成源极13、漏极14和第一减反射层11，从而可以减少掩膜板的数量，节约生产成本。
此外，如图9所示，在栅极16位于有源层12远离衬底10的一侧的情况下，阵列基板1还包括设置于有源层12靠近衬底10一侧的遮光层25，遮光层25在衬底10上的正投影至少覆盖有源层12在衬底10上的正投影。遮光层25与有源层12之间设置有缓冲层26。
其中，源极13或漏极14通过沿垂直于衬底10的方向，设置于层间介质层18、栅绝缘层17和缓冲层26上的第一过孔41，与遮光层25电连接。在此情况下，遮光层25可以避免环境光照射至有源层12，避免TFT产生阈值电压漂移。
例如，遮光层25可以是导电的，使遮光层25与源极13或者漏极14电连接，从而可以使遮光层25产生稳定的电压，避免产生浮栅效应，从而提高TFT的工作稳定性。
在一些实施例中，如图10和图11所示，阵列基板1还包括第二减反射层20。第二减反射层20位于栅极16靠近衬底10的一侧。
栅极16与第二减反射层20接触，且第二减反射层20在衬底10上的正投影覆盖栅极16在衬底10上的正投影。
其中，第二减反射层20的材料可以与第一减反射层10的材料相同。例如，二者的材料可以均包括氧化钼和氧化锌等金属氧化物中的至少一者；例如，二者的材料可以均为氧化钼。
可以理解的是，第二减反射层20在衬底10上的正投影覆盖栅极16在衬底10上的正投影，第二减反射层20可以对从衬底10入射至栅极16的环境光进行减反射，使得环境光的反射率降低，例如环境光的反射率从大约55％降到了大约6％，从而避免环境光在栅极16上发生反射后从衬底10出射，影响暗态显示效果的问题。
在此基础上，在一些实施例中，如图1和图7所示，阵列基板1还包括栅线21。栅线21与TFT的栅极16电连接。
其中，栅线21与栅极16同层设置。
如图12所示，第二减反射层20与栅线21接触，且第二减反射层20在衬底10上的正投影覆盖栅线21在衬底10上的正投影。
其中，栅线21与栅极16同材料，在工艺上栅线21与栅极16可以同步形成。栅线21与TFT的栅极16可以为一体结构。
在此情况下，由于栅线21与TFT的栅极16同层设置，因此，第二减反射层20位于栅线21靠近衬底10的一侧。并且，第二减反射层20与栅线21接触，且第二减反射层20在衬底10上的正投影覆盖栅线21在衬底10上的正投影，因此，第二减反射层20会对从衬底10入射至栅线21的环境光进行减反射，避免了环境光在栅线21上发生反射后从衬底10出射，影响暗态显示效果的问题。
在一些实施例中，如图1和图2所示，阵列基板1还包括第一电极22、以及与第一电极22相对设置的第二电极23。
其中，第一电极22和第二电极23的材料相同，例如可以采用包括ITO(氧化铟锡)等透明导电材料。
第二电极23位于源极13和漏极14靠近衬底10的一侧，第一电极22位于源极13和漏极14远离衬底10的一侧。
其中，第一电极22具有多条狭缝，第二电极23的结构呈块状。
第二电极23与TFT的栅极16同层设置，且相互绝缘。
第一电极22与源极13和漏极14之间设置有钝化层24。
其中，钝化层24可以为单层或多层结构。示例的，钝化层24的材料可以采用包括氮化硅(Si xN y)或者氧化硅(SiO x)等无机材料。
示例性的，在工艺上，可以先在衬底10上通过成膜、曝光、显影、刻蚀 等工艺，形成第二电极23。之后，在衬底10上通过成膜、曝光、显影、刻蚀等工艺，形成栅极16，此时栅极16和第二电极23位于同一层。在钝化层24远离衬底10一侧，通过成膜、曝光、显影、刻蚀等工艺，形成第一电极22。
在第一电极22为像素电极，第二电极23为公共电极的情况下，如图2所示，钝化层24设置有第二过孔42，该第二过孔42在垂直于衬底10的方向上穿过钝化层24，露出漏极14，第一电极22覆盖该第二过孔42与漏极14电连接。
在第二电极23为像素电极，第一电极22为公共电极的情况下，如图13和图14所示，钝化层24和栅绝缘层17中设置有第三过孔43，该第三过孔43在垂直于衬底10的方向上穿过钝化层24和栅绝缘层17，露出漏极14和第二电极23，阵列基板1还包括设置在第三过孔43的位置处的第一导电图案31，第一导电图案31至少覆盖在第三过孔43，并与漏极14和第二电极23接触，以使第二电极23与漏极14电连接。
其中，第一导电图案31与第一电极22同层同材料且相互绝缘。
需要说明的是，在第一电极22为公共电极的情况下，第一电极22可以单独设置，一个第一电极22对应一个亚像素(如图13所示)。或者，同一行亚像素中的至少两个亚像素中的第一电极22可以连为一体结构(图中未示出)。
在此基础上，如图1和图2、以及图13和图14所示，阵列基板1还包括公共电极线28。
其中，公共电极线28与栅极16同层同材料。公共电极线28与公共电极电连接。
同一行亚像素中的公共电极与同一根公共电极线28电连接。
如图1和图2所示，在第二电极23为公共电极的情况下，公共电极线28位于第二电极23远离衬底的一侧，且公共电极线28与第二电极23接触。如图13和图14所示，在第一电极22为公共电极的情况下，第一电极22通过沿垂直于衬底10的方向，设置于钝化层24和栅绝缘层17的第四过孔44，与公共电极线28电连接。
此外，可选的，如图1所示，阵列基板1还包括多个间隔设置的第二导电图案32。沿亚像素排列的行方向，任意相邻第二导电图案32至少间隔两个亚像素。一个公共电极通过第二导电图案32，和与该公共电极相邻的一行公共电极所电连接的公共电极线28电连接。在此情况下，由于同一行亚像素中的公共电极与同一根公共电极线28电连接，在公共电极通过公共电极线28 上电时，第二导电图案32可以使相邻两行亚像素中的公共电极的电信号接近相等，因此，可以使得各公共电极的压降减小。
本公开的实施例还提供一种显示装置100，如图15所示，该显示装置100包括上述的任一项实施例提供的阵列基板1。
显示装置100还包括对置基板2和背光模组3。对置基板2与阵列基板1相对设置，背光模组3设置于对置基板2远离阵列基板1的一侧。
其中，显示装置100还包括设置于阵列基板1和对置基板2之间的液晶层4。
可以理解的是，在阵列基板1包括第一电极22和第二电极23的情况下，当第一电极22和第二电极23通电时，位于液晶层4中的液晶分子可以在第一电极22与第二电极23形成的电场的作用下发生偏转。
由上面的描述可知，当环境光从阵列基板1远离对置基板2的一侧入射时，阵列基板1中的第一减反射层11可以减少环境光中发生反射的光线的量，降低阵列基板1内部发生反射的反射率，从而避免环境光在阵列基板1内部发生反射后，从阵列基板1远离对置基板2的一侧出射，影响暗态显示效果的问题。
上述显示装置100可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
参考图1和图2、以及图7和图8，本公开的实施例提供一种阵列基板1的制备方法，包括：
提供衬底10，在衬底10上形成TFT的有源层12。
其中，衬底10起支撑作用，能够使后续形成的各个层(例如有源层12、第一减反射层11等)具有较高的稳定性和可靠性。
示例性的，参考图2，在衬底10上形成有源层12之前，该衬底10上已形成栅极16和位于栅极16远离衬底10一侧的栅绝缘层17。
参考图1和图2、以及图7和图8，在有源层12远离衬底10的一侧，形 成TFT的源极13和漏极14。
其中，源极13和漏极14包括与有源层12接触的接触部分T1和不与有源层12接触的非接触部分T2。
示例性的，参考图8，在形成有源层12与形成源极13和漏极14之间，在有源层12远离衬底10一侧，沿垂直于衬底10的方向依次形成栅绝缘层17、栅极16以及层间介质层18，源极13和漏极14形成于层间介质层18远离衬底10的一侧。
在此基础上，阵列基板1的制备方法还包括：
参考图1和图2、以及图7和图8，在形成源极13和漏极14之前，在衬底10上形成第一减反射层11。
其中，第一减反射层11与源极13和漏极14中的至少一者的非接触部分T2接触，且第一减反射层11在衬底10上的正投影，与该非接触部分T2在衬底10上的正投影至少部分重叠。
示例性的，参考图2，第一减反射层11形成于源极13和漏极14与栅绝缘层17之间。参考图8，第一减反射层11形成于源极13和漏极14与层间介质层18之间。
第一减反射层11用于减少入射至其内部的光线中，发生反射的光线的量。这样，环境光由衬底10进入阵列基板1内部，经过第一减反射层11后，环境光中发生反射的光线的量被减少，降低了环境光在源极13和漏极14中的至少一者的非接触部分T2靠近衬底10一侧的表面上发生反射的反射率，从而避免环境光在阵列基板1内部发生反射后，从衬底10出射，影响暗态显示效果的问题。
在一些实施例中，在衬底10上形成有源层12、第一减反射层11、源极13和漏极14，如图16所示，包括以下步骤：
S101、如图17所示，在衬底10上形成有源层12。
S102、如图17所示，在衬底10上沉积待形成的第一减反射层11的材料，形成第一减反射薄膜101。
其中，第一减反射层11的材料包括金属氧化物，例如MoO x等。
S103、如图17所示，去除第一减反射薄膜101中覆盖或者大致覆盖有源层12的部分，使经过该去除工序的第一减反射薄膜101在衬底10上的正投影与有源层12无重叠或者大致无重叠。
其中，可以采用构图工艺，去除第一减反射薄膜101中覆盖或者大致覆盖有源层12的部分。例如，首先在第一减反射薄膜101远离衬底10的一侧 形成光刻胶层；然后对该光刻胶层进行曝光和显影，得到图案化的光刻胶层，该图案化的光刻胶层暴露第一减反射薄膜101中覆盖或者大致覆盖有源层12的部分的表面；最后，使用该图案化的光刻胶层对第一减反射薄膜101进行刻蚀，去除第一减反射薄膜101中覆盖或者大致覆盖有源层12的部分。
S104、如图17所示，在经过上述去除工序的第一减反射薄膜101远离衬底10的一侧，形成源极13和漏极14。
基于上述实施例，下面对制备有源层12、第一减反射层11、源极13和漏极14的一些具体制备步骤进行示例性的介绍。在下面的示例中，制备第一减反射层11和有源层12采用了同一张掩膜板，即均采用了制备有源层12的掩膜板，从而简化了制备工艺，节约了生产成本。
示例性地，在衬底10上形成有源层12、第一减反射层11、源极13和漏极14，如图18所示，包括以下步骤：
S111、如图19所示，在衬底10上沉积半导体材料，形成半导体薄膜102。
示例的，该半导体材料包括非晶硅(a-Si)或者多晶硅(p-Si)等。
S121、如图19所示，在半导体薄膜102远离衬底10的一侧涂覆第一光阻材料，形成第一光阻薄膜501。
S131、如图19所示，采用第一掩膜板，去除第一光阻薄膜501中除待形成有源层12的区域之外的部分，形成遮挡待形成有源层12的区域的第一光阻层51。
可以理解的是，第一掩膜板包括多个第一开口区。在第一光阻材料为正性光刻胶时，第一开口区对应于衬底10上除待形成有源层12的区域之外的区域。在第一光阻材料为负性光刻胶时，第一开口区对应于衬底10上待形成有源层12的区域。
S141、如图19所示，以第一光阻层51为掩膜，刻蚀半导体薄膜102，形成有源层12。
示例的，刻蚀半导体薄膜102时可以采用干法刻蚀。
S112、如图19所示，在有源层12远离衬底10的一侧沉积待形成第一减反射层11的材料，形成第一减反射薄膜101。
S113、如图19所示，在第一减反射薄膜101远离衬底10的一侧涂覆第二光阻材料，形成第二光阻薄膜502。
S123、如图19所示，采用第一掩膜板，去除有源层12的区域中的第二光阻薄膜502，在第一减反射薄膜101远离衬底10的一侧形成暴露有源层12的第二光阻层52。其中，第二光阻材料与第一光阻材料性质相反。
可以理解的是，当第一光阻材料为正性光刻胶，第二光阻材料为负性光刻胶时，第一掩膜板的第一开口区对应于衬底10上除待形成有源层12的区域之外的区域，第二光阻薄膜502中的位于待形成有源层12的区域内的部分会被去除，得到第二光阻层52。当第一光阻材料为负性光刻胶，第二光阻材料为正性光刻胶时，第一掩膜板的第一开口区对应于衬底10上待形成有源层12的区域，第二光阻薄膜502中的位于待形成有源层12的区域内的部分会被去除，得到第二光阻层52。
S133、如图19所示，以第二光阻层52为掩膜，刻蚀第一减反射薄膜101，去除第一减反射薄膜101中覆盖或者大致覆盖有源层12的部分，得到初始第一减反射层111。
可以理解的是，初始第一减反射层111在衬底10上的正投影与有源层12在衬底10上的正投影无重叠或者大致无重叠。
在此基础上，由于有源层12和初始第一减反射层采用同一张掩膜板得到，因此节省了生产成本。
S114、如图19所示，在初始第一减反射层111远离衬底10的一侧沉积待形成源极13和漏极14的材料，形成导电薄膜103。
其中，源极13和漏极14的材料可以采用包括铜(Cu)、铝(Al)、钼(Mo)、钛(Ti)、铬(Cr)和钨(W)等金属材料。
S124、如图19所示，采用第二掩膜板，刻蚀导电薄膜103和初始第一减反射层111，形成源极13、漏极14、以及第一减反射层11。
示例的，刻蚀导电薄膜103和初始第一减反射层111时可以采用湿法刻蚀。
可以理解的是，第二掩膜板包括多个第二开口区。在采用第二掩膜板，形成源极13、漏极14、以及第一减反射层11的过程中，当在导电薄膜103上涂覆正性光刻胶进行曝光、显影，刻蚀导电薄膜103和初始第一减反射层111时，第二开口区对应于衬底10上除待形成源极13和漏极14的区域之外的区域，当在导电薄膜103上涂覆负性光刻胶进行曝光、显影，刻蚀导电薄膜103和初始第一减反射层111时，第二开口区对应于衬底10上待形成源极13和漏极14的区域。
需要说明的是，在采用湿法刻蚀初始第一减反射层111的过程中，有源层12的沟道区裸露，由于有源层12的材料包含硅时采用干法刻蚀，因此刻蚀初始第一减反射层111的刻蚀液对有源层12的裸露部分产生的影响很小，可以忽略。
在另一些实施例中，在衬底10上形成第一减反射层11、有源层12、源极13和漏极14，如图20所示，包括以下步骤：
S201、如图21所示，在衬底10上沉积待形成第一减反射层11的材料，形成第一减反射薄膜101。
S202、如图21所示，在第一减反射薄膜101远离衬底10的一侧，形成有源层12。S203、如图21所示，在有源层12远离衬底10的一侧沉积待形成源极13和漏极14的材料，形成导电薄膜103。
S204、如图21所示，图案化导电薄膜103和第一减反射薄膜101，形成源极13、漏极14、以及第一减反射层11，并使第一减反射层11在衬底10上的正投影覆盖有源层12、源极13和漏极14在衬底10上的正投影。
可以理解的是，在图案化导电薄膜103和第一减反射薄膜101的过程中，去除衬底10上除待形成源极13和漏极14的区域之外的导电薄膜103、以及第一减反射层11的区域之外的第一减反射薄膜101，得到源极13、漏极14、以及第一减反射层11。
基于上述实施例，下面对制备第一减反射层11、有源层12、源极13和漏极14的一些具体制备步骤进行示例性的介绍。在下面的示例中，制备第一减反射层11和制备源漏金属层(包括源极13和漏极14)采用了同一张掩膜板，即均采用了制备源漏金属层的掩膜板，从而简化了制备工艺，节约了生产成本。
示例性地，在衬底上形成第一减反射层11、有源层12、源极13和漏极14，如图22所示，包括以下步骤：
S211、如图23所示，在衬底10上沉积待形成第一减反射层11的材料，形成第一减反射薄膜101。
S212、如图23所示，在第一减反射薄膜101远离衬底10的一侧沉积半导体材料，形成半导体薄膜102。
S222、如图23所示，采用第一掩膜板，图案化半导体薄膜102，形成有源层12。
S213、如图23所示，在有源层12远离衬底10的一侧沉积待形成源极13和漏极14的材料，形成导电薄膜103。
S214、如图23所示，采用第二掩膜板，刻蚀导电薄膜103和第一减反射薄膜101，得到源极13、漏极14和第一减反射层11。
在此基础上，在形成第一减反射层11的过程中，可以与形成源极13和漏极14采用同一掩膜板，无需额外增加用于形成第一减反射层11的掩膜板， 可以降低生产成本，减少生产工序。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种阵列基板，包括：
    衬底；
    设置于所述衬底上的薄膜晶体管；所述薄膜晶体管包括有源层，以及设置于所述有源层远离所述衬底一侧的源极和漏极；所述源极和所述漏极包括与所述有源层接触的接触部分和不与所述有源层接触的非接触部分；
    第一减反射层，所述第一减反射层位于所述源极和所述漏极靠近所述衬底的一侧；所述第一减反射层与所述源极和所述漏极中的至少一者的非接触部分接触，且所述第一减反射层在所述衬底上正投影，与该非接触部分在所述衬底上的正投影至少部分重叠。
  2. 根据权利要求1所述的阵列基板，其中，所述第一减反射层在所述衬底上的正投影与所述有源层在所述衬底上的正投影无重叠或者大致无重叠。
  3. 根据权利要求1所述的阵列基板，其中，所述第一减反射层位于所述有源层靠近所述衬底的一侧，所述有源层与所述第一减反射层接触；
    所述第一减反射层在所述衬底上的正投影覆盖所述有源层、所述源极和所述漏极在所述衬底上的正投影。
  4. 根据权利要求1～3中任一项所述的阵列基板，其中，所述第一减反射层的厚度H、所述第一减反射层的折射率η、以及入射至所述第一减反射层上的环境光的波长λ之间的关系为2×η×H＝λ/2。
  5. 根据权利要求1～4中任一项所述的阵列基板，其中，所述第一减反射层的厚度的取值范围为500nm～600nm；
    所述第一减反射层的折射率的取值范围为2.2～2.3。
  6. 根据权利要求1～5中任一项所述的阵列基板，其中，所述第一减反射层的材料包括金属氧化物。
  7. 根据权利要求6所述的阵列基板，其中，所述第一减反射层的材料包括氧化钼和氧化锌中的至少一者。
  8. 根据权利要求1～7中任一项所述的阵列基板，还包括：数据线；所述数据线与所述薄膜晶体管的源极电连接且同层设置；
    所述第一减反射层与所述数据线接触，且所述第一减反射层在所述衬底上的正投影覆盖所述数据线在所述衬底上的正投影。
  9. 根据权利要求1～8中任一项所述的阵列基板，其中，所述薄膜晶体管还包括栅极，所述栅极位于所述有源层靠近所述衬底的一侧；
    所述阵列基板还包括位于所述栅极与所述有源层之间的栅绝缘层。
  10. 根据权利要求1所述的阵列基板，其中，所述薄膜晶体管还包括栅 极，所述栅极位于所述有源层远离所述衬底的一侧；
    所述阵列基板还包括位于所述栅极与所述有源层之间的栅绝缘层，以及位于所述栅极与所述源极和所述漏极之间的层间介质层；
    所述第一减反射层位于所述层间介质层与所述源极和所述漏极之间；
    所述栅极绝缘层、所述层间介质层和所述第一减反射层中设置有至少两个接触孔，所述源极和所述漏极分别通过所述至少两个接触孔与所述有源层电接触；
    所述第一减反射层在所述衬底上的正投影，覆盖所述源极和所述漏极中，除处于所述至少两个接触孔处的部分以外的部分在所述衬底上的正投影。
  11. 根据权利要求9或10所述的阵列基板，还包括第二减反射层；所述第二减反射层位于所述栅极靠近所述衬底的一侧；
    所述栅极与所述第二减反射层接触，且所述第二减反射层在所述衬底上的正投影覆盖所述栅极在所述衬底上的正投影。
  12. 根据权利要求11所述的阵列基板，还包括栅线；所述栅线与所述薄膜晶体管的栅极电连接且同层设置；
    所述第二减反射层与所述栅线接触，且所述第二减反射层在所述衬底上的正投影覆盖所述栅线在所述衬底上的正投影。
  13. 一种显示装置，包括：
    如权利要求1～12中任一项所述的阵列基板；
    与所述阵列基板相对设置的对置基板；以及，
    背光模组，所述背光模组设置于所述对置基板远离所述阵列基板的一侧。
  14. 一种阵列基板的制备方法，包括：
    提供衬底，在所述衬底上形成薄膜晶体管的有源层；
    在所述有源层远离所述衬底的一侧形成所述薄膜晶体管的源极和漏极；所述源极和所述漏极包括与所述有源层接触的接触部分和不与所述有源层接触的非接触部分；
    所述制备方法还包括：在形成所述源极和所述漏极之前，在所述衬底上形成第一减反射层；所述第一减反射层与所述源极和所述漏极中的至少一者的非接触部分接触，且所述第一减反射层在所述衬底上的正投影，与该非接触部分在所述衬底上的正投影至少部分重叠。
  15. 根据权利要求14所述的制备方法，其中，在所述衬底上形成所述有源层、所述第一减反射层、所述源极和所述漏极，包括：
    在所述衬底上形成所述有源层；
    在所述衬底上沉积待形成第一减反射层的材料，形成第一减反射薄膜；
    去除所述第一减反射薄膜中覆盖或者大致覆盖所述有源层的部分，使经过该去除工序的第一减反射薄膜在所述衬底上的正投影与所述有源层无重叠或者大致无重叠；
    在经过上述去除工序的第一减反射薄膜远离所述衬底的一侧形成所述源极和所述漏极。
  16. 根据权利要求15所述的制备方法，其中，在所述衬底上形成所述有源层、所述第一减反射层、所述源极和所述漏极，包括：
    在所述衬底上沉积半导体材料，形成半导体薄膜；
    在所述半导体薄膜远离所述衬底的一侧涂覆第一光阻材料，形成第一光阻薄膜；
    采用第一掩膜板，去除所述第一光阻薄膜中除待形成有源层的区域之外的部分，形成遮挡待形成有源层的区域的第一光阻层；
    以所述第一光阻层为掩膜，刻蚀所述半导体薄膜，形成所述有源层；
    在所述有源层远离所述衬底的一侧沉积待形成第一减反射层的材料，形成第一减反射薄膜；
    在所述第一减反射薄膜远离所述衬底一侧涂覆第二光阻材料，形成第二光阻薄膜；
    采用所述第一掩膜板，去除所述有源层的区域中的所述第二光阻薄膜，在所述第一减反射薄膜远离所述衬底的一侧形成暴露所述有源层的第二光阻层；所述第二光阻材料与所述第一光阻材料性质相反；
    以所述第二光阻层为掩膜，刻蚀所述第一减反射薄膜，去除所述第一减反射薄膜中覆盖或者大致覆盖所述有源层的部分，得到初始第一减反射层；
    在所述初始第一减反射层远离所述衬底的一侧沉积待形成源极和漏极的材料，形成导电薄膜；
    采用第二掩膜板，刻蚀所述导电薄膜和所述初始第一减反射层，形成所述源极、所述漏极、以及所述第一减反射层。
  17. 根据权利要求14所述的制备方法，其中，在所述衬底上形成所述第一减反射层、所述有源层、所述源极和所述漏极，包括：
    在所述衬底上沉积待形成第一减反射层的材料，形成第一减反射薄膜；
    在所述第一减反射薄膜远离所述衬底的一侧形成所述有源层；
    在所述有源层远离所述衬底的一侧沉积待形成源极和漏极的材料，形成导电薄膜；
    图案化所述导电薄膜和所述第一减反射薄膜，形成所述源极、所述漏极和所述第一减反射层，并使所述第一减反射层在所述衬底上的正投影覆盖所述有源层、所述源极和所述漏极在所述衬底上的正投影。
  18. 根据权利要求17所述的制备方法，其中，在所述衬底上形成所述第一减反射层、所述有源层、所述源极和所述漏极，包括：
    在所述衬底上沉积待形成第一减反射层的材料，形成第一减反射薄膜；
    在所述第一减反射薄膜远离所述衬底的一侧沉积半导体材料，形成半导体薄膜；
    采用第一掩膜板，图案化所述半导体薄膜，形成所述有源层；
    在所述有源层远离所述衬底的一侧沉积待形成源极和漏极的材料，形成导电薄膜；
    采用第二掩膜板，刻蚀所述导电薄膜和所述第一减反射薄膜，得到所述源极、所述漏极和所述第一减反射层。
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