WO2021155559A1 - Dispositif capteur de lumière, procédé de fabrication de dispositif capteur de lumière - Google Patents

Dispositif capteur de lumière, procédé de fabrication de dispositif capteur de lumière Download PDF

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WO2021155559A1
WO2021155559A1 PCT/CN2020/074479 CN2020074479W WO2021155559A1 WO 2021155559 A1 WO2021155559 A1 WO 2021155559A1 CN 2020074479 W CN2020074479 W CN 2020074479W WO 2021155559 A1 WO2021155559 A1 WO 2021155559A1
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germanium
layer
sensor device
light sensor
silicon
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PCT/CN2020/074479
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English (en)
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Katsuno MOTONARI
Kudoh YOSHIHARU
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Huawei Technologies Co., Ltd.
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Priority to PCT/CN2020/074479 priority Critical patent/WO2021155559A1/fr
Priority to CN202080095152.8A priority patent/CN115039225A/zh
Publication of WO2021155559A1 publication Critical patent/WO2021155559A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Definitions

  • Embodiments of the present application relate to a light sensing function, and in particular, to a light sensor device used for an imaging apparatus having a TOF (time-of-flight) sensor, and a method for fabricating a light sensor device.
  • TOF time-of-flight
  • a TOF (time-of-flight) sensor is used for a wide variety of applications such as for face recognition for smart phone, object recognition for automotive autonomous driving, wide-area surveillance in the dark, healthcare, and gaming.
  • the TOF sensor can serve as an input device to both stationary and portable computing devices.
  • the TOF camera uses infrared light (lasers invisible to human eyes) to obtain depth information –it is a bit like how a bat senses its surroundings.
  • the sensor emits a light signal, which hits an object and returns to the sensor.
  • the time required to receive the returned light is then measured and it provides depth-mapping capabilities. This provides a huge advantage over other technologies, as it can accurately measure distances in a complete scene with a single laser pulse.
  • the TOF sensor has two issues: low sensitivity and a dark current which cause error of measurement of distance.
  • germanium (Ge) photodiode on silicon structure was proposed instead of a Si photodiode for near-infrared (NIR) photodiodes in silicon (Si) photonics.
  • Sensitivity of the photodiode is determined by absorption rate of photodiode material.
  • an absorption rate of Ge is 90%, which is more numerous than that of Si (20%) .
  • the sensitivity of the Ge photodiode is increased by 4.5 times in comparison to the Si photodiode.
  • Accuracy of measurement distance is improved by using Ge because a detection signal is clearly detected by distinguishing a false signal (dark signal) and a signal from a low-reflection object.
  • the dark current is a signal at a dark situation.
  • Photodiodes generate a small amount of current even in the absence of an optical signal. This is due to thermal generation of carriers. Ideally, the dark current is zero.
  • defects which causes the dark current.
  • One of the main defects is many dangling bonds of Ge and another is defects caused by mismatch of lattice constants between Si and Ge (4%) . They release electrons normally and move to the photodiode. It adversely affects signals and causes error of the measurement distance. It is an issue in applying a germanium photodiode to products.
  • a first aspect provides a light sensor device comprising:
  • germanium or germanium-silicon layers formed on the first substrate, the germanium or germanium-silicon layers including an n-typed germanium or germanium-silicon layer and a p-typed germanium or germanium-silicon layer;
  • a conductive layer composed of a p-typed silicon or silicon-germanium layer, wherein the conductive layer is formed on top and side of the germanium or germanium-silicon layers.
  • a conductive layer composed of a p-typed silicon or silicon-germanium layer is formed on the top and side of the germanium or germanium-silicon layers.
  • the p-Si layer on the top and sides of a Ge photodiode is fabricated. Therefore, the defects of dangling bonds can be suppressed by bonding with Si atoms, which results in reducing the dark current and improving accuracy enhancement of measuring distance. Also, detection of high wavelength lights (850 nm, 940 nm, and 1550 nm) can be achieved.
  • a metal electrode with high concentration ion implantation on the top of the Ge photodiode is not required. This structure can reduce defects or damage on surface on the Ge photodiode.
  • the conductive layer is connected to another conductive layer of another light sensor device adjacent to the light sensor device.
  • the conductive layer is connected to another conductive layer of another sensor device adjacent to the light sensor device. Therefore, the conductive layer which covers an array of pixels can be simply connected to ground.
  • the light sensor device further comprises:
  • a first metal electrode connected to the conductive layer in the middle of the light sensor device and the other light sensor device.
  • a first metal electrode is connected to the conductive layer in the middle of the light sensor device and the other light sensor device. Therefore, a metal electrode with high concentration ion implantation on the top of the Ge layer is not required.
  • This structure can reduce defects or damage on surface on Ge photodiode. Also, wire resistance from photodiode to ground or a power supply can be more decreased by using the metal electrode.
  • an insulating layer is formed between the first substrate and the germanium or germanium-silicon layers, and the first substrate and the germanium or germanium-silicon layers are connected via a metal region placed in the insulating layer.
  • an insulating layer is formed between the first substrate and the germanium or germanium-silicon layers, and the first substrate and the germanium or germanium-silicon layers are connected via a metal region placed in the insulating layer. Therefore, the Ge photodiode and the Si substrate can be fabricated independently and they can be combined with chip-to-chip bonding technology.
  • the conductive layer has a flat layer formed on the top of the germanium or germanium-silicon layers and extended such that the flat layer is connected to the other conductive layer of the other light sensor device.
  • the conductive layer has a flat layer formed on the top of the germanium or germanium-silicon layers and extended such that the flat layer is connected to the other conductive layer of the other light sensor device. Therefore, wire resistance from the photodiode to ground or a power supply can be more decreased.
  • the light sensor device further comprises:
  • a second metal electrode connected to the flat layer in the middle of the light sensor device and the other light sensor device.
  • a second metal electrode is connected to the flat layer in the middle of the light sensor device and the other light sensor device. Therefore, a metal electrode with high concentration ion implantation on the top of the Ge layer is not required.
  • This structure can reduce defects or damage on surface on Ge photodiode. Also, wire resistance from photodiode to ground or a power supply can be more decreased by using the metal electrode.
  • an additional metal electrode is not formed on an upper side of the germanium or germanium-silicon layers.
  • the conductive layer and the germanium or germanium-silicon layer are formed in a trench fabricated in a second substrate.
  • the conductive layer and the germanium or germanium-silicon layer are formed in a trench fabricated in a second substrate. Therefore, it is possible to fabricate the Ge photodiode in the second substrate independently of the first substrate.
  • a second aspect provides an imaging system, comprising:
  • a transmitter unit for emitting light to an object
  • a receiver unit including an array of said light sensor devices to output a signal according to received light reflected from the object
  • a processing unit for processing the output signal.
  • an imaging apparatus comprises an array of light sensor devices. Therefore, the defects of dangling bonds can be suppressed by bonding with Si atoms, which results in reducing the dark current and improving accuracy enhancement of measuring distance.
  • a third aspect provides a method of fabricating a light sensor device, the method comprising:
  • germanium or germanium-silicon layers on the substrate, the germanium or germanium-silicon layers including an n-typed germanium or germanium-silicon layer and a p-typed germanium or germanium-silicon layer;
  • a conductive layer composed of a p-typed silicon or silicon-germanium layer, wherein the conductive layer is formed on the top and side of the germanium or germanium-silicon layers.
  • forming the conductive layer comprises:
  • the conductive layer so as to connect to another conductive layer of the other light sensor device adjacent to the light sensor device.
  • the method further comprises:
  • the method further comprises:
  • forming the conductive layer comprises:
  • the conductive layer so as to have a flat layer formed on the top of the germanium or germanium-silicon layers and extended such that the flat layer is connected to the other conductive layer of the other light sensor device.
  • the method further comprises:
  • a fourth aspect provides a method of fabricating a light sensor device comprising:
  • the conductive layer composed of a p-typed silicon or silicon-germanium layer
  • germanium or germanium-silicon layers in the trench such that the conductive layer covers the top and side of the germanium or germanium-silicon layers, wherein the germanium or germanium-silicon layers include an n-typed germanium or germanium-silicon layer and a p-typed germanium or germanium-silicon layer.
  • forming the conductive layer comprises:
  • the conductive layer so as to connect to another conductive layer of another light sensor device adjacent to the light sensor device.
  • the method further comprises:
  • the method further comprises:
  • forming the conductive layer comprises:
  • the conductive layer so as to have a flat layer formed on the top of the germanium or germanium-silicon layers and extended such that the flat layer is connected to the other conductive layer of the other light sensor device.
  • the method further comprises:
  • FIG. 1 is a schematic cross sectional view of a Ge photodiode integrated with a Si optical waveguide
  • FIG. 2 is a schematic cross sectional view of pixel structure of TOF sensors according to an embodiment
  • FIG. 3 is a plane view of the TOF sensors
  • FIG. 4 is a diagram showing a method for fabricating TOF sensors
  • FIG. 5 is a schematic cross sectional view of pixel structure of TOF sensors according to an embodiment
  • FIG. 6 is a plane view of the TOF sensors
  • FIG. 7 is a schematic cross sectional view of pixel structure of TOF sensors according to an embodiment
  • FIG. 8 is a diagram showing a method for fabricating an upper chip according to an embodiment
  • FIG. 9 is a diagram showing a method for fabricating TOF sensors
  • FIG. 10 is a schematic cross sectional view of pixel structure of TOF sensors according to an embodiment
  • FIG. 11 is a diagram showing a method for fabricating an upper chip according to an embodiment
  • FIG. 12 is a diagram showing a method for fabricating TOF sensors
  • FIG. 13 is a schematic cross sectional view of pixel structure of TOF sensors according to an embodiment
  • FIG. 14 is a diagram showing a method for fabricating TOF sensors
  • FIG. 15 is a diagram showing a method for fabricating TOF sensors
  • FIG. 16 is a block diagram showing a structure of TOF system according to an embodiment.
  • FIG. 17 is a diagram showing a technique for determining characteristics of an object.
  • FIG. 1 is a schematic cross sectional view of a Ge photodiode integrated with a Si optical waveguide.
  • An undoped Ge photodiode layer 18-6 which takes mesa structures is fabricated on p+ or phosphorus-implanted n+ slab area of an SOI (silicon on insulator) layer 18-1.
  • a Si layer 18-2 covers the top and sides of Ge photodiode layer 18-6 and metal electrodes 18-3 are fabricated on the Ge photodiode layer 18-6.
  • N or p-typed dopant ions are implanted into the Si cap layer 18-2 and near the surface of the Ge photodiode layer 18-6 to form an n+ or p+ region 18-5.
  • SiO 2 masks 18-4 are formed on the Si layer 18-2 and etching is given to the SiO 2 masks 18-4 on the n+ or p+ region 18-5.
  • a metal electrode 18-3 is formed in the etched cavity on the top of the n+ or p+ region 18-5.
  • electrodes 18-7 are placed on the SOI layer 18-1 and sides of the SiO 2 masks 18-4.
  • a Si layer covers the top and sides of the Ge photodiode layer and (2) the metal electrodes are fabricated on the Ge photodiode layer.
  • defects of the dangling bond can be suppressed by bonding with Si atoms.
  • the etching damages the surface of the Ge photodiode, which causes more defects, i.e. the dark current. Embodiments of the present disclosure are provided to solve this problem regarding the dark current.
  • FIG. 2 illustrates a schematic cross sectional view of pixel structure of TOF sensors according to the first embodiment of the present disclosure. This figure corresponds to a cross section at dashed lines L shown in FIG. 3.
  • the TOF sensor is an example of a light sensor device.
  • a Ge photodiode 1-1 per each pixel is formed on a Si substrate 1-13.
  • a thickness of the Si substrate is about 3 ⁇ m.
  • the Ge photodiode 1-1 is stacked layers of a p-Ge layer 1-3 and an n-Ge layer 1-2.
  • the p-Ge layer 1-3 is doped with a p-dopant. For example, it may be doped with boron at a concentration of 10 17 /cm 3 .
  • the n-Ge layer 1-2 is doped with an n-dopant. For example, it may be doped with phosphorus at a concentration of 10 16 -10 19 /cm 3 .
  • a thickness of the Ge photodiode 1-1 is designed to have a substantial quantum efficiency. For example, the thickness is about 2 ⁇ m.
  • the p-Si layer 1-4 is formed on the top and sides of the Ge photodiode 1-1.
  • the p-Si layer 1-4 is doped with a p-dopant. For example, it may be doped with boron at a concentration of 10 16 -10 19 /cm 3 .
  • a thickness of the p-Si layer 1-4 is about 1 to 200 nm.
  • the p-Si layer 1-4 is a buffer layer for suppressing dark current caused by defects on a surface of Ge as shown in "A" of FIG. 2.
  • the p-Si layer 1-4 is also a conductive layer connected to GND (ground) and p-Si layers of adjacent TOF pixels. This connection is shown as "B" in FIG. 2.
  • the p-Si layer 1-4 and the Si substrate 1-13 are insulated by a SiO 2 layer 1-14. Additionally, an inter-layer 1-5, a passivation layer 1-6 and a lens 1-7 are fabricated on the p-Si layer 1-4.
  • the inter-layer 1-5 is a silicon oxide layer or a silicon nitride layer.
  • the passivation layer 1-6 is a silicon nitride layer. If water penetrates to the Si substrate 1-13, it will cause degradation in reliability of performance by chemical reaction of Si and water.
  • the passivation layer 1-6 is provided for preventing water from penetrating to the Si substrate 1-13.
  • the lens 1-7 is transparent material, resin or silicon nitride, which makes incident light to focus on the Ge photodiode.
  • lens 1-7 includes a flat portion 1-7a and a convex portion 1-7b.
  • FIG. 3 (a) illustrates a top view of the TOF sensors in FIG. 2.
  • FIG. 3 (b) illustrates a cross sectional view of the TOF sensors at a plane x1 indicated in FIG. 2.
  • FIG. 3 (c) illustrates a bottom view of the TOF sensors in FIG. 2.
  • a distance D between the centers of the lenses 1-7 may be 5 to 10 ⁇ m.
  • the Si substrate 1-13 has an n-typed Si region 1-8, a p-typed Si region 1-9, a p-typed Si region 1-10 and floating diffusion 1-11.
  • the n-typed Si region 1-8 is provided for electron transfer and is doped with an n-dopant. For example, it may be doped with phosphorus at a concentration of 10 17 /cm 3 .
  • the p-typed Si region 1-9 is provided for isolation between the floating diffusion 1-11 and the p-typed Si region 1-10.
  • the p-typed Si region 1-9 is doped with a p-dopant.
  • a p-dopant For example, it may be doped with boron at a concentration of10 16 -10 19 /cm 3 .
  • the p-typed Si region 1-10 may have a p+ doping, and it is doped with a p-dopant, e.g. boron at the concentration of 10 18 /cm 3 .
  • the floating diffusion 1-11 may have an n+ doping, and it may be doped with an n-dopant, e.g. phosphorus at the concentration of10 16 -10 19 /cm 3 .
  • the n-typed Si region 1-8 is for photo-electron conversion layer of (photo) diode which is configured at each pixel between the p-typed Si regions 1-9.
  • transfer gates 1-12 for reading electron is fabricated for each pixel.
  • the transfer gates 1-12 can transfer generated electrons in the Ge photodiode 1-15 to the floating diffusion 1-11 through the n-typed Si region 1-8 and the p-typed Si region 1-10.
  • metal contents and wires may be fabricated under the Si substrate 1-13 although they are omitted in the figure.
  • the metal contents and wires may transfer the generated electrons from the floating diffusion 1-11 to a signal processer as signals for calculating measured values.
  • the Ge photodiode 1-1 may be used to detect optical signals and convert the optical signals to electrical signals that may be further processed by another circuitry such as the signal processor. Specifically, the Ge photodiode 1-1 receives optical signals through the lens 1-7 and the passivation layer 1-6, and generates free carriers. The generated free carriers may drift or diffuse into the n-typed Si region 1-8.
  • a difference between a Fermi level of the p-typed Si region 1-10 and the Fermi level of the n-typed Si region 1-8 creates an electric field between the two regions, where free electrons collected from the Ge photodiode 1-1 by the n-typed Si region 1-8 are drifted to a region below the p-typed Si region 1-10 by the electric field.
  • the transfer gates 1-12 may be coupled to a voltage source.
  • a control signal from the voltage source controls a flow of free electrons from the region below the p-typed Si region 1-10 to the floating diffusion 1-11. For example, if a voltage of the control signal exceeds a threshold voltage, free electrons accumulated in the region below the p-typed Si region 1-10 will drift to the floating diffusion 1-11.
  • the signals (free electrons) from floating diffusion 1-11 may be read by the signal processor.
  • a material absorbs light at various wavelengths to generate free carriers depending on an energy bandgap associated with the material.
  • Si may have an energy bandgap of 1.12 eV
  • Ge may have an energy bandgap of 0.66 eV.
  • a material having a lower energy bandgap has a higher absorption coefficient at a particular wavelength. If the absorption coefficient of a material used for the photodiode is too low, the optical signal cannot be converted by the photodiode to an electrical signal efficiently. However, if the absorption coefficient of the material is too high, free carriers will be generated near the surface of the material, which may be recombined to reduce photoelectric conversion efficiency.
  • Si is not an efficient sensor material for NIR wavelengths (780 nm to 2500 nm) due to its large bandgap.
  • Ge has an absorption coefficient that may be too high for shorter wavelengths (e.g., blue) , where free carriers may recombine at its surface.
  • a photodiode array with Ge can detect NIR light.
  • a p-germanium-silicon (GeSi) layer can be used as the conductive layer.
  • the n-Ge layer 1-2 can be replaced with an n-GeSi layer.
  • the p-Ge layer 1-3 can be replaced with a p-GeSi layer.
  • the term “germanium-silicon (GeSi) " and “silicon-germanium (SiGe)" may be used interchangeably.
  • photodiode may be used interchangeably as the term “optical sensor” .
  • the Ge layer may be formed using blanket epitaxy, selective epitaxy, or other applicable technique.
  • a strained super lattice structure including multiple layers such as alternating SiGe layer with different compositions may be used for the absorption or forming a quantum well structure.
  • a germanium-silicon alloy may have an energy bandgap between 0.66 eV and 1.12 eV depending on the composition, which includes all suitable combinations of Si and Ge composition from 100 %Ge to more than 90 %Si.
  • dopants can be selected from suitable materials.
  • an n-type dopant can be selected from a group of phosphorus (P) , arsenic (As) , and antimony (Sb) .
  • a p-type dopant can be selected from a group of boron (B) , alminum (Al) , gallium (Ga) and indium (In) .
  • a Si substrate 1-13 is provided and is doped with dopants to form the n-typed Si region 1-8, p-typed Si region 1-9, p-typed Si region 1-10 and floating diffusion 1-11 as shown in (a) .
  • the transfer gates 1-12 are coupled to the p-typed Si region 1-10 and floating diffusion 1-11.
  • the SiO 2 layer 1-14 is deposited on the Si substrate by CVD (chemical vapor deposition) as shown in (b) .
  • resist coating is performed on the SiO 2 layer 1-14 and patterning is performed to form resists 4-1 as shown in (c) .
  • etching is given to the SiO 2 layer 1-14 to obtain isolated SiO 2 layers 1-14 as shown in (d) , and the n-Ge layer 1-2 and p-Ge layer 1-3 are deposited on the n-doped region 1-8 of the Si substrate 1-13 by CVD as shown in (e) .
  • stacked layers grow only on the n-doped region of the Si substrate 1-13. Therefore, the Ge photodiode 1-1 can be formed only on the n-typed Si region 1-8.
  • the p-Si layer 1-4 is formed to cover the surface of the SiO 2 layer 1-5 as shown in (f) .
  • the SiO 2 layer 1-5 is deposited on the p-Si layer as shown in (g) , and CMP (chemical mechanical polishing) is performed on the top of the SiO 2 layer 1-5 as shown in (h) .
  • CMP chemical mechanical polishing
  • a metal electrode is connected to the conductive layer in the middle of a light sensor device and an adjacent light sensor device.
  • FIG. 5 illustrates a schematic cross sectional view of pixel structure of TOF sensors according to the second embodiment of the present disclosure.
  • a layer structure from the gate transfers 1-12 to the p-Si layer 1-4 is as same as the first embodiment.
  • the TOF sensor includes the Ge photodiode 1-1 on the Si substrate 1-13.
  • the p-Si layer 1-4 is formed on the top and sides of the Ge photodiode 1-1.
  • the p-Si layer 1-4 is the buffer layer for suppressing the dark current caused by defects on the surface of the Ge photodiode 1-1.
  • a metal electrode 5-1 is connected to the p-Si layer.
  • the metal electrode 5-1 is a T-shaped electrode made of tungsten (W) and is placed in the middle of one TOF sensor device and the other one.
  • the top of the metal electrode 5-1 is placed in the passivation layer 1-6 and its vertically elongated member 5-2 penetrates into the SiO 2 layer 1-5.
  • FIG. 6 illustrates a plane view of the TOF sensors.
  • the metal electrode 5-1 can be connected to metal electrodes 6-1 which extend in the horizontal direction in boundary area of the TOF sensors.
  • the TOF sensor can improve the dark current because of at least the two reasons.
  • the p-Si layer on the top and sides of the Ge photodiode is fabricated, whereby the defects of dangling bonds can be suppressed by bonding of the Ge atoms with Si atoms.
  • a metal electrode is not formed on an upper side of the germanium layers. Because the metal electrode having high concentration ion implantation on the top of the Ge layer is not required, there is no defects or damage on surface on the Ge photodiode caused by etching.
  • the metal electrode 1-5 can be connected to GND. Accordingly, the wire resistance from the Ge photodiode to GND or power supply is more decreased than the first embodiment. This embodiment can achieve both lower dark current and lower wire resistance.
  • the layer structure from the gate transfer 1-12 to the p-Si layer 1-4 may be fabricated as same as FIG. 4 (a) to FIG. 4 (h) as described with respect to the first embodiment. Then, etching is given to the SiO 2 layer 1-5 such that cavities penetrates into the SiO 2 layer 1-5 so as to reach the p-Si layer 1-4. Then, the vertically elongated member 5-2 of the metal electrode 5-1 is inserted into the cavity. Finally, the passivation layer 1-6 and lens 1-7 are stacked on the SiO 2 layer sequentially as shown in FIG. 4 (i) .
  • the Ge photodiode is connected with the p-Si layer via a Si epitaxial layer.
  • FIG. 7 illustrates a schematic cross sectional view of pixel structure of TOF sensors according to the third embodiment of the present disclosure.
  • the TOF sensor consists of an upper chip 7-1 and a lower chip 7-7.
  • layers of the p-Ge layer 1-3 and n-Ge layer 1-2 are formed on a Si epitaxial layer 7-4 and a stacked metal region 7-3 which consists of a tungsten layer and a copper (Cu) layer.
  • a tungsten layer is about 50 to 100 nm
  • the copper (Cu) layer is about 100 to 300 nm) is formed.
  • the lower chip 7-7 consists of the transfer gates 1-12, the Si substrate 1-13, a Si epitaxial layer 7-5 and a stacked metal region 7-6 which consists of a tungsten layer and a copper (Cu) layer.
  • a tungsten layer (thickness is about 100 to 300 nm) is formed.
  • a copper (Cu) layer (thickness is about 100 to 300 nm) is formed.
  • the upper chip 7-1 and the lower chip 7-7 are bonded by bonding technology of the Cu side of the stacked metal region 7-3 of the upper chip 7-1 and the Cu side of the stacked metal region 7-6 of the lower chip 7-7.
  • the Si epitaxial layer 7-4 is deposited by Si epitaxial growth, for example MBE (Molecular Beam Epitaxy) growth technology or MOCVD (metal organic chemical vapor deposition) epitaxial technology.
  • a Si substrate (the second substrate) 7-2 is provided as shown in (a) .
  • Resist coating is performed on a lower surface of the Si substrate 7-2 to add resists 8-1 as shown in (b) .
  • Si etching is given on the lower surface of the Si substrate 7-2 to fabricate trenches (cavities) 8-2 and the resists 8-1 are removed as shown in (c) .
  • the p-Si layer 1-4 is grown on the lower surface of the Si substrate 7-2 as shown in (d) .
  • the p-Ge layer 1-3 and the n-Ge layer 1-2 are formed on the p-Si layer 7-1 by CVD or MOCVD as shown in (e) .
  • the lower surface of the p-Si layer is covered by the p-Ge layer 1-3 and the n-Ge layer 1-2.
  • Ge planarization is performed by CMP to expose the p-Si layer 1-4.
  • the Ge photodiode 1-1 can be formed in the trench 8-2 such that the p-Si layer 1-4 covers the top and side of the Ge photodiode 1-1.
  • a SiO 2 layer 7-4 is grown by CVD. Then, resist coating is performed to add resists 8-3 on the lower surface of the SiO 2 layer as shown in (h) .
  • Etching is given to remove the SiO 2 layer to the middle to create cavities 8-4, and the resists 8-2 are removed as shown in (i) .
  • resist coating is performed to add resists 8-5 on portions of the lower surface of the SiO 2 layer 7-4 as shown in (j) , and additional etching is given to form a step-wise cavities 8-6 as shown in (k) .
  • the step-wise cavities 8-6 can be formed as a rectangular shape.
  • plating is performed to plate the whole lower surface with W and Cu as shown in (l) .
  • CMP is performed to Cu to form the stacked metal region 7-3 as shown in (m) .
  • FIG. 9 illustrates a method for fabricating the TOF sensor according to this embodiment.
  • (a) shows the upper chip 7-1 for the Ge photodiode fabricated by the method as described with reference to FIG. 8.
  • (b) shows the lower chip for signal processing, in which the SiO 2 epitaxial layer 7-5 and the stacked metal region 7-6 are fabricated by the process as described with reference to FIG. 8 (l) and FIG. 8 (m) .
  • the upper chip 7-1 and the lower chip 7-7 are combined by chip-to-chip bonding as shown in (c) .
  • the passivation layer 1-6 and lens 1-7 are stacked on the Si substrate 7-2 sequentially as shown in (d) .
  • the p-Si layer has a flat surface across multiple TOF sensors.
  • FIG. 10 illustrates a schematic cross sectional view of pixel structure of TOF sensors according to the fourth embodiment of the present disclosure.
  • the TOF sensor consists of an upper chip 10-2 and a lower chip 7-7.
  • the upper chip 10-2 and the lower chip 7-7 are bonded by bonding technology of the stacked metal region 7-3 of the upper chip 10-2 and the stacked metal region 7-6 of the lower chip 7-7.
  • the TOF sensors according to this embodiment do not have the metal electrode.
  • the p-Si layer 1-4 of the upper chip 10-2 includes a top portion 10-1 which has a flat shape expanding in the horizontal direction across the multiple TOF sensors. Also, the top portion 10-1 is connected to GND. Other explanation is as same as the third embodiment.
  • the wire resistance from the Ge photodiode to GND is more decreased in comparison to the first embodiment.
  • the Si substrate 7-2 is provided as shown in (a) .
  • the Si substrate is doped by ion implantation of p-type impurity such that the top portion 10-1 is formed as shown in 10-1.
  • the p-type impurity is implanted from the lower portion of the Si substrate 7-2 as shown in arrows in (b) .
  • Resist coating is performed on a lower surface of the Si substrate 7-2 to add resists 8-1 as shown in (c) .
  • Si etching is given on the lower surface of the Si substrate 7-2 to fabricate trenches 8-2 and the resists 8-1 are removed as shown in (d) .
  • the p-Si layer 1-4 is grown on the lower surface of the Si substrate 7-2 as shown in (e) .
  • the p-Ge layer 1-3 and the n-Ge layer 1-2 are formed on the p-Si layer 7-1 by CVD or MOCVD as shown in (f) .
  • the lower surface of the p-Si layer is covered by the p-Ge layer 1-3 and the n-Ge layer 1-2.
  • Ge planarization is performed by CMP to expose the p-Si layer 1-4.
  • a SiO 2 layer 7-4 is grown by CVD.
  • resist coating is performed to add resists 8-3 on the lower surface of the SiO 2 layer as shown in (i) .
  • Etching is given to remove the SiO 2 layer 7-4 to the middle to create cavities 8-4, and the resists 8-2 are removed as shown in (j) .
  • resist coating is performed to add resists 8-5 on portions of the lower surface of the SiO 2 layer 7-4 as shown in (k) , and additional etching is given to form a step-wise cavity 8-6 as shown in (l) .
  • plating is performed to plate the whole lower surface with W and Cu as shown in (m) .
  • CMP is performed to Cu to form the stacked metal region 7-3 as shown in (n) .
  • FIG. 12 illustrates a method for fabricating the TOF sensor according to this embodiment.
  • (a) shows the upper chip 10-2 for the Ge photodiode fabricated by the method as described with reference to FIG. 11.
  • (b) shows the lower chip 7-7 for signal processing, in which the SiO 2 epitaxial layer 7-5 and the stacked metal region 7-6 are fabricated by the process as described with reference to FIG. 11 (m) and FIG. 11 (n) .
  • the upper chip 10-2 and the lower chip 7-7 are combined by chip-to-chip bonding as shown in (c) .
  • the passivation layer 1-6 and lens 1-7 are stacked on the Si substrate 7-2 sequentially as shown in (d) .
  • metal electrodes are added in the middle of the TOF sensors according to the fourth embodiment.
  • FIG. 13 illustrates a schematic cross sectional view of pixel structure of TOF sensors according to the fifth embodiment of the present disclosure.
  • a layer structure from the gate transfers 1-12 to the top portion 10-1 is as same as the fourth embodiment.
  • the TOF sensor includes the Ge photodiode 1-1 on the Si substrate 1-13.
  • a metal electrode 13-1 is connected to the top portion 10-1 in the middle of the TOF sensors.
  • the top of the metal electrode 13-1 is placed in the passivation layer 1-6 and penetrates into the Si substrate 7-2.
  • the lower edge of the metal electrode 13-1 is connected to the top portion 10-1.
  • a plane view of the TOF sensor according to this embodiments are as shown in FIG. 6. Other explanation is as same as the fourth embodiment.
  • the wire resistance from the Ge photodiode to GND is more decreased than the first embodiment.
  • FIG. 14 illustrates a method for fabricating the TOF sensor according to this embodiment.
  • (a) shows the upper chip10-2 for the Ge photodiode fabricated by the method as described with reference to FIG. 11.
  • (b) shows the lower chip 7-7 for signal processing, in which the SiO 2 epitaxial layer 7-5 and the stacked metal region 7-6 are fabricated by the process as described with reference to FIG. 11 (m) and FIG. 11 (n) .
  • the upper chip 10-2 and the lower chip 7-7 are combined by chip-to-chip bonding as shown in (c) .
  • the passivation layer 1-6 and resists 14-1 are stacked on the SiO 2 layer sequentially as shown in (d) .
  • etching is given to the Si substrate 7-2 to create cavity 14-2.
  • the metal electrode 13-1 is inserted into the cavity 14-2 as shown in (f) .
  • FIG. 15 The fabrication process continues to FIG. 15.
  • additional resist coating is performed to deposit resists 15-1.
  • etching is given to the metal electrode 13-1 to create cavities 15-2 as shown in (b) , thereby creating isolated metal electrodes 13-1.
  • an additional passivation layer 1-6 and lens 1-7 are stacked on the SiO 2 layer sequentially as shown in (c) .
  • time-of-flight (TOF) applications depth information of a three-dimensional object may be determined using a phase difference between a transmitted light pulse and a detected light pulse.
  • a two-dimensional array of pixels may be used to reconstruct a three-dimensional image of a three-dimensional object, where each pixel may include one or more photodiodes for deriving phase information of the three-dimensional object.
  • time-of-flight applications use light sources having wavelengths in the near-infrared (NIR) range.
  • NIR near-infrared
  • a light-emitting-diode (LED) may have a wavelength of 850 nm, 940 nm, or 1550 nm.
  • Si is an inefficient absorption material for NIR wavelengths.
  • photo-carriers may be generated deeply (e.g., greater than 10 ⁇ m in depth) in the Si substrate, and those photo-carriers may drift and/or diffuse to the photodiode junction slowly, which results in a decrease in the device bandwidth.
  • Ge has a higher absorption coefficient and higher mobility. The following equation indicates mobility ⁇ e for Ge and Si.
  • a small voltage swing is typically used to control photodiode operations in order to minimize power consumption.
  • FIG. 16 shows a TOF system 16-4 for determining characteristics of a target object 16-7.
  • the target object 16-7 may be a three-dimensional object.
  • the TOF system 16-4 which functions as an imaging system according to this embodiment may include a transmitter unit 16-1, a receiver unit 16-2, and a processing unit 16-3.
  • the transmitter unit 16-1 emits light 16-5 towards the target object 16-7.
  • the transmitter unit 16-1 may include one or more light sources, control circuitry, and/or optical elements.
  • the transmitter unit 16-1 may include one or more NIR light sources or visible LEDs, where the emitted light 16-5 may be collimated by a collimating lens for propagation in free space.
  • the receiver unit 16-2 receives the reflected light 16-6 that is reflected from the target object 16-7.
  • the receiver unit 16-2 may include one or more photodiodes, a control circuitry, and/or optical elements.
  • the receiver unit 16-2 may include an image sensor, where the image sensor includes multiple pixels fabricated on a semiconductor substrate. Each pixel may include one or more multi-gate photodiodes for detecting the reflected light 16-6, where the reflected light 16-6 may be focused to the photodiodes.
  • Each photodiode may be the multi-gate photodiode described herein.
  • the processing unit 16-3 processes the photo-carriers generated by the receiver unit 16-2 and determines characteristics of the target object 16-7.
  • the processing unit 16-3 may include a control circuitry, one or more processors, and/or a computer storage medium that may store instructions for determining the characteristics of the target object 16-7.
  • the processing unit 16 includes the readout circuit 1 16-8, a readout circuit 2 16-9 and a processor 16-10 that can process information associated with the collected photo-carriers to determine the characteristics of the target object 16-7.
  • the characteristics of the target object 16-7 may be depth information of the target object 16-7.
  • FIG. 17 shows one example technique for determining characteristics of the target object 16-7.
  • the transmitter unit 16-1 may emit light pulses modulated at a frequency fm with a duty cycle of 50%as an example.
  • the receiver unit 16-2 may receive reflected light pulses having a phase shift of ⁇ .
  • the multi-gate photodiodes are controlled such that the readout circuit 1 reads the collected charges Q1 in a phase synchronized with the emitted light pulses, and a readout circuit 2 reads the collected charges Q2 in an opposite phase with the emitted light pulses.
  • the distance D between the TOF system 16-4 and the target object 16-7 may be derived using the equation:
  • the present embodiments can be used for a TOF sensor for a smart phone mainly, for face recognition, a night camera by using high sensitivity of IR light. It is useful for a high resolution TOF sensor with lower dark current. Because Ge has a higher absorption coefficient than a Si layer, Ge provides higher sensitivity than Si in the same size of pixel.
  • a TOF sensor using Si photodiode has almost no quantum efficiency (QE) sensitivity high-wavelength, that using Ge has the sensitivity (QE > 40%) .
  • QE quantum efficiency

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Abstract

L'invention concerne un dispositif capteur de lumière et un procédé de fabrication d'un dispositif capteur de lumière qui peut réduire le courant d'obscurité et améliorer la sensibilité. Le dispositif capteur de lumière comprend : un substrat (1-13) ; des couches de germanium ou de germanium-silicium formées sur le substrat (1-13), les couches de germanium ou de germanium-silicium comprenant une couche de germanium ou de germanium-silicium de type n (1-2) et une couche de germanium ou de germanium-silicium de type p (1-3) ; une couche conductrice composée d'une couche de silicium ou de silicium-germanium de type p (1-4), la couche conductrice étant formée sur le dessus et le côté des couches de germanium ou de germanium-silicium. Le procédé de fabrication d'un dispositif capteur de lumière consiste à : fournir un substrat (1-13) ; former des couches de germanium ou de germanium-silicium sur le substrat (1-13), les couches de germanium ou de germanium-silicium comprenant une couche de germanium ou de germanium-silicium de type n (1-2) et une couche de germanium ou de germanium-silicium de type p (1-3) ; et former une couche conductrice composée d'une couche de silicium ou de silicium-germanium de type p (1-4), la couche conductrice étant formée sur le dessus et le côté des couches de germanium ou de germanium-silicium.
PCT/CN2020/074479 2020-02-07 2020-02-07 Dispositif capteur de lumière, procédé de fabrication de dispositif capteur de lumière WO2021155559A1 (fr)

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CN202080095152.8A CN115039225A (zh) 2020-02-07 2020-02-07 光传感器设备及其制备方法

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CN103000650A (zh) * 2012-12-10 2013-03-27 复旦大学 近红外-可见光可调图像传感器
CN103579275A (zh) * 2013-11-06 2014-02-12 复旦大学 一种半浮栅感光器件的制造方法
CN106531822A (zh) * 2016-11-29 2017-03-22 电子科技大学 一种光电探测器
CN108140656A (zh) * 2015-08-27 2018-06-08 奥特逻科集团 宽频谱光学传感器
CN110047969A (zh) * 2019-05-06 2019-07-23 北京工业大学 一种SOI基SiGe双异质结光敏晶体管探测器

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Publication number Priority date Publication date Assignee Title
US20060194415A1 (en) * 2005-02-28 2006-08-31 Sharp Laboratories Of America, Inc. Germanium infrared sensor for CMOS imagers
CN103000650A (zh) * 2012-12-10 2013-03-27 复旦大学 近红外-可见光可调图像传感器
CN103579275A (zh) * 2013-11-06 2014-02-12 复旦大学 一种半浮栅感光器件的制造方法
CN108140656A (zh) * 2015-08-27 2018-06-08 奥特逻科集团 宽频谱光学传感器
CN106531822A (zh) * 2016-11-29 2017-03-22 电子科技大学 一种光电探测器
CN110047969A (zh) * 2019-05-06 2019-07-23 北京工业大学 一种SOI基SiGe双异质结光敏晶体管探测器

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