WO2021147883A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021147883A1
WO2021147883A1 PCT/CN2021/072805 CN2021072805W WO2021147883A1 WO 2021147883 A1 WO2021147883 A1 WO 2021147883A1 CN 2021072805 W CN2021072805 W CN 2021072805W WO 2021147883 A1 WO2021147883 A1 WO 2021147883A1
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WIPO (PCT)
Prior art keywords
wiring
wiring group
metal layer
gate metal
group
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PCT/CN2021/072805
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English (en)
French (fr)
Inventor
韩林倩
唐国强
杨朝金
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/425,734 priority Critical patent/US11984452B2/en
Publication of WO2021147883A1 publication Critical patent/WO2021147883A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display panel and a display device.
  • full-screen is inseparable from the under-screen camera technology, that is, when the imaging function is not required, the camera emits light normally like other areas of the display panel; when the imaging function is required, the camera area has the normal imaging function.
  • the camera area requires high optical transmittance due to its imaging function, and the transmittance of the normal light-emitting area is far from meeting the needs of the camera.
  • the "H+L" design is adopted, that is, the normal area uses high PPI, and the higher transmittance area uses a low PPI design. For the low PPI area, the transmittance of the position where the pixel unit is arranged is low, and the transmittance of the blank area between the pixels is relatively high, thereby increasing the overall transmittance of the area.
  • an embodiment of the present disclosure provides a display panel including a first display area and a second display area, M first wiring groups and N second wiring groups arranged along a first direction, M and N is a positive integer;
  • the first wiring group and the second wiring group are alternately arranged in the first order;
  • the second display area at least part of the first wiring group and part of the second wiring group are alternately arranged in a second order, the second order is different from the first order, and the second order is alternately arranged so that adjacent first The blank area between the wiring groups increases.
  • embodiments of the present disclosure provide a display device, which includes the display panel described in the first aspect, and a sensor unit, which is arranged in a second display area of the display panel and is located on a base substrate away from the light emitting direction. Side, the photosensitive surface of the sensor unit faces the display panel.
  • FIG. 1 shows a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 shows a schematic top view of a partial structure of a second display area provided by an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of a wiring scheme of a first wiring group and a second wiring group
  • FIG. 4 shows a schematic top view of a wiring solution of a second wiring group provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic structural diagram of an adjusted second wiring group provided by an embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of wiring at the first opening A provided by an embodiment of the present disclosure
  • FIG. 7 shows a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure at the first opening A;
  • FIG. 8 shows a schematic top view of a wiring solution of a second wiring group provided by another embodiment of the present disclosure
  • FIG. 9 shows a schematic cross-sectional view of a display panel at the first opening A according to another embodiment of the present disclosure.
  • FIG. 10 shows a schematic top view of a wiring solution of a second wiring group provided by another embodiment of the present disclosure.
  • FIG. 1 shows a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel 1 includes a first display area 11 and a second display area 12.
  • Each display area includes a plurality of pixel unit areas (not shown in the figure), wherein the density of the pixel unit area of the first display area 11 is greater than that of the second display area.
  • the second display area 12 may be as shown in FIG. 1, and its shape may be a circle or other shapes. In this embodiment, the second display area 12 is set in a circular shape.
  • FIG. 2 shows a schematic top view of a partial structure of the second display area provided by an embodiment of the present disclosure.
  • the second display area 12 includes a plurality of light-transmitting areas 121 and a plurality of pixel unit areas 122. There are four pixel unit areas 122 around each light-transmitting area 121. The light is transmitted to the sensor (such as a camera) of the display panel through the light-transmitting area 121, and the sensor receives the light, thereby realizing a camera function.
  • a pixel unit area 122 is provided around the light-transmitting area 121, and the pixel unit area 122 enables the second display area to realize a display function. By multiplexing imaging and display functions in the second display area, the screen-to-body ratio of the display screen is effectively increased.
  • corresponding signal wiring needs to be set between the pixel unit areas.
  • a plurality of wiring groups in the row direction are arranged in the first direction x, and each wiring group is configured to drive the light-emitting device arranged in the pixel unit area when it is electrically connected to the pixel unit area arranged in the first direction. , Thereby forming rows of the pixel array.
  • the multiple wiring groups in the first direction are distinguished according to whether a connection is established with the pixel unit area in the second display area, and the wiring group that establishes a connection with the pixel unit area in the second display area is the first wiring group 123 -1, the wiring group that is not connected to the pixel unit area in the second display area is the second wiring group 123-2.
  • the first wiring group 123-1 and the second wiring group 123-2 are alternately arranged in the first display area and the second display area in a first order.
  • the first sequence as shown in Figure 2, from top to bottom, the first wiring group 123-1 with the same serial number is arranged in the upper area of the second wiring group 123-2 with the same serial number, and the two wiring groups are kept between A certain separation distance.
  • the relationship between the first wiring group 123-1 with the serial number 1 and the second wiring group 123-2 with the serial number 1 is that the first wiring group 123-1 with the serial number 1 is set in the serial number 1 The upper position of the second wiring group 123-2.
  • that A is disposed at an upper position (area) of B means that A is disposed at a position (area) of B away from the base substrate.
  • the first wiring group 123-1 is set in both the first display area and the second display area to connect adjacent pixel unit areas in the first direction.
  • the first wiring group 123-1 includes 4 wirings as an example, wiring 1, wiring 2, wiring 3, and wiring 4.
  • the number of wires included in the wire group depends on the circuit conditions, which is not limited in the present disclosure.
  • the second wiring group 123-2 connects adjacent pixel unit areas in the first direction in the first display area. In the second display area, although there is no pixel unit area, the second wiring group still extends along the first direction. After passing through the second display area, it connects to the first direction in the first display area. ⁇ pixel unit area.
  • the second wiring group 123-2 is not used to connect the pixel unit area in the second display area.
  • the second wiring group 123-2 includes 4 wirings as an example, wiring 5, wiring 6, wiring 7, and wiring 8. The number of wires included in the wire group depends on the circuit conditions, which is not limited in the present disclosure.
  • the signal lines included in the first wiring group 123-1 and the second wiring group 123-2 may be the same, for example, both include a reset control signal line, a reset signal line, a gate drive control line, and a light-emitting control signal line.
  • the signal lines included in the first wiring group 123-1 and the second wiring group 123-2 may also be partially the same. Depending on the circuit situation, the present disclosure does not limit this.
  • the second direction y multiple wiring groups in the column direction are set, both in the first display area and the second display area to connect adjacent pixel unit areas in the second direction.
  • the display area is connected to adjacent pixel unit areas in the second direction.
  • the second display area since there is no pixel unit area, it still continues to extend along the direction of the second direction.
  • a display area is connected to adjacent pixel unit areas in the second direction.
  • the wiring group in the second direction may include data signal lines, power supply voltage signal lines, and so on.
  • the wiring group is usually arranged on the source and drain layer.
  • FIG. 3 shows a schematic top view of a wiring scheme of the first wiring group and the second wiring group.
  • FIG. 3 shows the positional relationship between the first wiring group and the second wiring group with the same serial number.
  • the wiring 1, the wiring 3, and the wiring 4 included in the first wiring group 123-1 are arranged on the first gate metal layer (ie, the gate1 metal layer) 31, and the first wiring group
  • the wiring 2 included in 123-1 is disposed on the second gate metal layer (ie, the gate2 metal layer) 32.
  • the wiring 5, the wiring 7, and the wiring 8 included in the second wiring group 123-2 are arranged on the first gate metal layer (that is, the gate1 metal layer) 31, and the second wiring group 123-2 includes The wiring 6 is arranged on the second gate metal layer (that is, the gate2 metal layer) 32.
  • the density of the wiring of the first wiring group 123-1 and the second wiring group 123-2 in the second display area is such that the light entering the second display area is transmitted to The probability of the first gate metal layer is reduced, which may result in poor imaging quality of the second display area when it is multiplexed as a camera function.
  • the embodiment of the present disclosure proposes a solution to remove the multiple wiring groups provided in the second display area to the outside of the second display area to increase the light transmission area of the light transmission area, thereby improving the imaging quality of the second display area .
  • FIG. 4 shows a schematic top view of a wiring solution for a second wiring group provided by an embodiment of the present disclosure.
  • FIG. 4 shows the wiring relationship between the first wiring group and the second wiring group with the same serial number.
  • the second wiring group is not arranged between adjacent first wiring groups.
  • no second wiring group is provided between two adjacent first wiring groups.
  • the second wiring group 123-2 is arranged at the outer edge area of the second display area to reduce the occupied area of the second wiring group in the second display area, thereby improving the light transmittance of the light-transmitting area 121 and increasing The light transmittance of the light-transmitting area is increased, and the imaging quality when the second display area is multiplexed as an imaging function is improved.
  • the second wiring group 123-2 is arranged in the outer edge area of the second display area in a manner along the upper edge area of the schematic top view of the second display area, or may be the lower edge area of the schematic top view, for example, the second
  • the display area is circular and can be divided into an outer area of the upper semicircle and an outer area of the lower semicircle. Setting the second wiring group on the outer edge of the second display area can be adjusted by adjusting the second wiring group in the upper semicircle to the upper edge of the upper semicircle, and adjusting the second wiring group in the lower semicircle to the lower semicircle The lower edge.
  • the first trace group 123-1 includes four first traces, numbered from top to bottom, including trace 1, trace 2, trace 3, and trace 4.
  • the second wiring group 123-2 includes four second wirings, numbered from top to bottom, including wiring 5, wiring 6, wiring 7, and wiring 8.
  • All the traces of the second trace group 123-2 can pass through the first opening A on the 2nd trace, pass through the wiring area of the first trace group 123-1, and pass through the second trace on the 2nd trace.
  • the opening B passes through the wiring area of the first wiring group 123-1, and continues to extend along the wiring direction of the second wiring group 123-2 in the first display area.
  • the embodiments of the present disclosure convert the 5th, 7th, and 8th wiring in the second wiring group to the second gate.
  • FIG. 5 shows a schematic structural diagram of an adjusted second wiring group provided by an embodiment of the present disclosure.
  • a first opening A and a second opening B are provided on the second trace in the first trace group.
  • the first opening A and the second opening B cut the No. 2 wire into three parts.
  • Figure 5 starting from the left, along the first direction X, the position of the three parts and the first opening A and the second opening B The relationship is as follows: the first part, the first opening A, the second part, the second opening B, and the third part.
  • the perforated conductive line 2a is formed through the process steps, one end of the perforated conductive line 2a is connected to one end of the first part of the No. 2 trace, and the other end of the perforated conductive line 2a is connected to a new trace provided on the first gate metal layer 31 Connected.
  • the perforated conductive line 2b is formed, one end of the perforated conductive line 2b is connected to one end of the second part of the 2nd trace, and the other end of the perforated conductive line 2b is connected to the first gate metal layer 31. If the new trace is connected, the perforated conductive line 2a and the perforated conductive line 2b are connected on the first gate metal layer through a new trace.
  • the second opening B is provided with a perforated conductive line 2c and a perforated conductive line 2d, and the perforated conductive line 2c and the perforated conductive line 2d are connected on the first gate metal layer by a new wiring.
  • a perforated conductive line 5a, a perforated conductive line 7a and a perforated conductive line 8a, and a perforated conductive line 5b, a perforated conductive line 7b and a perforated conductive line 8b are provided between the second gate metal layer 32 and the first gate metal layer 31 .
  • the No. 5 trace provided on the first gate metal layer 31 is transferred to the second gate metal layer 32 through the perforated conductive line 5a, and is connected to the first new trace provided, that is, the AND shown in the figure An arc-shaped trace connected to the perforated conductive line 5a.
  • the No. 7 trace provided on the first gate metal layer 31 is transferred to the second gate metal layer 32 through the perforated conductive line 7a.
  • the No. 8 trace provided on the first gate metal layer 31 is transferred to the second gate metal layer 32 through the perforated conductive line 8a.
  • the first new trace corresponding to the perforated conductive line is provided in the second gate metal layer , Go through the first opening A of route 2 and continue to pass through the second opening B of route 2 along the boundary of the second display area, thereby connecting route 5, route 7 and route 8 The wire goes around the second display area in the second gate metal layer.
  • the second gate metal layer 32 and the first gate metal layer 31 are connected through the perforated conductive line 5b, the perforated conductive line 7b and the perforated conductive line 8b, which will correspond to the perforated conductive line 5b.
  • the first new trace (the trace is also corresponding to the perforated conductive line 5a) is converted to the first gate metal layer 31 through the perforated conductive line 5b.
  • the first new trace corresponding to the perforated conductive line 7b is converted to the first gate metal layer 31 through the perforated conductive line 7b.
  • the first new trace corresponding to the perforated conductive line 8b is converted to the first gate metal layer 31 through the perforated conductive line 8b.
  • the No. 6 trace provided on the second gate metal layer 32 passes through the first opening A and the second opening B along the boundary of the second display area, and then runs along the No. 6 trace in the first display area. The line direction continues to extend.
  • the second gate metal layer is obtained by adjusting the traces provided on the first gate metal layer through the above-mentioned embodiments, so as to bypass the second display area and increase the light transmission area of the second display area. , Which effectively improves the light transmittance of the second display area.
  • FIG. 6 shows a schematic diagram of wiring at the first opening A provided by an embodiment of the present disclosure.
  • the No. 6 trace in the second trace group 123-2 is arranged on the second gate metal layer. After passing through the first opening A by changing the original trace direction, the trace along the second display area The shape continues to extend.
  • the 5th, 7th and 8th traces in the second trace group 123-2 are arranged on the plane where the first gate metal layer is located, and pass through the first gate metal layer and the second gate metal layer.
  • Perforated conductive lines 5b, perforated conductive lines 7b and perforated conductive lines 8b are arranged between the polar metal layers, and the 5th, 7th and 8th traces arranged in the first gate metal layer 31 are adjusted to the second The gate metal layer 32 then bypasses the second display area by forming a first new trace in the second gate metal layer 32, thereby increasing the light transmission area of the second display area and improving the transmission of the second display area. Light rate.
  • FIG. 7 shows a schematic cross-sectional view of the display panel at the first opening A according to an embodiment of the present disclosure.
  • a first insulating layer 21 is provided on the base substrate 10, a first gate metal layer 31 is provided on the first insulating layer 21, a second insulating layer 22 is provided on the first gate metal layer 31, and the second insulating layer A second gate metal layer 32 is provided on 22.
  • the second gate metal layer 32 shown in FIG. 7 is the 2nd trace. As shown in Figure 7, the 5th trace, the 6th trace, the 7th trace and the 8th trace pass through the first opening area A.
  • FIG. 8 shows a schematic top view of a wiring solution for a second wiring group according to another embodiment of the present disclosure.
  • the second display area at least part of the first wiring group and part of the second wiring group are alternately arranged in the second order, and the second order is alternately arranged so that adjacent first wiring groups The blank area between them increases.
  • the second order is different from the first order. If the first order means that the i-th first wiring group is arranged in the upper area of the i-th second wiring group, the value of i is a positive integer less than or equal to M or N.
  • the alternate arrangement in the first order means that the first wiring group and the second wiring group with the same serial number are alternately arranged in a top-down order in the plane of the top view.
  • the second sequence arrangement includes removing the second wiring group from the adjacent first wiring group as shown in FIG. 4, and only the first wiring groups with different serial numbers in the second display area are in the order of the serial numbers. Arranged in sequence.
  • the alternate arrangement in the second sequence also includes arranging the second wiring group in the upper area of the first wiring group whose sequence numbers differ by m, where m is an integer smaller than i.
  • the i-th second wiring group is set in the upper area of the i-th first wiring group; when m is greater than an integer of 0, the i-th second wiring group is set in the i-th To the upper area of the m first wiring groups, m is an integer smaller than i.
  • the second wiring group Arrange the second wiring group; set part of the i-th second wiring group in the upper area of the i-th or i-th to m-th first wiring group, and m is an integer smaller than i.
  • the 5 to 8 traces of the 1 to 8 traces are adjusted to the upper area of the 1 to 4 traces in the second group, which can be handled as follows:
  • the 5th, 7th, and 8th traces in the second group pass through the perforated conductive lines arranged between the first gate metal layer and the second gate metal layer to connect the 5 Route No. 7, Route No. 7 and Route No. 8 are adjusted to the upper area of the wiring area of No. 1 to No. 4 in the second group.
  • the second new wire group may include a plurality of second new wires and a plurality of third new wires.
  • the 5th, 7th and 8th traces in the second group are located in the first gate metal layer 31, and pass through the first gate metal layer 31 and the second gate metal layer 31.
  • the perforated conductive wires 5a, 7a, 8a between the metal layers 32 are connected to the new wires provided in the second gate metal layer 32, wherein the new wires corresponding to the 5th and 7th wires are
  • the second new wiring after the second new wiring passes through the wiring areas of No. 1 to 4 in the second group, adjust the second new wiring back to the first gate metal layer 31 by setting the corresponding perforated wires, and continue Follow the original routing direction.
  • the new trace corresponding to trace 8 is the third new trace.
  • the third new trace continues to extend in the same direction as trace 6 to the second opening, and then the third trace is passed through the corresponding perforated wire.
  • the three new traces are adjusted back to the first gate metal layer.
  • the first trace, the third trace, and the fourth trace are arranged in the first gate metal layer 31, and the second trace is arranged on the second gate metal layer 32.
  • Set the first opening and the second opening adjust the 5th trace, the 7th trace and the 8th trace in the second group to the second gate metal layer 32, and the 5th trace and the 7th trace
  • the second new trace corresponding to the line intersects the orthographic projection area of the first trace, the third trace, and the fourth trace in the second gate metal layer 32 in the second group.
  • the third new trace corresponding to the 8th trace passes through the first opening and the second opening in turn, and the third new trace passes through the first trace, the 3rd trace, and the 4th trace in the second group.
  • the orthographic projection area in the second gate metal layer 32 is adjusted back into the first gate metal layer 31 by perforating conductive wires.
  • the 6th trace and the 8th trace in the second group can continue on the second gate metal layer 32, and continue along the same direction as the extension direction of the 1 to 4 traces in the second group. extend.
  • the 5th and 7th traces in the second group after passing through the wiring area of the 1 to 4 traces in the second group, return to the first gate metal layer through the perforated wires, so that they can be seen from the top view Going down, it is very similar to the wiring positions of the 6th and 8th traces on the second gate metal layer, and even overlaps. As a result, the area of the wiring area presented in the second display area is reduced, and the light transmittance of the second display area is increased.
  • FIG. 8 also shows that in the second display area, at least a part of the first wiring group and a part of the second wiring group are arranged in a second order:
  • the second wiring group is not provided between some adjacent first wiring groups, for example, the second wiring group is not provided between the first group and the second group;
  • the second wiring group of the second group is arranged in the upper area of the first wiring group of the second group;
  • part of the second wiring of the second wiring group of the third group is set in the upper area of the first wiring group of the third group, and the other part of the second wiring group of the third group is still It continues to extend in the second display area according to its extending direction in the first display area.
  • the embodiment of the present disclosure adjusts the originally dense arrangement position of the second wiring group and the first wiring group to have a larger light-transmitting area between adjacent first wiring groups through the above-mentioned second sequence arrangement, so that The light transmission area of the second display area is increased, thereby effectively increasing the light transmittance of the second display area.
  • two axisymmetric openings A and B are opened on the second trace in the first trace group 123-1.
  • the symmetry axis is a symmetry axis of the second display area along the second direction, and the second direction is a direction perpendicular to the first direction.
  • Figure 8 only shows a variety of different wiring situations at the opening A, the wiring situation of the opening B can be completed according to the wiring method shown in Figure 5, corresponding to the multiple wiring situations shown in Figure 8 ⁇ The routing.
  • the area occupied by the second wiring group in the second display area is reduced, thereby increasing the light transmittance of the second display area.
  • FIG. 9 shows a schematic cross-sectional view of a display panel at the first opening A according to another embodiment of the present disclosure.
  • Fig. 9 is a schematic cross-sectional view taken along the A-A' section line shown in Fig. 5 to the base substrate.
  • the second wiring group 123-2 is routed along the edge of the second display area in the second gate metal layer, and passes through the first opening A and the second opening B in turn, so that the length of the wiring is increased, thereby increasing
  • the resistance of the trace in the embodiments of the present disclosure, the cross-sectional area of the wire in the second gate metal layer of the new trace can be increased to make it larger than the wire cross-section of the second trace in the first gate metal layer. area.
  • the embodiment of the present disclosure can compensate for resistance by increasing the thickness of each second wire in the second wire group.
  • the resistance can be compensated by increasing the width of each second trace.
  • FIG. 10 shows a schematic top view of a wiring solution of the second wiring group provided by another embodiment of the present disclosure.
  • FIG. 10 shows that when m is greater than an integer of 0, that is, the i-th second wiring group is arranged in the upper region of the i-th to m-th first wiring group, m is an integer smaller than i.
  • the two symmetrical opening pairs on the left side can be realized according to the partial trace diagram of the two openings on the left side shown in Figure 10
  • the wiring design of the two opening positions on the right side is not shown in the figure. It can be implemented according to the wiring design corresponding to the single opening on the right side shown in FIG. 5.
  • the light transmission area between the first trace group of the first group and the second trace group Significant increase.
  • its routing can be considered to partially bypass the display area, and then adjust in the second display area in the manner that the second routing group of the second group is set in the upper area of the first routing group of the first group .
  • the embodiments of the present disclosure increase the blank area between two adjacent first wiring groups by adjusting the alternate arrangement relationship between the first wiring group and the second wiring group, thereby increasing the size of the second display area.
  • the light-transmitting area improves the light transmittance of the second display area.
  • the occupied area of the second wiring group in the second display area is effectively reduced, thereby improving
  • the light transmittance of the second display area is beneficial to improve the imaging quality of the second display area when it is multiplexed as a camera function.
  • the embodiments of the present disclosure also provide a display device, which includes the above-mentioned display panel and sensor unit, which is arranged in the second display area of the display panel and is located at a direction away from the light emission direction of the base substrate. side.
  • the photosensitive surface of the sensor unit faces the display panel.
  • the display panel provided by the embodiments of the present disclosure may be a flexible panel.
  • the base substrate includes a flexible substrate, and a flexible organic material such as polyimide (PI) may be selected.
  • PI polyimide
  • the display panel provided by the embodiment of the present disclosure is suitable for a display device that requires a sensor under the screen, where the sensor may be a camera.
  • the display device may be a tablet computer, a mobile phone, a touch-sensitive computer, etc.
  • the display panel and the display device provided by the embodiments of the present disclosure increase the blank area between adjacent first wiring groups by adjusting the wiring sequence, thereby increasing the light transmission area of the second display area and improving its transparency. Light rate.

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Abstract

一种显示面板和显示装置。该显示面板，包括第一显示区域和第二显示区域，沿第一方向设置的M个第一走线组和N个第二走线组，M和N为正整数，在第一显示区域内，第一走线组与第二走线组按照第一顺序交替排布；在第二显示区域内，至少部分第一走线组与部分第二走线组按照第二顺序交替排布，第二顺序与第一顺序不同，第二顺序交替排布使得相邻的第一走线组之间的空白区域增大。

Description

显示面板和显示装置
本申请要求于2020年1月22日提交中国专利局、申请号为202010075977.5、发明名称为“显示面板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及显示面板和显示装置。
背景技术
随着技术的发展，市场对于高屏占比的显示面板的需求越来越迫切，显示面板正朝着全屏化、轻薄化方向发展。全屏化的实现离不开屏下摄像头技术，即当不需要成像功能时，摄像头与显示面板的其他区域一样正常发光；当需要成像功能时，摄像头区域具有正常成像功能。然而，摄像头区域由于其成像功能需要较高的光学透过率，正常发光区的透过率远远无法满足摄像头的需求。采用“H+L”的设计，即正常区域使用高PPI，透过率较高的区域使用低PPI的设计。对于低PPI区域来说，设置像素单元的位置透过率较低，像素之间的空白区透过率则比较高，从而提高该区域的整体透过率。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示面板，包括第一显示区域和第二显示区域，沿第一方向设置的M个第一走线组和N个第二走线组，M和N为正整数；
在第一显示区域内，第一走线组与第二走线组按照第一顺序交替排布；
在第二显示区域内，至少部分第一走线组与部分第二走线组按照第二顺 序交替排布，第二顺序与第一顺序不同，第二顺序交替排布使得相邻的第一走线组之间的空白区域增大。
第二方面，本公开实施例提供了一种显示装置，该显示装置包括第一方面描述的显示面板，传感器单元，设置在显示面板的第二显示区域，且位于衬底基板背离出光方向的一侧，该传感器单元的感光面朝向所述显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本公开的其它特征、目的和优点将会变得更明显：
图1示出了本公开实施例提供的显示面板的结构示意图；
图2示出了本公开实施例提供的第二显示区域的局部结构的俯视示意图；
图3示出了一种第一走线组和第二走线组的布线方案的示意图；
图4示出了本公开实施例提供的第二走线组的布线方案的俯视示意图；
图5示出了本公开实施例提供调整后的第二走线组的结构示意图；
图6示出了本公开实施例提供的第一开口A处的走线示意图；
图7示出了本公开实施例提供的显示面板在第一开口A处的剖面示意图；
图8示出了本公开又一实施例提供的第二走线组的布线方案的俯视示意图；
图9示出了本公开又一实施例提供的显示面板在第一开口A处的剖面示意图；
图10示出了本公开又一实施例提供的第二走线组的布线方案的俯视示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的实施例仅仅用于解释相关公开，而非对该公开的限定。另外还 需要说明的是，为了便于描述，附图中仅示出了与公开相关的部分。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
请参考图1，图1示出了本公开实施例提供的显示面板的结构示意图。
显示面板1包括第一显示区域11和第二显示区域12，每个显示区域均包括多个像素单元区域(图中未示出)，其中第一显示区域11的像素单元区域的密度大于第二显示区域12的像素单元区域的密度。即在相同面积的第一显示区域和第二显示区域内，第二显示区域内的像素驱动电路的个数小于第一显示区域内的像素驱动电路的个数。
其中，第二显示区域12可以如图1所示，其形状可以是圆形，或者其他形状。在本实施例中，将第二显示区域12设置成圆形。
其中，第二显示区域12，请参考图2，图2示出了本公开实施例提供的第二显示区域的局部结构的俯视示意图。
如图2所示，第二显示区域12包括多个透光区域121和多个像素单元区域122。每个透光区域121周围有四个像素单元区域122。光线通过透光区域121透射到显示面板的传感器(例如摄像头)，传感器接收光线，从而实现摄像功能。并且，透光区域121的周围设置像素单元区域122，像素单元区域122使得第二显示区域实现显示功能。通过在第二显示区域复用成像和显示功能，有效地提高了显示屏的屏占比。
为了在第二显示区域实现成像和显示功能的复用，在像素单元区域之间需要设置相应的信号走线。例如，在第一方向x上设置行方向的多个走线组，每个走线组在与第一方向设置的像素单元区域导通连接时，设置为驱动该像素单元区域设置的发光器件工作，从而形成像素阵列的行。将第一方向的多个走线组按照是否在第二显示区域内与像素单元区域建立连接进行区分，在第二显示区域内与像素单元区域建立连接的走线组为第一走线组123-1，在第二显示区域内与像素单元区域未建立连接的走线组为第二走线组123-2。
如图2所示，第一走线组123-1和第二走线组123-2在第一显示区域和第二显示区域内按照第一顺序交替排布。第一顺序，如图2所示，至上而下， 相同序号的第一走线组123-1设置在相同序号的第二走线组123-2的上部区域，两组走线组之间保持一定的间隔距离。例如，序号为1的第一走线组123-1，与序号为1的第二走线组123-2的关系，是序号为1的第一走线组123-1设置在序号为1的第二走线组123-2的上部位置。
在本公开实施例中，A设置在B的上部位置(区域)是指A设置在B远离衬底基板方向的位置(区域)。
第一走线组123-1，在第一显示区域内和第二显示区域内都设置为连接第一方向上相邻的像素单元区域。本公开附图以第一走线组123-1包括4条走线为例，走线1，走线2，走线3，走线4。该走线组包含的走线的数量，根据电路情况而定，本公开对此不作限定。
第二走线组123-2，在第一显示区域内连接第一方向上相邻的像素单元区域。在第二显示区域，虽然没有设置像素单元区域，但第二走线组仍然沿着第一方向的走向继续延伸，穿过第二显示区域后，在第一显示区域内再连接第一方向上的像素单元区域。第二走线组123-2在第二显示区域内未用于连接像素单元区域。本公开附图以第二走线组123-2包括4条走线为例，走线5，走线6，走线7，走线8。该走线组包含的走线的数量，根据电路情况而定，本公开对此不作限定。
其中，第一走线组123-1和第二走线组123-2包括的信号线可以相同，例如均包括复位控制信号线、复位信号线、栅极驱动控制线、发光控制信号线等。第一走线组123-1和第二走线组123-2包括的信号线也可以部分相同。根据电路情况而定，本公开对此不作限定。
同理，在第二方向y上，设置列方向的多个走线组，在第一显示区域内和第二显示区域内都设置为连接第二方向上相邻的像素单元区域，在第一显示区域内连接第二方向上相邻的像素单元区域，在第二显示区域，由于没有设置像素单元区域，其仍然沿着第二方向的走向继续延伸，穿过第二显示区域后，在第一显示区域内连接第二方向上的相邻的像素单元区域。在第二方向的走线组可以包括数据信号线、电源电压信号线等。该走线组通常在源漏极层上设置。
下面结合图3理解一种第一走线组和第二走线组的布线情况。图3示出 了一种第一走线组和第二走线组的布线方案的俯视示意图。图3示出了序号相同的第一走线组和第二走线组的位置关系。
如图3所示，第一走线组123-1所包含的走线1，走线3，走线4设置在第一栅极金属层(即gate1金属层)31上，第一走线组123-1所包含的走线2设置在第二栅极金属层(即gate2金属层)32上。
第二走线组123-2所包含的走线5，走线7，走线8设置在第一栅极金属层(即gate1金属层)31上，第二走线组123-2所包含的走线6设置在第二栅极金属层(即gate2金属层)32上。
从图3的布线情况可知，在第二显示区域内的第一走线组123-1和第二走线组123-2的走线密集程度，使得进入第二显示区域内的光线被透射到第一栅极金属层的概率减小，这会导致第二显示区域在复用为摄像功能时，其成像质量较差。
本公开实施例提出了将在第二显示区域内设置的多个走线组移除到第二显示区域外部，以增加透光区域的透光面积，从而提升第二显示区域的成像质量的方案。请参考图4，图4示出了本公开实施例提供的第二走线组的布线方案的俯视示意图。图4示出了序号相同的第一走线组和第二走线组的布线关系。
如图4所示，在第二显示区域内，在相邻的第一走线组之间不排布第二走线组。
在图4中，两个相邻的第一走线组之间不设置第二走线组。将第二走线组123-2设置在第二显示区域的外部边缘区域，来减少第二走线组在第二显示区域的占用面积，从而使得透光区域121的透光性得到改善，增大了透光区域的透光率，提高了第二显示区域复用为成像功能时的成像质量。
第二走线组123-2设置在第二显示区域的外部边缘区域的方式可以是沿着第二显示区域的俯视示意图的上部边缘区域，也可以是俯视示意图的下部边缘区域，例如，第二显示区域为圆形可以划分为上半圆的外部区域和下半圆的外部区域。将第二走线组设置在第二显示区域的外部边缘可以是将上半圆内的第二走线组调整到上半圆的上部边缘，将下半圆内的第二走线组调整 到下半圆的下部边缘。
如图4所示，第一走线组123-1包括四根第一走线，按照至上而下进行编号，依次包括1号走线，2号走线，3号走线，4号走线。第二走线组123-2包括四根第二走线，按照至上而下进行编号，依次包括5号走线，6号走线，7号走线，8号走线。
其中第二走线组123-2的全部走线可以通过2号走线上的第一开口A，穿过第一走线组123-1的布线区域，并通过2号走线上的第二开口B，穿过第一走线组123-1的布线区域，沿着第二走线组123-2在第一显示区域内的走线方向继续延伸。
本公开实施例为了减少第二走线组123-2在第二显示区域占用面积，通过将第二走线组中5号走线，7号走线和8号走线转换到第二栅极金属层，将6号走线在第二栅极金属层的布线方式，均绕过第二显示区域12。这样可以减少第二走线组在第二显示区域内的占用面积，从而提高第二显示区域的透光率。
下面结合图5说明第二走线组绕过第二显示区域的示意图。图5示出了本公开实施例提供调整后的第二走线组的结构示意图。
如图5所示，在第二栅极金属层32上通过工艺步骤，在第一走线组中的2号走线上设置第一开口A和第二开口B。第一开口A和第二开口B将2号走线切分成三部分，在图5中，从左侧开始，沿第一方向X，该三部分与第一开口A和第二开口B的位置关系依次为：第一部分，第一开口A，第二部分，第二开口B，第三部分。
通过工艺步骤形成穿孔导电线2a，穿孔导电线2a的一端与2号走线的第一部分的一端连接，穿孔导电线2a的另一端与在第一栅极金属层31上设置的新的走线相连。
同样地，通过工艺步骤形成穿孔导电线2b，穿孔导电线2b的一端与2号走线的第二部分的一端连接，穿孔导电线2b的另一端与在第一栅极金属层31上设置的新的走线相连，则穿孔导电线2a与穿孔导电线2b在第一栅极金属层上通过新的走线相连。与前述方式相同，在第二开口B处设置穿孔导电 线2c和穿孔导电线2d，穿孔导电线2c与穿孔导电线2d在第一栅极金属层上通过新的走线相连。
在第二栅极金属层32与第一栅极金属层31之间，设置穿孔导电线5a，穿孔导电线7a和穿孔导电线8a，以及穿孔导电线5b，穿孔导电线7b和穿孔导电线8b。将在第一栅极金属层31上设置的5号走线，经过穿孔导电线5a转换到第二栅极金属层32上，与设置的第一新走线相连，即图中示出的与穿孔导电线5a相连的弧形的走线。同理，将在第一栅极金属层31上设置的7号走线，经过穿孔导电线7a转换到第二栅极金属层32上。将在第一栅极金属层31上设置的8号走线，经过穿孔导电线8a转换到第二栅极金属层32上。
在将5号走线、7号走线和8号走线转换至第二栅极金属层32上之后，在第二栅极金属层内通过设置的与穿孔导电线对应的第一新走线，穿过2号走线的第一开口A，并继续沿着第二显示区域的边界穿过2号走线的第二开口B，从而将5号走线、7号走线和8号走线在第二栅极金属层内绕过第二显示区域。
在绕过第二显示区域之后，通过穿孔导电线5b，穿孔导电线7b和穿孔导电线8b，连通第二栅极金属层32与第一栅极金属层31，将与穿孔导电线5b对应的第一新走线(该走线也是与穿孔导电线5a对应的)经过穿孔导电线5b转换至第一栅极金属层31。以及将与穿孔导电线7b对应的第一新走线，经过穿孔导线7b转换到第一栅极金属层31。将与穿孔导电线8b对应的第一新走线，经过穿孔导线8b转换到第一栅极金属层31。
设置在第二栅极金属层32上的6号走线沿着第二显示区域的边界依次穿过第一开口A和第二开口B后，沿着6号走线在第一显示区域的走线方向继续延伸。
本公开实施例通过上述实施例，将在第一栅极金属层上设置的走线调整得到第二栅极金属层，来实现绕过第二显示区域，增大第二显示区域的透光面积，其有效地提高了第二显示区域的透光率。
为了更清楚地理解本公开实施例提供的布线改进，将图5中左侧的对应第一开口A的虚线圆圈示意部分进行放大。图6示出了本公开实施例提供的 第一开口A处的走线示意图。
如图6所示，第二走线组123-2中6号走线设置在第二栅极金属层，通过改变原有走线方向穿过第一开口A后，沿着第二显示区域的形状继续延伸，第二走线组123-2中5号走线、7号走线和8号走线设置在第一栅极金属层所在平面，通过在第一栅极金属层与第二栅极金属层之间设置穿孔导电线5b，穿孔导电线7b和穿孔导电线8b，将第一栅极金属层31中设置的5号走线、7号走线和8号走线调整到第二栅极金属层32，然后通过在第二栅极金属层32内形成第一新走线，来绕过第二显示区域，从而增加第二显示区域的透光面积，提升第二显示区域的透光率。
下面结合图7，描述本公开实施例提供的走线剖面示意图。沿着图5所示A-A’剖线，得到图7示出的结构示意图，该A-A’剖线是沿着2号走线的第一开口A向衬底基板方向剖开的示意图。图7示出了本公开实施例提供的显示面板在第一开口A处的剖面示意图。
在衬底基板10上设置第一绝缘层21，在第一绝缘层21上设置第一栅极金属层31，在第一栅极金属层31上设置第二绝缘层22，在第二绝缘层22上设置第二栅极金属层32。图7中示意的第二栅极金属层32即为2号走线。如图7所示，5号走线，6号走线，7号走线和8号走线穿过第一开口区域A。
为了保持显示效果的均一性，防止过多的第二走线组在第二显示区域周边形成边框。请参考图8，图8示出了本公开又一实施例提供的第二走线组的布线方案的俯视示意图。如图8所示，在第二显示区域内，至少部分第一走线组与部分第二走线组按照第二顺序交替排布，第二顺序交替排布使得相邻的第一走线组之间的空白区域增大。第二顺序与第一顺序不同。若第一顺序是指第i个的第一走线组设置在第i个第二走线组的上部区域，i取值为小于等于M或N的正整数。第一顺序交替排布是指序号相同的第一走线组与第二走线组在俯视图平面内按照至上而下的顺序交替排布。第二顺序排布包括如图4所示的将第二走线组从相邻的第一走线组中移除后，第二显示区域内仅有序号不同的第一走线组按序号顺序依次排布。第二顺序交替排布还包括将第二走线组设置在序号相差m的第一走线组的上部区域，m为小于i的 整数。
当m为0时，即将第i个第二走线组设置在第i个第一走线组的上部区域；当m大于0的整数时，即将第i个第二走线组设置在第i至m个第一走线组的上部区域，m为小于i的整数。
为了更好地保持显示效果的均一性，防止过多的第二走线组在第二显示区域周边形成边框，在一示例性实施例中，在部分相邻的第一走线组之间不排布第二走线组；将部分第i个第二走线组设置在第i个或第i至m个第一走线组的上部区域，m为小于i的整数。
如图8示出的第2组(即i＝2)的8根走线，其中第二走线组123-2对应的5至8号走线，通过如图5示出的走线方式，设置在第2组内的第一走线组的1至4号走线的上部区域。图8仅示出了单侧开口的局部示意图。在本公开中，可以仅将第二走线组123-2对应的5至8号走线调整到1至4号走线的上部区域，来增加相邻的第一走线组之间的空白区域，从而增加第二显示区域的透过率。
可选地，如图8所示，至上而下的第1组(i＝1)1至8号走线，其走线分布方式可以参考图4的走线分布方式，第2组(i＝2)1至8号走线中的5至8号走线调整到第2组中的1至4号走线的上部区域，可以参照如下方式处理：
如图8所示，第2组中的5号走线、7号走线和8号走线通过在第一栅极金属层与第二栅极金属层之间设置的穿孔导电线，将5号走线、7号走线和8号走线调整到第2组中1至4号走线布线区域的上部区域位置。
在与5号走线、7号走线和8号走线对应的新走线穿过1至4号走线的布线区域后，可以通过穿孔导电线将新走线部分调整回第一栅极金属层，部分继续沿着第二栅极金属层。由于第一栅极金属层和第二栅极金属在空间上上下层的位置可以重叠，将图8中与第二组中5号走线、7号走线和8号走线对应的新走线，称为第二新走线组。第二新走线组可以包括多个第二新走线和多个第三新走线。
参考图5示出的方式，第2组中5号走线、7号走线和8号走线位于第 一栅极金属层31内，通过在第一栅极金属层31和第二栅极金属层32之间的穿孔导电线5a，7a，8a与在第二栅极金属层32内设置的新的走线相连，其中，与5号走线、7号走线对应的新走线为第二新走线，在第二新走线穿过第2组中1至4号的布线区域后，通过设置相应的穿孔导线将第二新走线调整回第一栅极金属层31，继续沿着原有的走线方向走线。与8号走线对应的新走线为第三新走线，第三新走线沿着与6号走线相同的走向方向继续延伸至第二开口，再通过与之对应的穿孔导线将第三新走线调整回第一栅极金属层。第2组中1号走线、3号走线、4号走线是布置在第一栅极金属层31内，2号走线布置在第二栅极金属层32，通过在2号走线设置的第一开口和第二开口，将第2组中的5号走线、7号走线和8号走线调整到第二栅极金属层32，与该5号走线、7号走线对应的第二新走线与第2组中1号走线、3号走线、4号走线在第二栅极金属层32内的正投影区域相交。与该8号走线对应的第三新走线依次穿过第一开口和第二开口，第三新走线在穿过第2组中1号走线、3号走线、4号走线在第二栅极金属层32内的正投影区域后，通过穿孔导电线调整回第一栅极金属层31内。
如图8中第2组中的6号走线和8号走线可以继续在第二栅极金属层32上，沿着第2组中1至4号走线的延伸方向相同的方向，继续延伸。第2组中5号走线和7号走线在穿过第2组中1至4号走线的布线区域后，通过设置的穿孔导线返回第一栅极金属层，从而使得从俯视图中看下去，与6号走线和8号走线在第二栅极金属层上的布线位置非常近似，甚至重叠。从而使得在第二显示区域内呈现的布线区域的面积减小，增加第二显示区域的透光率。
可选地，如图8所示，图8还示出了在第二显示区域内，至少部分第一走线组与部分第二走线组按照第二顺序排布：
在第二显示区域内，部分相邻的第一走线组之间不设置第二走线组，例如第1组和第2组之间不设置第二走线组；
在第二显示区域内，第2组的第二走线组设置在第2组的第一走线组的上部区域；
在第二显示区域内，第3组的第二走线组的部分第二走线设置在第3组 的第一走线组的上部区域，第3组的第二走线组的另一部分仍按照其在第一显示区域内的延伸方向继续在第二显示区域内延伸。按照布线设计综合考虑，可能存在一部分走线没有可调整的位置空间，从而保留其原有的走线方向。
本公开实施例通过上述第二顺序排布，将第二走线组与第一走线组原本密集的排布位置，调整为相邻第一走线组之间具有较大透光区域，使得第二显示区域的透光面积增加，从而有效地增加了第二显示区域的透光率。
如图4所示，在第一走线组123-1中2号走线上开设两个轴对称的开口A和开口B。对称轴为第二显示区域沿着第二方向设置的对称轴，第二方向为与第一方向垂直的方向。图8仅示出了开口A处的多种不同的走线情况，对开口B的走线情况可以按照图5示出的走线方式，完成与图8示出的多种走线情况相对应的走线。
本公开实施例通过将调整第二走线组在第二显示区域内的布线，使得第二走线组在第二显示区域内占用的面积减小，从而增加第二显示区域的透光率。
进一步地，在绕线过程中，由于绕线会导致电阻增加，本公开实施例还提出一种改进的走线结构以补偿电阻。请参考图9，图9示出了本公开又一实施例提供的显示面板在第一开口A处的剖面示意图。图9是沿着图5示出的A-A’剖线向衬底基板剖开得到的剖面示意图。第二走线组123-2在第二栅极金属层内通过沿着第二显示区域的边缘进行绕线，依次穿过第一开口A和第二开口B，使得走线长度增加，从而增加走线的电阻，本公开实施例可以通过增加上述新走线的在第二栅极金属层内的导线横截面积，使其大于第二走线在第一栅极金属层内的导线横截面积。例如，本公开实施例可以通过增加第二走线组内的每根第二走线的厚度来补偿电阻。
可选地，可以通过增加每根第二走线的宽度来补偿电阻。
可选地，请参考图10，图10示出了本公开又一实施例提供的第二走线组的布线方案的俯视示意图。图10示出了当m大于0的整数时，即将第i个第二走线组设置在第i至m个第一走线组的上部区域的情况，m为小于i的整数。
如图10所示，可以在第1(i＝1)组的第一走线组的2号走线上方开设多个开口对，通过其中一组开口对将第1组的第二走线组在第一栅极金属层的走线调整到第二显示区域外部，通过另外一组开口对将第2(i＝2)组的第二走线组在第一栅极金属层的走线调整到第1组的第一走线组的上部区域。图10示出了m＝1的情况，根据实际需要可以综合考虑透光与边框问题，选择m的取值。与上述实施方式相同的部分可以参考图4至图7的描述。
当第1组的第一走线组123-1的2号走线上开设两对对称的开口对时，可以按照图10示出的左侧两个开口的局部走线示意图实现左侧两个开口位置的走线设计，图中未示出右侧两个开口位置的走线设计，可以根据图5示出的右侧单个开口对应的走线设计来实现。
对于第3组的第二走线组设置在第3组的第一走线组的上部区域，则在第1组的第一走线组与第2组的走线组之间的透光面积显著增加，可选地其走线可以考虑部分绕过显示区域后，在第二显示区域内按照第2组的第二走线组设置在第1组的第一走线组上部区域的方式调整。综上，本公开实施例通过调整第一走线组与第二走线组的交替排布关系来增大相邻两个第一走线组之间的空白区域，从而增加第二显示区域的透光面积，提升第二显示区域的透光率。
本公开实施例，通过调整第二走线组在第一栅极金属层和第二栅极金属层的布线位置关系，有效地减少第二走线组在第二显示区域的占用面积，从而提升第二显示区域的透光率，有利于第二显示区域复用为摄像功能时，提升其成像质量。
在相同的构思下，本公开实施例还提供了一种显示装置，该显示装置包括上述的显示面板和传感器单元，设置在显示面板的第二显示区域，且位于衬底基板背离出光方向的一侧。传感器单元的感光面朝向显示面板。本公开实施例提供的显示面板可以为柔性面板，当显示面板为柔性基板时，衬底基板包括柔性衬底，可以选用柔性有机材料，例如聚酰亚胺(PI)。本公开实施例提供的显示面板适用于需要在屏下设置传感器的显示装置，其中传感器可以为摄像头。该显示装置可以是平板电脑、手机、触控式电脑等。
本公开实施例提供的显示面板和显示装置，通过调整走线的顺序来增大 相邻第一走线组之间的空白区域，从而来增大第二显示区域的透光面积，提升其透光率。
以上描述仅为本公开的实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离前述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (12)

  1. 一种显示面板，包括第一显示区域和第二显示区域，沿第一方向设置的M个第一走线组和N个第二走线组，M和N为正整数；
    在所述第一显示区域内，所述第一走线组与所述第二走线组按照第一顺序交替排布；
    在所述第二显示区域内，至少部分所述第一走线组与部分所述第二走线组按照第二顺序排布，所述第二顺序与所述第一顺序不同，所述第二顺序排布使得相邻的所述第一走线组之间的空白区域增大。
  2. 根据权利要求1所述的显示面板，其中，所述至少部分所述第一走线组与部分所述第二走线组按照第二顺序排布，包括：
    在相邻的所述第一走线组之间不设置所述第二走线组。
  3. 根据权利要求1所述的显示面板，其中，所述第一顺序是指第i个的第一走线组设置在第i个第二走线组的上部区域，i取值为小于等于M或N的正整数，则所述至少部分所述第一走线组与部分所述第二走线组按照第二顺序排布，包括：
    将第i个第二走线组设置在第i个或第i至m个第一走线组的上部区域，m为小于i的整数。
  4. 根据权利要求1所述的显示面板，其中，所述第一顺序是指第i个的第一走线组设置在第i个第二走线组的上部区域，i取值为小于等于M或N的正整数，则所述至少部分所述第一走线组与部分所述第二走线组按照第二顺序排布，包括：
    在部分相邻的所述第一走线组之间不设置所述第二走线组；
    将部分第i个第二走线组设置在第i个或第i至m个第一走线组的上部区域，m为小于i的整数。
  5. 根据权利要求1所述的显示面板，其中，所述第一顺序是指第i个的第一走线组设置在第i个第二走线组的上部区域，i取值为小于等于M或N的正整数，则所述至少部分所述第一走线组与部分所述第二走线组按照第二 顺序排布，包括：
    在部分相邻的所述第一走线组之间不设置所述第二走线组；
    将部分第i个第二走线组设置在第i个或第i至m个第一走线组的上部区域，m为小于i的整数；
    将部分第i个第二走线组中的部分第二走线设置在第i个或第i至m个第一走线组的上部区域；
    将部分第i个第二走线组中的另一部分第二走线仍按照其在所述第一显示区域内的延伸方向继续在所述第二显示区域内延伸。
  6. 根据权利要求1至5中任一项所述的显示面板，其中，所述显示面板包括第一栅极金属层和第二栅极金属层，所述第一走线组包括多个第一走线，所述第二走线组包括多个第二走线；其中，部分所述第一走线设置在所述第一栅极金属层内，部分所述第一走线设置在所述第二栅极金属层内；部分所述第二走线设置在所述第一栅极金属层内，部分所述第二走线设置在所述第二栅极金属层内；且设置在所述第一栅极金属层内的第一走线与第二走线不相交，设置在所述第二栅极金属层内的第一走线和第二走线不相交；
    则在所述第二显示区域内，所述第一走线组与所述第二走线组按照第二顺序排布包括：
    在所述第二栅极金属层内设置第一新走线组，通过所述第一新走线组与所述第二走线组相连来实现所述第二顺序；
    或者，在所述第二栅极金属层内设置第二新走线组，通过所述第二新走线组与所述第二走线组相连来实现所述第二顺序。
  7. 根据权利要求6所述的显示面板，其中，所述在所述第二栅极金属层内设置第一新走线组，通过所述第一新走线组与所述第二走线组相连来实现所述第二顺序，包括：
    在所述第二栅极金属层内设置所述第一新走线组，所述第一新走线组包括多个第一新走线，所述第一新走线沿着所述第二显示区域的外部边缘依次穿过第一开口和第二开口，所述第一开口和所述第二开口是在位于所述第二栅极金属层内的所述第一走线组中的第一走线上设置的；
    在所述第一栅极金属层与所述第二栅极金属层之间设置多个第一穿孔导电线，每个所述第一穿孔导电线一端与在所述第一栅极金属层内设置的与所述第一穿孔导电线对应的所述第二走线连接，另一端与在所述第二栅极金属层内设置的与所述第一穿孔导电线对应的所述第一新走线连接；
    所述第二走线组中位于所述第一栅极金属层的第二走线，经过与之相连的所述第一穿孔导电线，和与其对应的所述第一新走线相连接；
    所述第二走线组中位于所述第二栅极金属层的第二走线，沿着所述第二显示区域的外部边缘依次穿过所述第一开口和所述第二开口。
  8. 根据权利要求6所述的显示面板，其中，所述在所述第二栅极金属层内设置第二新走线组，通过所述第二新走线组与所述第二走线组相连来实现所述第二顺序，包括：
    在所述第二栅极金属层内设置所述第二新走线组，所述第二新走线组包括多个第二新走线和多个第三新走线，每个所述第二新走线在第一开口侧与所述第一走线组在所述第二栅极金属层上的正投影区域相交，每个所述第三新走线依次穿过第一开口和第二开口，并在第一开口侧和第二开口侧分别与所述第一走线组在所述第二栅极金属层上的正投影区域相交，所述第一开口和所述第二开口是在位于所述第二栅极金属层内的所述第一走线组中的第一走线上设置的；
    在所述第一栅极金属层与所述第二栅极金属层之间设置多个第二穿孔导电线，每个所述第二穿孔导电线一端与在所述第一栅极金属层内设置的与所述第二穿孔导电线对应的所述第二走线连接，另一端与在所述第二栅极金属层内设置的与所述第二穿孔导电线对应的所述第二新走线连接；
    所述第二走线组中位于所述第一栅极金属层的第二走线，经过与之相连的所述第二穿孔导电线，在所述第一开口侧和与其对应的所述第二新走线相连，并在所述第二开口侧和与其对应的所述第三新走线相连；
    所述第二走线组中位于所述第二栅极金属层的第二走线，依次沿着与所述第二新走线和所述第三新走线的相同的走线方向布线。
  9. 根据权利要求6所述的显示面板，其中，
    所述第一新走线在所述第二栅极金属层内的导线横截面积大于所述第二走线在所述第一栅极金属层内的导线横截面积。
  10. 根据权利要求8所述的显示面板，其中，
    所述第二新走线和所述第三新走线在所述第二栅极金属层内的导线横截面积大于所述第二走线在所述第一栅极金属层内的导线横截面积。
  11. 根据权利要求1至5任意一项所述的显示面板，其中，在相同面积的所述第一显示区域和所述第二显示区域内，所述第二显示区域内的像素驱动电路的个数小于所述第一显示区域内的像素驱动电路的个数。
  12. 一种显示装置，包括如权利要求1至10任意一项所述的显示面板，还包括传感器单元，所述传感器单元设置在所述显示面板的第二显示区域，且位于衬底基板背离出光方向的一侧，所述传感器单元的感光面朝向所述显示面板。
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