WO2021141126A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2021141126A1
WO2021141126A1 PCT/JP2021/000575 JP2021000575W WO2021141126A1 WO 2021141126 A1 WO2021141126 A1 WO 2021141126A1 JP 2021000575 W JP2021000575 W JP 2021000575W WO 2021141126 A1 WO2021141126 A1 WO 2021141126A1
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semiconductor
semiconductor device
semiconductor layer
electrode
film
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PCT/JP2021/000575
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English (en)
Japanese (ja)
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勲 ▲高▼橋
和良 則松
四戸　孝
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株式会社Flosfia
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
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Definitions

  • the present invention relates to a semiconductor device useful for a power device or the like.
  • Patent Document 1 describes a method in which a buffer layer is formed on a dissimilar substrate and a zinc oxide-based semiconductor layer is crystal-grown on the buffer layer.
  • Patent Document 2 describes that a nanodot mask is formed on a dissimilar substrate, and then a single crystal semiconductor material layer is formed.
  • Non-Patent Document 1 describes a method of crystal growing GaN on sapphire via a nanocolumn of GaN.
  • Non-Patent Document 2 describes a method of crystal growing GaN on Si (111) using a periodic SiN intermediate layer to reduce defects such as pits.
  • a high-quality epitaxial film can be obtained due to poor film formation speed, cracks, dislocations, warpage, etc. on the substrate, and dislocations, cracks, etc. on the epitaxial film. It was difficult, and there were problems in increasing the diameter of the substrate and increasing the thickness of the epitaxial film.
  • next-generation switching element capable of achieving high withstand voltage, low loss, and high heat resistance
  • a semiconductor device using gallium oxide (Ga 2 O 3 ) having a large bandgap is attracting attention, and a semiconductor device for power such as an inverter is attracting attention. It is expected to be applied to. Moreover, it is expected to be applied as a light receiving / receiving device for LEDs, sensors, etc. due to its wide band gap.
  • the gallium oxide can control the bandgap by mixing indium and aluminum with each other or in combination, and constitutes an extremely attractive material system as an InAlGaO-based semiconductor.
  • Patent Document 3 describes a method for producing an oxide crystal thin film by a mist CVD method using a bromide or iodide of gallium or indium.
  • Patent Documents 4 to 6 describe a multilayer structure in which a semiconductor layer having a corundum-type crystal structure and an insulating film having a corundum-type crystal structure are laminated on a base substrate having a corundum-type crystal structure. ..
  • Patent Documents 7 to 9 it has been studied to grow an ELO growth or the like of a gallium oxide film having a corundum structure. According to the methods described in Patent Documents 7 to 9, it is possible to obtain a gallium oxide film having a high-quality corundum structure, but the ELO film forming method using the difference in the coefficient of thermal expansion described in Patent Document 7 can be used.
  • the crystal film is actually examined, there is a tendency for facet growth, and there are problems such as dislocations and cracks due to this facet growth, and as described in Patent Document 10, It has been studied that the electrical characteristics are improved depending on the plane direction, but it is still unsatisfactory for application to a semiconductor device having excellent electrical characteristics. All of Patent Documents 3 to 10 are publications relating to patents or patent applications by the present applicant.
  • An object of the present invention is to provide a semiconductor device having excellent semiconductor characteristics, particularly electrical characteristics.
  • the semiconductor layer has at least a semiconductor layer and at least a first electrode and a second electrode arranged on the first surface side of the semiconductor layer.
  • a semiconductor device configured to allow current to flow in a first direction from an electrode to the second electrode, wherein the semiconductor layer has a colland structure, and the c-axis direction of the semiconductor layer is the direction of the c-axis.
  • the present invention relates to the following invention.
  • It has at least a semiconductor layer and at least a first electrode and a second electrode arranged on the first surface side of the semiconductor layer, respectively, and in the semiconductor layer, the first electrode to the first electrode.
  • a semiconductor device configured to allow current to flow in a first direction toward the two electrodes, wherein the semiconductor layer has a colland structure, and the c-axis direction of the semiconductor layer is the first direction. Is a semiconductor device.
  • the semiconductor layer contains a metal oxide containing at least one metal selected from gallium, indium, rhodium and iridium.
  • the semiconductor device of the present invention is excellent in semiconductor characteristics, particularly electrical characteristics.
  • FIG. 1 It is a schematic block diagram of the film forming apparatus preferably used in this invention. It is a schematic block diagram of the film forming apparatus (mist CVD) of another aspect from FIG. 1 which is preferably used in this invention. It is a figure which shows typically a preferable example of a power-source system. It is a figure which shows typically a preferable example of a system apparatus. It is a figure which shows typically a preferable example of the power supply circuit diagram of a power supply device. It is a figure which shows typically an example of the metal oxide film semiconductor field effect transistor (MOSFET) as one aspect of the semiconductor device of this invention. As one aspect of the semiconductor device of the present invention, a part of a schematic top view is shown.
  • MOSFET metal oxide film semiconductor field effect transistor
  • a schematic partial cross-sectional view for example, an example of the AA cross section of FIG. 7 is shown.
  • a partial cross-sectional view showing a specific example is shown, for example, an example of a specific AA cross section of FIG. It is a figure which shows typically a preferable example of a power card. It is a figure which shows the result of Test Example 1.
  • FIG. It is a figure which shows the result of Test Example 2.
  • the semiconductor device of the present invention has at least a semiconductor layer, and at least a first electrode and a second electrode arranged on the first surface side of the semiconductor layer, respectively.
  • a semiconductor device configured to allow current to flow in a first direction from an electrode to the second electrode, wherein the semiconductor layer has a colland structure, and the c-axis direction of the semiconductor layer is the direction of the c-axis. It is characterized in that it is in the first direction.
  • the semiconductor layer contains a metal oxide containing at least one metal selected from gallium, indium, rhodium and iridium.
  • the semiconductor layer contains at least a metal oxide containing gallium as a main component
  • the "main component” means that the metal oxide contains 50% or more in atomic ratio with respect to all the components in the semiconductor layer, preferably 70% or more, more preferably 90%. It means that the above is included, and it may be 100% depending on the embodiment.
  • the metal oxide contains at least gallium and further contains indium, rhodium or iridium, and it is also preferable that the metal oxide contains at least gallium and further contains indium and / and aluminum. It is more preferable that the metal oxide contains at least gallium because the characteristics as a power device such as switching characteristics can be made more excellent.
  • the first surface is the m surface because the electrical characteristics can be further improved.
  • the semiconductor layer is a crystalline oxide semiconductor layer, and preferably contains a crystalline oxide semiconductor.
  • the crystalline oxide semiconductor contains the metal oxide, and as described above, it preferably contains at least gallium, and more preferably contains gallium oxide and a mixed crystal thereof as a main component.
  • the crystal structure of the crystalline oxide semiconductor is not particularly limited, but in the present invention, it is preferable that the crystalline oxide semiconductor contains a metal oxide having a corundum structure as a main component.
  • the metal oxide is not particularly limited, but preferably contains at least one kind or two or more kinds of metals in the 4th to 6th periods of the periodic table, and more preferably contains at least gallium, indium, rhodium or iridium. It is preferable and most preferably contains gallium.
  • the metal oxide contains gallium and indium or / and aluminum.
  • the metal oxide containing gallium include ⁇ -Ga 2 O 3 or a mixed crystal thereof.
  • the semiconductor layer containing such a preferable metal oxide as a main component may have more excellent crystallinity and heat dissipation, and may have further excellent semiconductor characteristics. For example, when the metal oxide is ⁇ -Ga 2 O 3 , the atomic ratio of gallium contained in the semiconductor layer is 50% or more of the total metal components in the semiconductor layer, and ⁇ -Ga 2 It is sufficient if O 3 is contained in the semiconductor layer.
  • the atomic ratio of gallium in the metal component of the semiconductor layer is preferably 70% or more, more preferably 80% or more with respect to the total metal component in the semiconductor layer.
  • the semiconductor layer may be a single crystal or a polycrystal.
  • the semiconductor layer is usually in the form of a film, but is not particularly limited as long as it does not impair the object of the present invention, and may be in the form of a plate or a sheet.
  • the semiconductor layer may contain a dopant.
  • the dopant is not particularly limited as long as it does not interfere with the object of the present invention. It may be an n-type dopant or a p-type dopant. Examples of the n-dopant include tin, germanium, silicon, titanium, zirconium, vanadium, niobium and the like.
  • the carrier concentration may be appropriately set, and specifically, for example, it may be about 1 ⁇ 10 16 / cm 3 to 1 ⁇ 10 22 / cm 3 , and the carrier concentration may be, for example, about. 1 ⁇ 10 17 / cm 3 may be less than a low concentration.
  • the carrier concentration of the semiconductor layer may be contained at a high concentration of about 1 ⁇ 10 20 / cm 3 or more, but in the embodiment of the present invention, the carrier of the semiconductor layer may be contained.
  • the semiconductor layer can be obtained, for example, by the following suitable film forming method. For example, using a crystal substrate in which the second side is shorter than the first side, the c-axis direction is the first direction, and the first direction from the first electrode to the second electrode. It can be obtained by forming the semiconductor layer by growing epitaxial crystals by a mist CVD method or a mist epitaxy method so that a current flows through the semiconductor layer, and manufacturing a semiconductor device.
  • the crystal substrate is not particularly limited as long as it does not interfere with the object of the present invention, and may be a known substrate. It may be an insulator substrate, a conductive substrate, or a semiconductor substrate. It may be a single crystal substrate or a polycrystalline substrate. Examples of the crystal substrate include a substrate containing a crystal having a corundum structure as a main component.
  • the "main component" refers to a composition ratio in the substrate containing 50% or more of the crystals, preferably 70% or more, and more preferably 90% or more.
  • the crystal substrate having the corundum structure for example, a sapphire substrate, and alpha-type gallium oxide substrate, Ga 2 O 3 and Al 2 O 3 and a Al 2 O 3 is at most and 60 wt% or less than 0 wt% alpha Examples include a type mixed crystal substrate.
  • the crystal substrate is preferably a sapphire substrate.
  • the sapphire substrate include a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, an r-plane sapphire substrate, and the like. It is preferable to use a Ga 2 O 3 substrate.
  • the sapphire substrate may have an off angle. The off angle is not particularly limited, and is, for example, 0.01 ° or more, preferably 0.2 ° or more, and more preferably 0.2 ° to 12 °.
  • the sapphire substrate preferably has a crystal growth plane of a-plane, m-plane or r-plane, and is also preferably a c-plane sapphire substrate having an off-angle of 0.2 ° or more.
  • the thickness of the crystal substrate is not particularly limited, but is usually 10 ⁇ m to 20 mm, more preferably 10 to 1000 ⁇ m.
  • the ELO mask is used to make the second side shorter than the first side in the semiconductor layer and set the linear thermal expansion coefficient in the first crystal axis direction to the second crystal axis direction.
  • the first side direction is parallel or substantially parallel to the first crystal axis direction
  • the second side direction is likely to be parallel or substantially parallel to the second crystal axis direction.
  • the direction of crystal growth and the like may be controlled.
  • Suitable shapes of the crystal substrate include, for example, a triangle, a quadrangle (for example, a rectangle or a trapezoid), a polygon such as a pentagon or a hexagon, a U-shape, an inverted U-shape, an L-shape or a U-shape, and the like. Can be mentioned.
  • another layer such as a buffer layer or a stress relaxation layer may be provided on the crystal substrate.
  • the buffer layer include a layer made of a metal oxide having the same crystal structure as the crystal structure of the crystal substrate or the semiconductor layer.
  • the stress relaxation layer include an ELO mask layer and the like.
  • the means for the epitaxial crystal growth is not particularly limited and may be a known means as long as the object of the present invention is not impaired.
  • Examples of the epitaxial crystal growth means include a CVD method, a MOCVD method, a MOVPE method, a mist CVD method, a mist epitaxy method, an MBE method, an HVPE method, a pulse growth method, and an ALD method.
  • the epitaxial crystal growth means is a mist CVD method or a mist epitaxy method.
  • mist CVD method a raw material solution containing a metal is atomized (atomization step), droplets are suspended, and the obtained atomized droplets are conveyed to the vicinity of the crystal substrate by a carrier gas. Then, the atomized droplets are thermally reacted (condensation step).
  • the raw material solution contains a metal as a film-forming raw material, and is not particularly limited as long as it can be atomized, and may contain an inorganic material or an organic material.
  • the metal may be a metal alone or a metal compound, and is not particularly limited as long as the object of the present invention is not impaired, but gallium (Ga), iridium (Ir), indium (In), rhodium (Rh).
  • the metal is at least the fourth period to the periodic table.
  • the metal preferably contains one or more metals of the sixth cycle, more preferably at least gallium, indium, rhodium or iridium. Further, in the present invention, it is also preferable that the metal contains gallium and indium or / and aluminum. By using such a preferable metal, the semiconductor layer that can be preferably used in a semiconductor device or the like can be formed into a film.
  • a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or a salt can be preferably used.
  • the form of the complex include an acetylacetonate complex, a carbonyl complex, an ammine complex, and a hydride complex.
  • the salt form include organic metal salts (for example, metal acetate, metal oxalate, metal citrate, etc.), metal sulfide salts, nitrified metal salts, phosphor oxide metal salts, and metal halide metal salts (for example, metal chloride). Salts, metal bromide salts, metal iodide salts, etc.) and the like.
  • the solvent of the raw material solution is not particularly limited as long as the object of the present invention is not impaired, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or an inorganic solvent and an organic solvent. May be a mixed solvent of. In the present invention, it is preferable that the solvent contains water.
  • an additive such as a hydrohalic acid or an oxidizing agent may be mixed with the raw material solution.
  • the hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid.
  • the oxidizing agent include hydrogen peroxide (H 2 O 2 ), sodium peroxide (Na 2 O 2 ), barium peroxide (BaO 2 ), benzoyl peroxide (C 6 H 5 CO) 2 O 2 and the like.
  • Examples include hydrogen peroxide, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.
  • the raw material solution may contain a dopant.
  • the dopant is not particularly limited as long as it does not interfere with the object of the present invention.
  • Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium and niobium, and p-type dopants.
  • the concentration of the dopant may usually be about 1 ⁇ 10 16 / cm 3 to 1 ⁇ 10 22 / cm 3 , and the concentration of the dopant should be as low as about 1 ⁇ 10 17 / cm 3 or less, for example. You may. Further, according to the present invention, the dopant may be contained in a high concentration of about 1 ⁇ 10 20 / cm 3 or more.
  • a raw material solution containing a metal is prepared, the raw material solution is atomized, droplets are suspended, and atomized droplets are generated.
  • the mixing ratio of the metal is not particularly limited, but is preferably 0.0001 mol / L to 20 mol / L with respect to the entire raw material solution.
  • the atomizing means is not particularly limited as long as the raw material solution can be atomized, and may be a known atomizing means, but in the present invention, the atomizing means using ultrasonic vibration is preferable.
  • the mist used in the present invention floats in the air, and is more likely to be a mist that floats in space and can be transported as a gas with an initial velocity of zero, rather than being sprayed like a spray.
  • the droplet size of the mist is not particularly limited and may be a droplet of about several mm, but is preferably 50 ⁇ m or less, and more preferably 1 to 10 ⁇ m.
  • the atomized droplets are transferred to the substrate by the carrier gas.
  • the type of carrier gas is not particularly limited as long as the object of the present invention is not impaired, and examples thereof include oxygen, ozone, an inert gas (for example, nitrogen and argon), and a reducing gas (hydrogen gas, forming gas, etc.). A suitable example is given.
  • the type of the carrier gas may be one type, but may be two or more types, and a diluted gas having a changed carrier gas concentration (for example, a 10-fold diluted gas) or the like is used as the second carrier gas. It may be used further.
  • the carrier gas may be supplied not only at one location but also at two or more locations.
  • the flow rate of the carrier gas is not particularly limited, but is preferably 1 LPM or less, and more preferably 0.1 to 1 LPM.
  • the atomized droplets are reacted to form a film on the crystal substrate.
  • the reaction is not particularly limited as long as it is a reaction in which a film is formed from the atomized droplets, but in the present invention, a thermal reaction is preferable.
  • the thermal reaction may be such that the atomized droplets react with heat, and the reaction conditions and the like are not particularly limited as long as the object of the present invention is not impaired.
  • the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent of the raw material solution, but the temperature is preferably not too high, more preferably 650 ° C or lower.
  • the thermal reaction may be carried out under any atmosphere of vacuum, non-oxygen atmosphere, reducing gas atmosphere and oxygen atmosphere as long as the object of the present invention is not impaired, and the thermal reaction may be carried out under atmospheric pressure or pressure. It may be carried out under either reduced pressure or reduced pressure, but in the present invention, it is easier to calculate the evaporation temperature and the equipment and the like can be simplified if it is performed under atmospheric pressure. preferable. Further, the film thickness can be set by adjusting the film formation time.
  • the film forming apparatus 19 preferably used in the present invention will be described with reference to the drawings.
  • the film forming apparatus 19 of FIG. 1 supplies a carrier gas source 22a for supplying a carrier gas, a flow control valve 23a for adjusting the flow rate of the carrier gas sent out from the carrier gas source 22a, and a carrier gas (diluted).
  • the raw material solution 24a is housed in the mist source 24.
  • the substrate 20 is installed on the hot plate 28, and the hot plate 28 is operated to raise the temperature in the film forming chamber 30.
  • the flow rate control valves 23 (23a, 23b) are opened to supply the carrier gas into the film forming chamber 30 from the carrier gas source 22 (22a, 22b), and the atmosphere of the film forming chamber 30 is sufficiently replaced with the carrier gas. After that, the flow rate of the carrier gas and the flow rate of the carrier gas (dilution) are adjusted respectively.
  • the ultrasonic vibrator 26 is vibrated and the vibration is propagated to the raw material solution 24a through the water 25a to atomize the raw material solution 24a and generate atomized droplets 24b.
  • the atomized droplets 24b are introduced into the film forming chamber 30 by a carrier gas and transported to the substrate 20, and the atomized droplets 24b thermally react in the film forming chamber 30 under atmospheric pressure to cause a thermal reaction on the substrate 20.
  • a film semiconductor layer
  • the mist CVD device 19 of FIG. 2 has a susceptor 21 on which the substrate 20 is placed, a carrier gas supply means 22a for supplying the carrier gas, and a flow rate adjustment for adjusting the flow rate of the carrier gas sent out from the carrier gas supply means 22a.
  • a supply pipe 27 composed of a mist generation source 24 in which 24a is housed, a container 25 in which water 25a is stored, an ultrasonic vibrator 26 attached to the bottom surface of the container 25, and a quartz tube having an inner diameter of 40 mm, and a supply tube 27. It is provided with a heater 28 installed in a peripheral portion of the above, and an exhaust port 29 for discharging mist, droplets and exhaust gas after a thermal reaction.
  • the susceptor 21 is made of quartz, and the surface on which the substrate 20 is placed is inclined from the horizontal plane. By making both the supply tube 27 and the susceptor 21 serving as the film forming chamber from quartz, it is possible to prevent impurities derived from the apparatus from being mixed into the film formed on the substrate 20.
  • the mist CVD apparatus 19 can be handled in the same manner as the film forming apparatus 19.
  • the semiconductor layer can be more easily formed on the crystal growth surface of the crystal substrate.
  • the semiconductor layer is usually formed by epitaxial crystal growth.
  • the semiconductor layer is useful for semiconductor devices, especially power devices.
  • Semiconductor devices formed using the semiconductor layer include transistors and TFTs such as MIS and HEMT, Schottky barrier diodes using semiconductor-metal junctions, JBS, PN or PIN diodes combined with other P layers, and receivers. Examples include a light emitting element.
  • the crystalline oxide semiconductor can be grown to form a semiconductor layer, and if desired, can be peeled off from the crystal substrate and used as a semiconductor layer (film) in a semiconductor device.
  • the semiconductor layer can also be used, for example, by arranging it on a substrate having higher thermal conductivity than the crystal substrate.
  • the semiconductor device is preferably used for a horizontal element (horizontal device) in which electrodes are formed on one side of the semiconductor layer.
  • Suitable examples of the semiconductor device include, for example, a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), and a metal oxide film.
  • Examples thereof include a semiconductor field effect transistor (MOSFET), an electrostatic induction transistor (SIT), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), and a light emitting diode (LED).
  • n + type semiconductor layer, n-semiconductor layer, etc. an n-type semiconductor layer
  • FIG. 6 shows an example in the case of a horizontal MOSFET.
  • the semiconductor device according to the embodiment of the present invention includes at least one semiconductor layer (for example, 131a), and a first electrode (for example, 135b) and a second electrode (for example, 135c) arranged on the first surface side of the semiconductor layer, respectively. ) And at least.
  • a current is configured to flow in a first direction from the first electrode to the second electrode.
  • the semiconductor layer has a corundum structure, and the c-axis direction of the semiconductor layer is the first direction.
  • the first surface of the semiconductor layer is the m-plane, and according to such a preferable aspect, the electrical characteristics of the semiconductor device can be made better.
  • the MOSFET of FIG. 6 includes an n-type semiconductor layer 131a, a first n + type semiconductor layer 131b, a second n + type semiconductor layer 131c, a gate insulating film 134, a gate electrode 135a, and a source electrode 135b. It includes a drain electrode 135c, a buffer layer 138 and a semi-insulator layer 139. Further, for example, as shown in FIG. 6, by embedding the n + type semiconductor layer in the n ⁇ type semiconductor layer, a current can flow more satisfactorily as compared with other horizontal MOSFETs.
  • the electrode material may be a known electrode material, and the electrode material includes, for example, Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn. , Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag or other metals or alloys thereof, tin oxide, zinc oxide, renium oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide. Examples thereof include metal oxide conductive films such as (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures and laminates thereof.
  • IZO metal oxide conductive films
  • organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures and laminates thereof.
  • the electrode can be formed by a known means such as a vacuum vapor deposition method or a sputtering method. More specifically, for example, when an electrode is formed by using two kinds of the first metal and the second metal among the metals, a layer made of the first metal and a layer made of the second metal are formed. It can be carried out by laminating and patterning the layer made of the first metal and the layer made of the second metal by using a photolithography technique.
  • FIG. 7 shows a part of a schematic top view for explaining a main part as one aspect of the semiconductor device of the present invention, but the number, shape, and arrangement of electrodes of the semiconductor device are appropriately determined. It is selectable.
  • FIG. 8 is a partial cross-sectional view for explaining a main part as one aspect of the semiconductor device of the present invention, and shows, for example, the AA cross section of FIG.
  • the semiconductor device 100 includes at least one semiconductor layer (for example, 2), and a first electrode (for example, 5b) and a second electrode (for example, 5b) arranged on the first surface side of the semiconductor layer 2, respectively. For example, it has at least 5c).
  • a current is configured to flow in a first direction from the first electrode to the second electrode.
  • the semiconductor layer has a corundum structure, and the c-axis direction of the semiconductor layer is the first direction.
  • the first surface of the semiconductor layer is the m-plane, and according to such a preferable aspect, the electrical characteristics of the semiconductor device can be made better. it can.
  • the semiconductor device 100 has an oxide semiconductor film 2 containing crystals containing at least gallium oxide.
  • the oxide semiconductor film 2 includes an inverted channel region 2a.
  • the crystal contains gallium oxide as a main component.
  • the crystal may be a mixed crystal.
  • the semiconductor device 100 has an oxide film 2b at a position in contact with the inverted channel region 2a.
  • FIG. 9 is a schematic cross-sectional view for explaining a specific example as one aspect of the semiconductor device of the present invention, and shows, for example, an example of a specific AA cross section of FIG.
  • the semiconductor device 200 includes at least one semiconductor layer (for example, 2), and a first electrode (for example, 5b) and a second electrode (for example, 5b) arranged on the first surface side of the semiconductor layer 2, respectively. For example, it has at least 5c).
  • a current is configured to flow in a first direction from the first electrode to the second electrode.
  • the semiconductor layer has a corundum structure, and the c-axis direction of the semiconductor layer is the first direction.
  • the first surface of the semiconductor layer is the m-plane, and according to such a preferable aspect, the electrical characteristics of the semiconductor device can be made better. it can.
  • the semiconductor device 200 has an oxide semiconductor film 2 containing crystals containing at least gallium oxide, and the oxide semiconductor film 2 includes an inverted channel region 2a.
  • the crystal has a corundum structure.
  • the semiconductor device 200 has a first semiconductor region 1a and a second semiconductor region 1b. In this embodiment, as shown in FIG. 9, the inverting channel region 2a is located between the first semiconductor region 1a and the second semiconductor region 1b in a plan view.
  • the inverting channel region of the oxide semiconductor film 2 is inverted, so that the first semiconductor region 1a and the second semiconductor region 1b are energized. Further, in the present embodiment, the first semiconductor region 1a and the second semiconductor region 1b are located in the oxide semiconductor film 2, and the upper surface of the first semiconductor region 1a and the second semiconductor region are located. It is arranged in the oxide semiconductor film 2 so that the upper surface of 1b and the upper surface of the inversion channel region 2a are flush with each other. In the first surface side 200a of the semiconductor device 200, the oxide semiconductor film 2 including the first semiconductor region 1a and the inverting channel region 2a and the second semiconductor region 1b form a flat surface.
  • the oxide semiconductor film 2 has an oxide film 2b provided in contact with the inverting channel region 2a2, the oxide containing the first semiconductor region 1a and the inverting channel region 2a. This is included when the semiconductor film 2 and the second semiconductor region 1b have a flat surface.
  • the first semiconductor region 1a and the second semiconductor region 1b may be embedded in the oxide semiconductor film 2 or may be arranged in the oxide semiconductor film 2 by ion implantation.
  • the oxide semiconductor film 2 in this embodiment is a p-type semiconductor film, and the first semiconductor region 1a and the second semiconductor region 1b are n-type.
  • the oxide semiconductor film 2 may contain a p-type dopant.
  • the semiconductor device 200 may have an oxide film 2b arranged on the inverting channel region 2a.
  • the oxide film 2b has a crystal structure belonging to the trigonal system to which the corundum structure belongs.
  • the oxide film 2b contains at least one of the elements of Group 15 of the periodic table, and preferably contains phosphorus.
  • the oxide film 2b may further contain at least one of the elements of Group 13 of the Periodic Table, and the conductor device 200 is electrically connected to the first semiconductor region 1a. It has a first electrode 5b and a second electrode 5c that is electrically connected to the second semiconductor region 1b.
  • the semiconductor device 200 has a third electrode 5a between the first electrode 5b and the second electrode 5c, which is separated from the inversion channel region 2a by the insulating film 4a. Further, as shown in the drawing, the first electrode 5b, the second electrode 5c, and the third electrode 5a are arranged on the first surface side 200a of the semiconductor device 200. Specifically, the semiconductor device 200 has an insulating film 4a arranged on the oxide film 2b on the inversion channel region 2a, and the third electrode 5a is arranged on the insulating film 4a. Further, in the semiconductor device 200, the first electrode 5b and the first semiconductor region 1a are electrically connected, but are partially located between the first electrode 5b and the first semiconductor region 1a.
  • the semiconductor device 200 may have another layer on the second surface side 200b of the semiconductor device 200, that is, on the lower surface side of the oxide semiconductor film 2, and has a substrate 9 as shown in FIG. You may be doing it.
  • the first semiconductor region 1a has a portion that overlaps with the first electrode 5b and a portion that overlaps with the third electrode 5a in a plan view. There is.
  • the second semiconductor region 1b has a portion that overlaps with the second electrode 5c and a portion that overlaps with the third electrode 5a in a plan view.
  • the inverted channel region 2a of the oxide semiconductor film 2 is inverted from p-type to n-type and n.
  • a mold channel layer is formed, the first semiconductor region 1a and the second semiconductor region 1b are conducted, and electrons flow from the source electrode to the drain electrode. Further, by setting the voltage of the third electrode 5b to zero, a channel layer cannot be formed in 2a in the inverted channel region, resulting in turn-off.
  • the first electrode 5b may be a source electrode
  • the second electrode 5c may be a drain electrode
  • the third electrode 5a may be a gate electrode
  • the insulating film 4a is a gate insulating film
  • the insulating film 4b is a field insulating film.
  • An oxide semiconductor film containing a crystal containing gallium oxide and / or an oxide semiconductor film containing a crystal having a corundum structure can be obtained by forming a film using a method of epitaxial crystal growth.
  • the method for growing epitaxial crystals is not particularly limited and may be a known means as long as the object of the present invention is not impaired.
  • Examples of the epitaxial crystal growth method include a CVD method, a MOCVD (Metalorganic Chemical Vapor) method, a MOVPE (Metalorganic Vapor-phase epitaxy) method, a mist CVD method, a mist epitaxy method, and an MBE (Molecular Beam) method.
  • Examples include the HVPE (Hydride Vapor Phase Epitaxy) method and the pulse growth method.
  • HVPE HydroVPE
  • the mist CVD method or the mist epitaxy method it is preferable to use the mist CVD method or the mist epitaxy method.
  • the materials of the first electrode 165a and the second electrode 165b include, for example, Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Metals such as Hf, W, Ir, Zn, In, Pd, Nd or Ag or alloys thereof, tin oxide, zinc oxide, renium oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO) and the like. Examples thereof include metal oxide conductive films, organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof.
  • the film forming method of the electrode is not particularly limited, and is a wet method such as a printing method, a spray method, and a coating method, a physical method such as a vacuum vapor deposition method, a sputtering method, and an ion plating method, CVD, and plasma CVD. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from chemical methods such as a method.
  • the semiconductor device of the present invention is suitably used as a power module, an inverter or a converter by using a known method, and further preferably used for a semiconductor system using a power supply device, for example. ..
  • the power supply device can be manufactured from the semiconductor device or as the semiconductor device by connecting to a wiring pattern or the like by a conventional method.
  • the power supply system 170 is configured by using the plurality of power supply devices 171 and 172 and the control circuit 173.
  • the power supply system can be used in the system apparatus 180 by combining the electronic circuit 181 and the power supply system 182.
  • An example of the power supply circuit diagram of the power supply device is shown in FIG. FIG.
  • FIG. 5 shows a power supply circuit of a power supply device including a power circuit and a control circuit.
  • the DC voltage is switched at a high frequency by an inverter 192 (composed of MOSFETs A to D), converted to AC, and then insulated and transformed by a transformer 193.
  • an inverter 192 composed of MOSFETs A to D
  • DCL195 smoothing coils L1 and L2
  • a capacitor smoothing coils L1 and L2
  • a DC voltage is output.
  • the voltage comparator 197 compares the output voltage with the reference voltage
  • the PWM control circuit 196 controls the inverter 192 and the rectifier MOSFET 194 so as to obtain a desired output voltage.
  • the semiconductor device is preferably a power card, includes a cooler and an insulating member, and the coolers are provided on both sides of the semiconductor layer via at least the insulating member. It is more preferable that heat radiating layers are provided on both sides of the semiconductor layer, and that the cooler is provided on the outside of the heat radiating layer at least via the insulating member.
  • FIG. 10 shows a power card which is one of the preferred embodiments of the present invention. The power card of FIG.
  • a double-sided cooling type power card 201 which includes a refrigerant tube 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin portion 209, a semiconductor chip 301a, and a metal heat transfer plate (protruding terminal). Section) 302b, a heat sink and an electrode 303, a metal heat transfer plate (protruding terminal section) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308.
  • the cross section in the thickness direction of the refrigerant tube 202 has a large number of flow paths 222 partitioned by a large number of partition walls 221 extending in the flow path direction at predetermined intervals from each other. According to such a suitable power card, higher heat dissipation can be realized and higher reliability can be satisfied.
  • the semiconductor chip 301a is joined by a solder layer 104 on the inner main surface of the metal heat transfer plate 302b, and the metal heat transfer plate (protruding terminal portion) 302b is formed by the solder layer 304 on the remaining main surface of the semiconductor chip 301a. It is joined so that the anode electrode surface and the cathode electrode surface of the flywheel diode are connected to the collector electrode surface and the emitter electrode surface of the IGBT in so-called antiparallel.
  • Examples of the materials of the metal heat transfer plates (protruding terminal portions) 302b and 303b include Mo and W.
  • the metal heating plates (protruding terminal portions) 302 and 303b have a thickness difference that absorbs the difference in thickness of the semiconductor chips 101a and 101b, whereby the outer surface of the metal heat transfer plate 102 is flat.
  • the resin sealing portion 209 is made of, for example, an epoxy resin, and is molded by covering the side surfaces of the metal heat transfer plates 302b and 303b, and the semiconductor chip 301a is molded by the resin sealing portion 209. However, the outer main surface, that is, the contact heat receiving surface of the metal heat transfer plates 302b and 303b is completely exposed.
  • the metal heat transfer plates (protruding terminal portions) 302b and 303b project to the right in FIG. 10 from the resin sealing portion 209, and the control electrode terminal 305, which is a so-called lead frame terminal, is, for example, a semiconductor chip 301a on which an IGBT is formed.
  • the gate (control) electrode surface and the control electrode terminal 305 are connected.
  • the insulating plate 208 which is an insulating spacer, is made of, for example, an aluminum nitride film, but may be another insulating film.
  • the insulating plate 208 completely covers and adheres to the metal heat transfer plates 302b and 303b, but the insulating plate 208 and the metal heat transfer plates 302b and 303b may simply come into contact with each other or have good heat such as silicon grease. Heat transfer materials may be applied or they may be joined in various ways. Further, the insulating layer may be formed by ceramic spraying or the like, the insulating plate 208 may be bonded on the metal heat transfer plate, or may be bonded or formed on the refrigerant tube.
  • the refrigerant tube 202 is manufactured by cutting an aluminum alloy into a plate material formed by a pultrusion molding method or an extrusion molding method to a required length.
  • the cross section in the thickness direction of the refrigerant tube 202 has a large number of flow paths 222 partitioned by a large number of partition walls 221 extending in the flow path direction at predetermined intervals from each other.
  • the spacer 203 may be, for example, a soft metal plate such as a solder alloy, or may be a film (film) formed by coating or the like on the contact surfaces of the metal heat transfer plates 302b and 303b.
  • the surface of the soft spacer 3 is easily deformed to adapt to the minute irregularities and warpage of the insulating plate 208 and the minute irregularities and warpage of the refrigerant tube 202 to reduce the thermal resistance.
  • a known good thermal conductive grease or the like may be applied to the surface of the spacer 203 or the like, or the spacer 203 may be omitted.
  • the semiconductor device of the present invention can be used in all fields such as semiconductors (for example, compound semiconductor electronic devices, etc.), electronic parts / electrical equipment parts, optical / electrophotographic related devices, industrial parts, etc., but is particularly useful for power devices and the like. Is.

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Abstract

L'invention concerne un dispositif à semi-conducteur présentant d'excellentes caractéristiques semi-conductrices, en particulier des caractéristiques électriques. L'invention concerne un dispositif à semi-conducteur qui comporte au moins : une couche semi-conductrice ; et une première électrode et une seconde électrode disposées chacune sur un premier côté de surface de la couche semi-conductrice, le dispositif à semi-conducteur étant configuré de telle sorte que, dans la couche semi-conductrice, un courant circule dans une première direction allant de la première électrode vers la seconde électrode, la couche semi-conductrice ayant une structure de corindon, et la direction d'un axe c de la couche semi-conductrice étant la première direction.
PCT/JP2021/000575 2020-01-10 2021-01-08 Dispositif à semi-conducteur WO2021141126A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016035696A1 (fr) * 2014-09-02 2016-03-10 株式会社Flosfia Structure stratifiée, procédé de fabrication de celle-ci, dispositif à semi-conducteur, et film cristallin
JP2016098166A (ja) * 2014-11-26 2016-05-30 株式会社Flosfia 結晶成長用基板、結晶性積層構造体およびそれらの製造方法ならびにエピタキシャル成長方法
JP2018082144A (ja) * 2016-08-31 2018-05-24 株式会社Flosfia 結晶性酸化物半導体膜および半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016035696A1 (fr) * 2014-09-02 2016-03-10 株式会社Flosfia Structure stratifiée, procédé de fabrication de celle-ci, dispositif à semi-conducteur, et film cristallin
JP2016098166A (ja) * 2014-11-26 2016-05-30 株式会社Flosfia 結晶成長用基板、結晶性積層構造体およびそれらの製造方法ならびにエピタキシャル成長方法
JP2018082144A (ja) * 2016-08-31 2018-05-24 株式会社Flosfia 結晶性酸化物半導体膜および半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MORIYA, RYO ET AL.: "Anisotropy of electric characteristics in a-Ga203", LECTURE PREPRINTS OF THE 67TH JSAP SPRING MEETING 2020, 28 February 2020 (2020-02-28) *

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