WO2021139296A1 - Structure d'encapsulation et procédé d'encapsulation - Google Patents

Structure d'encapsulation et procédé d'encapsulation Download PDF

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Publication number
WO2021139296A1
WO2021139296A1 PCT/CN2020/120863 CN2020120863W WO2021139296A1 WO 2021139296 A1 WO2021139296 A1 WO 2021139296A1 CN 2020120863 W CN2020120863 W CN 2020120863W WO 2021139296 A1 WO2021139296 A1 WO 2021139296A1
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WO
WIPO (PCT)
Prior art keywords
chip unit
layer
light
shielding layer
chip
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Application number
PCT/CN2020/120863
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English (en)
Chinese (zh)
Inventor
杜鹏
钱孝青
张�廷
汤杰夫
喻琼
Original Assignee
苏州晶方半导体科技股份有限公司
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Publication of WO2021139296A1 publication Critical patent/WO2021139296A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements

Definitions

  • the invention belongs to the field of semiconductor technology, and specifically relates to a packaging structure and a packaging method.
  • Wafer Level Chip Size Packaging technology is a technology in which the entire wafer is packaged and tested and then cut to obtain a single finished chip. The packaged chip size is the same as that of the bare chip. Wafer-level chip packaging technology has overturned the traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless ChipCarrier) and organic leadless chip carrier (Organic Leadless ChipCarrier), and conforms to the market's increasingly lighter, smaller and shorter microelectronic products. , Thinning and low price requirements. Chips packaged by wafer-level chip packaging technology have reached a high degree of miniaturization, and the cost of the chip has been significantly reduced with the reduction of the chip and the increase of the wafer size. Wafer-level chip packaging technology is a technology that can integrate IC design, wafer manufacturing, packaging and testing, and is a hot spot and development trend in the current packaging field.
  • the image sensor chip as a chip that can convert optical images into electronic signals, has a sensing area.
  • Si has good light transmission ability in the 1000-7000nm infrared band and far-infrared band. Near-infrared light (750-1400nm), short-wavelength infrared light (1400-3000nm) and mid-wavelength infrared light (3000-8000nm) can be transmitted. Over the Si layer. Therefore, under a specific light source, the infrared light on the back of the chip will interfere with the front sensing area by the transparent Si layer, causing distortion.
  • An embodiment of the present invention provides a package structure to solve the problem that infrared light will interfere with the front sensing area by the transparent Si layer in the prior art, including:
  • a packaging structure including:
  • a chip unit, the first surface of the chip unit includes a sensing area
  • the light-shielding layer at least partially covers the non-first surface of the chip unit.
  • the light shielding layer covers the second surface of the chip unit opposite to the first surface.
  • the light-shielding layer covers part or all of the side surfaces of the chip unit.
  • the material of the light shielding layer is metal or black organic matter.
  • the metal is aluminum
  • the black organic substance is vinyl
  • the packaging structure further includes:
  • An upper cover plate the upper cover plate covering the first surface of the chip unit
  • the supporting structure is located between the upper cover plate and the chip unit, and the sensing area is located in a cavity enclosed by the supporting structure and the first surface of the chip unit.
  • the chip unit further includes:
  • a through hole of the chip unit penetrates from a second surface of the chip unit opposite to the first surface, and the through hole exposes the solder pad;
  • An insulating layer covering the second surface of the chip unit and the surface of the sidewall of the through hole;
  • a metal layer located on the surface of the insulating layer and electrically connected to the solder pad;
  • a solder resist layer located on the surface of the metal layer and the insulating layer, the solder resist layer having openings exposing part of the metal layer;
  • a window exposing the external protrusion is opened on the light shielding layer.
  • An embodiment of the present invention also provides a packaging method of a packaging structure, including:
  • the wafer is divided by a dicing process to form a packaging structure of multiple chip units.
  • a light shielding layer is formed on part or all of the side surfaces of the chip unit.
  • a metal light-shielding layer is sputtered on the second surface of the chip unit.
  • spin coating, spray coating or pasting is used to form a light-shielding layer of black photosensitive organic material on the second surface of the chip unit.
  • the present invention adds a black organic matter or a metal light-shielding layer on the back of the chip to prevent infrared light from interfering with the front sensing area by the transparent Si layer.
  • FIG. 1 is a cross-sectional view of the package structure in Embodiment 1 of the present application.
  • FIGS. 2 to 8 are schematic diagrams of intermediate structures formed by the packaging structure in Embodiment 1 of the present application;
  • Embodiment 3 is a cross-sectional view of the package structure in Embodiment 2 of the present application.
  • the packaging structure includes a chip unit 210, an upper cover plate 330 and a light shielding layer 500.
  • the chip unit 210 has a first surface 210 a and a second surface 210 b opposite to the first surface 210 a, and the first surface 210 a includes a sensing area 211.
  • the chip unit 210 further includes a bonding pad 212, a through hole (not labeled), an insulating layer 213, a metal layer 214, a solder resist layer 215, and an external bump 216.
  • the bonding pad 212 is located outside the sensing area 211; the through hole penetrates through the second surface of the chip unit opposite to the first surface, and the through hole exposes the bonding pad 212; the insulating layer 213 covers the chip unit The second surface and the sidewall surface of the through hole; the metal layer 214 is located on the surface of the insulating layer and is electrically connected to the solder pad 212; the solder resist layer 215 is located on the surface of the metal layer and the insulating layer, and the resist The solder layer has openings exposing part of the metal layer; the outer bumps 216 fill the openings and are exposed outside the surface of the solder resist layer.
  • the upper cover plate 330 includes a first surface 330a and a second surface 330b opposite to the first surface 330a.
  • the first surface 330a has a support structure 320, and the upper cover plate 330 covers the first surface 210a of the chip unit 210.
  • the support structure 320 is located Between the upper cover 330 and the chip unit 210, and the sensing area 211 is located in the cavity enclosed by the support structure 320 and the first surface 210a of the chip unit 210.
  • the light-shielding layer 500 covers the second surface 210b of the chip unit 210, and the light-shielding layer 500 is provided with a window 510 for exposing the external bumps 216.
  • the material of the light-shielding layer 500 is a black photosensitive organic material or a metal that has undergone a blackening treatment, which has the characteristics of opacity or low light transmission.
  • the light-shielding layer 500 may be vinyl; the light-shielding layer 500 may also be blackened aluminum, so that the light cannot be specularly reflected on its surface, and the light-shielding performance is good.
  • the second surface 210b of the chip unit 210 is covered by the light-shielding layer 500. Since the light-shielding layer 500 does not transmit light, the infrared light I1 will not pass through the Si material through the second surface 210b. , It will not interfere with the sensing area 211.
  • FIGS. 2 to 9 are schematic diagrams of intermediate structures formed during the packaging process of the packaging method according to the embodiment of the present invention.
  • FIGS. 2 and 3 a wafer 200 to be packaged is provided, wherein FIG. 2 is a schematic top view of the structure of the wafer 200 to be packaged, and FIG. 3 is a cross-sectional view along A-A1 in FIG. 4.
  • the wafer 200 to be packaged has a first surface 200 a and a second surface 200 b opposite to the first surface 200 a.
  • the first surface 200 a of the wafer 200 to be packaged has a plurality of chip units 210 and a scribe lane area 220 located between the chip units 210.
  • the multiple chip units 210 on the wafer 200 to be packaged are arranged in an array, the dicing lane area 220 is located between adjacent chip units 210, and the wafer 200 to be packaged is subsequently diced along the dicing lane area 220.
  • a plurality of chip package structures including the chip unit 210 may be formed.
  • the chip unit 210 is an image sensor chip unit, and the chip unit 210 has a sensing area 211 and a bonding pad 212 located outside the sensing area 211.
  • the sensing area 211 is an optical sensing area. For example, it may be formed by a plurality of photodiode arrays. The photodiodes can convert the optical signal irradiated to the sensing area 211 into electrical signals.
  • the bonding pad 212 serves as an input and output terminal for connecting the device in the sensing area 211 with an external circuit.
  • the chip unit 210 is formed on a silicon substrate, and the chip unit 210 may also include other functional devices formed in the silicon substrate.
  • a cover substrate 300 is provided.
  • the cover substrate 300 includes a first surface 300a and a second surface 300b opposite to the first surface 300a.
  • a plurality of support structures 320 are formed on the first surface 300a of the cover substrate 300.
  • the groove structure enclosed by the supporting structure 320 and the first surface 300a of the cover substrate 300 corresponds to the sensing area 211 on the wafer 200 to be packaged.
  • the capping substrate 300 covers the first surface 200 a of the wafer 200 to be packaged in a subsequent process, and is used to protect the sensing area 211 on the wafer 200 to be packaged. Since light is required to pass through the cover substrate 300 to reach the sensing area 211, the cover substrate 300 has high light transmittance and is a light transmitting material. The two surfaces 300a and 300b of the cover substrate 300 are flat and smooth, and will not scatter or diffuse the incident light.
  • the material of the cover substrate 300 may be inorganic glass, organic glass, or other light-transmitting materials with specific strength.
  • the thickness of the cover substrate 300 is 300 ⁇ m to 500 ⁇ m, for example, it may be 400 ⁇ m. If the thickness of the cover substrate 300 is too large, the thickness of the final chip package structure will be too large, which cannot meet the needs of thin and light electronic products; if the thickness of the cover substrate 300 is too small, it will cause the cover substrate 300 to be thinner and lighter. The strength is small, it is easy to damage, and it can't provide enough protection for the sensing area covered in the follow-up.
  • the support structure 320 is formed by depositing a support structure material layer on the first surface 300 a of the capping substrate 300 and then etching. Specifically, a supporting structure material layer (not shown) covering the first surface 300a of the capping substrate 300 is formed first, and then the supporting structure material layer is patterned, and after removing part of the supporting structure material layer, the supporting structure 320 is formed.
  • the position of the groove structure enclosed by the supporting structure 320 and the first surface 300a of the capping substrate 300 on the capping substrate 300 corresponds to the position of the sensing area 211 on the wafer 200 to be packaged, so that after the subsequent bonding process
  • the sensing area 211 may be located in a groove enclosed by the support structure 320 and the first surface 300a of the cover substrate 300.
  • the material of the support structure material layer is wet film or dry film photoresist, which is formed by spraying, spin coating, or pasting processes, and the support structure material layer is exposed and developed for patterning to form the support structure 320.
  • the support structure material layer may also be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc., formed by a deposition process, and subsequently patterned to form the support structure 320 using photolithography and etching processes.
  • an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the support structure 320 may also be formed by etching the cover substrate 300. Specifically, a patterned photoresist layer may be formed on the capping substrate 300, and then the capping substrate 300 may be etched using the patterned photoresist layer as a mask, and the supporting structure 320 may be formed in the capping substrate 300.
  • the supporting structure 320 is the convex part on the first surface 300 a of the cover substrate 300.
  • the first surface 300a of the capping substrate 300 and the first surface 200a of the wafer 200 to be packaged are opposed and combined, so that the support structure 320 and the first surface 200a of the wafer 200 to be packaged form a cavity (Not labeled), the sensing area 211 is located in the cavity.
  • the cover substrate 300 and the wafer 200 to be packaged are combined by an adhesive layer (not shown).
  • an adhesive layer may be formed on the top surface of the supporting structure 320 on the first surface 300a of the cover substrate 300 and/or on the first surface 200a of the wafer 200 to be packaged by spraying, spin coating or pasting. Then, the first surface 300a of the cover substrate 300 and the first surface 200a of the wafer 200 to be packaged are pressed against each other, and are combined by an adhesive layer.
  • the adhesive layer can not only achieve the bonding effect, but also play the role of insulation and sealing.
  • the adhesive layer may be a polymer adhesive material, such as polymer materials such as silica gel, epoxy resin, and benzocyclobutene.
  • the support structure 320 and the first surface 200a of the wafer 200 to be packaged form a cavity.
  • the position of the cavity corresponds to the position of the sensing region 211, and the area of the cavity is slightly larger than the area of the sensing region 211, so that the sensing region 211 is located in the cavity.
  • the bonding pads 212 on the wafer 200 to be packaged are covered by the support structure 320 on the cover substrate 300.
  • the capping substrate 300 can protect the wafer 200 to be packaged in the subsequent process.
  • the wafer to be packaged 200 is packaged.
  • the wafer to be packaged 200 is thinned from the second surface 200b of the wafer to be packaged 200 to facilitate subsequent through hole etching.
  • the thinning of the wafer to be packaged 200 can be made by mechanical polishing or chemical mechanical polishing. Process, etc.;
  • the wafer 200 to be packaged is etched from the second surface 200b of the wafer 200 to be packaged to form a through hole (not labeled), and the through hole exposes the solder on the first surface 200a of the wafer to be packaged 200 Pad 212;
  • an insulating layer 213 is formed on the second surface 200b of the wafer 200 to be packaged and on the sidewall of the through hole.
  • the insulating layer 213 exposes the solder pad 212 at the bottom of the through hole.
  • the insulating layer 213 may be the wafer to be packaged.
  • the second surface 200b of the circle 200 provides electrical insulation, and can also provide electrical insulation for the substrate of the wafer 200 to be packaged exposed by the through holes.
  • the material of the insulating layer 213 can be silicon oxide, silicon nitride, silicon oxynitride or insulating. Resin; Next, a metal layer 214 connected to the bonding pad 212 is formed on the surface of the insulating layer 213.
  • the metal layer 214 can be used as a rewiring layer to guide the bonding pad 212 to the second surface 200b of the wafer 200 to be packaged, and then connect to the external circuit Connect, the metal layer 214 is formed after the metal film is deposited and etched; then, a solder resist layer 215 with openings (not labeled) is formed on the surface of the metal layer 214 and the surface of the insulating layer 213, and the openings expose part
  • the material of the solder resist layer 215 is an insulating dielectric material such as silicon oxide, silicon nitride, etc., which is used to protect the metal layer 214; then, an outer bump 216 is formed on the surface of the solder resist layer 215, and the outer bump
  • the opening 216 is filled with the opening, and the external bump 216 may be a connection structure such as a solder ball or a metal pillar, and the material may be a metal material such as copper, aluminum, gold, tin, or lead.
  • a light shielding layer 500 is formed on the second surface 210 b of the chip unit 210, and the light shielding layer 500 is provided with a window 510 for exposing the external protrusion 216.
  • the light shielding layer 500 may partially cover the second surface 210b of the chip unit 210, as long as it can prevent the backside light I1 of the chip unit from passing through the Si material into the photosensitive area.
  • the light-shielding material layer 500 is an opaque or low-transmissive black organic material, such as vinyl.
  • the black organic material is a photosensitive material, which can be patterned through a photolithography process.
  • the method of forming the light-shielding material layer 500 includes: forming a black photosensitive organic material layer on the second surface 210b of the chip unit 210 by spin coating, spraying or pasting; according to the positive and negative development characteristics of the black photosensitive organic material, Expose the area of the black photosensitive organic material layer where the window 510 is to be formed, or expose the area outside the window 510 to be formed, and after developing, form a plurality of windows corresponding to the outer bumps 216 in the black photosensitive organic material layer 510; Finally, the black photosensitive organic material layer is baked and hardened to enhance the mechanical strength of the black photosensitive organic material layer and its adhesion to the chip unit 210.
  • the thickness of the black photosensitive organic material is 10 ⁇ m-50 ⁇ m
  • the light-shielding material layer 500 is formed of vinyl, since the vinyl is an organic material, it is difficult to be completely opaque. By appropriately increasing the thickness of the vinyl material layer, a better shading effect can be achieved. However, the greater the thickness of the vinyl material layer, the more difficult it is for light to penetrate the vinyl material layer to the bottom during the exposure process, that is, vinyl material. The bottom of the material layer cannot be fully exposed, which increases the difficulty of development and affects the resolution of the formed pattern. In addition, as an organic matter, the vinyl material is easy to produce particles during the exposure and development process, which will pollute the chip and cause light transmittance. Bad.
  • the light-shielding material layer 500 may also be metal, and the metal may be blackened, so that the light cannot be specularly reflected on the surface.
  • the metal can be aluminum, aluminum alloy or other suitable metal materials.
  • the method for forming the light-shielding material layer 500 includes: forming a metal material layer on the second surface 210b of the chip unit 210 through a sputtering process.
  • the metal material layer is an aluminum material layer; The syrup blackens the metal material layer.
  • the aluminum material layer can be treated with a sulfur-containing alkaline solution to form a black sulfide film layer on the aluminum material layer to improve the shading effect of the aluminum material layer;
  • a patterned photoresist layer is formed on the blackened metal material layer, the patterned photoresist layer exposes the area where the window 510 is to be formed, and the patterned photoresist layer is used as a mask to mask the blackened metal
  • the material layer is etched until it reaches the surface of the chip unit 210, and the patterned photoresist layer is removed to form a light-shielding material layer 500 with a plurality of windows 510.
  • the blackened metal material not only has a good shading effect, but also has a thinner thickness, which is conducive to the lightness and thinness of the final package structure.
  • the thickness of the blackened metal material layer is 1 ⁇ m-10 ⁇ m, preferably, it may be 5 ⁇ m, 6 ⁇ m, or the like.
  • forming the light-shielding material layer 500 on the second surface 210b of the chip unit 210 can also be performed before the capping substrate 300 is combined with the wafer 200 to be packaged, or in the subsequent first cutting. After the process, the present invention does not limit this, and can be selected according to specific process conditions.
  • the chip package structure obtained by subsequent cutting can be connected to an external circuit through the external bumps 216.
  • the sensing area 211 of the chip unit converts the optical signal into an electrical signal
  • the electrical signal can be transmitted to an external circuit for processing through the bonding pad 212, the metal layer 214, and the external bump 216 in sequence.
  • the wafer to be packaged 200, the cover substrate 300 and the light-shielding material layer 500 are cut along the dicing area 220 of the wafer to be packaged 200 to form a plurality of package structures as shown in FIG. 1.
  • the cutting can be cut with a slicing knife or laser cutting, and the slicing knife can be cut with a metal knife or a resin knife.
  • the light-shielding material layer 500 not only includes the light-shielding layer 520 formed on the second surface 200b of the wafer 200 to be packaged, but also includes the light-shielding layer 520 formed on the side surface 200c of the wafer 200 to be packaged.
  • the light-shielding layer 530 is not only includes the light-shielding layer 520 formed on the second surface 200b of the wafer 200 to be packaged, but also includes the light-shielding layer 520 formed on the side surface 200c of the wafer 200 to be packaged.
  • the light shielding layer 530 on the side 200c of the wafer 200 to be packaged is fabricated after the wafer is cut.
  • the light-shielding layer 520 on the second surface 200b of the wafer 200 to be packaged may be manufactured simultaneously with the light-shielding layer 530 after the wafer is cut, or it may be pre-made before the wafer is cut.
  • the material selection and manufacturing process of the light-shielding layer in this embodiment are the same as those in Embodiment 1, and will not be repeated.
  • composition taught by the present invention is also basically The above is composed of or composed of the described components, and the process taught by the present invention is basically composed of the described process steps or a set of described process steps.
  • a single component may be replaced by multiple components and multiple components may be replaced by a single component to provide an element or structure or perform one or several given functions. This substitution is considered to be within the scope of the present invention except where it is substituted here that will not operate to practice the specific embodiments of the present invention.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

L'invention concerne une structure d'encapsulation et un procédé d'encapsulation. La structure d'encapsulation comprend : une unité de puce, une première surface de l'unité de puce comprenant une région d'induction ; et une couche de protection contre la lumière, la couche de protection contre la lumière recouvrant au moins partiellement une surface autre que la première surface de l'unité de puce. Selon la présente invention, l'ajout de la couche de protection contre la lumière, qui est constituée d'une substance organique noire ou d'un métal, sur la face arrière d'une puce, permet d'empêcher que de la lumière infrarouge soit transmise à travers une couche de Si et perturbe la région d'induction sur la face avant de la puce.
PCT/CN2020/120863 2020-01-09 2020-10-14 Structure d'encapsulation et procédé d'encapsulation WO2021139296A1 (fr)

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CN202010021547.5A CN111370434A (zh) 2020-01-09 2020-01-09 封装结构和封装方法
CN202010021547.5 2020-01-09

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WO2021139296A1 true WO2021139296A1 (fr) 2021-07-15

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Publication number Priority date Publication date Assignee Title
CN111370434A (zh) * 2020-01-09 2020-07-03 苏州晶方半导体科技股份有限公司 封装结构和封装方法
CN115602674A (zh) * 2022-09-21 2023-01-13 华天科技（昆山）电子有限公司（Cn） 一种图像传感器集成天线封装结构及封装方法

Citations (4)

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Publication number Priority date Publication date Assignee Title
CN105070734A (zh) * 2015-09-02 2015-11-18 苏州晶方半导体科技股份有限公司 封装结构及封装方法
CN110197835A (zh) * 2019-07-05 2019-09-03 中国电子科技集团公司第五十八研究所 一种光电器件封装方法及封装结构
CN209822643U (zh) * 2019-07-05 2019-12-20 中国电子科技集团公司第五十八研究所 一种光电器件封装结构
CN111370434A (zh) * 2020-01-09 2020-07-03 苏州晶方半导体科技股份有限公司 封装结构和封装方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105070734A (zh) * 2015-09-02 2015-11-18 苏州晶方半导体科技股份有限公司 封装结构及封装方法
CN110197835A (zh) * 2019-07-05 2019-09-03 中国电子科技集团公司第五十八研究所 一种光电器件封装方法及封装结构
CN209822643U (zh) * 2019-07-05 2019-12-20 中国电子科技集团公司第五十八研究所 一种光电器件封装结构
CN111370434A (zh) * 2020-01-09 2020-07-03 苏州晶方半导体科技股份有限公司 封装结构和封装方法

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