WO2021137693A1

WO2021137693A1 - Integrated rc oscillator for generating an oscillation signal with a trimming signal

Info

Publication number: WO2021137693A1
Application number: PCT/MY2020/050160
Authority: WO
Inventors: Hanif CHE LAH; Chieu Yin alias Chee Chieu Yin CHIA; Rohana Musa
Original assignee: Mimos Berhad
Priority date: 2019-12-31
Filing date: 2020-11-19
Publication date: 2021-07-08

Abstract

The present invention discloses a resistor-capacitor oscillator, comprising a current bias circuit (12) with trimming resistors, a timing controller (13), a comparator (14), and a phase divider (16). The current bias circuit (12) has trimming resistors that corresponds to the trimming signal to bias the trimming signal to a first reference current and a second reference current. The timing controller (13) has a timing resistor (R0), a first capacitor part (26) and a second capacitor part (27). The timing controller (13) generates a first reference voltage (V1) and a second reference voltage (V2). The comparator (14) compares the first reference voltage (V1) to the second reference voltage (V2) to produce an oscillation signal. The phase divider (16) uses the oscillation signal as a first phase signal (phi) and produces an inverted oscillation signal as a second phase signal (phiB). The first phase signal (phi) and second phase signal (phiB) is used to provide feedback to the timing controller (13).

Description

INTEGRATED RC OSCILLATOR FOR GENERATING AN OSCILLATION SIGNAL WITH A TRIMMING SIGNAL

The present invention relates to RC oscillator circuits, more particularly to trimmable RC oscillator circuits with compensation for temperature and process variations.

A conventional oscillator uses a crystal to provide frequency reference. Generally, time is needed for conventional oscillator to amplify noises generated internally to an operational level. The generated frequency output from the oscillator is used as a clock signal for circuits in general. The demand for more efficient and smaller system leads to a new oscillator system that can be used without a crystal.

RC oscillator circuit which uses a resistor and capacitor provides resonance frequency with reasonable accuracy. It uses a combination of an amplifier and an RC network to produce oscillations due to the phase shift between the stages. RC oscillator is inexpensive, consumes low power, and has fast start up time.

A typical RC oscillator has a resistor part, a capacitor part, a bias circuit, a ramp and hold circuit, a comparator, a divider, an oscillator part. The bias circuit generates a reference voltage and a ramp current inversely proportional to the resistance of the resistor part. The ramp and hold circuit charges the capacitor part using the ramp current. The oscillation frequency is determined by the resistance of the resistor part and capacitance value of the capacitor part.

The resistor part and capacitor part implemented in a CMOS semiconductor process have variation in their resistance value and capacitance value according to temperature changes and process corners. The fluctuation of frequency output will vary with temperature. The frequency variations are a result of the temperature coefficients of the resistive and capacitive elements.

US patent no. 5,963,105 described a crystal-less RC oscillator that provides a circuitry for compensation of temperature coefficient of resistive elements. A bandgap reference having a stable temperature coefficient is used. A resistive network includes two trimmable resistors such that the resistive network in combination with the bandgap reference compensates for the absolute value of the resistive element in a selected temperature range. A feedback frequency is used to control the frequency of oscillating signal.

US patent no. 7,498,884 disclosed a self-calibrating RC oscillator. The RC oscillator comprises a resistor part having a first resistor having a resistance value reduced with increases in temperature; and a second resistor connected in series to the first resistor and having a resistance value increasing with an increase in temperature.A feedback frequency is also used to control the frequency of oscillating signal.

An integrated RC oscillator design that generates a highly stable output frequency with trimming circuits to compensate for process and temperature variation is useful. A low variation parts per million (ppm) RC oscillator is designed for this purpose.

An integrated RC oscillator that generates a stable frequency with trimming circuit to compensate for process and temperature variation is developed. A low variation 0.1% ppm RC oscillator implemented in a 0.18 µm CMOS technology with trimming in the biasing current and capacitor array is presented.

The proposed invention comprises of decoders, a current bias circuit, a RC timing controller, a comparator, a Schmitt trigger, a phase divider and a level shifter.

The decoder interprets input trimming bits to select the appropriate trimming current resistor that generates the reference current bias; select appropriate trimming capacitor arrays to generate the phase timing; and determine the total period of output frequency.

The current bias circuit generates two matching current sources which are used to charge the capacitor arrays; and as a reference current to generate first reference voltage V1 and second reference voltage V2 as differential inputs to the comparator. The RC timing control is used to control the ramp-up of the first reference voltages and second reference voltage where the ramp up timing period is defined by the timing resistor and related trimming capacitors.

The comparator compares the first reference voltage and second reference voltage to generate an oscillation output which is low or high phase in a square clock signal. The Schmitt trigger removes noise and prevents potential voltage glitches from the output of the comparator. It also sharpens the signal edge of the output of the comparator and generates a clean rail to rail frequency output.

The phase divider processes the signal from Schmitt trigger into two differential phases. The differential phase signals is fed back to the RC timing controller, which is connected to the switches that are used to control the ramp up of the first and second reference voltage. The level shifter is used to shift up the magnitude of the frequency output voltage.

These and other features, aspects, and advantages of the present invention will be more fully understood when considered with respect to the following detailed description, appended claims, and accompanying drawings, where like reference numerals denote like structural elements, and wherein:

illustrates a diagram of a RC oscillator, in accordance to the present invention.

illustrates a diagram of various signals of the RC oscillator.

illustrates a diagram of an embodiment of the thermometer decoder circuit.

illustrates a diagram of an embodiment of the current bias circuit.

illustrates a diagram of an embodiment of the RC timing controller.

illustrates a diagram of an embodiment of the comparator.

illustrates a diagram of an embodiment of the Schmitt trigger.

illustrates a diagram of an embodiment of the phase divider.

illustrates a diagram of an embodiment of the level shifter.

illustrates a flow chart of the process of generating an oscillation signal.

A preferred embodiment of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well known functions or constructions are not described in detail since they would obscure the description with unnecessary detail.

The present invention provides an RC oscillator circuit to generate stable 200 kHz output frequency with high accuracy and stability. A low variation ppm RC oscillator with trimming circuit is designed. shows an overview of the RC oscillator which comprises of a decoder 11, a current biasing circuit 12, a timing controller 13, a comparator 14, a Schmitt trigger 15, a phase divider 16 and a level shifter 17.

The RC oscillator generates a square wave oscillation at Output based on the resistance of the resistor part and capacitance of the capacitor part. Trimming bits 0-2 provide a way to compensate the oscillator frequency from temperature fluctuations and process corner variations. The RC oscillator uses supply Vosc_vdd. The EN signal turns on the current biasing and comparator circuit and will start the oscillation at the Output.

shows various relevant signals in oscillation, namely a first phase signal phi, a first reference voltage V1, a second phase signal phiB, a second reference voltage V2 and the output oscillation signal.

An embodiment of the decoder 11 and thermometer decoder 11a are shown in which converts the trimming signal in three binary bits OSC_SEL0, OSC_SEL1 and OSC_SEL2 into eight trimming bit S0, S1, S2, S3, S4, S5, S6 and S7 and seven trimming bit S1, S2, S3, S4, S5, S6 and S7 respectively. The decoder is designed with the utilization of a gate combination of AND, OR, NAND and NOT gate in CMOS 180 nm technology. For the 3to8 decoder 11 outputs, only two are used, which are S1 and S7 to control the current bias circuit. For the decoder 11a, seven thermometer bits are used to control switches in the RC timing control. The three input bits can be adjusted to select the trimming current resistor in order to generate the reference current bias and also to select the trimming capacitor arrays to generate the phase timing period to define the total period of output frequency.

The current bias circuit 12 is a current generator that supplies matching biasing current to the trimming capacitors. shows an embodiment of the current bias circuit 12 which is configured to generate a first reference biasing current source I_CS1 and a second reference biasing current source I_CS2. The generated reference current may vary significantly over process and temperature variation. A person having ordinary skill in the art can design a similar current bias.

The current bias circuit 12 with compensating trimming resistor is designed to control process corners and temperature variations. The current bias circuit 12 has trimming circuits, which consists of trimming resistors R1, R2, R3, R4 and R5 that corresponds to the trimming signals; and NMOS transistor switches M11, M12, M13 and M14. A 3 bit to 8 bit decoder 11 is used to control the switches in the current bias circuit 12.

As an example, if three input bits are ‘100’, the output signals S1 and S7 will trigger low 0 and signals S1B and S7B to high 1. These signals are then used to control switches M11, M14, M12 and M13 respectively. In this situation, switch M11 and M14 are open, OFF while switch M12 and M13 are closed, ON. Then the reference current Io will be generated based on the sum of resistance R1, R2 and R5 which are connected in series. Current mirrors I_CS1 and I_CS2 match one another to mirror the current Io as a reference current. Both current mirrors I_CS1 and I_CS2current are used to change trimming

capacitor array

26, 27, in the timing controller and also are used to generate the first reference voltage V1 and second reference V2 as differential inputs to the comparator 14.

The circuit diagram shown in is the RC timing controller 13. The circuit consists of a fixed timing resistor R0, a first capacitor part 26, a second capacitor part 27 and NMOS transistor switches SW1 to SW6. Each group of trimming

capacitor arrays

26 and 27 has seven capacitors C1a to C7a and C1b to C7b in parallel for each bit of trimming signal, respectively. Each capacitor is connected in series with respective switch SC1a to SC7a and SC1b to SC7b. Also connected in parallel with the group of trimming capacitors are discharge capacitors C0a and C0b. Each of the switches SC1a to SC7a and SC1b to SC7b are controlled by the respective binary S1 to S7 generated by the decoder 11. When the respective binary value is high, the corresponding capacitor is switched on and connected to the circuit while when the respective value is low, the switch is open and the corresponding capacitor is disconnected from the circuit. The value of S1 to S7 controls the capacitance of

capacitor arrays

26, 27. The NMOS switches SW1 to SW6 are connected to signal phi and phiB which are signals feedback from the phase divider. In operation, the RC control circuit, the switches SW1, SW2, SW5 and SW6 are used to control the charge and discharge of trimming capacitors; and the switches SW3, SW4 are used to control current I_CS1, I_CS2 through resistor R0 in order to generate first reference voltage V1 and second reference voltage V2.

shows an embodiment of the comparator circuit, where two stage open loop comparator circuits consists of two different voltage reference V1 and V2. The PMOS differential input pair M1 and M2 as the first stage with NMOS active loads M3 and M4. The first stage of the comparator is biased by a PMOS transistor M7. The PMOS differential pair is followed by a second stage, a common source amplifier. The second stage consists of an NMOS transistor M5 with PMOS active load M6. Both two stage are biased by transferring reference current Iref generated through resistor R2. In order to implement high gain in the open loop comparator, the two stage op-amp without compensation will be an excellent implementation. In order to achieve the desired resolution, the comparator 14 requires a differential input and sufficient gain. The comparator converts voltage V1 into

logic

1 or 0 by comparing reference voltage V2 against V1. If V1 is greater than V2, the comparator produces an output signal OUT, which is 0. Otherwise, the output signal OUT is 1. The comparator 14 uses two cascading CMOS inverters M14, M15, M16 and M17 for low power consumption and high speed. A person having ordinary skilled in the art can devise a similar comparator that achieves the same function.

shows the schematic of an embodiment of Schmitt trigger circuit 15. It is used to generate a clean output signal from a noisy input signal. The output from comparator 14 known as a phase output change when roles of V1 and V2 are switched. To prevent glitches from the comparator 14, the first buffer stage is a Schmitt trigger 15. It is used to sharpen the input signal edge from the comparator 14 to produce a clean rail to rail frequency output.

shows the phase divider which consists of two

inverters

200 and 201 connected in series. The input signal to the first inverter comes from the Schmitt trigger 15. Then inverter 200 will invert the signal and produce the second phase signal phiB. The phiB signal is connected to inverter 201 and produces a first phase signal phi. The phase signals phi and phiB is then feed back into the RC timing controller 13 to control switches SW1 to SW6.

The circuit design in shows the level shifter 17 to move up the magnitude of the frequency output voltage from Vosc_vdd to Vdd voltage. A cross coupled PMOS load p11, p12 is used. The input IN is connected to a low voltage supply Vosc_vdd and the output is connected to a high supply voltage Vdd. When the input signals IN is at vssa, n11 turns ON and n12 turns OFF. Due to positive feedback of the cross coupled p11 and p12 transistor, node T1 is pulled down to vssa and node T2 goes to Vdd. No leakage current path exists between Vdd and vssa. Similarly, the operation reverses if input signal IN switches to Vosc_vdd. Then, n11 turns OFF and n12 turns ON. So, n12 pulls down T2 to vssa and T1 goes to Vdd. The transition time from low voltage to high voltage is decided by the current driving capability of p11. The pull down NMOS has to overcome the PMOS latch action before the output changes state. The size of n11 and n12 is larger than p11 and p12. A person having ordinary skilled in the art can devise a similar level shifter that achieves the same function.

shows a flow chart of the method to produce the oscillation signal with the trimming signal. First, the trimming signal is biased with trimming resistors to create a bias first reference current I_CS1 and second reference current I_CS2. The first reference current I_CS1 is charged with a first group of capacitors and discharged with a first discharge capacitor to generate a first reference voltage V1. The second reference current I_CS2 is charged with a second group of capacitors and discharged with a second discharge capacitor to generate a second reference voltage V2. The first reference voltage V1 is compared to the second reference voltage V2 to produce an output oscillating signal.

The oscillation signal is used as the first phase signal Phi. An inverted oscillation signal is used as a second phase signal PhiB.

The first phase signal Phi controls the first reference current I_CS1 and discharging through first discharging capacitor C0a, and second phase signal PhiB provides phase feedback to the array of capacitors C1a to C7a in first capacitor part 26.

The second phase signal PhiB controls the second reference current I_CS2 and discharging through second discharging capacitor C0b, and first phase signal Phi provides phase feedback to the array of capacitors C1b to C7b in second capacitor part 27.

The output frequency of the oscillator is measured externally by using a frequency counter to verify the output meets the design specifications.

Accordingly, an integrated RC oscillator that generates stable frequency with trimming circuit to compensate process and temperature variation is developed. A low variation 0.1% ppm RC oscillator implemented in a 0.18 µm CMOS technology with trimming in the biasing current and capacitor array is presented.

It is to be understood that although the invention has been described with reference to particular embodiments, the embodiments are merely illustrative of the principles and applications of the present invention, as changes and modifications may become apparent to those skilled in the art, without departing from the scope of the present invention as defined by the appended claims.

Claims

A resistor-capacitor oscillator for generating a stable oscillation signal with a trimming signal, the oscillator comprising:
a current bias circuit (12) with trimming resistors that corresponds to the trimming signal, the circuit biases the trimming signal to a first reference current (I_CS1) and a second reference current (I_CS2);
a timing controller (13) having a timing resistor (R0); a first capacitor part (26), and second capacitor part (27);
wherein the first capacitor part (26) has a first discharge capacitor (C0a) and a first group of capacitors in parallel that corresponds to the trimming signal and the capacitors are charged by first reference current (I_CS1) to produce a first reference voltage (V1);
wherein the second capacitor part (27) has a second discharge capacitor (C0b) and a second group of capacitors in parallel that corresponds to the trimming signal and the capacitors are charged by second reference current (I_CS2) to produce a second reference voltage (V2);
a comparator (14) that compares the first reference voltage (V1) to the second reference voltage (V2) to produce an oscillation signal; and
a phase divider (16) to use the oscillation signal as a first phase signal (Phi) and produce an inverted oscillation signal as a second phase signal (PhiB);
wherein the first phase signal (Phi) controls the first reference current (I_CS1) and discharging the first discharge capacitor (C0a), and second phase signal (PhiB) provides phase feedback to the first group of capacitors in the first capacitor part (26); and
wherein the second phase signal (PhiB) controls second reference current (I_CS2) and discharging the second discharge capacitor (C0b), and first phase signal (Phi) provides phase feedback to the second group of capacitors in the second capacitor part (27).
The oscillator as claimed in claim 1, wherein the trimming signal have seven bits; and the first group of capacitors in first capacitor part (26) and second group of capacitors in second capacitor part (27) have seven capacitors in parallel for each bit of trimming signal, respectively.
The oscillator as claimed in claim 2, further comprising a thermometer decoder (11a) to turn a three bit trimming signal into the seven bit signal.
The oscillator as claimed in claim 1, further comprising a Schmitt trigger (15) to remove noise from the oscillation signal.
The oscillator as claimed in claim 1, further comprising a level shifter (17) to shift up the magnitude of the oscillation signal.
A method of generating a stable oscillation signal with a trimming signal, the method comprising:
biasing the trimming signal with trimming resistors that corresponds to trimming signal to a first reference current (I_CS1) and a second reference current (I_CS2);
charging the first reference current (I_CS1) with a first group of capacitors in parallel that corresponds to the trimming signal;
discharging the first reference current (I_CS1) with a first discharge capacitor (C0a);
generating a first reference voltage (V1) from the first reference current (I_CS1);
charging the second reference current (I_CS2) with a second group of capacitors in parallel that corresponds to the trimming signal;
discharging the second reference current (I_CS2) with a second discharge capacitor (C0b);
generating a second reference voltage (V2) from the second reference current (I_CS2);
comparing the first reference voltage (V1) and the second reference voltage (V2) to produce an oscillating signal;
using the oscillation signal as a first phase signal (Phi);
producing an inverted oscillation signal as a second phase signal (PhiB);
feeding the first phase signal (Phi) to control the first reference current (I_CS1) and discharging of current through the first discharging capacitor (C0a), and feeding second phase signal (PhiB) to the first group of capacitors; and
feeding the second phase signal (PhiB) to control the second reference current (I_CS2) and discharging of current through the second discharging capacitor (C0b), and feeding first phase signal (Phi) to the second group of capacitors.
The method as claimed in claim 6, wherein the trimming signal have seven bits; and the first group of capacitors and second group of capacitors have seven capacitors in parallel for each bit of trimming signal, respectively.
The method as claimed in claim 7, further comprising a decoding of the trimming signal into the seven bit signal for each group of capacitors.
The method as claimed in claim 6, further comprising removing noise from the oscillation signal.
The method as claimed in claim 6, further comprising shifting up the magnitude of the oscillation signal.