WO2021136200A1 - Procédé de chargement d'amorceur, support de stockage et terminal incorporé - Google Patents

Procédé de chargement d'amorceur, support de stockage et terminal incorporé Download PDF

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Publication number
WO2021136200A1
WO2021136200A1 PCT/CN2020/140308 CN2020140308W WO2021136200A1 WO 2021136200 A1 WO2021136200 A1 WO 2021136200A1 CN 2020140308 W CN2020140308 W CN 2020140308W WO 2021136200 A1 WO2021136200 A1 WO 2021136200A1
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Prior art keywords
boot program
processor
controlled
program file
controlled processor
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PCT/CN2020/140308
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English (en)
Chinese (zh)
Inventor
贾克明
江永湛
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京信网络系统股份有限公司
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Publication of WO2021136200A1 publication Critical patent/WO2021136200A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Definitions

  • This application relates to the field of embedded technology, and in particular to a method for loading a boot program, a storage medium, and an embedded terminal.
  • a boot program is generally required to initialize and configure the processor after the device is powered on or reset.
  • the boot program is generally stored in the memory supporting the processor, such as Flash.
  • processor chips there are multiple processor chips on the device. In the scenario, each processor chip is equipped with a memory to store the boot program. This method requires a higher cost, and further increases the area of the hardware board, the resource utilization is low, the loading efficiency of the boot program is low, and when booting When the program needs to be upgraded, a programmer or an emulator needs to be used to burn and update the boot program on the memory. The loading, upgrade and recovery of the boot program are inefficient and costly.
  • this application provides a method for loading a boot program, including:
  • the master boot program file is read, and the master boot program file is sent to the controlled processor by simulating the SPI Flash timing, so that the controlled processor starts the boot corresponding to the master boot program file program.
  • this application provides a boot program loading method from the perspective of a controlled processor, which includes the following steps:
  • the present application also provides a computer-readable storage medium having a computer program stored on the computer-readable storage medium, and when the computer program is executed by a processor, the aforementioned boot program loading method is implemented.
  • the present application also provides an embedded terminal, the embedded terminal includes one or more processors, the processor includes a master processor and a controlled processor; a memory, the memory includes a non- Volatile memory; one or more computer programs, wherein the one or more computer programs are stored in the memory; the embedded terminal is used to execute the aforementioned boot program loading method.
  • This application provides a method for loading, upgrading, and restoring a boot program.
  • the controlled processor is reset by the master control processor, and the controlled processor is controlled to restart.
  • the controlled processor uses the SPI
  • the interface sends the signal timing of loading the boot program to the main control processor, and the SPI interface simulates the interface of SPI Flash through the GPIO interface of the main control processor.
  • the main control processor receives the signal timing, the main control processor Read the master boot program file, and send the master boot program file to the controlled processor by simulating SPI Flash timing, and give the controlled processor a response.
  • the controlled processor When the controlled processor receives the response, it can use the SPI interface Read the main boot program file, start the boot program corresponding to the main boot program file, load the boot program to complete the initial configuration of the device corresponding to the controlled processor, which ensures that the boot program of the controlled processor can be normal Load and complete upgrade as a whole, and there is no need for a separate memory to store the boot program, which reduces the cost of loading the boot program and improves the efficiency of loading the boot program.
  • FIG. 1 is a schematic flowchart of an embodiment of a method for loading a boot program from the perspective of a main control processor of the present application;
  • FIG. 2 is a schematic diagram of an embodiment of an application environment of a method for loading a boot program of this application
  • FIG. 3 is a schematic diagram of an embodiment of a boot program loading device corresponding to FIG. 1 of this application;
  • FIG. 5 is a schematic diagram of another embodiment of an application environment of a method for loading a boot program of this application
  • FIG. 6 is a schematic flowchart of an embodiment of a method for loading a boot program from the perspective of a controlled processor according to the present application
  • FIG. 7 is a schematic diagram of an embodiment of a boot program loading device corresponding to FIG. 6.
  • the embodiment of the present application provides a method for loading a boot program.
  • the method is shown in FIG. 1 and includes the following steps:
  • the application environment of this embodiment is shown in Figure 2.
  • the application environment includes a main control processor, a controlled processor, and a non-volatile memory.
  • the main control processor saves two master and backup controlled processor boot program files, so The boot program files of the master and backup two controlled processors are stored on the non-volatile memory that is matched with the master processor, and the non-volatile memory is connected to the master processor, and the non-volatile memory can use Nor flash Or Nand Flash, used to store two boot program files related to the master processor and the master and backup of the controlled processor.
  • the boot program is required to initialize and configure the processor.
  • the main control processor is used as the main body of execution, and the main control processor resets the controlled processor and sends a reset signal to the controlled processor , Control the controlled processor to restart.
  • S11 Receive the signal timing of loading the boot program sent through the SPI interface after the controlled processor is started, and the SPI interface simulates the interface of the SPI Flash through the GPIO interface of the master control processor.
  • the master control processor receives the loading guide sent through the SPI interface after the controlled processor is started.
  • the signal timing of the program specifically, the master control processor and the controlled processor are connected through the SPI (Serial Peripheral Interface) interface, and the SPI interface is the SPI Flash simulated by the master processor through the GPIO interface.
  • Interface that is, the main control processor is connected to the controlled processor through the GPIO (General-Purpose Input Output) interface simulating the SPI interface of SPI Flash, and the controlled processor sends the load to the main control processor through the SPI interface
  • the signal timing of the boot program correspondingly, the master control processor receives the signal timing of loading the boot program sent through the SPI interface after the controlled processor is started.
  • the SPI Flash is a Flash (not easy to communicate) that uses SPI communication. Lost storage media).
  • S12 Read the main boot program file, and send the main boot program file to the controlled processor by simulating SPI Flash timing, so that the controlled processor starts the boot program corresponding to the main boot program file.
  • the main control processor when the main control processor receives the signal timing, the main control processor reads the main boot program file.
  • the main control processor reads the main boot program from the non-volatile memory. File, and then send the master boot program file to the controlled processor through the simulated SPI Flash timing, and convert the master boot program file into the simulated SPI Flash timing through the SPI interface and send it to the controlled processor, and give it to the controlled processor Reply, so that after receiving the reply, the controlled processor starts the boot program corresponding to the main boot program file, and the main control processor simulates SPI Flash through the GPIO interface, including simulating SPI Flash and SPI interfaces.
  • This embodiment provides a method for loading, upgrading and restoring a boot program.
  • the controlled processor is reset by the master control processor, and the controlled processor is controlled to restart. After the controlled processor is started, the controlled processor passes The SPI interface sends the signal timing of loading the boot program to the main control processor, and the SPI interface simulates the interface of SPI Flash through the GPIO interface of the main control processor.
  • the main control processor receives the signal timing, the main control processes The controller reads the master boot program file, and sends the master boot program file to the controlled processor by simulating SPI Flash timing, and gives the controlled processor a response.
  • the interface reads the main boot program file, starts the boot program corresponding to the main boot program file, loads the boot program to complete the initial configuration of the device corresponding to the controlled processor, which ensures that the boot program of the controlled processor can be Normal loading and complete upgrade as a whole, and there is no need for a separate memory to store the boot program, which reduces the cost of loading the boot program and improves the efficiency of loading the boot program.
  • the method further includes :
  • the backup boot program file is switched to the master boot program file, and a reset signal is sent to the controlled processor again.
  • the master control processor sends the master boot program file to the controlled processor, and the controlled processor starts the boot program corresponding to the master boot program file, and when the startup is completed, sends the master boot program file to the master control processor
  • the startup message is completed, and the master control processor needs to monitor whether the boot program has completed startup in real time.
  • the set time threshold is defined as a preset time, and then the master control processor determines whether it is in advance.
  • the start-up completion message sent by the controlled processor is received within the time, if it is, it is determined that the controlled processor has finished starting the boot program corresponding to the main boot program file; if not, it is determined that the controlled processor starts all If the boot program corresponding to the master boot program file is abnormal, the master control processor can know the completion status of loading the boot program by the controlled processor in real time.
  • the master control processor determines that the boot program corresponding to the master boot program file started by the controlled processor is abnormal, it switches the backup boot program file to the master boot program file, and sends a reset signal to the controlled processor again,
  • the abnormality includes that the controlled processor fails to start the boot program corresponding to the main boot program file within a preset time or the controlled processor fails to start the boot program corresponding to the main boot program file, and the main control processing
  • the processor does not receive the start-up completion message sent by the controlled processor within the preset time, and it is determined that the current boot program file may have errors, and other boot program files need to be replaced for the controlled processor in time.
  • the main control processor saves the main and backup two controlled processor boot program files.
  • the main control processor After not receiving the startup completion message sent by the controlled processor within the preset time, the main control processor switches the backup boot program file to the main boot program File, and at this time, it is necessary to reset the controlled processor again and send a reset signal to the controlled processor again.
  • the master control processor is connected to the reset signal of the controlled processor through a GPIO interface , Used to control the reset of the controlled processor, and determine whether the controlled processor has completed the startup of the master boot program file within the preset time by monitoring whether the completed startup message sent by the controlled processor is received within the preset time
  • the boot program file is switched, and the main control processor tries to load another boot program file for recovery, and restores the process of loading the boot program by the controlled processor to ensure controlled processing
  • the device can finish loading the boot program to better control the controlled processor to complete the boot program startup and complete the controlled processor initialization.
  • the method after sending the reset signal to the controlled processor, the method further includes:
  • the preset time is set for the master control processor, and the master control processor After sending the reset signal to the controlled processor, the timer is started, and then the timing time of the timer is configured as the preset time T, and then the subsequent process is executed, and the judgment is made within the preset time T of the timer Whether the controlled processor has finished starting the boot program corresponding to the master boot program file, if the master control processor does not receive the controlled processor startup completion message within the preset time T, it is determined that the controlled processor startup is abnormal Therefore, it can quickly monitor whether the startup of the controlled processor is abnormal, which facilitates switching the boot program file for the controlled processor, and improves the normal rate of loading the boot program by the controlled processor.
  • the method further includes:
  • the main control processor sends a reset signal to the controlled processor to control the controlled processor. After restarting, if the main control processor receives an instruction to upgrade the boot program, in response to the instruction, it switches the current main program file to the backup program file, and obtains the newly downloaded upgrade boot program file from the remote server.
  • the embodiment defines the newly downloaded boot program file obtained from the remote server as the upgrade boot program file, and then saves the newly downloaded upgrade boot program file as the master boot program file, so that the controlled processor can load the latest boot Program;
  • the main control processor receives an instruction to upgrade the boot program at any time, the main control processor switches the current main program file to a backup program file, and obtains a new download from the remote server And then save the newly downloaded upgrade boot program file as the main boot program file.
  • the upgrade of the boot program file does not affect the operation of the controlled processor.
  • the boot program file of the controlled processor can be upgraded in time through the main control processor, which improves the upgrade efficiency of the boot program file and switches the previous main boot program file to The backup boot program file ensures that the controlled processor can load the boot program normally.
  • the controlled processor includes at least two controlled processors; the main control processor is connected to at least two controlled processors;
  • reading the main boot program file includes:
  • the main control processor When the main control processor receives the signal timing, obtains the identity of the controlled processor, determines the target master boot program file of the controlled processor according to the identity, and reads the target master boot program file.
  • FIG. 5 it is a schematic diagram of another embodiment of the application environment of the bootloader loading method of the present application.
  • the controlled processor includes at least two controlled processors, and the main control processor is connected to At least two controlled processors are connected; in the scenario of multiple connected controlled processors, when the master control processor receives the signal timing, the identity of the controlled processor needs to be determined.
  • the master The processor configures different boot program files for different controlled processors. When the main control processor receives the signal timing, it obtains the identity of the controlled processor, and determines the target host of the controlled processor based on the identity.
  • Boot program file so as to read the target master boot program file, configure different boot program files for different controlled processors, so as to be compatible with different controlled processors to load boot programs, and improve the compatibility of boot program loading;
  • the main control processor configures the same boot program file for the same type of controlled processor, and when the main control processor receives the signal timing, it obtains the identity of the controlled processor and determines the recipient The type of the control processor determines the target master boot program file of the controlled processor, so that the target master boot program file is read, thereby reducing the resource occupation of the master control processor and improving resource utilization.
  • the main control processor is connected to the reset signal of the controlled processor through a GPIO interface, and is used to send a reset signal to the controlled processor.
  • the main control processor is connected to the reset signal of the controlled processor through a GPIO interface, and both the main control processor and at least two processors are connected to the reset signal of the controlled processor through the GPIO interface for Send a reset signal to the controlled processor.
  • the message channel shown includes the use of an Ethernet network interface channel, and also includes the use of communication links such as SPI, I2C, UART, CANBUS, etc., through which the message channel can be transmitted Whether the controlled processor has completed the boot program startup message.
  • the present application provides a method for loading a boot program from the perspective of a controlled processor, which includes the following steps:
  • S20 Receive a reset signal from the main control processor, and perform a restart operation.
  • the application environment of this embodiment includes a master control processor, a controlled processor, and a non-volatile memory.
  • the master control processor stores two master and backup controlled processor boot program files, and the master and backup two controlled processors boot
  • the program file is stored in the non-volatile memory that is matched with the main control processor, and the non-volatile memory is connected to the main control processor.
  • the non-volatile memory can use Nor Flash or Nand Flash to store the main control processor.
  • the related program and the master and backup boot program files of the controlled processor When the device is powered on, the boot program is required to initialize the processor configuration.
  • the controlled processor is the main body of execution.
  • the master processor sends a reset signal to the controlled processor, and When the controlled processor receives the reset signal, it performs a restart operation.
  • S21 Send the signal timing of loading the boot program to the main control processor through the SPI interface, and the SPI interface simulates the interface of the SPI Flash through the GPIO interface of the main control processor.
  • the controlled processor After the controlled processor is started, the controlled processor needs to load the boot program for initial configuration.
  • the controlled processor sends the signal timing of loading the boot program to the main control processor through the SPI interface after startup.
  • the master control processor and the controlled processor are connected through an SPI (Serial Peripheral Interface) interface, and the SPI interface is the interface of the SPI Flash simulated by the master processor through the GPIO interface, that is, the master
  • the processor is connected to the controlled processor through the GPIO (General-Purpose Input Output) interface simulating the SPI interface of SPI Flash
  • the controlled processor sends the signal timing of loading the boot program to the master control processor through the SPI interface
  • the master control processor receives the signal timing of loading the boot program sent through the SPI interface after the controlled processor is started, where the SPI Flash is a Flash (non-volatile storage medium) that uses SPI communication. .
  • S22 Read the main boot program file sent by the main control processor by simulating SPI Flash timing through the SPI interface, and start the boot program corresponding to the main boot program file.
  • the master control processor receives the signal timing, reads the master boot program file, and then converts the master boot program file into an analog SPI Flash timing through the SPI interface and gives the controlled processor a response.
  • the master control processor responds to the signal timing, then reads the master boot program file sent by the master control processor by simulating the SPI Flash timing through the SPI interface, that is, reads the content information of the SPI Flash from the SPI interface
  • the content information of the SPI Flash is the master boot program file, so as to obtain the master boot program file, and then the controlled processor starts the boot program corresponding to the master boot program file, and loads the Boot the program to complete the initial configuration of the device corresponding to the controlled processor.
  • This embodiment provides a method for loading, upgrading and restoring a boot program.
  • the controlled processor is reset by the master control processor, and the controlled processor is controlled to restart. After the controlled processor is started, the controlled processor passes The SPI interface sends the signal timing of loading the boot program to the main control processor, and the SPI interface simulates the interface of SPI Flash through the GPIO interface of the main control processor.
  • the main control processor receives the signal timing, the main control processes The controller reads the master boot program file, and sends the master boot program file to the controlled processor by simulating SPI Flash timing, and gives the controlled processor a response.
  • the interface reads the main boot program file, starts the boot program corresponding to the main boot program file, loads the boot program to complete the initial configuration of the device corresponding to the controlled processor, which ensures that the boot program of the controlled processor can be Normal loading and complete upgrade as a whole, and there is no need for a separate memory to store the boot program, which reduces the cost of loading the boot program and improves the efficiency of loading the boot program.
  • the method further includes:
  • the controlled processor starts the boot program corresponding to the main boot program file, and when the boot is completed, sends a start-up completion message to the main control processor, so that the main control processor can monitor in real time whether the boot program is The startup is completed, if the startup is not completed, according to the above embodiment, the master control processor will switch the backup boot program file to the master boot program file, and send a reset signal to the controlled processor again.
  • the main control processor can know the completion status of loading the boot program by the controlled processor in real time, thereby ensuring that the controlled processor can complete the loading boot program.
  • the present application provides a boot program loading device, including:
  • Reset module 10 used to send a reset signal to the controlled processor to control the controlled processor to restart;
  • Timing receiving module 11 used to receive the signal timing of loading the boot program sent through the SPI interface after the controlled processor is started, and the SPI interface simulates the interface of SPI Flash through the GPIO interface of the master control processor;
  • File reading module 12 when the signal timing is received, the main boot program file is read, and the main boot program file is sent to the controlled processor by simulating the SPI Flash timing, so that the controlled processor can start the controlled processor.
  • the boot program corresponding to the main boot program file is described.
  • the device further includes:
  • Status monitoring module used to determine whether the start-up completion message sent by the controlled processor is received within a preset time; if so, determine that the controlled processor has completed starting the boot program corresponding to the main boot program file; if not, It is determined that the boot program corresponding to the master boot program file started by the controlled processor is abnormal, the backup boot program file is switched to the master boot program file, and a reset signal is sent to the controlled processor again.
  • the status monitoring module further includes executing:
  • the device further includes:
  • File upgrade module used to receive an instruction to upgrade the boot program; in response to the instruction, switch the current main program file to a backup program file; obtain the newly downloaded upgrade boot program file from the remote server; The upgrade boot program file is saved as the main boot program file.
  • the controlled processor includes at least two controlled processors; the main control processor is connected to at least two controlled processors;
  • the file reading module 12 also includes executing:
  • the main control processor When the main control processor receives the signal timing, obtains the identity of the controlled processor, determines the target master boot program file of the controlled processor according to the identity, and reads the target master boot program file.
  • the main control processor is connected to the reset signal of the controlled processor through a GPIO interface, and is used to send a reset signal to the controlled processor.
  • the present application provides a boot program loading device, including:
  • Signal receiving module 20 used to receive the reset signal of the main control processor and perform a restart operation
  • Timing sending module 21 used to send the signal timing of loading the boot program to the master control processor through the SPI interface, and the SPI interface simulates the interface of SPI Flash through the GPIO interface of the master control processor;
  • the program starting module 22 is used to read the main boot program file sent by the main control processor by simulating the SPI Flash timing through the SPI interface, and start the boot program corresponding to the main boot program file.
  • the device further includes:
  • Message sending module used to send a complete start message to the main control processor.
  • the present application provides a computer-readable storage medium on which a computer program is stored.
  • the boot program described in the above-mentioned embodiment can be loaded.
  • the computer-readable storage medium includes, but is not limited to, any type of disk (including floppy disk, hard disk, optical disk, CD-ROM, and magneto-optical disk), ROM (Read-Only Memory), RAM (Random Access) Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, magnetic card or Light card.
  • a storage device includes any medium that stores or transmits information in a readable form by the device, and may be a read-only memory, a magnetic disk, or an optical disk.
  • a computer-readable storage medium can send a reset signal to a controlled processor to control the controlled processor to restart; receive a loading boot program sent through an SPI interface after the controlled processor is started
  • the SPI interface simulates the SPI Flash interface through the GPIO interface for the master control processor; when the signal timing is received, the master boot program file is read, and the master boot program file is sent by simulating the SPI Flash timing To the controlled processor, so that the controlled processor can start the boot program corresponding to the main boot program file, or it can receive the reset signal of the main control processor and perform the restart operation; send to the main control processor through the SPI interface Load the signal timing of the boot program, the SPI interface simulates the interface of SPI Flash through the GPIO interface of the master control processor; reads the master boot program file sent by the master control processor through the simulated SPI Flash timing through the SPI interface, and starts it The boot program corresponding to the main boot program file.
  • the controlled processor is reset by the master control processor, and the controlled processor is controlled to restart.
  • the controlled processor sends a message to the controlled processor through the SPI interface.
  • the main control processor sends the signal timing of loading the boot program, and the SPI interface simulates the SPI Flash interface through the GPIO interface by the main control processor.
  • the main control processor receives the signal timing, the main control processor reads The master boot program file, and send the master boot program file to the controlled processor by simulating the SPI Flash timing, and give the controlled processor a response.
  • the main boot program file starts the boot program corresponding to the main boot program file, and loads the boot program to complete the initial configuration of the device corresponding to the controlled processor, which ensures that the boot program of the controlled processor can be loaded normally and The whole upgrade is complete, and no separate memory is needed to store the boot program, which reduces the cost of loading the boot program and improves the efficiency of loading the boot program.
  • the computer-readable storage medium provided by the embodiment of the present application can implement the above-mentioned embodiment of the boot program loading method.
  • the present application also provides an embedded terminal.
  • the embedded terminal includes a processor 403, a memory 405, an input unit 407, a display unit 409 and other devices.
  • the memory 405 may be used to store a computer program 401 and various functional modules, and the processor 403 runs the computer program 401 stored in the memory 405 to execute various functional applications and data processing of the device.
  • the memory 405 may be internal memory or external memory, or include both internal memory and external memory.
  • the internal memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or random access memory.
  • the input unit 407 is used to receive signal input and user input.
  • the input unit 407 can include a touch panel and other input devices.
  • the touch panel can collect user touch operations on or near it and follow a preset program Drive the corresponding connection device.
  • the display unit 409 may be used to display information input by the user or information provided to the user and various menus of the computer device.
  • the display unit 409 may take the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the processor 403 is the control center of the computer equipment. It uses various interfaces and lines to connect the various parts of the entire computer. By running or executing the software programs and/or modules stored in the memory 403, and calling the data stored in the memory, execute Various functions and processing data.
  • the embedded terminal includes one or more processors 403, the processors include a master processor and a controlled processor; and one or more memories 405, the memories include non-transitory One or more computer programs 401, wherein the one or more computer programs 401 are stored in the memory 405 and configured to be executed by the one or more processors 403, the one or more computers
  • the program 401 is configured to execute the boot program loading method described in the above embodiment.
  • An embedded terminal provided by an embodiment of the application can send a reset signal to a controlled processor to control the controlled processor to restart; receive a signal to load a boot program sent through an SPI interface after the controlled processor is started Timing, the SPI interface simulates the interface of SPI Flash through the GPIO interface of the master control processor; when the signal timing is received, the master boot program file is read, and the master boot program file is sent to the receiver by simulating the SPI Flash timing Control processor, so that the controlled processor can start the boot program corresponding to the main boot program file, or it can receive the reset signal of the main control processor and perform the restart operation; send the loading guide to the main control processor through the SPI interface
  • the SPI interface simulates the interface of SPI Flash through the GPIO interface of the master control processor; reads the master boot program file sent by the master control processor through the simulated SPI Flash timing through the SPI interface, and starts the The boot program corresponding to the main boot program file.
  • the controlled processor is reset by the master control processor, and the controlled processor is controlled to restart.
  • the controlled processor sends a message to the controlled processor through the SPI interface.
  • the main control processor sends the signal timing of loading the boot program, and the SPI interface simulates the SPI Flash interface through the GPIO interface by the main control processor.
  • the main control processor receives the signal timing, the main control processor reads The master boot program file, and send the master boot program file to the controlled processor by simulating the SPI Flash timing, and give the controlled processor a response.
  • the main boot program file starts the boot program corresponding to the main boot program file, and loads the boot program to complete the initial configuration of the device corresponding to the controlled processor, which ensures that the boot program of the controlled processor can be loaded normally and The whole upgrade is complete, and no separate memory is needed to store the boot program, which reduces the cost of loading the boot program and improves the efficiency of loading the boot program.
  • the embedded terminal provided in the embodiment of the present application can implement the above-provided embodiment of the boot program loading method.

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Abstract

L'invention concerne un procédé de chargement d'amorceur, un support de stockage et un terminal incorporé. Le procédé consiste à : envoyer un signal de réinitialisation à un processeur commandé pour commander le redémarrage du processeur commandé (S10) ; recevoir une séquence temporelle de signal, qui est envoyée, au moyen d'un SPI, par le processeur commandé après le démarrage, pour charger un amorceur, le SPI étant une interface pour un processeur de commande principal pour simuler une mémoire flash SPI au moyen d'une interface GPIO (S11) ; et lors de la réception de la séquence temporelle de signal, lire un fichier d'amorceur principal et envoyer le fichier d'amorceur principal au processeur commandé au moyen de la simulation d'une séquence temporelle de la mémoire flash SPI, de telle sorte que le processeur commandé démarre un amorceur correspondant au fichier d'amorceur principal (S12). La présente invention peut réduire le coût de chargement de l'amorceur et améliorer l'efficacité du chargement de l'amorceur.
PCT/CN2020/140308 2019-12-31 2020-12-28 Procédé de chargement d'amorceur, support de stockage et terminal incorporé WO2021136200A1 (fr)

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CN201911420302.3 2019-12-31
CN201911420302.3A CN111240753A (zh) 2019-12-31 2019-12-31 引导程序的加载方法、存储介质及嵌入式终端

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