WO2021136049A1 - 分布式多网元时钟传输系统 - Google Patents

分布式多网元时钟传输系统 Download PDF

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Publication number
WO2021136049A1
WO2021136049A1 PCT/CN2020/138826 CN2020138826W WO2021136049A1 WO 2021136049 A1 WO2021136049 A1 WO 2021136049A1 CN 2020138826 W CN2020138826 W CN 2020138826W WO 2021136049 A1 WO2021136049 A1 WO 2021136049A1
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WIPO (PCT)
Prior art keywords
unit
slave
clock
master station
delay
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PCT/CN2020/138826
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English (en)
French (fr)
Inventor
徐慧俊
卜斌龙
王瑞伟
李学锋
李健
黄文昌
贺璟
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京信网络系统股份有限公司
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Publication of WO2021136049A1 publication Critical patent/WO2021136049A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/001—Synchronization between nodes
    • H04W56/0015—Synchronization between nodes one node acting as a reference for the others

Definitions

  • the present disclosure relates to the field of wireless communication technology, and in particular to a distributed multi-network element clock transmission system.
  • Distributed base stations provide a better solution to the above problems.
  • the principle is to use the distribution system to evenly distribute the signal of the mobile communication base station in every corner of the room, so as to ensure that the indoor area has an ideal signal coverage.
  • Distributed base stations have the advantages of low cost, strong environmental adaptability, and convenient engineering construction. Especially in the future mobile networks, distributed base stations will be widely used.
  • distributed base stations are generally composed of baseband units, extension units, and remote radio units; during network deployment, the baseband units and extension units are connected by optical fibers, and the extension units It is connected to the remote radio unit by network cable or optical fiber.
  • the remote radio unit In high-rise buildings, it is usually covered by multiple cells, and multiple baseband units need to be deployed. If each baseband unit deploys a clock source synchronization module, it will greatly increase the difficulty and difficulty of construction. Construction cost.
  • the technical problem to be solved by the present disclosure is to solve the problems of the existing traditional distributed base station that the clock source wiring construction is difficult and the construction cost is high.
  • a distributed multi-network element clock transmission system including:
  • the master station unit is used to obtain a 1pps signal through the clock source recovery module, and perform frequency synchronization of the master station according to the 1pps signal, and is used for time delay calculation.
  • the slave unit is connected to the master unit via optical fiber; the slave unit is used to obtain the slave station associated clock from the CPRI signal transmitted by the master station unit, and synchronize the frequency of the slave station according to the slave station associated clock, and is used for time delay Calculation.
  • the expansion unit is connected to the master station unit or the slave station unit through optical fiber; the expansion unit is used to obtain the extended associated clock from the CPRI signal transmitted by the master unit or the CPRI signal transmitted by the slave unit, and expand according to the extended associated clock Unit frequency synchronization.
  • the remote unit is connected to the extension unit through optical fiber or network cable; the remote unit is used to obtain the end associated clock from the CPRI signal or network data signal transmitted by the extension unit, and synchronize the frequency of the remote unit according to the end associated clock, and use Time delay synchronization is performed according to the transmission delay calculation result of the master station unit or the connected slave station unit.
  • the master station unit obtains a 1pps signal for frequency synchronization, and the subsequent slave station units, extension units, and remote units obtain random signals according to the signals transmitted by the master station unit.
  • Channel clock which can realize the frequency synchronization of each unit; and the master unit and slave unit as the master can perform delay calculation, and transmit the delay calculation result to the corresponding remote unit to complete the system delay Synchronize.
  • the embodiments of the present disclosure can reduce the difficulty and cost of the clock source wiring construction, and improve the stability of clock transmission.
  • FIG. 1 is a first schematic structural diagram of a distributed multi-network element clock transmission system in an embodiment
  • FIG. 2 is a schematic diagram of the alignment of the clock source synchronization frame header in an embodiment
  • Figure 3 is a schematic diagram of a frame header configuration in an embodiment
  • FIG. 4 is a second schematic structural diagram of a distributed multi-network element clock transmission system in an embodiment
  • FIG. 5 is a schematic diagram of the structure of a clock source synchronization module of the master station in an embodiment
  • FIG. 6 is a schematic diagram of the structure of a clock source synchronization module of a slave station in an embodiment
  • FIG. 7 is a schematic structural diagram of an optical path synchronization module in an embodiment
  • Figure 8 is a schematic structural diagram of an end synchronization module in an embodiment
  • FIG. 9 is a schematic diagram of time delay measurement of a distributed multi-network element clock transmission system in an embodiment
  • Fig. 10 is a third schematic structural diagram of a distributed multi-network element clock transmission system in an embodiment.
  • Distributed multi-network element architecture such as a distributed base station, includes three-level network elements of a host unit, an expansion unit, and a remote unit.
  • the master unit can be divided into a master unit and a slave unit, both of which belong to the baseband unit; the master unit and the slave unit, the slave unit and the slave unit, the expansion unit and the expansion unit are all connected by optical fiber, and the expansion unit and the remote The units are connected by optical fiber or network cable.
  • the embodiment of the present application only needs to obtain a 1pps signal through the master station unit to achieve frequency synchronization and time delay synchronization of other units in the system.
  • a distributed multi-network element clock transmission system is provided, as shown in FIG. 1, including:
  • the master station unit is used to obtain a 1pps (PulsePerSecond, second pulse) signal through the clock source recovery module, and perform frequency synchronization of the master station according to the 1pps signal, and is used for time delay calculation.
  • a 1pps PulsePerSecond, second pulse
  • the slave unit is connected to the master unit via optical fiber; the slave unit is used to obtain the slave station associated clock from the CPRI (Common Public Radio Interface) signal transmitted by the master station unit, and perform the slave station according to the slave station associated clock
  • the frequency is synchronized and used for delay calculation.
  • the expansion unit is connected to the master station unit or the slave station unit through optical fiber; the expansion unit is used to obtain the extended associated clock from the CPRI signal transmitted by the master unit or the CPRI signal transmitted by the slave unit, and expand according to the extended associated clock Unit frequency synchronization.
  • the remote unit is connected to the extension unit through optical fiber or network cable; the remote unit is used to obtain the end associated clock from the CPRI signal or network data signal transmitted by the extension unit, and synchronize the frequency of the remote unit according to the end associated clock, and use Time delay synchronization is performed according to the transmission delay calculation result of the master station unit or the connected slave station unit.
  • the master unit can cascade multiple slave units via optical fiber, and can also be star-connected with multiple slave units.
  • the master station unit is connected to the corresponding expansion unit; specifically, the master station unit can be connected in cascade or star connection with each expansion unit.
  • the slave unit is also connected to the corresponding expansion unit; specifically, the slave unit can be connected in cascade or star connection with each expansion unit.
  • the expansion unit can be connected to the corresponding remote unit; specifically, the expansion unit can be star-connected with each remote unit.
  • the rear stage of the master unit includes at least one expansion unit; the rear stage of the expansion unit includes at least one remote unit; the master unit can also be extended to connect multiple slave units; the rear stage of the slave unit includes at least one expansion unit, based on this , It can complete the distributed architecture of the network elements and realize the all-round coverage of the signal.
  • the master unit can be equipped with a clock source recovery module or connected to a clock source recovery module.
  • the clock source is a 1588 network clock
  • the master station unit is equipped with a 1588 network clock recovery module, which can parse the ptp data packet based on the IEEE 1588V2 protocol, and recover the 1pps signal.
  • the clock source is a GPS clock source
  • the master station unit is connected to a GPS (Global Positioning System, global positioning system) module to obtain a 1pps signal.
  • the master station unit performs master station frequency synchronization according to the 1pps signal; further, the master station unit can generate a signal and transmit it to the subsequent network element.
  • the slave unit obtains the CPRI signal transmitted by the master unit through the optical fiber, and restores the slave station associated clock based on the CPRI signal to perform clock synchronization; further, according to the slave station associated clock, the slave station unit can synchronize the slave station frequency, Ensure that it is consistent with the frequency of the master unit.
  • the extension unit connected to the master station unit or the slave station unit can obtain the CPRI signal transmitted by the baseband unit to which it is connected through optical fiber, and restore the extended accompanying clock based on the CPRI signal, perform clock synchronization, and can perform clock synchronization according to the extension.
  • the channel clock synchronizes the frequency of the extension unit to ensure that it is consistent with the frequency of the connected baseband unit.
  • the remote unit obtains the CPRI signal transmitted by the extension unit through the optical fiber, or obtains the network data signal transmitted by the extension unit through the network cable, and restores the end associated clock based on the CPRI signal or the network data signal, performs clock synchronization, and can perform clock synchronization according to the end associated route
  • the clock synchronizes the frequency of the remote unit to ensure that it is consistent with the frequency of the connected extension unit.
  • the master station unit and the slave station unit as the baseband unit can respectively calculate the delay of the subsequent network elements, and send the calculated delay result to the corresponding remote unit for delay synchronization.
  • the baseband unit can determine an air interface 10ms (millisecond) frame header synchronously by GPS, IEEE 1588V2 or other synchronization sources, and keep the 10ms frame header of CPRI and LTE (Long Term Evolution) data Frame header alignment; further, the baseband unit can calculate the delay of each level of fiber and configure the size of the delay buffer of each level of remote unit according to the internal delay, so that the downlink data of each level of remote unit can reach the air interface at the same time , The uplink data arrives at the baseband unit at the same time.
  • the master station unit can read the time stamp information from the GPS module, and convert it into a subframe number to write to FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) ) Register, FPGA updates the frame number before the next second pulse. At the same time, FPGA maintains the local frame number and distributes the frame number to each network element through the CPRI control word.
  • the master unit can also calculate the time delay of the subsequent slave unit, so that the slave unit can calculate the corresponding uplink and downlink advance. It should be noted that frequency synchronization can be achieved based on the existing structure or method, which is not specifically limited here; in the same way, delay calculation and delay synchronization can be achieved by using existing methods, which are not specifically limited here. .
  • the embodiment of the application only needs to deploy the clock source recovery module in the master station unit, and transmit the associated clock through the optical fiber or network cable set for communication, so that the subsequent network elements can complete frequency synchronization and delay synchronization. Based on this, It can reduce the clock source wiring construction difficulty and construction cost, and at the same time, based on the transmission demand of the communication line, it can effectively improve the clock transmission stability.
  • the master station unit includes a master station clock source synchronization module, a master station processing module, and a master station transmission module.
  • the master station clock source synchronization module is respectively connected to the master station processing module and the master station transmission module, and the master station processing module is connected to the master station transmission module.
  • the clock source synchronization module of the master station is used to obtain the 1pps signal and synchronize the frequency of the master station according to the 1pps signal.
  • the main station processing module is used for time delay calculation.
  • the master station transmission module is used to connect the slave station unit and/or the expansion unit through the optical fiber.
  • the master station clock source synchronization module in the master station unit can be used to obtain a 1pps signal through the clock source recovery module, and perform frequency synchronization between the master station and the clock source according to the 1pps signal.
  • the master station clock source synchronization module can be set in the baseband circuit of the master station unit, such as FPGA.
  • the clock source synchronization module of the master station can send the clock signal to the subsequent network element through the master station transmission module.
  • the master station clock source synchronization module can also be used for delay measurement, measuring the delay between adjacent network elements.
  • the master station processing module can send query information to the downstream network elements through the master station transmission module, so that the downstream network elements can feed back the delay data; the master station processing module can calculate based on the feedback delay data to obtain the information of the downstream network elements.
  • the delay calculation result is transmitted to the corresponding downstream network element through the transmission module of the master station to complete the delay synchronization.
  • the master station delay calculation module may be provided in the processor of the master station unit, such as a microcontroller.
  • the embodiments of the present application can complete frequency synchronization and delay calculation based on the baseband circuit and processor in the master station unit, and the transmission line on the communication link, reduce the construction difficulty and construction cost of the clock source wiring, and improve the stability.
  • the master station clock source synchronization module includes a master station clock source detection unit for obtaining a 1pps signal, and a master station phase detection unit, a master station control unit, and a master station digital-to-analog voltage control conversion unit. Unit, master station loop filter, master station crystal oscillator unit, master station timing generator, master station phase-locked loop and master station counter.
  • the master station clock source detection unit is connected to the master station control unit through the master station phase detection unit; the master station control unit is respectively connected to the master station digital-to-analog voltage control conversion unit and the master station timing generator; the master station digital-to-analog voltage control conversion unit sequentially passes through the master station ring
  • the path filter and the master station crystal oscillator unit are connected to the master station phase-locked loop; the master station phase-locked loop is connected to the master station phase detection unit through the master station counter.
  • the master station clock source detection unit is used to implement 1pps pulse detection and give an indication of the presence of a 1pps signal.
  • the master station phase detection unit is used for phase error detection to obtain the phase difference between the local clock and the input reference signal.
  • the master station control unit is used for the initial synchronization of the clock source, such as frequency offset compensation, and can also be used to cooperate with the master station timing generator to achieve 10ms frame header synchronization and SFN (Single Frequency Network) synchronization (aligned with the 1pps boundary) ), etc.; and, the master station control unit can also be used to calculate the configuration value of the master station digital-to-analog voltage control conversion unit according to the PID algorithm.
  • the master station digital-to-analog voltage control conversion unit is used for accurate voltage value output; the master station loop filter is used for loop filtering; the master station crystal oscillator unit is used for precise frequency output; the master station phase-locked loop is used for frequency locking; the master station counter It is used for precise frequency division and outputs the corresponding frequency to the master station phase detection unit, so that the master station phase detection unit compares the frequency with the frequency output by the master station clock source detection unit to obtain the phase difference.
  • the clock source synchronization module of the master station can quickly complete frequency synchronization according to the 1pps signal.
  • the master station processing module is used to:
  • the target network element is the extension unit or the remote unit that is connected to the main station unit.
  • the uplink delay and downlink delay of the target network element are sent to the target network element.
  • the master station processing module when it realizes the delay calculation, it can first send query information to the target network element, so that the target network element transmits the link processing delay, the downlink data processing delay and the uplink data to the master station processing module. Processing delay and other data, further, the master station processing module sends query information to the upper level network element of the target network element, so that the upper level network element transmits the corresponding uplink delay and downlink delay to the master station processing module Road delay. Based on the acquired data, the main station processing module calculates the uplink delay and the downlink delay of the target network element and sends them to the target network element. Based on this, the master station unit can calculate the time delay between the master station unit and the target network element connected to the master station.
  • the master station unit also needs to send the uplink advance and downlink advance to the last-level target network element.
  • the last-level target network element can process the delay calculation result, the uplink advance and the downlink advance of the master unit. Obtain the uplink delay buffer value and the downlink delay buffer value, and then configure the register to complete the uplink and downlink frame synchronization. Based on this, the delay calculation can be centrally set on the baseband unit such as the master station unit, simplifying the data processing process of the subsequent network elements, and improving the stability of the delay processing.
  • the main station processing module is also used to:
  • the uplink delay and downlink delay of the slave unit, as well as the uplink advance and the downlink advance are sent to the slave unit, so that the slave unit obtains the slave downlink advance and the slave uplink advance.
  • the master station processing module when the master station processing module realizes the delay calculation of the slave station unit, it can first send query information to the slave station unit, so that the slave station unit transmits the link processing delay and the downlink data processing time to the master station processing module. Further, the master station processing module sends query information to the upper-level baseband network element of the slave station unit, so that the upper-level baseband network element transmits the corresponding uplink to the master station processing module. Road delay and downlink delay. Based on the acquired data, the master station processing module calculates the uplink time delay and the downlink time delay of the slave station unit and sends them to the slave station unit. Based on this, the master unit can calculate the time delay between the master unit and the slave unit.
  • the master unit also sends the uplink advance and downlink advance to the slave unit; the slave unit can process the delay calculation result, the uplink advance and the downlink advance of the master unit, and obtain the slave uplink advance of the slave unit In turn, the delay calculation of the subsequent network element of the slave unit can be realized.
  • the slave station unit can realize the delay calculation and synchronization of the subsequent network elements without setting a clock source recovery module, thereby reducing the construction difficulty and construction cost of the clock source wiring, and improving the stability.
  • the slave unit includes a slave clock source synchronization module, a slave processing module, and a slave transmission module.
  • the slave station clock source synchronization module is respectively connected to the slave station processing module and the slave station transmission module, the slave station processing module is connected to the slave station transmission module, and the slave station transmission module is connected to the master station unit through an optical fiber.
  • the slave transmission module is used to obtain the CPRI signal transmitted by the master unit.
  • the slave station clock source synchronization module is used to obtain the slave station associated clock from the CPRI signal transmitted by the master station unit, and synchronize the slave station frequency according to the slave station associated clock.
  • the slave processing module is used for delay calculation.
  • the slave clock source synchronization module in the slave unit can be used to obtain the CPRI signal transmitted by the master unit through the slave transmission module, and restore the associated clock of the slave station, perform clock synchronization, and the slave station and the master station.
  • the frequency is synchronized.
  • the slave station clock source synchronization module can be set in the baseband circuit of the slave station unit, such as an FPGA.
  • the slave station clock source synchronization module can send the clock signal to the subsequent network element through the slave station transmission module.
  • the slave clock source synchronization module can also be used for delay measurement to measure the delay between adjacent network elements.
  • the slave processing module can send query information to the downstream network element through the slave transmission module, so that the downstream network element feeds back the delay data; the slave processing module can calculate based on the delay data to obtain the delay of the downstream network element The calculation result is transmitted to the corresponding downstream network element through the slave transmission module to complete the time delay synchronization.
  • the slave station delay calculation module may be provided in the processor of the slave station unit, such as a microcontroller.
  • the embodiments of the present application can complete frequency synchronization and delay calculation based on the baseband circuit and processor in the slave station unit, and the transmission line on the communication link, reduce the construction difficulty and construction cost of the clock source wiring, and improve the stability.
  • the slave clock source synchronization module includes a slave clock source detection unit for acquiring the slave clock associated with the channel, and a slave phase detection unit, a slave control unit, and a slave number.
  • the slave station clock source detection unit is connected to the slave station control unit through the slave station phase detection unit; the slave station control unit is respectively connected to the slave station digital-to-analog voltage control conversion unit and the slave station timing generator; the slave station digital-to-analog voltage control conversion unit sequentially passes through the slave station loop
  • the path filter and the slave crystal oscillator unit are connected to the slave phase-locked loop; the slave phase-locked loop is connected to the slave phase detection unit through the slave counter.
  • the slave clock source detection unit is used for CPRI associated clock detection and extraction.
  • the phase detection unit of the slave station is used for phase error detection to obtain the phase difference between the local clock and the input reference signal.
  • the slave station control unit is used for the initial synchronization of the clock source, such as frequency offset compensation, etc., and can also be used to cooperate with the slave station timing generator to achieve 10ms frame header synchronization and SFN synchronization (aligned to the 1pps boundary), etc.; and, the slave station control unit It can also be used to calculate the configuration value of the slave station digital-to-analog voltage control conversion unit according to the PID algorithm.
  • the slave digital-to-analog voltage control conversion unit is used for accurate voltage value output; the slave loop filter is used for loop filtering; the slave crystal oscillator unit is used for accurate frequency output; the slave phase-locked loop is used for frequency locking; the slave counter Used for precise frequency division, and output the corresponding frequency output from the slave clock source detection unit.
  • the slave clock source synchronization module can quickly complete frequency synchronization according to the associated clock in the CPRI signal.
  • the slave processing module is used to:
  • the target network element is the extension unit or the remote unit that is connected to the slave unit.
  • the uplink delay and downlink delay of the target network element are sent to the target network element.
  • the slave processing module when it realizes the delay calculation, it can first send query information to the target network element, so that the target network element transmits the link processing delay, the downlink data processing delay and the uplink data to the slave processing module. Processing delay and other data, further, the slave processing module sends query information to the upper-level network element of the target network element, so that the upper-level network element transmits the corresponding uplink delay and downlink to the slave processing module Road delay. Based on the acquired data, the slave processing module calculates the uplink delay and the downlink delay of the target network element and sends them to the target network element. Based on this, the slave station unit can calculate the time delay between the slave station unit and the target network element connected to the slave station.
  • the slave unit also needs to send the uplink advance and downlink advance to the last-level target network element.
  • the last-level target network element can process the delay calculation result, the uplink advance and the downlink advance of the slave unit. Obtain the uplink delay buffer value and the downlink delay buffer value, and then configure the register to complete the uplink and downlink frame synchronization. Based on this, the delay calculation can be centrally set on the baseband unit such as the slave unit, simplifying the data processing process of the subsequent network elements, and improving the stability of the delay processing.
  • the expansion unit includes an optical path synchronization module, an expansion processing module, and an expansion transmission module.
  • the optical path synchronization module is respectively connected to the expansion processing module and the expansion transmission module, the expansion processing module is connected to the expansion transmission module, and the expansion transmission module is connected to the master station unit or the slave station unit through an optical fiber.
  • the optical path synchronization module is used to obtain the extended associated clock and synchronize the frequency of the extended unit according to the extended associated clock.
  • the extended processing module is used for delay calculation.
  • the optical path synchronization module is used for optical path synchronization; specifically, the optical path synchronization module recovers the associated clock from the CPRI signal transmitted by the extension transmission module, thereby achieving frequency synchronization between the extension unit and the baseband unit.
  • the extended processing module can be used to calculate the time delay with neighboring network elements.
  • the optical path synchronization module may be set in the baseband circuit of the expansion unit, and the expansion processing module may be set in the processor of the expansion unit, which is not specifically limited here.
  • the expansion transmission module is used to realize the cascade connection between expansion units and can also be used to connect the remote unit; the expansion transmission module may include a first transmission unit for signal transmission with the cascade expansion unit, and a first transmission unit for communicating with the remote unit.
  • the second transmission unit for signal transmission can realize frequency synchronization without setting a clock source recovery module, which reduces the construction difficulty and construction cost of the clock source wiring, and improves the stability.
  • the optical path synchronization module includes a serdes clock recovery unit for obtaining the extended associated clock, a first-level clock unit, a second-level clock unit, a first local clock, and a second local clock. .
  • the serdes clock recovery unit is respectively connected to the first-level clock unit and the second-level clock unit; the first-level clock unit is respectively connected to the first local clock and the second-level clock unit; the second-level clock unit is connected to the second local clock.
  • the serdes clock recovery unit recovers the accompanying clock from the CPRI signal, and realizes the phase discrimination and control between the output frequency of the second-level clock unit and the CPRI accompanying clock, and outputs a stable accompanying clock.
  • the associated clock recovered by serdes is used as the reference clock of the first-level clock unit; the first-level clock unit realizes the phase discrimination and control of the associated clock and the first local clock, and outputs a stable first-way clock, which is given to as a reference signal The second-level clock unit.
  • the first clock is used as the reference clock of the second-level clock unit
  • the second-level clock unit realizes the phase discrimination and control of the first clock and the second local clock, outputs a stable local accompanying clock, and transmits it to serdes to recover the clock unit.
  • the second-level clock unit can also output other clocks. Based on this, the embodiment of the present application can realize the optical path synchronization of the expansion unit through a simple structure.
  • the remote unit includes an end synchronization module, an end processing module, and an end transmission module.
  • the end synchronization module is respectively connected to the end processing module and the end transmission module, the end processing module is connected to the end transmission module, and the end transmission module is connected to the expansion unit through an optical fiber or a network cable.
  • the end synchronization module is used to obtain the end associated clock and synchronize the frequency of the remote unit according to the end associated clock.
  • the end processing module is used for delay calculation and delay synchronization.
  • the end synchronization module can recover the associated clock from the CPRI signal or network data signal transmitted by the end transmission module, and realize the frequency synchronization between the remote unit and the expansion unit; the end processing module can be used according to the link transmitted by the baseband unit Delay and uplink and downlink advances, calculate the uplink and downlink delay buffer value and configure the corresponding registers to complete the delay synchronization.
  • the end synchronization module includes an associated clock recovery unit for obtaining an end associated clock, an end phase detection unit, an end control unit, an end digital-to-analog conversion unit, and an end loop filter. Detector, end crystal unit, end phase-locked loop and end counter.
  • the associated clock recovery unit is connected to the end control unit through the end phase detection unit; the end control unit is connected to the end loop filter through the end digital-to-analog conversion unit; the end loop filter is connected to the end phase-locked loop through the end crystal unit; the end phase-locked loop Connect the end phase discriminating unit through the end counter.
  • the associated clock recovery unit is used to restore the associated clock signal according to the CPRI signal or the network data signal, and send the restored associated clock signal to the end phase discrimination unit.
  • the terminal phase detection unit is used for phase error detection to obtain the phase difference between the local reference clock and the associated clock.
  • the terminal digital-to-analog conversion unit is used to output the voltage value according to the digital-to-analog conversion.
  • the end loop filter unit is used for loop filtering.
  • the end crystal unit is used to output a specific frequency.
  • the end phase locked loop is used for frequency locking.
  • the end counter is used to accurately divide the frequency and output the corresponding frequency to the end phase discriminating unit, so that the end phase discriminating unit compares the frequency with the frequency output by the clock recovery unit to obtain the phase difference.
  • the end processing module is used to calculate the uplink delay buffer according to the uplink delay, downlink delay, uplink advance and downlink advance transmitted by the master unit or the accessed slave unit.
  • the value and the downstream delay buffer value are also configured in the register.
  • the terminal processing module can obtain the query information of the baseband unit through the terminal transmission module, and feedback the corresponding delay data to the baseband unit according to the query information; further, the terminal processing module obtains the query information through the terminal transmission module
  • the delay calculation result of the baseband unit and the uplink and downlink advancement are further calculated to obtain the uplink and downlink delay buffer value and configured in the register to complete the uplink and downlink frame synchronization.
  • T_advance_DL is the downlink advance
  • T_advance_UL is the uplink advance
  • T1_14 is the link delay from the first-level network element to the second-level network element
  • T2_14 is the second-level network element Link delay to the third level network element
  • Tn-1_14 is the link delay from the n-1 level network element to the nth level network element
  • T1_23 is the two ports from the first level network element to the second level network element
  • T2_23 is the link processing delay between the two ports of the second-level network element to the third-level network element
  • Tn-1_23 is the two ports of the n-1th level network element to the nth-level network element
  • Td2 is the downlink data processing delay of the second-level network element
  • Tu2 is the uplink data processing delay of the second-level network element
  • Td3 is the downlink data processing delay of the third-level network element
  • Tu3 is the second-level network element's downlink data processing delay
  • the first-level network element delay calculation module After the second-level network element is connected to the first-level network element, the first-level network element delay calculation module sends a query message to the second-level network element, and the second-level network element delay measurement module sets the link processing delay T1_23, The downlink data processing delay Td2 and the uplink data processing delay Tu2 are sent to the first-level network element through the CPRI C&M channel, and the first-level network element delay calculation module calculates the link delay between the two network elements (T1_14-T1_23) /2, the delay calculation module calculates the uplink delay (T1_14-T1_23)/2+Tu2 and the downlink delay (T1_14-T1_23)/2+Td2 respectively, and sends the calculation result back to the second-level network element.
  • the first-level network element delay calculation module After the third-level network element is connected to the first-level network element, the first-level network element delay calculation module sends a query message to the third-level network element, and the third-level network element delay measurement module sets the link processing delay T2_23, The downlink data processing delay Td3 and the uplink data processing delay Tu3 are sent to the first-level network element through the CPRI C&M channel, and the first-level network element delay calculation module sends a query message to the second-level network element.
  • the delay measurement module sends the link delay T2_14 to the first-level network element, and the first-level network element delay calculation module calculates the link delay between the two network elements: (T1_14-T1_23)/2+(T2_14-T2_23 )/2, the delay calculation module then separately calculates the uplink delay (T1_14-T1_23)/2+Tu2+(T2_14-T2_23)/2+Tu3 and the downlink delay (T1_14-T1_23)/2+Td2+(T2_14-T2_23) /2+Td3, and send the calculation result back to the third-level network element.
  • the first level network element delay calculation module sends a query message to the nth level network element, and the nth level network element delay measurement module connects the link The processing delay Tn-1_23, the downlink data processing delay Tdn, and the uplink data processing delay Tun are sent to the first-level network element through the CPRIC&M channel, and the first-level network element delay calculation module sends a query message to the n-1th level network Element, the n-1 level network element delay measurement module sends the link delay Tn-1_14 to the first level network element, and the first level network element delay calculation module calculates the link delay between the two network elements: (T1_14-T1_23)/2+(T2_14-T2_23)/2+ whil+(Tn-1_14-Tn-1_23)/2, the delay calculation module calculates the uplink delay (T1_14-T1_23)/2+Tu2+ (T2_14-T
  • the nth level delay calculation module calculates the upstream delay buffer value as:
  • the downstream delay buffer value is:
  • the last-level network element configures the corresponding FPGA register to complete the uplink and downlink frame synchronization.
  • the time delay measurement module may belong to the clock source synchronization module and be set in the baseband circuit; the delay calculation module may belong to the processing module and be set in the processor of the baseband unit.
  • all slave units need to be connected to the master unit and maintain a heartbeat; the extension unit and remote unit of each level of baseband unit can be connected to the baseband unit; the baseband unit is based on each network The model and number of levels reported by the element determine the type and topology of the network element, and save the relevant information.
  • T_advance_DL is the downlink advance of the baseband unit
  • T_advance_UL is the downlink advance of the baseband unit.
  • the delay calculation module of the master station sends a query message to the extension unit, and the extension unit uploads the link processing delay (Tau-cp1, Tcp1-cp2...Tcp(n-1) )-cp(n)), downlink data processing delay (Tdcp1, Tdcp2...Tdcpn) and uplink data processing delay (Tucp1, Tucp2...Tucpn)
  • the master station sends a query message to its upper-level cascade expansion unit
  • the upper-level cascaded extension unit delay measurement module reports the link delay
  • the master station delay calculation module calculates the downlink delay from the master station to the extension unit N:
  • the master station delay calculation module sends a query message to the remote unit, and the remote unit uploads the link processing delay, the downlink data processing delay, and the uplink data processing delay,
  • the master station sends a query message to its upper-level expansion unit, the upper-level expansion unit delay measurement module reports the link delay, and the master station unit calculation module calculates the downlink delay between the master station and the remote unit M:
  • the remote unit delay calculation module calculates the uplink delay buffer value:
  • Tu_buf T_advance_UL– ⁇ Tau-cp1+Tdcp1+->+Tcp(n-1)-cp(n)+Tdcpn+Tcp(n)-dp(m)+Tddpm ⁇ ;
  • the downstream delay buffer value is:
  • Td_buf T_advance_DL— ⁇ Tau-cp1+Tucp1+...+Tcp(n-1)-cp(n)+Tucpn+Tcp(n)-dp(m)+Tudpm ⁇ .
  • the remote unit M configures the corresponding FPGA register to complete the uplink and downlink frame synchronization.
  • the master station delay calculation module sends a query message to the slave station, and the slave station uploads the link processing delay (Tmau-sau1...Tsau( y-1)-sau(y)), downlink data processing delay (Tdau1...Tdauy) and uplink data processing delay (Tuau1...Tuauy);
  • the master station sends a query message to its upper-level cascaded baseband unit,
  • the upper-level cascaded baseband unit delay measurement module reports the link delay, and the master station unit calculation module calculates the downlink delay between the master station and the slave station N:
  • T_advance_DL T_advance_DL– ⁇ Tau-cp1+Tdcp1+...+Tcp(n-1)-cp(n)+Tdcpn+Tcp(n)-dp(m)+Tddpm ⁇ ;
  • T_advance_UL T_advance_UL— ⁇ Tmau-sau1+Tuau1+Tsau(y-1)-sau(y)+Tuauy ⁇ , as the uplink advance of the slave station.
  • extension unit, remote unit under the slave station, and the extension unit under the master station, and the remote unit delay configuration process are exactly the same, except that the system advancement T_advance_DL, T_advance_UL and the difference between ‘T_advance_DL,’ T_advance_UL are not repeated here.
  • the master station unit obtains a 1pps signal for frequency synchronization, and the subsequent slave station units, extension units, and remote units obtain random signals according to the signals transmitted by the master station unit.
  • Channel clock which can realize the frequency synchronization of each unit; and the master unit and slave unit as the master can perform delay calculation, and transmit the delay calculation result to the corresponding remote unit to complete the system delay Synchronize. It can reduce the construction difficulty and construction cost of clock source wiring, improve the stability of clock transmission, and has strong industrial practicability.

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Abstract

本申请涉及一种分布式多网元时钟传输系统，主站单元通过时钟源恢复模块获取1pps信号，并根据1pps信号进行主站频率同步，且可用于时延计算。从站单元在主站单元传输的CPRI信号中获取从站随路时钟，进行从站频率同步及时延计算。扩展单元在主站单元传输的CPRI信号中或从站单元传输的CPRI信号中获取扩展随路时钟，进行扩展单元频率同步。远端单元在扩展单元传输的CPRI信号或网络数据信号中获取末端随路时钟，进行远端单元频率同步，且可用于根据主站单元或接入的从站单元传输的时延计算结果进行时延同步。由主站单元获取1pps信号进行频率同步，后级网元根据主站单元传输的信号实现频率同步和时延同步，减少时钟源布线施工难度和建设成本，提高时钟传递稳定性。

Description

分布式多网元时钟传输系统
本公开要求于2019年12月31日提交中国专利局、申请号为201911413816.6、发明名称为“分布式多网元时钟传输系统”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及无线通信技术领域，尤其涉及一种分布式多网元时钟传输系统。
背景技术
随着城市里移动用户的飞速增加以及高层建筑越来越多，话务密度和覆盖要求也不断上升。由于建筑物规模大，对移动电话信号有很强的屏蔽作用。分布式基站为上述问题提供了较佳的解决方案。其原理是利用分布系统将移动通信基站的信号均匀分布在室内每个角落，从而保证室内区域拥有理想的信号覆盖。分布式基站具有低成本、环境适应性强、工程建设方便的优势，尤其是在未来的移动网络中，分布式基站将得到非常广泛的应用。
在实现过程中，发明人发现传统技术中至少存在如下问题：目前分布式基站一般由基带单元、扩展单元和远端射频单元组成；在网络部署时，基带单元和扩展单元通过光纤相连，扩展单元和远端射频单元通过网线或者光纤相连；而在高层建筑中，一般由多个小区覆盖完成，需要部署多台基带单元，如果每台基带单元部署一个时钟源同步模块，则大大增加施工难度和建设成本。
发明内容
(一)要解决的技术问题
本公开要解决的技术问题是解决现有的传统分布式基站存在时钟源布线施工难度大和建设成本高的问题。
(二)技术方案
为了解决上述技术问题，本公开实施例提供了一种分布式多网元时钟传输系统，包括：
主站单元，用于通过时钟源恢复模块获取1pps信号，并根据1pps信号进行主站频率同步，且用于时延计算。
从站单元，通过光纤连接主站单元；从站单元用于在主站单元传输的CPRI信号中获取从站随路时钟，并根据从站随路时钟进行从站频率同步，且用于时延计算。
扩展单元，通过光纤连接主站单元或从站单元；扩展单元用于在主站单元传输的CPRI信号中或从站单元传输的CPRI信号中获取扩展随路时钟，并根据扩展随路时钟进行扩展单元频率同步。
远端单元，通过光纤或网线连接扩展单元；远端单元用于在扩展单元传输的CPRI信号或网络数据信号中获取末端随路时钟，并根据末端随路时钟进行远端单元频率同步，且用于根据主站单元或接入的从站单元传输的时延计算结果进行时延同步。
(三)有益效果
本公开实施例提供的上述技术方案与现有技术相比具有如下优点：
本公开实施例提供的该分布式多网元时钟传输系统中，由主站单元获取1pps信号进行频率同步，后级的从站单元、扩展单元和远端单元根据主站单元传输的信号获取随路时钟，进而可实现各单元的频率同步；并且，作为主机的主站单元和从站单元可进行时延计算，并将时延计算结果传输给对应的远端单元，以完成系统的时延同步。基于此，本公开实施例可减少时钟源布线施工难度和建设成本、提高时钟传递稳定性。
附图说明
图1为一个实施例中分布式多网元时钟传输系统的第一示意性结构图；
图2为一个实施例中时钟源同步帧头对齐示意图；
图3为一个实施例中帧头配置示意图；
图4为一个实施例中分布式多网元时钟传输系统的第二示意性结构图；
图5为一个实施例中主站时钟源同步模块的结构示意图；
图6为一个实施例中从站时钟源同步模块的结构示意图；
图7为一个实施例中光路同步模块的结构示意图；
图8为一个实施例中末端同步模块的结构示意图；
图9为一个实施例中分布式多网元时钟传输系统的时延测量示意图；
图10为一个实施例中分布式多网元时钟传输系统的第三示意性结构图。
具体实施方式
分布式多网元架构，例如分布式基站，包括主机单元、扩展单元和远端单元三级网元。主机单元可分为主站单元和从站单元，均属于基带单元；主站单元与从站单元、从站单元与从站单元、扩展单元与扩展单元间均采用光纤连接，扩展单元与远端单元间采用光纤或者网线连接。本申请实施例只需要通过主站单元获取1pps信号，即可实现系统中其它单元的频率同步和时延同步。
在一个实施例中，提供了一种分布式多网元时钟传输系统，如图1所示，包括：
主站单元，用于通过时钟源恢复模块获取1pps(PulsePerSecond，秒脉冲)信号，并根据1pps信号进行主站频率同步，且用于时延计算。
从站单元，通过光纤连接主站单元；从站单元用于在主站单元传输的CPRI(CommonPublicRadioInterface，通用公共无线电接口)信号中获取从站随路时钟，并根据从站随路时钟进行从站频率同步，且用于时延计算。
扩展单元，通过光纤连接主站单元或从站单元；扩展单元用于在主站单元传输的CPRI信号中或从站单元传输的CPRI信号中获取扩展随路时钟，并根据扩展随路时钟进行扩展单元频率同步。
远端单元，通过光纤或网线连接扩展单元；远端单元用于在扩展单元传输的CPRI信号或网络数据信号中获取末端随路时钟，并根据末端随路时钟进行远端单元频率同步，且用于根据主站单元或接入的从站单元传输的时延计算结果进行时延同步。
具体而言，主站单元可通过光纤级联多个从站单元，也可与多个从站单元星型连接。并且，主站单元连接对应的扩展单元；具体地，主站单元可与各扩展单元级联连接或星型连接。同样地，从站单元也连接对应的扩展单元；具体地，从站单元可与各扩展单元级联连接或星型连接。扩展单元可连接对应的远端单元；具体地，扩展单元可与各远端单元星型连接。即，主站单元后级包括至少一个扩展单元；扩展单元后级包括至少一个远端单元；主站单元还可扩展连接多个从站单元；从站单元后级包括至少一个扩展单元，基于此，可完成网元的分布式架构，实现信号的全方位覆盖。
主站单元可设有时钟源恢复模块，或连接时钟源恢复模块。在一个示例中，时钟源为1588网络时钟，则主站单元设有1588网络时钟恢复模块，可基于IEEE 1588V2协议，解析ptp数据包，恢复得到1pps信号。在另一个示例中，时钟源为GPS时钟源，则主站单元连接GPS(GlobalPositioningSystem，全球定位系统)模块，获取1pps信号。主站单元根据1pps信号进行主站频率同步；进一步地，主站单元可生成信号并传输给后级网元。
从站单元通过光纤获取主站单元传输的CPRI信号，并基于该CPRI信号恢复从站随路时钟，进行时钟同步；进一步地，根据从站随路时钟，从站单元可进行从站频率同步，保证与主站单元的频率一致。同样地，接入主站单元或从站单元的扩展单元可通过光纤获取其接入的基带单元传输的CPRI信号，并基于该CPRI信号恢复扩展随路时钟，进行时钟同步，且可根据扩展随路时钟进行扩展单元频率同步，保证与接入的基带单元的频率一致。远端单元通过光纤获取扩展单元传输的CPRI信号，或通过网线获取扩展单元传输的网络数据信号，并基于该CPRI信号或网络数据信号恢复末端随路时钟，进行时钟同步，且可根据末端随路时钟进行远端单元频率同步，保证与接入的扩展单元的频率一致。
此外，作为基带单元的主站单元和从站单元可分别计算其后级的网元的时延，并将计算得到的时延结果发送给对应的远端单元，以进行时延同步。示例性地，如图2所示，基带单元可由GPS、IEEE 1588V2 或者其他同步源同步确定一个空口10ms(毫秒)帧头，并保持CPRI的10ms帧头与LTE(Long Term Evolution，长期演进)数据帧头对齐；进一步地，基带单元可通过计算各级光纤时延，并根据内部时延，配置每一级远端单元时延缓存区大小，以达到每一级远端单元下行数据同时到达空口，上行数据同时到达基带单元。具体地，如图3所示，在收到GPS同步指示后，主站单元可从GPS模块读取时戳信息，并换算成子帧号写入FPGA(Field Programmable Gate Array，现场可编程逻辑门阵列)寄存器，FPGA在下一秒脉冲到来前更新帧号，同时FPGA维护本地帧号，并通过CPRI控制字，将帧号分发到各网元。并且，主站单元还可计算得到后级的从站单元的时延，以使从站单元计算得到对应的上下行提前量。需要说明的是，频率同步可基于现有的结构或方法来实现，此处不做具体限定；同理，时延计算与时延同步可采用现有的方法来实现，此处不做具体限定。
本申请实施例仅需在主站单元中部署时钟源恢复模块即可，并通过通信设置的光纤或网线来传输随路时钟，以使后级网元完成频率同步和时延同步，基于此，可减少时钟源布线施工难度和建设成本，同时，基于通信线路的传输需求，能够有效提高时钟传递稳定性。
在一个实施例中，如图4所示，主站单元包括主站时钟源同步模块、主站处理模块和主站传输模块。
主站时钟源同步模块分别连接主站处理模块和主站传输模块，主站处理模块连接主站传输模块。
主站时钟源同步模块用于获取1pps信号，并根据1pps信号进行主站频率同步。
主站处理模块用于进行时延计算。
主站传输模块用于通过光纤连接从站单元和/或扩展单元。
具体而言，主站单元中的主站时钟源同步模块可用于通过时钟源恢复模块获取1pps信号，且根据1pps信号进行主站与时钟源的频率同步。可选地，主站时钟源同步模块可设置于主站单元的基带电路中，例如FPGA等。进一步地，主站时钟源同步模块可通过主站传输模块将时钟信号发送给后级网元。此外，主站时钟源同步模块还可用于时延测量，测量与相邻网元间的时延。
主站处理模块可通过主站传输模块向后级网元发送查询信息，以使后级网元反馈时延数据；主站处理模块可基于反馈的时延数据进行计算，得到后级网元的时延计算结果并通过主站传输模块传输给对应的后级网元，以完成时延同步。可选地，主站时延计算模块可设置于主站单元的处理器中，例如微控制器等。
本申请实施例可基于主站单元中的基带电路和处理器，以及通信链路上的传输线路来完成频率同步和时延计算等，减少时钟源布线的施工难度和建设成本，提高稳定性。
在一个实施例中，如图5所示，主站时钟源同步模块包括用于获取1pps信号的主站时钟源检测单元，以及主站鉴相单元、主站控制单 元、主站数模压控转换单元、主站环路滤波器、主站晶振单元、主站定时产生器、主站锁相环和主站计数器。
主站时钟源检测单元通过主站鉴相单元连接主站控制单元；主站控制单元分别连接主站数模压控转换单元和主站定时产生器；主站数模压控转换单元依次通过主站环路滤波器和主站晶振单元连接主站锁相环；主站锁相环通过主站计数器连接主站鉴相单元。
具体而言，主站时钟源检测单元用于实现1pps脉冲检测、给出1pps信号存在指示。主站鉴相单元用于相位误差检测，得出本地时钟与输入参考信号相位差。主站控制单元用于时钟源初始同步，例如频偏补偿等，还可用于与主站定时产生器配合，实现10ms帧头同步和SFN(Single Frequency Network，单频网)同步(与1pps边界对齐)等；并且，主站控制单元还可用于根据PID算法计算主站数模压控转换单元的配置值。
主站数模压控转换单元用于精准电压值输出；主站环路滤波器用于环路滤波；主站晶振单元用于精准频率的输出；主站锁相环用于频率的锁定；主站计数器用于精准的频率分频，输出对应的频率给主站鉴相单元，以使主站鉴相单元将该频率与主站时钟源检测单元输出的频率进行比较，得到相位差。
基于上述结构，主站时钟源同步模块可快速根据1pps信号完成频率同步。
在一个实施例中，主站处理模块用于：
根据获取到的目标网元的链路处理时延、下行数据处理时延和上行数据处理时延，以及目标网元的上一级网元的上行链路时延和下行链路时延，计算得到目标网元的上行链路时延和下行链路时延；目标网元为接入主站单元的扩展单元或远端单元。
将目标网元的上行链路时延和下行链路时延发送给目标网元。
向最后一级的目标网元发送上行提前量和下行提前量，以使最后一级的目标网元获取上行时延缓存值与下行时延缓存值。
具体而言，主站处理模块在实现时延计算时，可先向目标网元发送查询信息，以使目标网元向主站处理模块传输链路处理时延、下行数据处理时延和上行数据处理时延等数据，进一步地，主站处理模块向目标网元的上一级网元发送查询信息，以使上一级网元向主站处理模块传输对应的上行链路时延和下行链路时延。主站处理模块基于获取到的数据，计算得到目标网元的上行链路时延和下行链路时延并发送给目标网元。基于此，主站单元可计算得到主站单元与接入该主站的目标网元之间的时延。并且，主站单元还需向最后一级的目标网元发送上行提前量和下行提前量，最后一级的目标网元可处理时延计算结果、主站单元的上行提前量和下行提前量，得到上行时延缓存值与下行时延缓存值，进而可配置寄存器，完成上下行帧同步。基于此，时延计算可集中设置于主站单元等基带单元上，简化后级网元的数据处理过程，且提高时延处理的稳定性。
在一个实施例中，主站处理模块还用于：
根据获取到的从站单元的链路处理时延、下行数据处理时延和上行数据处理时延，以及从站单元的上一级基带网元的上行链路时延和下行链路时延，计算得到从站单元的上行链路时延和下行链路时延。
将从站单元的上行链路时延和下行链路时延，以及上行提前量和下行提前量发送给从站单元，以使从站单元获取从站下行提前量和从站上行提前量。
具体而言，主站处理模块在实现从站单元的时延计算时，可先向从站单元发送查询信息，以使从站单元向主站处理模块传输链路处理时延、下行数据处理时延和上行数据处理时延等数据，进一步地，主站处理模块向从站单元的上一级基带网元发送查询信息，以使上一级基带网元向主站处理模块传输对应的上行链路时延和下行链路时延。主站处理模块基于获取到的数据，计算得到从站单元的上行链路时延和下行链路时延并发送给从站单元。基于此，主站单元可计算得到主站单元与从站单元之间的时延。并且，主站单元还向从站单元发送上行提前量和下行提前量；从站单元可处理时延计算结果、主站单元的上行提前量和下行提前量，得到从站单元的从站上行提前量和下行提前量，进而可实现该从站单元的后级网元的时延计算。
本申请实施例中，从站单元无需设置时钟源恢复模块即可实现对后级网元的时延计算和同步，减少时钟源布线的施工难度和建设成本，提高稳定性。
在一个实施例中，如图4所示，从站单元包括从站时钟源同步模块、从站处理模块和从站传输模块。
从站时钟源同步模块分别连接从站处理模块和从站传输模块，从站处理模块连接从站传输模块，从站传输模块通过光纤连接主站单元。
从站传输模块用于获取主站单元传输的CPRI信号。
从站时钟源同步模块用于在主站单元传输的CPRI信号中获取从站随路时钟，并根据从站随路时钟进行从站频率同步。
从站处理模块用于进行时延计算。
具体而言，从站单元中的从站时钟源同步模块可用于通过从站传输模块获取主站单元传输的CPRI信号，并从中恢复从站的随路时钟、进行时钟同步以及从站与主站的频率同步。可选地，从站时钟源同步模块可设置于从站单元的基带电路中，例如FPGA等。进一步地，从站时钟源同步模块可通过从站传输模块将时钟信号发送给后级网元。此外，从站时钟源同步模块还可用于时延测量，测量与相邻网元间的时延。
从站处理模块可通过从站传输模块向后级网元发送查询信息，以使后级网元反馈时延数据；从站处理模块可基于时延数据进行计算，得到后级网元的时延计算结果并通过从站传输模块传输给对应的后级网元，以完成时延同步。可选地，从站时延计算模块可设置于从站单元的处理器中，例如微控制器等。
本申请实施例可基于从站单元中的基带电路和处理器，以及通信链路上的传输线路来完成频率同步和时延计算等，减少时钟源布线的施工难度和建设成本，提高稳定性。
在一个实施例中，如图6所示，从站时钟源同步模块包括用于获取从站随路时钟的从站时钟源检测单元，以及从站鉴相单元、从站控制单元、从站数模压控转换单元、从站环路滤波器、从站晶振单元、从站定时产生器、从站锁相环和从站计数器。
从站时钟源检测单元通过从站鉴相单元连接从站控制单元；从站控制单元分别连接从站数模压控转换单元和从站定时产生器；从站数模压控转换单元依次通过从站环路滤波器和从站晶振单元连接从站锁相环；从站锁相环通过从站计数器连接从站鉴相单元。
具体而言，从站时钟源检测单元用于CPRI随路时钟检测和提取。从站鉴相单元用于相位误差检测，得出本地时钟与输入参考信号相位差。从站控制单元用于时钟源初始同步，例如频偏补偿等，还可用于与从站定时产生器配合，实现10ms帧头同步和SFN同步(与1pps边界对齐)等；并且，从站控制单元还可用于根据PID算法计算从站数模压控转换单元的配置值。
从站数模压控转换单元用于精准电压值输出；从站环路滤波器用于环路滤波；从站晶振单元用于精准频率的输出；从站锁相环用于频率的锁定；从站计数器用于精准的频率分频，输出与从站时钟源检测单元输出的对应频率。基于上述结构，从站时钟源同步模块可快速根据CPRI信号中的随路时钟完成频率同步。
在一个实施例中，从站处理模块用于：
根据获取到的目标网元的链路处理时延、下行数据处理时延和上行数据处理时延，以及目标网元的上一级网元的上行链路时延和下行链路时延，计算得到目标网元的上行链路时延和下行链路时延；目标网元为接入从站单元的扩展单元或远端单元。
将目标网元的上行链路时延和下行链路时延发送给目标网元。
向最后一级的目标网元发送上行提前量和下行提前量，以使最后一级的目标网元获取上行时延缓存值与下行时延缓存值。
具体而言，从站处理模块在实现时延计算时，可先向目标网元发送查询信息，以使目标网元向从站处理模块传输链路处理时延、下行数据处理时延和上行数据处理时延等数据，进一步地，从站处理模块向目标网元的上一级网元发送查询信息，以使上一级网元向从站处理模块传输对应的上行链路时延和下行链路时延。从站处理模块基于获取到的数据，计算得到目标网元的上行链路时延和下行链路时延并发送给目标网元。基于此，从站单元可计算得到从站单元与接入该从站的目标网元之间的时延。并且，从站单元还需向最后一级的目标网元发送上行提前量和下行提前量，最后一级的目标网元可处理时延计算结果、从站单元的上行提前量和下行提前量，得到上行时延缓存值与下行时延缓存值，进而可配置寄存器，完成上下行帧同步。基于此， 时延计算可集中设置于从站单元等基带单元上，简化后级网元的数据处理过程，且提高时延处理的稳定性。
在一个实施例中，如图4所示，扩展单元包括光路同步模块、扩展处理模块和扩展传输模块。
光路同步模块分别连接扩展处理模块和扩展传输模块，扩展处理模块连接扩展传输模块，扩展传输模块通过光纤连接主站单元或从站单元。
光路同步模块用于获取扩展随路时钟，并根据扩展随路时钟进行扩展单元频率同步。
扩展处理模块用于时延计算。
具体而言，光路同步模块用于光路同步；具体地，光路同步模块从扩展传输模块传输的CPRI信号中恢复随路时钟，进而实现扩展单元与基带单元的频率同步。扩展处理模块可用于计算与相邻网元的时延。示例性地，光路同步模块可设于扩展单元的基带电路中，扩展处理模块可设置与扩展单元的处理器中，此处不做具体限定。扩展传输模块用于实现扩展单元之间级联，还可用于连接远端单元；扩展传输模块可包括用于与级联扩展单元进行信号传输的第一传输单元，和用于与远端单元进行信号传输的第二传输单元。基于此，本申请实施例中，分布式基站中的扩展单元无需设置时钟源恢复模块即可实现频率同步，减少时钟源布线的施工难度和建设成本，提高稳定性。
在一个实施例中，如图7所示，光路同步模块包括用于获取扩展随路时钟的serdes时钟恢复单元、第一级时钟单元、第二级时钟单元、第一本地时钟和第二本地时钟。
serdes时钟恢复单元分别连接第一级时钟单元和第二级时钟单元；第一级时钟单元分别连接第一本地时钟和第二级时钟单元；第二级时钟单元连接第二本地时钟。
具体而言，serdes时钟恢复单元从CPRI信号中恢复随路时钟，并实现第二级时钟单元输出频率与CPRI随路时钟的鉴相和控制，输出稳定的随路时钟。serdes恢复的随路时钟作为第一级时钟单元的参考时钟；第一级时钟单元实现随路时钟与第一本地时钟的鉴相和控制，输出稳定的第一路时钟，并作为参考信号给到第二级时钟单元。第一路时钟作为第二级时钟单元的参考时钟，第二级时钟单元实现第一路时钟与第二本地时钟的鉴相和控制，输出稳定的本地随路时钟，并传输给到serdes恢复时钟单元。进一步地，第二级时钟单元还可输出其他时钟。基于此，本申请实施例可通过简单的结构实现扩展单元的光路同步。
在一个实施例中，如图4所示，远端单元包括末端同步模块、末端处理模块和末端传输模块。
末端同步模块分别连接末端处理模块和末端传输模块，末端处理模块连接末端传输模块，末端传输模块通过光纤或网线连接扩展单元。
末端同步模块用于获取末端随路时钟，并根据末端随路时钟进行 远端单元频率同步。
末端处理模块用于进行时延计算和时延同步。
具体而言，末端同步模块可从末端传输模块传输的CPRI信号或网络数据信号中恢复随路时钟，并实现远端单元与扩展单元的频率同步；末端处理模块可用于根据基带单元传输的链路时延和上下行提前量，计算得到上下行时延缓存值并配置相应的寄存器，以完成时延同步。
在一个实施例中，如图8所示，末端同步模块包括用于获取末端随路时钟的随路时钟恢复单元，以及末端鉴相单元、末端控制单元、末端数模转换单元、末端环路滤波器、末端晶振单元、末端锁相环和末端计数器。
随路时钟恢复单元通过末端鉴相单元连接末端控制单元；末端控制单元通过末端数模转换单元连接末端环路滤波器；末端环路滤波器通过末端晶振单元连接末端锁相环；末端锁相环通过末端计数器连接末端鉴相单元。
具体而言，随路时钟恢复单元用于根据CPRI信号或者网络数据信号恢复出随路时钟信号，并把恢复的随路时钟信号给到末端鉴相单元。末端鉴相单元用于相位误差检测，得出本地参考时钟与随路时钟的相位差。末端数模转换单元用于根据数模转换，输出电压值。末端环路滤波器单元用于环路滤波。末端晶振单元用于输出特定频率。末端锁相环用于频率锁定。末端计数器用于精准地频率分频，输出对应的频率给末端鉴相单元，以使末端鉴相单元将该频率与随路时钟恢复单元输出的频率进行比较，得到相位差。
在一个实施例中，末端处理模块用于根据主站单元或接入的从站单元传输的上行链路时延、下行链路时延、上行提前量和下行提前量，计算得到上行时延缓存值与下行时延缓存值并配置于寄存器中。
具体而言，在远端单元中，末端处理模块可通过末端传输模块获取基带单元的查询信息，并根据查询信息反馈相应的时延数据给基带单元；进一步地，末端处理模块通过末端传输模块获取基带单元的时延计算结果和上下行提前量，进而计算得到上下行时延缓存值并配置于寄存器中，完成上下行帧同步。
在一个实施例中，如图9所示，T_advance_DL为下行提前量，T_advance_UL为上行提前量，T1_14为第一级网元到第二级网元的链路时延，T2_14为第二级网元到第三级网元的链路时延，Tn-1_14为第n-1级网元到第n级网元的链路时延，T1_23为第一级网元到第二级网元两端口间的链路处理时延，T2_23为第二级网元到第三级网元两端口间的链路处理时延，Tn-1_23为第n-1级网元到第n级网元两端口间的链路处理时延，Td2为第二级网元下行数据处理时延，Tu2为第二级网元上行数据处理时延，Td3为第三级网元下行数据处理时延，Tu3为第三级网元上行数据处理时延，Tdn为第n级网元下行数据处理时延，Tun为第n级网元上行数据处理时延。
第二级网元接入第一级网元后，第一级网元时延计算模块发送查 询消息到第二级网元，第二级网元时延测量模块把链路处理时延T1_23、下行数据处理时延Td2、上行数据处理时延Tu2通过CPRI C&M通道发送给第一级网元，由第一级网元时延计算模块计算两网元间的链路时延(T1_14-T1_23)/2，时延计算模块再分别计算上行时延(T1_14-T1_23)/2+Tu2和下行时延(T1_14-T1_23)/2+Td2，并把计算结果发回给第二级网元。
第三级网元接入第一级网元后，第一级网元时延计算模块发送查询消息到第三级网元，第三级网元时延测量模块把链路处理时延T2_23、下行数据处理时延Td3、上行数据处理时延Tu3通过CPRI C&M通道发送给第一级网元，第一级网元时延计算模块发送查询消息到第二级网元，第二级网元时延测量模块把链路时延T2_14发送给第一级网元，由第一级网元时延计算模块计算两网元间的链路时延：(T1_14-T1_23)/2+(T2_14-T2_23)/2，时延计算模块再分别计算上行时延(T1_14-T1_23)/2+Tu2+(T2_14-T2_23)/2+Tu3和下行时延(T1_14-T1_23)/2+Td2+(T2_14-T2_23)/2+Td3，并把计算结果发回给第三级网元。
以此类推，当第n级网元接入第一级网元后，第一级网元时延计算模块发送查询消息到第n级网元，第n级网元时延测量模块把链路处理时延Tn-1_23、下行数据处理时延Tdn、上行数据处理时延Tun通过CPRIC&M通道发送给第一级网元，第一级网元时延计算模块发送查询消息到第n-1级网元，第n-1级网元时延测量模块把链路时延Tn-1_14发送给第一级网元，由第一级网元时延计算模块计算两网元间的链路时延：(T1_14-T1_23)/2+(T2_14-T2_23)/2+……+(Tn-1_14-Tn-1_23)/2，时延计算模块再分别计算上行时延(T1_14-T1_23)/2+Tu2+(T2_14-T2_23)/2+Tu3+……+(Tn-1_14-Tn-1_23)/2+Tun和下行时延(T1_14-T1_23)/2+Td2+(T2_14-T2_23)/2+Td3+……+(Tn-1_14-Tn-1_23)/2+Tdn，并把计算结果发回给第n级网元。
若第n级网元为最后一级网元，则第n级时延计算模块计算上行时延缓存值为：
Tu_buf＝T_advance_UL–{(T1_14-T1_23)/2+Tu2+(T2_14-T2_23)/2+Tu3+……+(Tn-1_14-Tn-1_23)/2+Tun}。
下行时延缓存值为：
Td_buf＝T_advance_DL–{(T1_14-T1_23)/2+Td2+(T2_14-T2_23)/2+Td3+……+(Tn-1_14-Tn-1_23)/2+Tdn}。
最后一级网元配置相应的FPGA寄存器即完成上下行帧同步。应该注意的是，时延测量模块可属于时钟源同步模块，设于基带电路中；时延计算模块可属于处理模块，设于基带单元的处理器中。
在一个实施例中，如图10所示，所有从站单元需接入主站单元并维持心跳；每级基带单元下扩展单元和远端单元接入该基带单元即可； 基带单元根据各网元上报的型号和级数判断网元类型和拓扑关系，并保存相关信息。
T_advance_DL为基带单元下行提前量，T_advance_UL为基带单元下行提前量。在主站下的扩展单元接入主站后，主站时延计算模块发送查询消息到该扩展单元，扩展单元上传链路处理时延(Tau-cp1、Tcp1-cp2……Tcp(n-1)-cp(n))、下行数据处理时延(Tdcp1、Tdcp2……Tdcpn)和上行数据处理时延(Tucp1、Tucp2……Tucpn)，主站发送查询消息到其上一级级联扩展单元，上一级级联扩展单元时延测量模块上报链路时延，由主站时延计算模块计算主站到扩展单元N间的下行链路时延：
Tau-cp1+Tdcp1+……+Tcp(n-1)-cp(n)+Tdcpn；
上行链路时延：
Tau-cp1+Tucp1+……+Tcp(n-1)-cp(n)+Tucpn。
该扩展单元下的远端接入主站后，主站时延计算模块发送查询消息到该远端单元，远端单元上传链路处理时延、下行数据处理时延和上行数据处理时延，主站发送查询消息到其上一级扩展单元，上一级扩展单元时延测量模块上报链路时延，由主站单元计算模块计算主站到远端单元M间的下行链路时延：
Tau-cp1+Tdcp1+……+Tcp(n-1)-cp(n)+Tdcpn+Tcp(n)-dp(m)+Tddpm；
上行链路时延：
Tau-cp1+Tucp1+……+Tcp(n-1)-cp(n)+Tucpn+Tcp(n)-dp(m)+Tudpm。
并把时延计算结果、连同T_advance_DL和T_advance_UL发回给远端单元M，则远端单元时延计算模块计算上行时延缓存值为：
Tu_buf＝T_advance_UL–{Tau-cp1+Tdcp1+……+Tcp(n-1)-cp(n)+Tdcpn+Tcp(n)-dp(m)+Tddpm}；
下行时延缓存值为：
Td_buf＝T_advance_DL–{Tau-cp1+Tucp1+……+Tcp(n-1)-cp(n)+Tucpn+Tcp(n)-dp(m)+Tudpm}。
远端单元M配置相应的FPGA寄存器即完成上下行帧同步。
在一个实施例中，如图10所示，从站接入主站后，主站时延计算模块发送查询消息到该从站，从站上传链路处理时延(Tmau-sau1……Tsau(y-1)-sau(y))、下行数据处理时延(Tdau1……Tdauy)和上行数据处理时延(Tuau1……Tuauy)；主站发送查询消息到其上一级级联基带单元，上一级级联基带单元时延测量模块上报链路时延，由主站单元计算模块计算主站到从站N间的下行链路时延：
Tmau-sau1+Tdau1+Tsau(y-1)-sau(y)+Tdauy；
上行链路时延：
Tmau-sau1+Tuau1+Tsau(y-1)-sau(y)+Tuauy。
并把时延计算结果、连同T_advance_DL、T_advance_UL发回给 从站Y，则从站计算从站的下行提前量‘T_advance_DL：
‘T_advance_DL＝T_advance_DL–{Tau-cp1+Tdcp1+…+Tcp(n-1)-cp(n)+Tdcpn+Tcp(n)-dp(m)+Tddpm}；
从站的下行提前量‘T_advance_UL：
‘T_advance_UL＝T_advance_UL–{Tmau-sau1+Tuau1+Tsau(y-1)-sau(y)+Tuauy}，作为从站的上行提前量。
则从站下扩展单元、远端单元与主站下的扩展单元、远端单元时延配置流程完全相同，只是系统提前量T_advance_DL、T_advance_UL与’T_advance_DL、’T_advance_UL的区别，此处不再赘述。
工业实用性
本公开实施例提供的该分布式多网元时钟传输系统中，由主站单元获取1pps信号进行频率同步，后级的从站单元、扩展单元和远端单元根据主站单元传输的信号获取随路时钟，进而可实现各单元的频率同步；并且，作为主机的主站单元和从站单元可进行时延计算，并将时延计算结果传输给对应的远端单元，以完成系统的时延同步。可减少时钟源布线施工难度和建设成本、提高时钟传递稳定性，具有很强的工业实用性。

Claims (12)

  1. 一种分布式多网元时钟传输系统，其特征在于，包括：
    主站单元，用于通过时钟源恢复模块获取1pps信号，并根据所述1pps信号进行主站频率同步，且用于时延计算；
    从站单元，通过光纤连接所述主站单元；所述从站单元用于在所述主站单元传输的CPRI信号中获取从站随路时钟，并根据所述从站随路时钟进行从站频率同步，且用于时延计算；
    扩展单元，通过光纤连接所述主站单元或所述从站单元；所述扩展单元用于在所述主站单元传输的CPRI信号中或所述从站单元传输的CPRI信号中获取扩展随路时钟，并根据所述扩展随路时钟进行扩展单元频率同步；
    远端单元，通过光纤或网线连接所述扩展单元；所述远端单元用于在所述扩展单元传输的CPRI信号或网络数据信号中获取末端随路时钟，并根据所述末端随路时钟进行远端单元频率同步，且用于根据所述主站单元或接入的所述从站单元传输的时延计算结果进行时延同步。
  2. 根据权利要求1所述的分布式多网元时钟传输系统，其特征在于，
    所述主站单元包括主站时钟源同步模块、主站处理模块和主站传输模块；
    所述主站时钟源同步模块分别连接所述主站处理模块和所述主站传输模块，
    所述主站处理模块连接所述主站传输模块；
    所述主站时钟源同步模块用于获取所述1pps信号，并根据所述1pps信号进行所述主站频率同步；
    所述主站处理模块用于进行时延计算；
    所述主站传输模块用于通过光纤连接所述从站单元和/或所述扩展单元。
  3. 根据权利要求2所述的分布式多网元时钟传输系统，其特征在于，所述主站时钟源同步模块包括用于获取所述1pps信号的主站时钟源检测单元，以及主站鉴相单元、主站控制单元、主站数模压控转换单元、主站环路滤波器、主站晶振单元、主站定时产生器、主站锁相环和主站计数器；
    所述主站时钟源检测单元通过所述主站鉴相单元连接所述主站控制单元；所述主站控制单元分别连接所述主站数模压控转换单元和所述主站定时产生器；所述主站数模压控转换单元依次通过所述主站环路滤波器和所述主站晶振单元连接所述主站锁相环；所述主站锁相环通过所述主站计数器连接所述主站鉴相单元。
  4. 根据权利要求2所述的分布式多网元时钟传输系统，其特征在于，
    所述主站处理模块用于：
    根据获取到的目标网元的链路处理时延、下行数据处理时延和上行数据处理时延，以及所述目标网元的上一级网元的上行链路时延和下行链路时延，计算得到所述目标网元的上行链路时延和下行链路时延；所述目标网元为接入所述主站单元的所述扩展单元或所述远端单元；
    将所述目标网元的上行链路时延和下行链路时延发送给所述目标网元；
    向最后一级的目标网元发送上行提前量和下行提前量，以使所述最后一级的目标网元获取上行时延缓存值与下行时延缓存值。
  5. 根据权利要求2所述的分布式多网元时钟传输系统，其特征在于，
    所述主站处理模块还用于：
    根据获取到的所述从站单元的链路处理时延、下行数据处理时延和上行数据处理时延，以及所述从站单元的上一级基带网元的上行链路时延和下行链路时延，计算得到所述从站单元的上行链路时延和下行链路时延；
    将所述从站单元的上行链路时延和下行链路时延，以及上行提前量和下行提前量发送给所述从站单元，以使所述从站单元获取从站下行提前量和从站上行提前量。
  6. 根据权利要求1所述的分布式多网元时钟传输系统，其特征在于，
    所述从站单元包括从站时钟源同步模块、从站处理模块和从站传输模块；
    所述从站时钟源同步模块分别连接所述从站处理模块和所述从站传输模块，
    所述从站处理模块连接所述从站传输模块，所述从站传输模块通过光纤连接所述主站单元；
    所述从站传输模块用于获取所述主站单元传输的CPRI信号；
    所述从站时钟源同步模块用于在所述主站单元传输的CPRI信号中获取所述从站随路时钟，并根据所述从站随路时钟进行所述从站频率同步；
    所述从站处理模块用于进行时延计算。
  7. 根据权利要求6所述的分布式多网元时钟传输系统，其特征在于，所述从站时钟源同步模块包括用于获取所述从站随路时钟的从站时钟源检测单元，以及从站鉴相单元、从站控制单元、从站数模压控转换单元、从站环路滤波器、从站晶振单元、从站定时产生器、从站锁相环和从站计数器；
    所述从站时钟源检测单元通过所述从站鉴相单元连接所述从站控制单元；所述从站控制单元分别连接所述从站数模压控转换单元和所述从站定时产生器；所述从站数模压控转换单元依次通过所述从站环 路滤波器和所述从站晶振单元连接所述从站锁相环；所述从站锁相环通过所述从站计数器连接所述从站鉴相单元。
  8. 根据权利要求1所述的分布式多网元时钟传输系统，其特征在于，所述扩展单元包括光路同步模块、扩展处理模块和扩展传输模块；
    所述光路同步模块分别连接所述扩展处理模块和所述扩展传输模块，所述扩展处理模块连接所述扩展传输模块，所述扩展传输模块通过光纤连接所述主站单元或所述从站单元；
    所述光路同步模块用于获取扩展随路时钟，并根据所述扩展随路时钟进行所述扩展单元频率同步；
    所述扩展处理模块用于时延计算。
  9. 根据权利要求8所述的分布式多网元时钟传输系统，其特征在于，所述光路同步模块包括用于获取所述扩展随路时钟的serdes时钟恢复单元、第一级时钟单元、第二级时钟单元、第一本地时钟和第二本地时钟；
    所述serdes时钟恢复单元分别连接所述第一级时钟单元和所述第二级时钟单元；所述第一级时钟单元分别连接所述第一本地时钟和所述第二级时钟单元；所述第二级时钟单元连接所述第二本地时钟。
  10. 根据权利要求1所述的分布式多网元时钟传输系统，其特征在于，所述远端单元包括末端同步模块、末端处理模块和末端传输模块；
    所述末端同步模块分别连接所述末端处理模块和所述末端传输模块，所述末端处理模块连接所述末端传输模块，所述末端传输模块通过光纤或网线连接所述扩展单元；
    所述末端同步模块用于获取末端随路时钟，并根据所述末端随路时钟进行所述远端单元频率同步；
    所述末端处理模块用于进行时延计算和时延同步。
  11. 根据权利要求10所述的分布式多网元时钟传输系统，其特征在于，所述末端同步模块包括用于获取所述末端随路时钟的随路时钟恢复单元，以及末端鉴相单元、末端控制单元、末端数模转换单元、末端环路滤波器、末端晶振单元、末端锁相环和末端计数器；
    所述随路时钟恢复单元通过所述末端鉴相单元连接所述末端控制单元；所述末端控制单元通过所述末端数模转换单元连接所述末端环路滤波器；所述末端环路滤波器通过所述末端晶振单元连接所述末端锁相环；所述末端锁相环通过所述末端计数器连接所述末端鉴相单元。
  12. 根据权利要求10所述的分布式多网元时钟传输系统，其特征在于，
    所述末端处理模块用于根据所述主站单元或接入的所述从站单元传输的上行链路时延、下行链路时延、上行提前量和下行提前量，计算得到上行时延缓存值与下行时延缓存值并配置于寄存器中。
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