WO2021131897A1 - Solder bump forming member, method for manufacturing solder bump forming member, and method for manufacturing electrode substrate provided with solder bump - Google Patents

Solder bump forming member, method for manufacturing solder bump forming member, and method for manufacturing electrode substrate provided with solder bump Download PDF

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Publication number
WO2021131897A1
WO2021131897A1 PCT/JP2020/046731 JP2020046731W WO2021131897A1 WO 2021131897 A1 WO2021131897 A1 WO 2021131897A1 JP 2020046731 W JP2020046731 W JP 2020046731W WO 2021131897 A1 WO2021131897 A1 WO 2021131897A1
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Prior art keywords
solder
substrate
particles
recess
bumps
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PCT/JP2020/046731
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French (fr)
Japanese (ja)
Inventor
純一 畠
邦彦 赤井
勝将 宮地
芳則 江尻
Original Assignee
昭和電工マテリアルズ株式会社
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Application filed by 昭和電工マテリアルズ株式会社 filed Critical 昭和電工マテリアルズ株式会社
Priority to CN202080097284.4A priority Critical patent/CN115152007A/en
Priority to JP2021567299A priority patent/JPWO2021131897A1/ja
Priority to KR1020227023758A priority patent/KR20220122663A/en
Publication of WO2021131897A1 publication Critical patent/WO2021131897A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81091—Under pressure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81095—Temperature settings
    • H01L2224/81096—Transient conditions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8191—Cleaning, e.g. oxide removal step, desmearing

Definitions

  • the present invention relates to a solder bump forming member, a method for manufacturing a solder bump forming member, and a method for manufacturing an electrode substrate with solder bumps.
  • solder ball arrangement sheet is known (see, for example, Patent Document 1).
  • a method for manufacturing a solder bump forming sheet in which a solder ball or a solder powder is held at a predetermined position including the following steps is known (see, for example, Patent Document 2).
  • A. Prepare a sheet on one side with a number of recesses in place, the bottom of which is made of an adhesive;
  • B. Each recess of the sheet is filled with solder powder, and the adhesive on the bottom of the recess adheres and holds the solder powder;
  • the solder powder that is not held by the adhesive is removed from the sheet, and D.I. Cover the solder powder in the recesses of the sheet.
  • a method of forming solder bumps on an electrode by transferring a solder ball arranged in a groove to an adhesive roll surface and further transferring the solder ball to an adhesive on an electrode is known (for example, Patent Documents). 3).
  • the transfer sheet and the manufacturing method shown in Patent Documents 1 and 2 require an adhesive layer for holding the solder particles. Therefore, the adhesive layer component may be softened, melted, and decomposed to become a contaminant by heating above the melting point of the solder to melt and coalesce the solder, and further to transfer the solder onto the electrode.
  • the presence of contaminants between the solder and the electrodes may hinder the stable formation of solder bumps.
  • the substrate and semiconductor package on which the electrodes are formed are exposed to the cleaning liquid, resulting in an increase in processes, defects in the substrate / semiconductor package, and poor cleaning. There is a risk that problems will occur.
  • the adhesive component may remain on the surface of the solder balls and cause a problem in joining. Further, the thickness of the pressure-sensitive adhesive and the unevenness of the surface of the pressure-sensitive adhesive can be controlled when the size of the solder ball is about 100 ⁇ m, but it becomes more difficult as the size becomes smaller as 50 ⁇ m and 30 ⁇ m. Therefore, if solder balls (particles) having a size of less than 30 ⁇ m are transferred and moved via an adhesive, it becomes difficult to increase the transfer rate.
  • the present invention has been made in view of the above circumstances, and manufactures a connection structure having excellent insulation reliability and conduction reliability even if the connection points of circuit members to be electrically connected to each other are minute. It is an object of the present invention to provide a member for forming a solder bump and a method for manufacturing the same. Another object of the present invention is to provide a method for manufacturing an electrode substrate with solder bumps using the member.
  • One aspect of the present invention includes a substrate having a plurality of recesses, solder particles and a fluidizing agent in the recesses, and the average particle size of the solder particles is 1 to 35 ⁇ m. V.
  • the present invention relates to a solder bump forming member having a value of 20% or less.
  • the solder bump forming member is useful for manufacturing a connection structure having excellent insulation reliability and conduction reliability even if the connection points of the circuit members to be electrically connected to each other are minute.
  • the fluidizing agent may include at least one selected from the group consisting of succinic acid, glutaric acid, adipic acid, pimelic acid, suberic acid, benzoic acid, and malic acid.
  • a flat surface portion may be formed on a part of the surface of the solder particles.
  • the distance between adjacent recesses may be 0.1 times or more the average particle size of the solder particles.
  • One aspect of the present invention includes a substrate having a plurality of recesses, a pre-step of preparing solder particles and a fluidizing agent, and an arranging step of arranging the solder particles and the fluidizing agent in the recesses, for forming solder bumps.
  • the present invention relates to a manufacturing method of a member.
  • One aspect of the present invention is to fuse a preparatory step for preparing a substrate having a plurality of recesses and solder fine particles, a storage step for storing at least a part of the solder fine particles in the recesses, and a solder fine particles housed in the recesses.
  • the present invention relates to a method for manufacturing a solder bump forming member, comprising a fusion step of forming solder particles in the recesses and an injection step of arranging a fluidizing agent in the recesses in which the solder particles are formed.
  • the average particle size of the solder particles is 1 to 35 ⁇ m, and C.I. V. The value may be 20% or less.
  • C.I. V. In one aspect of the method for manufacturing a member for forming a solder bump, C.I. V. The value may exceed 20%.
  • One aspect of the method for manufacturing the solder bump forming member may further include a reduction step of exposing the solder fine particles contained in the recesses to a reducing atmosphere before the fusion step.
  • the solder fine particles may be fused in a reducing atmosphere in the fusion step.
  • One aspect of the present invention is a preparatory step for preparing the solder bump forming member and a substrate having a plurality of electrodes, and a surface having a recess of the solder bump forming member and a surface having electrodes of the substrate are opposed to each other.
  • the present invention relates to a method for manufacturing an electrode substrate with solder bumps, which comprises an arrangement step of contacting the solder particles and a heating step of heating the solder particles to a temperature equal to or higher than the melting point of the solder particles.
  • the solder particles may be heated to a temperature equal to or higher than the melting point of the solder particles while contacting the solder bump forming member and the substrate in a pressurized state.
  • One aspect of the method for manufacturing an electrode substrate with solder bumps may further include a reduction step of exposing the solder particles to a reducing atmosphere before the placement step.
  • One aspect of the method for manufacturing an electrode substrate with solder bumps may further include a reduction step of exposing the solder particles to a reducing atmosphere after the placement step and before the heating step.
  • the solder particles may be heated to a temperature equal to or higher than the melting point of the solder particles in a reducing atmosphere.
  • One aspect of the method for manufacturing an electrode substrate with solder bumps may further include a removal step of removing the solder bump forming member from the substrate after the heating step.
  • One aspect of the method for manufacturing an electrode substrate with solder bumps may further include a cleaning step of removing solder particles that are not bonded to the electrodes after the removal step.
  • a member and a method for manufacturing the member can be provided. Further, according to the present invention, it is possible to provide a method for manufacturing an electrode substrate with solder bumps using the member.
  • FIG. 1 is a cross-sectional view schematically showing a solder bump forming member according to an embodiment.
  • FIG. 2A is a view of the solder particles viewed from the side opposite to the opening of the recess in FIG. 1, and
  • FIG. 2B is a quadrangle circumscribing the projected image of the solder particles created by two pairs of parallel lines. It is a figure which shows the distance X and Y (where Y ⁇ X) between the opposite sides in the case of.
  • FIG. 3A is a plan view schematically showing an example of the substrate, and FIG. 3B is a cross-sectional view taken along the line Ib-Ib of FIG. 3A.
  • FIG. 4 (a) to 4 (h) are cross-sectional views schematically showing an example of the cross-sectional shape of the concave portion of the substrate.
  • FIG. 5 is a cross-sectional view schematically showing a state in which solder fine particles are contained in the recesses of the substrate.
  • 6 (a) and 6 (b) are cross-sectional views schematically showing an example of a manufacturing process of an electrode substrate with solder bumps.
  • 7 (a) and 7 (b) are cross-sectional views schematically showing an example of a manufacturing process of the connection structure.
  • FIG. 8 is a cross-sectional view schematically showing an example of the substrate.
  • each component in the composition means the total amount of the plurality of substances present in the composition when a plurality of substances corresponding to each component are present in the composition, unless otherwise specified.
  • the numerical range indicated by using "-" indicates a range including the numerical values before and after "-" as the minimum value and the maximum value, respectively.
  • the upper limit value or the lower limit value of the numerical range of one step may be replaced with the upper limit value or the lower limit value of the numerical range of another step.
  • the upper limit value or the lower limit value of the numerical range may be replaced with the value shown in the examples.
  • solder bump forming member includes a substrate having a plurality of recesses, solder particles and a fluidizing agent in the recesses, and the average particle size of the solder particles is 1 to 35 ⁇ m. V. The value is 20% or less.
  • FIG. 1 is a cross-sectional view schematically showing a solder bump forming member according to an embodiment.
  • the solder bump forming member 10 includes a substrate 60 having a plurality of recesses 62, and solder particles 1 and a fluidizing agent F in the recesses 62.
  • one solder particle 1 is arranged so as to be arranged in a horizontal direction (horizontal direction in FIG. 1) in a state of being separated from one adjacent solder particle 1.
  • the solder particles 1 may be in contact with the side surface and / or the bottom surface thereof in the recess 62.
  • the fluidizing agent F may be present between the solder particles 1 and the bottom surface of the recess 62.
  • the solder bump forming member may be in the form of a film (solder bump forming film), sheet form (solder bump forming sheet), or the like.
  • solder particles The average particle size of the solder particles 1 is, for example, 35 ⁇ m or less, preferably 30 ⁇ m or less, 25 ⁇ m or less, 20 ⁇ m or less, or 15 ⁇ m or less.
  • the average particle size of the solder particles 1 is, for example, 1 ⁇ m or more, preferably 2 ⁇ m or more, more preferably 3 ⁇ m or more, and further preferably 5 ⁇ m or more.
  • the average particle size of the solder particles 1 can be measured by using various methods according to the size. For example, a dynamic light scattering method, a laser diffraction method, a centrifugal sedimentation method, an electrical detection band method, a resonance type mass measurement method, or the like can be used. Further, a method of measuring the particle size from an image obtained by an optical microscope, an electron microscope, or the like can be used. Specific devices include a flow-type particle image analyzer, a microtrack, a Coulter counter, and the like.
  • the average particle diameter of the solder particles 1 is the diameter equivalent to the projected area circle (a circle having an area equal to the projected area of the particles) when the solder particles 1 are observed from a direction perpendicular to the main surface of the solder bump forming member 10. Diameter).
  • C. of solder particles 1 V The value is preferably 20% or less, more preferably 10% or less, still more preferably 7% or less, from the viewpoint of achieving more excellent conductivity reliability and insulation reliability.
  • the lower limit of the value is not particularly limited.
  • C.I. V. The value may be 1% or more, and may be 2% or more.
  • FIG. 2A is a view of the solder particles 1 viewed from the side opposite to the opening of the recess 62 in FIG.
  • the solder particles 1 have a shape in which a flat surface portion 11 having a diameter A is formed on a part of the surface of a sphere having a diameter B.
  • the solder particles 1 shown in FIGS. 1 and 2A have a flat surface portion 11 because the bottom portion of the recess 62 is flat, but when the bottom portion of the recess 62 has a shape other than a flat surface, the shape of the bottom portion is formed. It will have a surface with a different shape corresponding to.
  • a flat surface portion 11 may be formed on a part of the surface of the solder particles 1, and at this time, the surface other than the flat surface portion 11 is preferably spherical crown-shaped. That is, the solder particles 1 may have a flat surface portion 11 and a spherical crown-shaped curved surface portion.
  • the ratio (A / B) of the diameter A of the flat surface portion 11 to the diameter B of the solder particles 1 may be, for example, more than 0.01 and less than 1.0 (0.01 ⁇ A / B ⁇ 1.0), and is 0. It may be 1 to 0.9.
  • the flat surface portion 11 and the bottom surface of the recess 62 may be in contact with each other. As shown in FIG.
  • the solder particles 1 since the solder particles 1 have the flat surface portion 11 and the flat surface portion and the bottom surface of the recess are in contact with each other, the solder particles 1 are less likely to be detached from the solder bump forming member 10. ..
  • the flat surface portion may also be generated at a portion where the inner wall portion of the recess 62 and the solder particles 1 are in contact with each other.
  • the flat surface portion 11 is used. It does not necessarily have to be in contact with the bottom surface of the recess 62.
  • the ratio of Y to X (Y).
  • / X) may be more than 0.8 and less than 1.0 (0.8 ⁇ Y / X ⁇ 1.0), and may be 0.9 or more and less than 1.0.
  • solder particles 1 can be said to be particles closer to a true sphere. Since the solder particles 1 are close to a true sphere, the contact between the solder particles 1 and the electrodes is less likely to be uneven, and a stable connection tends to be obtained.
  • FIG. 2B is a diagram showing distances X and Y (where Y ⁇ X) between opposite sides when a quadrangle circumscribing the projected image of the solder particles is created by two pairs of parallel lines.
  • a quadrangle circumscribing the projected image of the solder particles is created by two pairs of parallel lines.
  • an arbitrary particle is observed with a scanning electron microscope to obtain a projected image.
  • Two pairs of parallel lines are drawn with respect to the obtained projected image, and the pair of parallel lines are arranged at the position where the distance between the parallel lines is the minimum, and the other pair of parallel lines are arranged at the position where the distance between the parallel lines is the maximum.
  • Find the Y / X of the particle This operation is performed on 300 solder particles, the average value is calculated, and the Y / X of the solder particles is obtained.
  • the solder particles 1 may contain tin or a tin alloy.
  • tin alloy for example, In—Sn alloy, In—Sn—Ag alloy, Sn—Au alloy, Sn—Bi alloy, Sn—Bi—Ag alloy, Sn—Ag—Cu alloy, Sn—Cu alloy and the like are used. be able to. Specific examples of these tin alloys include the following examples.
  • the solder particles may contain indium or an indium alloy.
  • the indium alloy for example, an In—Bi alloy, an In—Ag alloy, or the like can be used. Specific examples of these indium alloys include the following examples. -In-Bi (In66.3% by mass, Bi33.7% by mass, melting point 72 ° C.) -In-Bi (In33.0% by mass, Bi67.0% by mass, melting point 109 ° C) -In-Ag (In97.0% by mass, Ag3.0% by mass, melting point 145 ° C)
  • the tin alloy or indium alloy can be selected according to the application (temperature at the time of connection) of the solder particles 1.
  • an In—Sn alloy or a Sn—Bi alloy may be adopted, and in this case, the solder particles can be fused at 150 ° C. or lower.
  • a material having a high melting point such as Sn—Ag—Cu alloy or Sn—Cu alloy is used, high reliability can be maintained even after being left at a high temperature.
  • the solder particles 1 may contain one or more selected from Ag, Cu, Ni, Bi, Zn, Pd, Pb, Au, P and B.
  • Ag or Cu may be contained from the following viewpoints. That is, when the solder particles 1 contain Ag or Cu, the melting point of the solder particles 1 can be lowered to about 220 ° C., and the bonding strength with the electrodes is further improved, so that better conduction reliability can be obtained. It becomes easy to obtain.
  • the Cu content of the solder particles 1 is, for example, 0.05 to 10% by mass, and may be 0.1 to 5% by mass or 0.2 to 3% by mass.
  • the Cu content is 0.05% by mass or more, it becomes easy to achieve better solder connection reliability.
  • the solder particles 1 have a low melting point and excellent wettability, and as a result, the connection reliability of the joint portion by the solder particles 1 tends to be good.
  • the Ag content of the solder particles 1 is, for example, 0.05 to 10% by mass, and may be 0.1 to 5% by mass or 0.2 to 3% by mass.
  • the Ag content is 0.05% by mass or more, it becomes easy to achieve better solder connection reliability.
  • the Ag content is 10% by mass or less, the solder particles 1 have a low melting point and excellent wettability, and as a result, the connection reliability of the joint portion by the solder particles 1 tends to be good.
  • the fluidizing agent F has a function of flowing as a fluid phase during reflow and pushing out the solder particles 1 from the recess 62 toward the electrode side.
  • the fluidizing agent F may be a flux, an organic solvent, or the like. The flux has the effect of dissolving the oxides on the surface of the solder particles and the surface of the electrode to improve the wettability of the solder on the electrode.
  • the boiling point of the fluidizing agent F may be higher than the melting point of the solder.
  • the boiling point of the fluidizing agent F is higher than the melting point of the solder, so that the fluidizing agent F flows in the recess, and the solder particles also flow as the fluidizing agent F flows. To do.
  • the flow of the fluidizing agent F and the solder particles facilitates contact between the electrode surface and the solder particles, and as a result, the formation of solder bumps is promoted.
  • the solder bumps are formed on the electrodes when the heating temperature is at least higher than the melting point of the solder particles, higher than the softening point or melting point of the fluidizing agent F, and lower than the boiling point of the fluidizing agent F. It becomes easy to be formed.
  • the heating temperature is raised above the boiling point of the fluidizing agent F after the solder bumps are sufficiently formed, the residue derived from the fluidizing agent F on the surface of the substrate and the surface of the electrode can be reduced.
  • Various organic solvents that can be used for the fluidizing agent F include cyclohexane (boiling point: 80 ° C.), cycloheptane (boiling point: 118 ° C.), cyclooctane (boiling point: 149 ° C.), heptane (boiling point: 98 ° C.), and octane (boiling point: boiling point).
  • Nonan (boiling point: 150 ° C), Decane (boiling point: 174 ° C), Undecane (boiling point: 196 ° C), Dodecan (boiling point: 215 ° C), Tridecane (boiling point: 234 ° C), Tetradecane (boiling point: 254 ° C) ), Pentadecane (boiling point: 269 ° C), hexadecane (boiling point: 287 ° C), heptadecane (boiling point: 302 ° C), octadecane (boiling point: 317 ° C), nonadecan (boiling point: 330 ° C) and other aliphatic hydrocarbons can be used.
  • These aliphatic hydrocarbons are non-polar and do not have a reducing function for solder and metals used for electrodes such as Au and Cu, but can be appropriately selected as a solvent having a boiling point equal to or higher than the melting point of solder, and can be appropriately selected by heating. It has the function of flowing the solder particles and bringing the solder particles into contact with the electrode surface.
  • Examples of various organic solvents that can be used for the fluidizing agent F include pentanol, hexanol, heptanol, octanol, decanol, ethylene glycol, diethylene glycol, propylene glycol, butylene glycol, ⁇ -terpineol, isobornylcyclohexanol (MTPH) and the like.
  • Monovalent and polyhydric alcohols ethylene glycol butyl ether, ethylene glycol phenyl ether, diethylene glycol methyl ether, diethylene glycol ethyl ether, diethylene glycol butyl ether, diethylene glycol isobutyl ether, diethylene glycol hexyl ether, triethylene glycol methyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, Diethylene glycol dibutyl ether, diethylene glycol butyl methyl ether, diethylene glycol isopropyl methyl ether, triethylene glycol dimethyl ether, triethylene glycol butyl methyl ether, propylene glycol propyl ether, dipropylene glycol methyl ether, dipropylene glycol ethyl ether, dipropylene glycol propyl ether, dipropylene glycol Ethers such as propylene glycol butyl ether, dipropylene glycol dimethyl ether, triprop
  • Examples of mercaptans having an alkyl group having 1 to 18 carbon atoms include ethyl mercaptan, n-propyl mercaptan, i-propyl mercaptan, n-butyl mercaptan, i-butyl mercaptan, t-butyl mercaptan, pentyl mercaptan, and hexyl mercaptan. And dodecyl mercaptan.
  • Examples of mercaptans having a cycloalkyl group having 5 to 7 carbon atoms include cyclopentyl mercaptan, cyclohexyl mercaptan and cycloheptyl mercaptan.
  • Other examples of the organic solvent include alicyclic amines such as monoalkylamines, dialkylamines, trialkylamines, alkanolamines, cyclohexylamines and dicyclohexylamines, and aromatic amines such as diphenylamines and triphenylamines.
  • examples of the organic solvent include ethylene diethanolamine, n-butyl diethanolamine, diethanolamine, N, N-bis (2-hydroxyethyl) isopropanolamine and the like.
  • a glycol ether-based solvent can also be used.
  • the solvent having a boiling point of 200 ° C. or lower include dipropylene glycol monomethyl ether, propylene glycol monobutyl ether, diethylene glycol dimethyl ether, ethylene glycol monoallyl ether, and ethylene glycol monoisopropyl ether. Solvents having a boiling point exceeding 200 ° C.
  • glycol monohexyl ether examples include ethylene glycol monohexyl ether, diethylene glycol monohexyl ether, triethylene glycol monomethyl ether, ethylene glycol mono-2-ethylhexyl ether, diethylene glycol mono-2-ethylhexyl ether, diethylene glycol dibutyl ether, and triethylene.
  • Glycolbutylmethyl ether, tetraethylene glycol dimethyl ether and the like can be mentioned.
  • a flux that is generally used for solder bonding or the like can be used.
  • the flux can be appropriately selected according to the composition of the solder particles, the melting point, the surface condition, the heating / atmosphere conditions at the time of transfer, and the like.
  • zinc chloride, a mixture of zinc chloride and an inorganic halide, a mixture of zinc chloride and an inorganic acid, a molten salt, phosphoric acid, a derivative of phosphoric acid, an organic halide, hydrazine, an organic acid, pine fat and the like can be mentioned. These may be used alone or in combination of two or more.
  • Examples of the molten salt include ammonium chloride.
  • Examples of the organic acid include lactic acid, citric acid, stearic acid, glutamic acid, glutaric acid and the like.
  • Examples of the organic acid that can be used for the flux include an organic acid having 8 to 16 carbon atoms.
  • Examples of organic acids having 8 to 16 carbon atoms include capric acid, methylheptanic acid, ethylhexanoic acid, propylpentanoic acid, pelargonic acid, methyloctanoic acid, ethylheptanoic acid, propylhexanoic acid, capric acid, methylnonanoic acid and ethyl.
  • Saturated fatty acids Saturated fatty acids; octenoic acid, nonenic acid, methylnonenic acid, decenoic acid, undecenoic acid, dodecenoic acid, tridecenoic acid, tetradecenoic acid, myristoleic acid, pentadecenoic acid, hexadecenoic acid, palmitreic acid, sapienoic acid and other unsaturated fatty acids; terephthal Aromas such as acid, pyromellitic acid, o-phenoxy benzoic acid, methyl benzoic acid, ethyl benzoic acid, propyl benzoic acid, butyl benzoic acid, pentyl benzoic acid, hexyl benzoic acid, heptyl benzoic acid, octyl benzoic acid, nonyl benzoic acid
  • Group carboxylic acids include.
  • pine fat include activated pine fat and non-activated pine fat.
  • Pine fat is a rosin whose main component is abietic acid.
  • the melting point of the flux may be 50 ° C. or higher, 70 ° C. or higher, or 80 ° C. or higher.
  • the melting point of the flux may be 200 ° C. or lower, 160 ° C. or lower, 150 ° C. or lower, or 140 ° C. or lower.
  • the melting point range of the flux may be 80 to 190 ° C. and may be 80 to 140 ° C. or lower.
  • Fluxes having a melting point in the range of 80 to 190 ° C include succinic acid (melting point 186 ° C), glutaric acid (melting point 96 ° C), adipic acid (melting point 152 ° C), pimeric acid (melting point 104 ° C), and suberic acid (melting point 104 ° C).
  • Dicarboxylic acids such as 142 ° C., benzoic acid (melting point 122 ° C.), malic acid (melting point 130 ° C.) and the like can be mentioned.
  • the fluidizing agent may include at least one selected from the group consisting of succinic acid, glutaric acid, adipic acid, pimelic acid, suberic acid, benzoic acid, and malic acid.
  • the amount of the fluidizing agent F present in the recess 62 is not particularly limited, but is 1 to 50 parts by mass with respect to 100 parts by mass of the solder particles 1 from the viewpoint of easily obtaining an appropriate fluidizing action, flux effect, and the like. It may be 1 to 20 parts by mass, and may be 20 to 50 parts by mass.
  • the fluidizing agent F may be a mixture with a solvent or a resin material. As the solvent, the above-mentioned various organic solvents can be used. In the case of a mixture, the concentration of the fluidizing agent F can be appropriately adjusted according to the solder particles 1.
  • the softening point or melting point may be adjusted so that the fluidity of the mixture is increased by heating. If the softening point or melting point is higher than room temperature, the solder particles 1 are less likely to fall out of the recess 62 at room temperature, and can be easily handled before the solder bump forming step.
  • the solvent constituting the mixture include high boiling point solvents and the like. The high boiling point solvent does not easily remain on the electrode because it volatilizes by reheating after the solder particles 1 are made to flow on the electrode.
  • an alcohol solvent or the like can be used. If it is an alcohol solvent, reducing property can be exhibited.
  • the material constituting the substrate 60 for example, an inorganic material such as silicon, various ceramics, glass, a metal such as stainless steel, and an organic material such as various resins can be used.
  • the substrate 60 may be a material having heat resistance that does not deteriorate at the melting temperature of the solder fine particles.
  • the substrate 60 may be made of a material having heat resistance that does not deform even at the temperature at which the solder fine particles are melted.
  • the substrate 60 may be a material that does not change by alloying with a material constituting the solder fine particles or by reacting with the material.
  • the recess 62 of the substrate 60 can be formed by a known method such as a cutting method, a photolithography method, or an imprint method.
  • a cutting method such as a cutting method, a photolithography method, or an imprint method.
  • the recess 62 having an accurate size can be formed in a short process.
  • the surface of the substrate 60 may have a coating layer.
  • the coating layer may be a material that is difficult or not alloyed with the material constituting the solder fine particles.
  • an inorganic substance or an organic substance can be used as the coating layer.
  • the coating layer includes inorganic substances having a strong oxide layer on the surface such as aluminum and chromium, oxides such as titanium oxide, nitrides such as boron nitride, carbon-based materials such as diamond-like carbon, diamond and graphite, and fluororesins. Highly heat-resistant resin such as polyimide can be used.
  • the coating layer may have a role of adjusting the wettability with the solder. By providing the coating layer on the surface of the substrate 60, the wettability with the solder can be appropriately adjusted according to the purpose of use.
  • the coating layer As a method for forming the coating layer, laminating, solution dipping, coating, painting, impregnation, sputtering, plating, etc. can be used.
  • the material of the substrate 60 may be an electrode for transferring the solder particles and a material having similar or the same physical characteristics as the substrate on which the electrode is formed. For example, if the materials have a similar coefficient of thermal expansion (CTE) or the same material, misalignment is unlikely to occur during transfer of solder particles.
  • CTE coefficient of thermal expansion
  • the substrate 60 may be provided with an alignment mark. This alignment mark should be readable by the camera. There may also be an alignment mark on the substrate side having the electrodes. By providing the alignment mark of the base 60 and the substrate having the electrode, when the solder particles are transferred onto the electrode, the alignment mark on the base 60 and the substrate having the electrode are provided by the camera mounted on the alignable device. By reading the alignment mark, it is possible to accurately grasp the position of the recess 62 having the solder particles and the position of the electrode that transfers the solder particles. Further, by providing the alignment mark of the substrate 60 and the substrate having the electrode, the solder particles can be transferred onto the electrode with high positional accuracy.
  • the substrate 60 may be made of an organic material.
  • the organic material may be a polymer material, and thermoplastic, thermosetting, photocurable materials and the like can be used.
  • an organic material By using an organic material, the range of choice of physical properties is widened, so that it is easy to form the substrate 60 according to the purpose.
  • the substrate 60 (including the recess 62) can be easily bent or stretched.
  • various methods can be used for forming the recess 62. As a method for forming the recess 62, imprint, photolithography, cutting, laser machining, or the like can be used.
  • a mold having a desired shape can be pressed against a substrate 60 made of an organic material to form an arbitrary shape on the surface.
  • a concave portion 62 having a desired pattern can be formed.
  • a photocurable resin can be used to form the recess 62, and when the photocurable resin is applied to the mold (mold), exposed, and then the mold (mold) is peeled off, a substrate 60 having the recess 62 is formed. it can.
  • the recess 62 can be formed by a drill or the like.
  • the substrate may be composed of a plurality of organic materials. Further, the substrate may have a plurality of layers, and the plurality of layers may be made of different organic materials.
  • the organic material may be a polymer material, and thermoplastic, thermosetting, photocurable materials and the like can be used.
  • the substrate has two layers made of an organic material, and a recess may be formed in the organic material layer on one side. By forming multiple layers, it is possible to select each material by dividing the function, such as selecting a material having an appropriate wettability with the solder for the material of the recess that comes into contact with the solder.
  • FIG. 8 is a cross-sectional view schematically showing an example of a substrate.
  • the substrate 600 includes a base layer 601 and a recessed layer 602.
  • the base layer 601 is a layer that supports the recess layer 602, and the recess layer 602 is a layer on which the recess 62 is formed by processing.
  • a resin material having excellent heat resistance and dimensional stability can be used for the base layer 601, and a material having excellent workability of the recess 62 can be selected for the recess layer 602.
  • a thermoplastic resin such as polyethylene terephthalate or polyimide can be used for the base layer 601 and a thermosetting resin capable of forming the recess 62 by an imprint mold can be used for the recess layer 602.
  • a substrate 600 (including the recess 62) having excellent flatness can be obtained by sandwiching a thermosetting resin between polyethylene terephthalate and an imprint mold and heating and pressurizing the resin.
  • a material having high light transmittance may be used for the base layer 601.
  • the material having high light transparency may be, for example, polyethylene terephthalate, transparent (colorless type) polyimide, polyamide or the like.
  • the recess 62 is formed using a photocurable material
  • a photocurable material for example, an appropriate amount of the photocurable material is applied to the surface of the imprint mold, a polyethylene terephthalate film is placed on the surface, and the recess 62 is added by a roller from the polyethylene terephthalate side. Irradiate ultraviolet light while pressing. Then, after the photocurable material is cured, the imprint mold is peeled off to obtain a substrate 600 having a layer of polyethylene terephthalate and a layer of the photocurable material, and the recess 62 formed of the photocurable material. be able to.
  • the material composition of the inner wall and the bottom of the recess 62 can be changed.
  • the inner wall and the bottom of the recess 62 may be made of the same resin material. Further, the inner wall and the bottom of the recess 62 may be made of different resin materials (for example, a thermosetting material and a thermoplastic material).
  • a photosensitive material may be used as the organic material.
  • the photosensitive material may be a positive type photosensitive material or a negative type photosensitive material.
  • the recess 62 can be easily formed by forming a photosensitive material having a uniform thickness on the surface of a thermoplastic polyethylene terephthalate film and performing exposure and development.
  • the method using exposure and development is widely used in the manufacture of semiconductors, wiring boards, etc., and is a highly versatile method.
  • a direct drawing method such as a direct laser exposure.
  • the material of the base layer 601 thicker than the thickness of the material forming the concave layer 602
  • the physical characteristics of the entire substrate 600 can be dominated by the characteristics of the material of the base layer 601.
  • the material of the base layer 601 can compensate for the weakness.
  • a material that is hard to heat-shrink is selected as the material of the base layer 601 and the thickness of the base layer 601 is set to be larger than the thickness of the material forming the concave layer 602.
  • a combination of a resin material having excellent heat resistance or dimensional stability and a material in which components are less likely to elute at the melting temperature of solder fine particles, and a resin material having excellent heat resistance or dimensional stability and wettability with solder can be obtained.
  • An organic material can be appropriately selected according to the purpose, such as a combination with an appropriate material.
  • the substrate may be a substrate 600 composed of a base layer 601 and a recessed layer 602.
  • the recess layer 602 as a photosensitive material, the recess 62 can be produced by photolithography.
  • the recess layer 602 By using a light or thermosetting material, a thermoplastic material, or the like for the recess layer 602, the recess 62 can be easily produced by the imprint method. Further, since the characteristics of the entire substrate can be adjusted by changing the thickness of the base layer 601, there is an advantage that a substrate having desired characteristics can be produced.
  • the substrate 60 may be made of an inorganic material.
  • silicon silicon wafer
  • stainless steel aluminum and the like can be used as the inorganic material.
  • contamination countermeasures are easy, and they can contribute to high yield and stable production.
  • solder particles formed in the recess 62 are transferred to an electrode on a silicon wafer, if the substrate 60 is made of a silicon wafer, a material having a similar CTE or the same material will be used. As a result, misalignment, warpage, etc.
  • a method for forming the recess 62 processing by laser, cutting or the like, dry etching or wet etching method, electron beam drawing (for example, FIB processing) or the like can be used. Dry etching is widely used in the production of semiconductors, MEMS, etc., and can process inorganic materials with high accuracy on the order of microns to nano.
  • the substrate 60 glass, quartz, sapphire or the like can be used. Since these materials are transparent, they can be easily aligned when the solder particles in the recess 62 are transferred to another substrate on which the electrodes are formed.
  • processing by laser, cutting or the like dry etching or wet etching method, electron beam drawing (for example, FIB processing) or the like can be used.
  • the advantage of using an inorganic material is that it is superior in dimensional stability compared to an organic material.
  • the solder particles in the recess 62 are transferred onto the electrode, they can be transferred with high positional accuracy. For example, when transferring solder particles to a plurality of electrodes having a size and pitch on the order of micrometers, if an inorganic material having excellent dimensional stability is used, the solder particles can be transferred to the same position on any of the electrodes.
  • the substrate may be composed of a plurality of materials. Further, the substrate may have a plurality of layers, and the plurality of layers may be made of different materials.
  • the organic-inorganic composite material for example, a combination of an inorganic material and an inorganic material, or a combination of an inorganic material and an organic material can be used. The combination of the inorganic material and the organic material can achieve both dimensional stability and workability of the recess 62.
  • Examples of the substrate having a combination of an inorganic material and an organic material include a substrate having a base layer 601 made of a metal such as silicon, various ceramics, glass, and stainless steel, which is an inorganic material, and a concave layer 602 made of an organic material. Can be mentioned.
  • a substrate can be obtained, for example, by forming a photosensitive material on the surface of a silicon wafer and forming recesses by exposure and development.
  • the inner wall and bottom of the recess 62 may be made of a photosensitive material, or the inner wall of the recess 62 may be made of a photosensitive material and the bottom may be made of a silicon wafer.
  • the configuration of the recess 62 can be appropriately selected according to the purpose such as wettability with the solder particles in the recess 62 and ease of transfer to the electrode.
  • a photosensitive material layer is further provided on the surface of the silicon wafer by forming a photosensitive material on the surface of the silicon wafer and curing it, and the surface of the layer is provided with a layer of the photosensitive material.
  • a method of providing the recess 62 by forming a photosensitive material again and performing exposure and development can be used.
  • the photosensitive material on the surface side of the silicon wafer and the photosensitive material provided on the outermost layer may have different compositions.
  • the photosensitive material can be appropriately selected in consideration of the wettability and stainability of the solder particles.
  • the surface of the photosensitive material layer on the outermost layer may come into contact with the electrode or the surface of the substrate having the electrode. Therefore, a photosensitive material that does not damage the electrode and the substrate or does not contaminate the electrode and the substrate can be appropriately selected.
  • the photosensitive material may be a material that prevents elution of uncured components and contamination by halogen-based materials, silicone-based materials, and the like. Further, the photosensitive material may be a material having high resistance to a reducing atmosphere, flux, etc. when transferring solder particles to an electrode.
  • the photosensitive material may be a material that is resistant to a reducing atmosphere such as formic acid, hydrogen, and hydrogen radicals.
  • the photosensitive material may be a material having high resistance to the temperature at which the solder particles are transferred to the electrode.
  • the photosensitive material may be a material that is resistant to temperatures of 100 ° C. or higher and 300 ° C. or lower. Since the melting point of the solder particles differs depending on the constituent material, the heat resistant temperature of the photosensitive material can also be selected according to the solder material to be used.
  • tin-silver-copper solder eg SAC305 (melting point 219 ° C)
  • SAC305 melting point 219 ° C
  • a material having heat resistance can be used.
  • tin-bismuth solder eg SnBi58 (melting point 139 ° C.)
  • a material having a heat resistance of 140 ° C. or higher can be used, and a material having a heat resistance of 160 ° C. or higher can be used industrially. Wider usage likelihood.
  • indium solder melting point 159 ° C.
  • a material having a heat resistance of 170 ° C. or higher can be used.
  • indium-tin solder eg, melting point 120 ° C.
  • a material having a heat resistance of 130 ° C. or higher can be used.
  • Examples of the other substrate include a substrate having a recess 62 formed of a thermosetting or thermoplastic resin on a stainless steel plate.
  • the substrate can be obtained by sandwiching a thermosetting material (resin) between a stainless steel plate and an imprint mold, heating under pressure, and then peeling off the imprint mold.
  • Examples of the other substrate include a substrate having a recess 62 formed of a photocurable material on a glass plate.
  • the substrate can be obtained by applying a photocurable material on a glass plate and exposing the substrate while pressing the imprint mold to cure the photocurable material and peeling off the imprint mold.
  • the material composition of the inner wall and the bottom of the recess 62 can be changed depending on the pressurizing condition.
  • the inner wall and the bottom of the recess 62 can be made of the same resin material.
  • the inner wall of the recess 62 can be made of a resin material and the bottom can be made of an inorganic material.
  • a composite material containing glass fiber, a filler, etc. and a resin component can also be used.
  • the composite material include a copper-clad laminate for a wiring board and the like.
  • a photosensitive material, a thermosetting resin, a photocurable resin, or the like can be applied to the surface of the copper-clad laminate to form the recess 62 as described above.
  • the copper-clad laminate mainly contains a large amount of resin material, the CTE can be lowered by combining with glass fiber, various fillers, and the like, so that the above-mentioned dimensional stability can be ensured.
  • the recess 62 is also formed on the same copper-clad laminate so that the CTEs of both become the same or close to each other, and the position at the time of transferring the solder particles in the recess 62 is obtained. It has the advantage of being easy to align and less likely to cause misalignment.
  • a packaging encapsulant can also be used as the material for the recess layer 602.
  • the sealing material any solid, liquid or film form can be used.
  • the recess 62 can be formed by laminating a sealing material on a glass, silicon wafer, or the like in a thin layer and pressurizing and heating with an imprint mold.
  • the method for manufacturing the solder bump forming member 10 includes a preparatory step of preparing a substrate having a plurality of recesses and solder fine particles, a storage step of storing at least a part of the solder fine particles in the recesses, and a solder fine particles housed in the recesses.
  • a fusion step of forming solder particles in the recesses by fusing the solder particles and an injection step of arranging (injecting) a fluidizing agent (fluid phase) in the recesses in which the solder particles are formed are provided.
  • FIG. 3A is a plan view schematically showing an example of the substrate 60
  • FIG. 3B is a cross-sectional view taken along the line Ib-Ib of FIG. 3A.
  • the substrate 60 shown in FIG. 3A has a plurality of recesses 62.
  • the plurality of recesses 62 may be regularly arranged in a predetermined pattern.
  • the positions and numbers of the plurality of recesses 62 may be set according to the shape, size, pattern, etc. of the electrodes to be connected.
  • the distance L between adjacent recesses is not particularly limited, but can be 0.1 times or more the average particle size of the contained solder particles, and may be 1 time or more.
  • the distance L can be appropriately adjusted by arranging the electrodes forming the solder bumps.
  • the distance between the recesses is not the distance between the centers of the recesses, but the distance from the edge of the recess opening to the edge.
  • the recess 62 of the base 60 is preferably formed in a tapered shape in which the opening area expands from the bottom 62a side of the recess 62 toward the surface 60a side of the base 60. That is, as shown in FIGS. 3A and 3B, the width of the bottom 62a of the recess 62 (the width a in FIGS. 3A and 3B) is the opening at the surface 60a of the recess 62. Is preferably narrower than the width of (width b in FIGS. 3 (a) and 3 (b)).
  • the size of the recess 62 may be set according to the size of the target solder particles.
  • the shape of the recess 62 may be a shape other than the shapes shown in FIGS. 3 (a) and 3 (b).
  • the shape of the opening on the surface 60a of the recess 62 may be an ellipse, a triangle, a quadrangle, a polygon, or the like, in addition to the circular shape as shown in FIG. 3A.
  • the shape of the recess 62 in the cross section perpendicular to the surface 60a may be, for example, the shape shown in FIG. 4 (a) to 4 (h) are cross-sectional views schematically showing an example of the cross-sectional shape of the concave portion of the substrate.
  • the width (width b) of the opening on the surface 60a of the recess 62 is the maximum width in the cross-sectional shape.
  • the width (width b) of the opening is the maximum width in the cross-sectional shape, when the solder particles 1 are transferred onto the electrodes, the solder particles 1 can easily come out from the recess 62, and the transfer rate is improved. Can be expected. Further, by appropriately adjusting the width (width b) of the opening, the position shift when the solder particles 1 are transferred onto the electrodes is less likely to occur, and the solder bumps are easily formed at the correct positions.
  • the solder fine particles prepared in the preparatory step may contain fine particles having a particle size smaller than the width (width b) of the opening on the surface 60a of the recess 62, and may contain more fine particles having a particle size smaller than the width b. Is preferable.
  • the D10 particle size of the particle size distribution is preferably smaller than the width b
  • the D30 particle size of the particle size distribution is more preferably smaller than the width b
  • the D50 particle size of the particle size distribution is smaller than the width b. More preferred.
  • the particle size distribution of the solder fine particles can be measured using various methods according to the size. For example, a dynamic light scattering method, a laser diffraction method, a centrifugal sedimentation method, an electrical detection band method, a resonance type mass measurement method, or the like can be used. Further, a method of measuring the particle size from an image obtained by an optical microscope, an electron microscope, or the like can be used. Specific devices include a flow-type particle image analyzer, a microtrack, a Coulter counter, and the like.
  • the value is not particularly limited, but from the viewpoint of improving the filling property into the recess 62 by the combination of large and small fine particles, C.I. V.
  • the value is preferably high.
  • C.I. V. The value may exceed 20%, preferably 25% or more, more preferably 30% or more.
  • V. The value is calculated by dividing the standard deviation of the particle size measured by the above method by the average particle size (D50 particle size) and multiplying by 100.
  • the solder fine particles may contain tin or a tin alloy.
  • tin alloy for example, In—Sn alloy, In—Sn—Ag alloy, Sn—Au alloy, Sn—Bi alloy, Sn—Bi—Ag alloy, Sn—Ag—Cu alloy, Sn—Cu alloy and the like are used. be able to. Specific examples of these tin alloys include the following examples.
  • the solder fine particles may contain indium or an indium alloy.
  • the indium alloy for example, an In—Bi alloy, an In—Ag alloy, or the like can be used. Specific examples of these indium alloys include the following examples. -In-Bi (In66.3% by mass, Bi33.7% by mass, melting point 72 ° C.) -In-Bi (In33.0% by mass, Bi67.0% by mass, melting point 109 ° C) -In-Ag (In97.0% by mass, Ag3.0% by mass, melting point 145 ° C)
  • the above tin alloy or indium alloy can be selected according to the application (temperature at the time of use) of the solder particles.
  • an In—Sn alloy or a Sn—Bi alloy may be adopted.
  • solder particles that can be fused at 150 ° C. or lower can be obtained.
  • a material having a high melting point such as Sn—Ag—Cu alloy or Sn—Cu alloy is used, solder particles capable of maintaining high reliability even after being left at a high temperature can be obtained.
  • the solder fine particles may contain one or more selected from Ag, Cu, Ni, Bi, Zn, Pd, Pb, Au, P and B.
  • Ag or Cu may be contained from the following viewpoints. That is, when the solder fine particles contain Ag or Cu, the melting point of the obtained solder particles can be lowered to about 220 ° C., and the solder particles having excellent bonding strength with the electrode can be obtained, so that better conduction reliability can be obtained. The effect of obtaining sex is achieved.
  • the Cu content of the solder fine particles is, for example, 0.05 to 10% by mass, and may be 0.1 to 5% by mass or 0.2 to 3% by mass.
  • the Cu content is 0.05% by mass or more, it becomes easy to obtain solder particles capable of achieving good solder connection reliability. Further, when the Cu content is 10% by mass or less, solder particles having a low melting point and excellent wettability can be easily obtained, and as a result, the connection reliability of the electrode with solder bumps tends to be improved.
  • the Ag content of the solder fine particles is, for example, 0.05 to 10% by mass, and may be 0.1 to 5% by mass or 0.2 to 3% by mass.
  • the Ag content is 0.05% by mass or more, it becomes easy to obtain solder particles capable of achieving good solder connection reliability.
  • the Ag oil content is 10% by mass or less, solder particles having a low melting point and excellent wettability can be easily obtained, and as a result, the connection reliability of the electrode with solder bumps tends to be improved.
  • the solder fine particles prepared in the preparatory step are accommodated in each of the recesses 62 of the substrate 60.
  • the accommodating step may be a step of accommodating all the solder fine particles prepared in the preparatory step into the recess 62, and a part of the solder fine particles prepared in the preparatory step (for example, the width b of the opening of the recess 62 among the solder fine particles). It may be a step of accommodating a smaller particle) in the recess 62.
  • FIG. 5 is a cross-sectional view schematically showing a state in which the solder fine particles 111 are housed in the recess 62 of the substrate 60. As shown in FIG. 5, a plurality of solder fine particles 111 are housed in each of the plurality of recesses 62.
  • the amount of the solder fine particles 111 contained in the recess 62 is, for example, preferably 20% or more, more preferably 30% or more, still more preferably 50% or more, based on the volume of the recess 62. , 60% or more is most preferable. As a result, the variation in the accommodating amount is suppressed, and it becomes easy to obtain solder particles having a smaller particle size distribution.
  • the method of accommodating the solder fine particles in the recess 62 is not particularly limited.
  • the accommodating method may be either dry or wet.
  • the solder fine particles prepared in the preparation step are placed on the substrate 60, and the surface 60a of the substrate 60 is rubbed with a squeegee to remove the excess solder fine particles while accommodating sufficient solder fine particles in the recess 62. can do.
  • the width b of the opening of the recess 62 is larger than the depth of the recess 62, solder fine particles may pop out from the opening of the recess 62.
  • a squeegee is used, the solder fine particles protruding from the opening of the recess 62 are removed.
  • Examples of the method of removing the excess solder fine particles include a method of blowing compressed air, a method of rubbing the surface 60a of the substrate 60 with a non-woven fabric or a bundle of fibers, and the like. Since these methods have a weaker physical force than the squeegee, they are preferable for handling easily deformable solder fine particles. Further, in these methods, the solder fine particles protruding from the opening of the recess 62 can be left in the recess.
  • the fusion step is a step of fusing the solder fine particles 111 contained in the recess 62 (for example, by heating to 130 to 260 ° C.) to form the solder particles 1 inside the recess 62.
  • the solder fine particles 111 housed in the recess 62 are united by melting and spheroidized by surface tension.
  • the molten solder follows the bottom portion 62a to form the flat surface portion 11.
  • the formed solder particles 1 have a shape having a flat surface portion 11 on a part of the surface. In this way, the solder bump forming member 10 shown in FIG. 1 is obtained.
  • Examples of the method of melting the solder fine particles 111 contained in the recess 62 include a method of heating the solder fine particles 111 to a temperature equal to or higher than the melting point of the solder. Due to the influence of the oxide film, the solder fine particles 111 may not melt or spread even when heated at a temperature equal to or higher than the melting point, and may not be united. Therefore, the solder fine particles 111 are exposed to a reducing atmosphere to remove the surface oxide film of the solder fine particles 111, and then heated to a temperature equal to or higher than the melting point of the solder fine particles 111 to melt the solder fine particles 111 and spread them wet. It can be unified.
  • the solder fine particles 111 are melted in a reducing atmosphere.
  • the method for manufacturing the solder bump forming member may further include a reduction step of exposing the solder fine particles contained in the recesses to the reducing atmosphere before the fusion step. Further, in the fusion step of the method for manufacturing the solder bump forming member, the solder fine particles may be fused in a reducing atmosphere.
  • the method for creating a reducing atmosphere is not particularly limited as long as the above effects can be obtained, and for example, there is a method using hydrogen gas, hydrogen radical, formic acid gas, or the like.
  • a hydrogen reduction furnace, a hydrogen radical reduction furnace, a formic acid reduction furnace, or a conveyor furnace or a continuous furnace thereof the solder fine particles 111 can be melted in a reducing atmosphere.
  • These devices may be equipped with a heating device, a chamber filled with an inert gas (nitrogen, argon, etc.), a mechanism for evacuating the inside of the chamber, etc., which makes it easier to control the reducing gas. Become. Further, if the inside of the chamber can be evacuated, the voids can be removed by reducing the pressure after the solder fine particles 111 are melted and united, and the solder particles 1 having further excellent connection stability can be obtained.
  • Profiles such as reduction, melting conditions, temperature, and atmosphere adjustment in the furnace of the solder fine particles 111 may be appropriately set in consideration of the melting point, particle size, recess size, material of the substrate 60, and the like of the solder fine particles 111.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, vacuumed, and then the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the surface oxide film of the solder fine particles 111 is formed.
  • the reducing gas is removed by vacuuming, and then the gas is heated to a temperature equal to or higher than the melting point of the solder fine particles 111 to dissolve and coalesce the solder fine particles to form the solder particles in the recess 62. After filling with nitrogen gas, the temperature inside the furnace is returned to room temperature to obtain solder particles 1. Further, for example, the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, and after vacuuming, the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the in-core heater is used.
  • the solder fine particles 111 are heated to remove the surface oxide film of the solder fine particles 111, then the reducing gas is removed by vacuuming, and then the solder fine particles 111 are heated to the melting point or higher to dissolve and coalesce the solder fine particles. After forming the solder particles in the recess 62, the temperature inside the furnace is returned to room temperature after filling with nitrogen gas to obtain the solder particles 1.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, and after vacuuming, the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the in-core heater is used.
  • the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the in-core heater is used.
  • the surface oxide film of the solder fine particles 111 is removed by reduction, and at the same time, the solder fine particles are melted and united to form solder particles in the recess 62, which is reduced by vacuuming.
  • the temperature in the furnace is returned to room temperature after filling with nitrogen gas, and the solder particles 1 can be obtained. In this case, since the temperature rise and fall in the furnace need only be adjusted once, there is an advantage that the processing can be performed in a short time.
  • the inside of the furnace may be made into a reducing atmosphere again to add a step of removing the surface oxide film that could not be completely removed. As a result, it is possible to reduce residues such as solder fine particles remaining unfused and a part of the oxide film remaining unfused.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on the conveyor and passed through a plurality of zones in succession to obtain the solder particles 1.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on a conveyor set at a constant speed and passed through a zone filled with an inert gas such as nitrogen or argon at a temperature lower than the melting point of the solder fine particles 111.
  • the surface oxide film of the solder fine particles 111 is removed by passing through a zone in which a reducing gas such as formic acid gas having a temperature lower than the melting point of the solder fine particles 111 exists, and then nitrogen or nitrogen having a temperature equal to or higher than the melting point of the solder fine particles 111 is removed.
  • the solder fine particles 111 are melted and coalesced by passing through a zone filled with an inert gas such as argon, and then passed through a cooling zone filled with an inert gas such as nitrogen or argon to obtain solder particles 1. be able to.
  • the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on a conveyor set at a constant speed and passed through a zone filled with an inert gas such as nitrogen or argon having a temperature equal to or higher than the melting point of the solder fine particles 111. Subsequently, the surface oxide film of the solder fine particles 111 is removed, melted and coalesced by passing through a zone in which a reducing gas such as formic acid gas having a temperature equal to or higher than the melting point of the solder fine particles 111 exists, and then nitrogen or argon or the like is used.
  • the solder particles 1 can be obtained by passing through a cooling zone filled with the inert gas.
  • a film-like material can be continuously processed by roll-to-roll.
  • a continuous roll product of the substrate 60 in which the solder fine particles 111 are filled in the recesses is produced, a roll unwinder is installed on the inlet side of the conveyor furnace, and a roll winder is installed on the outlet side of the conveyor furnace to maintain a constant speed.
  • the solder fine particles 111 filled in the recesses can be fused.
  • the solder particles 1 having a uniform size can be formed regardless of the material and shape of the solder fine particles 111.
  • indium-based solder can be precipitated by plating, but it is difficult to precipitate it in the form of particles, and it is soft and difficult to handle.
  • indium-based solder particles having a uniform particle size can be easily produced.
  • the formed solder particles 1 can be handled in a state of being housed in the recess 62 of the substrate 60, the solder particles 1 can be transported and stored without being deformed.
  • solder particles 1 are housed in the recesses 62 of the substrate 60, the solder particles can be brought into contact with the electrodes without being deformed.
  • the average particle size of the obtained solder particles may be 1 to 35 ⁇ m, and C.I. V. The value may be 20% or less.
  • solder fine particles 111 may have a large variation in particle size distribution or a distorted shape, and can be suitably used as a raw material if they can be accommodated in the recess 62.
  • the shape of the recess 62 of the substrate 60 can be freely designed by lithography, machining, imprinting, or the like. Since the size of the solder particles 1 depends on the amount of the solder fine particles 111 accommodated in the recess 62, the size of the solder particles 1 can be freely designed by designing the recess 62.
  • the fluidizing agent is arranged in the recess 62 in which the solder particles 1 are formed.
  • the method of arranging the fluidizing agent is not particularly limited, but for example, a method of immersing the substrate 60 in a liquid fluidizing agent solution and pulling it up, or applying the liquid fluidizing agent on the substrate 60 (particularly on the recess 62). , Dropping and the like. Further, in the case of a solid fluidizing agent, a method of arranging a fluidizing agent having a diameter smaller than the diameter of the recess 62 on the surface of the substrate 60 and filling the recess 62 with a squeegee can be mentioned.
  • a method of arranging the fluidizing agent by CVD, vapor deposition, sputtering, or the like can be mentioned.
  • the excess fluidizing agent overflowing from the recess 62 may be removed. Examples of the removing method include volatilization under reduced pressure, squeegee, wiping, scraping, laser etching, and blasting.
  • liquid fluidizing agent For example, an appropriate amount of the liquid fluidizing agent is dropped onto the substrate 60 (on the recess 62), the liquid fluidizing agent is spread in the recess 62 by the squeegee, and then filled in the recess 62.
  • the liquid fluidizing agent can be removed.
  • the fluidizing agent that cannot be completely removed by the squeegee can be wiped off with, for example, a dust-free clean cloth.
  • the method for manufacturing the solder bump forming member 10 includes a pre-step of preparing a substrate having a plurality of recesses, solder particles and a fluidizing agent, and an arrangement step of arranging the solder particles and the fluidizing agent in the recesses. You may. In this way, the solder particles 1 can be once taken out from the substrate 60, and the solder particles 1 and the fluidizing agent F can be rearranged in the recesses of the substrate again to produce a solder bump forming member. According to this method, the solder particles 1 can be separated from the solder fine particles 111 that did not become the solder particles 1 in the melting step, the solder fine particles 111 existing outside the recess 62, other residues, foreign substances, and the like.
  • the substrate 60 having the solder particles 1 in the recess 62 is immersed in the solvent, and the solder particles 1 are taken out from the recess 62.
  • the substrate 60 from which the solder particles 1 have been taken out is pulled out from the solvent, foreign matter is removed from the solvent by passing the solvent through a filter, a mesh, or the like.
  • the solder particles 1 are once dispersed in a solvent and allowed to stand to perform sedimentation separation.
  • the solder particles 1 and the residue for example, solder fine particles 111 and foreign matter
  • the mixture of the solder particles 1 and the solvent is vacuum-dried to obtain high-purity solder particles 1.
  • the solder particles 1 are rearranged in the recess 62 on the surface of the substrate 60.
  • the fluidizing agent can be arranged in the recess 62.
  • the solder particles 1 may be arranged in the recess 62 after the fluidizing agent is arranged in the recess 62 in advance.
  • the fluidizing agent and the solder particles 1 may be mixed in advance, and the mixture may be arranged in the recess 62.
  • the substrate on which the solder particles are rearranged may be the substrate used when producing the solder particles, or may be a different substrate.
  • solder particles 1 in addition to those obtained by the above method, an atomizing method, a water atomizing method, a method of cutting and dissolving fine wires, and a method of producing fine solder droplets using a precision ejection head.
  • Those prepared by a known method such as, etc. can be used.
  • the method for manufacturing an electrode substrate with solder bumps includes a preparatory step for preparing the solder bump forming member and a substrate having a plurality of electrodes, and a surface having a recess of the solder bump forming member and a surface having electrodes of the substrate. It includes an arrangement step of bringing the solder particles into contact with each other and a heating step of heating the solder particles to a temperature equal to or higher than the melting point of the solder particles.
  • substrates (circuit members) having a plurality of electrodes on the surface include chip components such as IC chips (semiconductor chips), resistor chips, capacitor chips, and driver ICs; rigid type package substrates. These circuit members are provided with circuit electrodes, and are generally provided with a large number of circuit electrodes.
  • substrates having a plurality of electrodes on the surface include wiring substrates such as flexible tape substrates having metal wiring, flexible printed wiring boards, and glass substrates on which indium tin oxide (ITO) is vapor-deposited.
  • ITO indium tin oxide
  • Electrodes include copper, copper / nickel, copper / nickel / gold, copper / nickel / palladium, copper / nickel / palladium / gold, copper / nickel / gold, copper / palladium, copper / palladium / gold, and copper.
  • / Tin, copper / silver, indium tin oxide and other electrodes can be mentioned.
  • Electrodes can be formed by electroless plating or electroplating or sputtering or etching of metal foil.
  • FIG. 6A and 6 (b) are cross-sectional views schematically showing an example of a manufacturing process of an electrode substrate with solder bumps.
  • the substrate 60 shown in FIG. 6A is in a state in which one solder particle 1 and a fluidizing agent F are housed in each of the recesses 62.
  • the substrate 2 has a plurality of electrodes 3 on the surface.
  • the surface on the electrode 3 side of the substrate 2 is brought into contact with the surface of the substrate 60 on the opening side of the recess 62 so as to face each other.
  • the number of solder particles 1 that come into contact with the individual electrodes 3 is not particularly limited, and may be one particle per electrode and may be a plurality of particles per electrode.
  • the force acting between the solder particles 1 and the recess 62 (for example, an intermolecular force such as van der Waals force) is larger than the gravity applied to the solder particles 1, it is assumed that the main surface of the substrate 60 is directed downward. However, the solder particles 1 do not fall off and remain in the recess 62. Further, when at least a part of the solder particles 1 is in contact with the bottom portion and / or the inner wall portion of the recess 62 and has a flat portion, the solder particles 1 are in close contact with the recess 62 and are difficult to fall off.
  • an intermolecular force such as van der Waals force
  • the fluidizer F is heated by heating the entire electrode substrate and substrate 60 to a temperature higher than the melting point of the solder particles 1 (for example, 130 to 260 ° C.) while the solder particles and the electrodes are in contact with each other.
  • the solder particles 1 that have become easier to flow come into contact with the electrode 3 and melt to form solder bumps on the electrode 3.
  • the solder particles 1 are brought into contact with the solder bump forming member 10 and the substrate 2 in a pressurized state, and the temperature of the solder particles 1 is equal to or higher than the melting point of the solder particles. May be heated to.
  • the pressurized state is a state in which the solder bump forming member 10 and the substrate 2 are pressed against each other with a force of about 30 to 600 Pa in the directions of arrows A and B in FIG. 6A.
  • the solder particles 1 are housed in the recess 62 and are pressed against the electrodes. Therefore, even if the solder particles 1 flow due to the action of the fluidizing agent F, the solder particles 1 in the adjacent recesses 62 are unlikely to be mixed with each other, and solder bumps of the same size can be formed only on the desired electrodes. In addition, it is difficult for the solder to bridge the adjacent electrodes, and short-circuit defects can be suppressed.
  • the solder particles 1 are rapidly oxidized by heating in the atmosphere, and it is difficult for the solder particles 1 to spread wet on the electrode 3, so that the atmosphere at the time of heating is preferably a deoxidized atmosphere.
  • it may be an inert gas atmosphere such as nitrogen or argon, a vacuum atmosphere, or the like.
  • a reflow furnace (under a nitrogen atmosphere) and a vacuum reflow furnace generally used in the solder joining process can be used, and a conveyor type reflow furnace under a nitrogen atmosphere, a batch type (chamber type) reflow furnace and the like can be used.
  • a laminator can also be used. If it is a roller type laminator, pressurization and heating can be applied at the same time. Further, a vacuum pressurizing laminator can also be used. The vacuum pressurizing laminator is preferable because the inside of the chamber can be evacuated and pressurization and heating can be performed at the same time, so that the solder bumps can be easily transferred onto the electrode 3. In addition, since continuous transportation by the carrier film is possible, there is an advantage that productivity can be increased.
  • solder particles 1 may not melt or spread even when heated at a temperature higher than the melting point due to the influence of the oxide film. Therefore, the solder particles 1 can be melted by exposing the solder particles 1 to a reducing atmosphere, removing the surface oxide film of the solder particles 1, and then heating the solder particles 1 to a temperature equal to or higher than the melting point of the solder particles 1. Further, it is preferable that the solder particles 1 are melted in a reducing atmosphere. By heating the solder particles 1 to a temperature equal to or higher than the melting point of the solder particles 1 and creating a reducing atmosphere, the oxide film on the surface of the solder particles 1 is reduced, and the oxide film on the electrode surface is further reduced to melt the solder particles 1. Wetting and spreading can proceed efficiently.
  • the method for manufacturing an electrode substrate with solder bumps further includes a reduction step of exposing the solder particles (and / or electrodes) to a reducing atmosphere before the placement step or after the placement step and before the heating step. It's okay.
  • the solder particles may be heated to a temperature equal to or higher than the melting point of the solder particles in a reducing atmosphere.
  • the electrodes and the opening surfaces of the solder bump forming members are brought into close contact with each other (under pressure if necessary), so that the solder bumps are formed only on the electrodes and the adjacent electrodes. Bridges due to solder between them are easily suppressed.
  • the description of the manufacturing method of the solder bump forming member can be referred to as appropriate.
  • the method for manufacturing an electrode substrate with solder bumps may further include a removal step of removing the solder bump forming member from the substrate after the heating step.
  • the solder bump forming member 10 is removed from the substrate 2 (removal step) to obtain the electrode substrate 20 with solder bumps.
  • FIG. 6B is a schematic view of the electrode substrate 20 with solder bumps thus obtained.
  • the method for manufacturing the electrode substrate with solder bumps may further include a cleaning step of removing the solder particles 1 not bonded to the electrode after the removing step.
  • the cleaning method include blowing compressed air, rubbing the surface of the substrate with a non-woven fabric or a bundle of fibers, and the like.
  • an electrode substrate 20 with solder bumps having a substrate 2, an electrode 3, and a solder bump 1A in this order.
  • connection structure 7 (a) and 7 (b) are cross-sectional views schematically showing an example of a manufacturing process of the connection structure.
  • a method of manufacturing the connection structure will be described with reference to FIGS. 7 (a) and 7 (b).
  • the electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance.
  • another substrate 4 having a plurality of other electrodes 5 on the surface is prepared.
  • both are arranged so that the solder bump 1A and the other electrode 5 face each other.
  • pressure is applied in the thickness direction of the laminated body of these members (directions of arrows A and B shown in FIG. 7A).
  • the solder bump 1A melts between the electrode 3 and the other electrodes 5. After that, by cooling the whole, a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other.
  • an atmosphere in which oxygen is blocked For example, heating in an atmosphere of an inert gas such as nitrogen is preferable.
  • an inert gas such as nitrogen is preferable.
  • a vacuum reflow furnace, a nitrogen reflow furnace, or the like can be used.
  • solder bump 1A it is preferable to heat the solder bump 1A in a reducing atmosphere in order to melt the solder bump 1A by heating and more preferably join the opposing electrodes 3 and 5 to each other.
  • Hydrogen gas, hydrogen radicals, formic acid and the like can be used to create a reducing atmosphere.
  • a hydrogen reduction furnace, a hydrogen reflow furnace, a hydrogen radical furnace, a formic acid furnace, these vacuum furnaces, a continuous furnace, and a conveyor furnace can be used.
  • the oxide film on the surface of the solder bump 1A and the oxide film on the surface of the electrode 5 can be reduced and removed, so that the solder bump 1A easily wets and spreads on the electrode 5, and the electrode is passed through the solder layer 1B. A more stable bond is achieved between 3 and the electrode 5.
  • the electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance. Further, another substrate 4 having a plurality of other electrodes 5 on the surface is prepared. Then, both are arranged so that the solder bump 1A and the other electrode 5 face each other. Then, pressure is applied in the thickness direction of the laminated body of these members (directions of arrows A and B shown in FIG. 7A). By heating the whole to a temperature higher than the melting point of the solder bump 1A (for example, 130 to 260 ° C.) when pressurizing, the solder bump 1A melts between the electrode 3 and the other electrodes 5.
  • a temperature higher than the melting point of the solder bump 1A for example, 130 to 260 ° C.
  • a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other.
  • an atmosphere of an inert gas such as nitrogen
  • a reducing atmosphere examples include the above-mentioned hydrogen gas, hydrogen radicals, formic acid and the like.
  • a hydrogen reduction furnace, a hydrogen reflow furnace, a hydrogen radical furnace, a formic acid furnace, these vacuum furnaces, a continuous furnace, a conveyor furnace, and the like can be used.
  • a material having a reducing action can be used as a method of creating a reducing atmosphere.
  • a flux material or a material containing a flux component can be arranged in the vicinity of the solder bump 1A, the electrode 5, and the electrode 3.
  • a paste, a film or the like containing a flux material and a material containing a flux component can be used.
  • the electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance.
  • a flux material or a paste containing a flux component is arranged on the entire surface of the electrode substrate 20 on which the solder bumps 1A are formed, or in the vicinity of the electrode 3 including the solder bumps 1A and the solder bumps 1A.
  • solder bump 1A and the other electrode 5 face each other.
  • the solder bump 1A and the other electrode 5 are brought into contact with each other through, for example, a flux material or a paste containing a flux component, and brought to a temperature higher than the melting point of the solder bump 1A (for example, 130 ° C. to 260 ° C.). At least by heating, the solder bump 1A melts between the electrode 3 and the other electrodes 5.
  • a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other. After that, when the flux component is washed and removed, corrosion of the solder layer 1B, the electrode 3 and the electrode 5 due to the flux residue can be suppressed.
  • the electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance. Further, another substrate 4 having a plurality of other electrodes 5 on the surface is prepared, and a flux material or a paste containing a flux component is arranged on the entire surface of the substrate 4 having the electrodes 5 or near the surface of the electrodes 5. Then, both are arranged so that the solder bump 1A and the other electrode 5 face each other. After that, the solder bump 1A and the other electrode 5 are brought into contact with each other via, for example, a flux material and a paste containing a flux component, and brought to a temperature higher than the melting point of the solder bump 1A (for example, 130 ° C. to 260 ° C.). At least by heating, the solder bump 1A melts between the electrode 3 and the other electrodes 5. After that, by cooling the whole, a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other.
  • the electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance.
  • a film containing a flux component is arranged on the surface side of the electrode substrate 20 on which the solder bumps 1A are formed.
  • another substrate 4 having a plurality of other electrodes 5 on the surface is prepared. Then, both are arranged so that the solder bump 1A and the other electrode 5 face each other. After that, the solder bump 1A and the other electrode 5 are kept in contact with each other via a film containing a flux component, or a pressure is applied between the opposing electrodes 3 and 5 to contain the flux component between them.
  • the electrode 3 and other parts are heated by at least heating to a temperature higher than the melting point of the solder bump 1A (for example, 130 ° C. to 260 ° C.) in a state where the solder bump 1A and the electrode 5 are in contact with each other so as to push the film away.
  • the solder bump 1A melts between the electrodes 5.
  • a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other.
  • the paste and film containing the flux component may contain a thermosetting material.
  • the thermosetting component is cured at the same time as the solder bump 1A is melted, and the electrode substrate 20 and the substrate 4 can be fixed.
  • the curing of the thermosetting material may be carried out by heating again in a subsequent step separately from the melting and heating of the solder bump 1A.
  • the film containing the flux component may be placed on the surface side of the substrate 4 on which the electrode 5 is formed in advance.
  • the selection of the placement position of the film containing the flux component on the solder bump 1A side or the substrate 4 side having the electrode 5 depends on the shape of the electrode, the shape and size of the solder bump 1A, and the joining process. It can be selected as appropriate according to convenience.
  • a heating method for melting the solder bump 1A under vacuum, for example, a method of heating a heating plate in a reflow furnace and transmitting it to the solder bump 1A via a substrate 2 and a substrate 4 in contact with the heating plate, infrared rays. There is a method using radiation such as. Further, in addition to or in combination with the above-mentioned heating method using a heating plate and infrared rays, a method of heating the solder bump 1A via the heated gas and gas can be used. Specifically, the solder bump 1A can be heated by heating the inert gas, nitrogen, hydrogen, hydrogen radicals, and formic acid.
  • the flux material and the flux component may include at least one selected from the group consisting of succinic acid, glutaric acid, adipic acid, pimelic acid, suberic acid, benzoic acid, and malic acid.
  • a method of using electromagnetic waves such as microwaves.
  • a specific electromagnetic wave that heats the components of the electrode 3, the electrode 5, and the solder bump 1A can be applied from the outside.
  • the substrate 4 and the substrate 2 are resin substrates
  • the electromagnetic wave is transmitted through the substrate 4 and the substrate 2, and the electrode 3 and the solder bump 1A or the electrode 5 are formed. It is heated by electromagnetic waves.
  • the portion to be joined can be selectively heated, there is an advantage that an extra heat history is not left.
  • the solder bump 1A can be melted and the electrode 3 and the electrode 5 can be reliably joined. Further, since the heat history is unlikely to remain in the entire system to be joined, there is an advantage that warpage and decomposition after joining can be easily suppressed. Further, when microwaves are used, the solder bump 1A can be melted in a shorter time than using a heating plate, infrared rays, heating gas, etc. as described above, so that the heat history to the entire system to be joined is reduced. There is an advantage that the above-mentioned effect can be easily obtained.
  • the solder bump 1A and the electrode 5 to be joined or melted can be locally heated. Therefore, it is not necessary to heat the entire system, and even if there are materials with low heat resistance, other electronic components, etc. that do not want to be heated in the vicinity of the electrodes 3 and 5, the solder bumps 1A are melted and joined. be able to.
  • Another method is to use ultrasonic waves. For example, when an ultrasonic vibrator is arranged on the side opposite to the electrode 3 of the substrate 2 and ultrasonic waves are applied, the solder bump 1A is melted by the vibration energy of the ultrasonic waves. As a result, the electrode 3 and the electrode 5 previously arranged at the opposite positions of the electrode 3 are joined via the solder layer 1B. Since the solder bump 1A can be melted in a short time in the bonding by ultrasonic waves, it is not necessary to apply heat to the entire substrate 2 and the substrate 4, and even if the substrate 2 and the substrate 4 are made of a material having low heat resistance, the electrodes are surely electrode. 3 and the electrode 5 can be joined.
  • FIG. 7B is a schematic view of the connection structure 30 obtained in this way. That is, FIG. 7B schematically shows a state in which the electrode 3 of the substrate 2 and the other electrode 5 of the other substrate 4 are connected via a solder layer 1B formed by fusion. It is shown.
  • the term "fused” means that at least a part of the electrode is joined by a solder (solder bump 1A) melted by heat, and then the solder is joined to the surface of the electrode through a step of solidifying the solder. Means the state.
  • the connection structure 30 includes a first circuit member having a plurality of electrodes on the substrate and its surface, a second circuit member having a plurality of other electrodes on the other substrate and its surface, and a plurality of electrodes and a plurality of electrodes. It can be said that a solder layer is provided between the other electrodes.
  • the space between the first circuit member and the second circuit member can be filled with, for example, an underfill material containing an epoxy resin as a main agent.
  • connection structures such as semiconductor memory and semiconductor logic chips, connection parts for primary and secondary mounting of semiconductor packages, and junctions such as CMOS image elements, laser elements, and LED light emitting elements.
  • Examples include devices such as cameras, sensors, liquid crystal displays, personal computers, mobile phones, smartphones, and tablets used.
  • Step a1 Classification of solder fine particles 100 g of Sn-Bi solder fine particles (manufactured by 5N Plus, melting point 139 ° C., Type 8) are immersed in distilled water, ultrasonically dispersed, then allowed to stand, and the solder fine particles float in the supernatant. Was recovered. This operation was repeated to recover 10 g of solder fine particles. The average particle size of the obtained solder fine particles was 1.0 ⁇ m, and C.I. V. The value was 42%.
  • Step b1 Arrangement on the substrate
  • the opening diameter is 2.3 ⁇ m ⁇
  • the bottom diameter is 2.0 ⁇ m ⁇
  • the depth is 2.0 ⁇ m (the bottom diameter of 2.0 ⁇ m ⁇ is 2.3 ⁇ m ⁇ when the opening is viewed from the top surface, as shown in Table 1.
  • a substrate polyimide film, thickness 100 ⁇ m
  • the plurality of recesses were regularly arranged at intervals of 1.0 ⁇ m.
  • the solder fine particles average particle diameter 1.0 ⁇ m, CV value 42%) obtained in step a were placed in the recesses of the substrate.
  • Step c1 Formation of solder particles
  • the substrate in which the solder fine particles are arranged in the recesses in step b1 is placed in a hydrogen reduction furnace (Vacuum soldering device manufactured by Shinko Seiki Co., Ltd.), evacuated, and then hydrogen gas is put into the furnace. It was introduced and the inside of the furnace was filled with hydrogen. Then, after keeping the inside of the furnace at 280 ° C. for 20 minutes, the inside of the furnace was evacuated again, nitrogen was introduced to return the pressure to atmospheric pressure, and then the temperature inside the furnace was lowered to room temperature to form solder particles inside the recesses. ..
  • a hydrogen reduction furnace Vauum soldering device manufactured by Shinko Seiki Co., Ltd.
  • Step d1 Arrangement of flux 20 parts by mass of adipic acid as a flux component was added to 90 parts by mass of dihydroterpineol and mixed to prepare a fluid phase. This flowing phase was placed in the recess in which the solder particles obtained in step c1 were placed. Then, the surface side on which the concave portion of the substrate was formed was rubbed with a rubber squeegee to remove an excess fluid phase (flux component) that was not filled in the concave portion. Then, the surface of the base material was further wiped with a dust-free clean cloth to prepare a film for forming solder bumps.
  • Step c2 Formation of solder particles
  • the substrate in which the solder fine particles were arranged in the recesses in step b1 was put into a hydrogen radical reduction furnace (Plasma reflow device manufactured by Shinko Seiki Co., Ltd.), evacuated, and then hydrogen gas was introduced into the furnace.
  • the inside of the furnace was filled with hydrogen gas.
  • the inside of the furnace was adjusted to 120 ° C. and irradiated with hydrogen radicals for 5 minutes.
  • the hydrogen gas in the furnace is removed by vacuuming, and after heating to 170 ° C., nitrogen is introduced into the furnace to return it to atmospheric pressure, and then the temperature inside the furnace is lowered to room temperature to remove the solder particles. Formed.
  • Step c3 Formation of solder particles
  • the substrate in which the solder fine particles were arranged in the recesses in step b1 was put into a formic acid reduction furnace, evacuated, and then formic acid gas was introduced into the furnace to fill the inside of the furnace with formic acid gas. .. Then, the inside of the furnace was adjusted to 130 ° C., and the temperature was maintained for 5 minutes. After that, formic acid gas in the furnace is removed by vacuuming, and after heating to 180 ° C., nitrogen is introduced into the furnace to return it to atmospheric pressure, and then the temperature in the furnace is lowered to room temperature to remove the solder particles. Formed.
  • Step c4 Formation of solder particles
  • the substrate in which the solder fine particles were arranged in the recesses in step b1 was put into a formic acid conveyor reflow furnace (Heller Industries, Inc., 1913MK) and adjusted to 190 ° C. while being conveyed by the conveyor.
  • the soldered nitrogen zone, nitrogen and formic acid gas mixing zone, and nitrogen zone were passed continuously.
  • the nitrogen and formic acid gas mixing zone was passed in 20 minutes to form solder particles in the recesses.
  • Step e1 Preparation of evaluation chip Seven types of chips with gold bumps (3.0 ⁇ 3.0 mm, thickness: 0.5 mm) shown below were prepared.
  • Chip C1 ... Area 100 ⁇ m ⁇ 100 ⁇ m, space 40 ⁇ m, height: 10 ⁇ m, number of bumps 362 Chip C2: Area 75 ⁇ m ⁇ 75 ⁇ m, space 20 ⁇ m, height: 10 ⁇ m, number of bumps 362 Chip C3: Area 40 ⁇ m ⁇ 40 ⁇ m, space 16 ⁇ m, height: 7 ⁇ m, number of bumps 362 Chip C4: Area 20 ⁇ m ⁇ 20 ⁇ m, space 7 ⁇ m, height: 5 ⁇ m, number of bumps 362 Chip C5: Area 10 ⁇ m ⁇ 10 ⁇ m, space 6 ⁇ m, height: 3 ⁇ m, number of bumps 362 Chip C6: Area 10 ⁇ m ⁇ 10 ⁇ m, space 4 ⁇ m, height
  • Step f1 Solder bump formation (no formic acid gas used) Using the solder bump forming film (Production Example 7) produced in step c2 according to the procedures i) to iii) shown below, a chip with gold bumps (3.0 ⁇ 3.0 mm, thickness: 0.5 mm). ) was formed with solder bumps.
  • a glass plate having a thickness of 0.3 mm was placed on the hot plate, and the evaluation chip was placed on the glass plate with the gold bump facing up.
  • the solder bump forming film was arranged so that the gold bump surface of the evaluation chip and the solder bump forming film were in contact with each other so that the opening surface side of the recess of the solder bump forming film was directed downward.
  • a glass plate having a thickness of 0.3 mm was placed on the solder bump forming film, and a stainless steel weight was placed on the glass plate to bring the solder bump forming film into close contact with the gold bump.
  • a bell-shaped glass cover that allows nitrogen gas to be blown inside was prepared. With this glass cover, a sample in which a film for forming a solder bump was laminated on the evaluation chip prepared in ii) was covered. Next, nitrogen gas was introduced into the glass cover and the entire sample was placed in a nitrogen atmosphere. The hot plate of the hot plate was heated to 160 ° C. and heated for 5 minutes. Then, after returning the hot plate to room temperature, nitrogen gas was stopped and the hot plate was opened to the atmosphere.
  • the top weight, glass plate, and solder bump forming film were removed in this order. Subsequently, the evaluation chip was immersed in a methanol solution, the fluidized bed was washed and removed, and vacuum dried (40 ° C. for 60 minutes) to obtain an evaluation chip with solder bumps.
  • the evaluation chip obtained in step f1 was fixed to the surface of the pedestal for SEM observation, and the surface was subjected to platinum sputtering.
  • the number of solder bumps placed on the gold bumps was counted by SEM, and the average number of solder bumps placed on one gold bump was calculated.
  • the results are shown in Table 3.
  • the height of the solder bumps from the gold bumps was measured using a laser microscope (LEXT OLS5000-SAF manufactured by Olympus Corporation), and the average value of 100 pieces was calculated. The results are shown in Table 3.
  • solder bump formation and its evaluation were carried out by the same method as described above, except that the solder bump forming film of Production Examples 8 to 12 was used instead of the solder bump forming film of Production Example 7.
  • the evaluation results are shown in Table 3.
  • Comparative Production Example 1 A comparative solder bump forming film having solder particles in the recesses was produced in the same manner as in Production Example 8 except that step d1 (flux arrangement) was not performed. Solder bump formation and its evaluation were performed by the same method as in step f1 except that the comparative solder bump forming film was used. The results are shown in Table 3.
  • solder bumps could be formed on the gold bumps of the evaluation chips, but in Comparative Production Examples 1, no solder bumps were observed on the gold bumps of any of the evaluation chips.
  • the flux component removes the oxide film on the surface of the solder particles by heating and also cleans the surface of the gold bump (electrode). Then, the solder particles are carried to the surface of the gold bump by the flowing phase while being melted, and the solder bump can be formed on the gold bump. As shown in FIG. 1, since the fluidized phase exists in the recess, the fluidized phase removes the oxide film near the surface of the solder particles facing the gold bumps (electrodes), and the solder particles and the gold bumps are separated from each other. Contact is activated.
  • the solder particles can be in contact with the gold bump surface.
  • the flow of the solder particles and the flux in the surface direction of the solder bump forming member is suppressed, and the solder bump can be formed on the gold bump. Further, for the same reason, it is difficult for the solder particles of the adjacent recesses to join each other, and good solder bumps can be formed.
  • the concave opening surface is partially in contact with the evaluation chip side, it can be easily removed by subsequent cleaning because there is no metal (electrode) in which the solder spreads wet. Further, as shown above, since the solder particles and the flux are present in the recesses, the flow of the solder particles is suppressed in the surface direction of the solder bump forming member, and it is difficult to cause a short-circuit defect of the gold bump.
  • Step f2 Solder bump formation (using formic acid gas) Using the solder bump forming film (Production Example 7) produced in step c2 according to the procedures i) to iii) shown below, a chip with gold bumps (3.0 ⁇ 3.0 mm, thickness: 0.5 mm). ) was formed with solder bumps. i) A glass plate having a thickness of 0.3 mm was placed on a stainless steel plate having a thickness of 5 mm, and an evaluation chip was placed on the glass plate with a gold bump facing up.
  • the solder bump forming film was arranged so that the gold bump surface of the evaluation chip and the solder bump forming film were in contact with each other so that the opening surface side of the recess of the solder bump forming film was directed downward. Further, a glass plate having a thickness of 0.3 mm was placed on the solder bump forming film, and a stainless steel weight was placed on the glass plate to bring the solder bump forming film into close contact with the gold bump.
  • the stainless plate prepared in iii) was placed and flowed at a speed of 40 mm / s. In the conveyor furnace, the sample first passed through the nitrogen gas zone.
  • solder bump formation and its evaluation were performed by the same method as in step f2, except that the solder bump forming film of Production Examples 8 to 12 was used instead of the solder bump forming film of Production Example 7.
  • the evaluation results are shown in Table 4.
  • solder bumps could be formed on the gold bumps.
  • the number of solder bumps tends to increase as compared with the case where the atmosphere is not formic acid gas (Table 3). This is because the surface oxide film of the solder particles in the recess was sufficiently reduced by the flux component contained in the fluid phase and formic acid gas, and the organic matter on the surface of the gold pad was also removed by the formic acid gas. It is probable that solder bumps were easily formed on the surface. When the solder bumps obtained using the formic acid gas atmosphere were observed with a microscope and an electron microscope, the spherical distortion was less than that of the solder bumps obtained without using the formic acid gas atmosphere.
  • Comparative Production Example 1 formation of solder bumps was confirmed on the gold bumps, but the number of bumps tended to be smaller than that of Production Examples 7 to 12. Even when the same Comparative Production Example 1 was used, no solder bumps were formed when the formic acid gas atmosphere was not used, but when the formic acid gas atmosphere was used, the solder particles in some of the recesses were not formed. The surface oxide film was removed by formic acid gas, and a certain amount of solder was placed on the gold bumps. However, since the side of the recess is pressed against the gold bump, it is considered that the formic acid gas did not sufficiently remove the surface oxide film of the solder particles in the recess.
  • Step g1 Preparation of evaluation substrate Seven types of substrates with gold bumps (70 ⁇ 25 mm, thickness: 0.5 mm) shown below were prepared. The gold bumps are also formed with lead-out wiring for resistance measurement. Substrate D1 ...
  • Step h1 Joining the electrodes
  • the evaluation chip with solder bumps produced in step f1 was used to connect to the evaluation substrate with gold bumps via the solder bumps.
  • the evaluation substrate was placed on the lower hot plate of the formic acid reflow furnace (manufactured by Shinko Seiki Co., Ltd., batch type vacuum soldering device) with the gold bumps facing up.
  • the solder bump surface of the evaluation chip on which the solder bumps were formed was directed downward, and the gold bump surface of the evaluation substrate and the solder bumps were arranged so as to be in contact with each other and fixed so as not to move.
  • connection structure was prepared. The combinations of each material in the connection structure are as follows.
  • Chip C1 / Solder bump forming film / substrate D1 (2) Chip C2 / Solder bump forming film / Substrate D2 (3) Chip C3 / Solder bump forming film / Substrate D3 (4) Chip C4 / Solder bump forming film / Substrate D4 (5) Chip C5 / Solder bump forming film / Substrate D5 (6) Chip C6 / Solder bump forming film / Substrate D6 (7) Chip C7 / Solder bump forming film / Substrate D7
  • connection structure> A conduction resistance test and an insulation resistance test were performed on a part of the obtained connection structure as follows.
  • the DC resistance values were measured at the solder joints (4 points) at the chip corners where the impact was greatest, and when the measured values increased 5 times or more from the initial resistance, it was considered that breakage had occurred and evaluation was performed. A total of 80 points were measured at 4 points for each sample. The results are shown in Table 6. When the criteria of A or B below were satisfied after 20 drops, the solder connection reliability was evaluated as good. A: There were no solder connections where the initial resistance increased by 5 times or more. B: The number of solder connection portions increased by 5 times or more from the initial resistance was 1 or more and 5 or less. C: The number of solder connection portions increased by 5 times or more from the initial resistance was 6 or more and 20 or less. D: There were 21 or more solder connection parts that increased by 5 times or more from the initial resistance.
  • the initial value of the insulation resistance and the value after the migration test (standing at temperature 60 ° C., humidity 90%, 20V application for 100, 500, 1000 hours) were measured for 20 samples, and all of them were measured. of 20 samples was calculated the ratio of the sample insulation resistance is 10 9 Omega more.
  • the insulation resistance was evaluated from the obtained ratio according to the following criteria. The results are shown in Table 7. If the following criteria A or B are satisfied after 1000 hours of the migration test, it can be said that the insulation resistance is good.
  • Step i1 Preparation of evaluation substrate A liquid photosensitive resist (manufactured by Hitachi Kasei Co., Ltd., AH series) was applied to a thickness of 2.3 ⁇ m on a 6-inch silicon wafer by a spin coating method.
  • the photosensitive resist on this silicon wafer is exposed and developed to have an opening diameter of 3.1 ⁇ m ⁇ , a bottom diameter of 2.0 ⁇ m ⁇ , and a depth of 2.3 ⁇ m (the bottom diameter of 2.0 ⁇ m ⁇ is an opening diameter of 3 when the opening is viewed from the top surface.
  • An evaluation pattern having a recess located in the center of 1 ⁇ m ⁇ was formed.
  • One of the evaluation patterns has a size of 20 mm ⁇ 20 mm, and the above-mentioned recess is arranged in an area of 10 mm ⁇ 10 mm at the center thereof.
  • the positions of the recesses are arranged at positions (X-direction pitch, Y-direction pitch) relative to the electrode arrangement pattern of the evaluation chip C8, which will be described later, and three alignment marks are also arranged. This was cut out to a size of 20 mm ⁇ 20 mm by a dicer to obtain a substrate 1 for evaluation.
  • the outline of the evaluation substrate is shown in Table 8.
  • Evaluation substrates 2 to 6 were prepared with the thickness, opening diameter and pitch of the photosensitive resist as the values shown in Table 8.
  • Step j1 Preparation of solder particles
  • the solder bump forming films having the solder particles in the recesses shown in Production Examples 7 to 12 in Table 2 were obtained.
  • a stainless steel vat was filled with isopropyl alcohol, the obtained film for forming solder bumps was immersed, and ultrasonic waves of 28 kHz and 600 W were applied for 5 minutes.
  • the solder particles were separated from the recesses and dispersed in the isopropyl alcohol solvent. The solvent in which the solder particles were dispersed was allowed to stand, and the supernatant was discarded.
  • solder particles 1 to 6 having the same particle size.
  • the outline of the solder particles 1 to 6 is shown in Table 9.
  • Step k1 Arrangement of fluidizing agent and solder particles Dodecane and solder particles 1 were placed in a glass bottle with a lid and dispersed by ultrasonic waves. The dispersion liquid was dropped on the surface of the evaluation substrate 1 of 20 mm ⁇ 20 mm fixed on the glass plate, the surface of the evaluation substrate 1 was rubbed with a urethane squeegee, and the solder particles 1 and dodecane were filled in the recesses. Excess solder particles 1 and dodecane on the surface of the evaluation substrate 1 were wiped off with a clean cloth to obtain a solder bump forming film in which the solder particles 1 and dodecane were arranged in the recesses of the evaluation substrate 1.
  • Step e2 Preparation of evaluation chip
  • Chip C8 size 8 ⁇ 4 ⁇ m, pitch in X direction 16 ⁇ m, pitch in Y direction 8 ⁇ m, height: 3 ⁇ m, number of bumps 382000
  • Chip C9 Size 16 ⁇ m ⁇ 8 ⁇ m, X-direction pitch 32 ⁇ m, Y-direction pitch 16 ⁇ m, height: 5 ⁇ m, number of bumps 95700
  • Chip C10 Size 24 ⁇ m ⁇ 12 ⁇ m, X-direction pitch 48 ⁇ m, Y-direction pitch 24 ⁇ m, height: 8 ⁇ m, number of bumps 42500 Chip C11 ...
  • Step f3 Solder bump formation: Nitrogen atmosphere Using the evaluation solder bump forming film 25 produced in step k1 according to the procedures i) to iii) shown below, a chip with gold bumps (10 mm ⁇ 10 mm, thickness: Solder bumps were formed at 0.5 mm). i) The chip C8 was fixed on a glass plate of 30 mm ⁇ 30 mm (thickness 0.5 mm) with the gold bump facing up. This was adsorbed and fixed to the stage of a flip chip bonder (FC3000: manufactured by Toray Industries, Inc.).
  • FC3000 flip chip bonder
  • the evaluation substrate 1 having a size of 20 mm ⁇ 20 mm was picked up by the heating and pressurizing head, the alignment mark was read by the camera, the electrode position of the chip C8 and the recess of the evaluation substrate 1 were opposed to each other, and the evaluation substrate 1 was temporarily placed.
  • a bell-shaped glass cover that allows nitrogen gas to be blown inside was prepared. The entire hot plate was covered with this glass cover, and the temperature of the hot plate of the hot plate was raised to 150 ° C.
  • the sample prepared in ii) was placed on a hot plate, a stainless steel weight was placed on the evaluation substrate 1 on the uppermost stage, and the sample was heated in a nitrogen atmosphere for 3 minutes.
  • the chip C8 was immersed in a methanol solution, the fluidized bed was washed and removed, and vacuum dried (at 40 ° C. for 60 minutes) to obtain an evaluation chip 25 with solder bumps.
  • solder bump evaluation Formic acid gas not used>
  • the evaluation chip 25 obtained in step f1 was fixed to the surface of the SEM observation pedestal, and the surface was subjected to platinum sputtering.
  • the number of solder bumps formed on the gold bumps was counted by SEM, the solder bump formation rate was calculated, and the evaluation was performed according to the following evaluation criteria. The results are shown in Table 11. It can be said that the evaluation of the solder bump formation rate is good when the criteria of A or B are satisfied.
  • Solder bump formation rate is 90% or more
  • B Solder bump formation rate is 80% or more and less than 90%
  • C Solder bump formation rate is 70% or more and less than 80%
  • D Solder bump formation rate is 60% or more and less than 70%
  • E Solder bump formation rate is less than 60%
  • solder bumps were sufficiently formed on the gold bumps. Solder bumps were formed only on the electrodes and no solder particles were present between the electrodes. Since the opening surface of the recess of the solder bump forming film is pressed against the electrode surface, there is a low possibility that the melted solder leaks from the electrode surface even if there is a fluid phase, and the solder bump can be stably formed.
  • Step f4 Solder bump formation: Formic acid atmosphere Solder bumps were formed and evaluated using the same method as in step f3, except that iii) in step f3 was replaced with the following method. The evaluation results are shown in Table 12. iii) A glass plate on which the evaluation base 1 was placed on the chip C8 was placed and fixed on a hot plate of a formic acid furnace (manufactured by Shinko Seiki Co., Ltd.), and a stainless steel weight was placed on the evaluation base 1. .. After vacuum degassing the inside of the furnace, the treatment was carried out at 150 ° C. for 3 minutes in a formic acid atmosphere, and the pressure was returned to atmospheric pressure.
  • the chip C8 was immersed in a methanol solution, the fluid phase was washed and removed, and vacuum dried (at 40 ° C. for 60 minutes) to obtain an evaluation chip 43 with solder bumps.
  • step f4 solder bumps were formed in the combinations shown in Table 12 to obtain evaluation chips 44 to 60.
  • Table 12 shows the evaluation results obtained in the same manner as above.
  • Step f5 Solder bump formation: Vacuum pressurization Solder bumps were formed and evaluated by the same method as in step f3, except that iii) in step f3 was replaced with the following method. The evaluation results are shown in Table 13. iii) A glass plate on which the evaluation substrate 1 was placed on the chip C8 was placed on a carrier film of a vacuum pressurizing laminator (MVL-500: manufactured by Japan Steel Works, Ltd.). The upper and lower heating plate temperature was set to 145 ° C., and the treatment was performed at a pressure of 0.5 MPa and a pressurization time of 3 s. Then, the evaluation substrate 1 was removed.
  • VML-500 vacuum pressurizing laminator
  • step f5 solder bumps were formed in the combinations shown in Table 13 to obtain evaluation chips 62 to 78.
  • Table 13 shows the evaluation results obtained in the same manner as above.
  • Step e3 Preparation of evaluation chip
  • Step f6 Solder bump formation: Vacuum pressurization Solder bumps were formed and evaluated by the same method as in step f3, except that iii) in step f3 was replaced with the following method. The evaluation results are shown in Table 14. iii) A glass plate on which the evaluation substrate 1 was placed on the chip C14 was placed on a carrier film of a vacuum pressurizing laminator (MVL-500: manufactured by Japan Steel Works, Ltd.). The temperature of the upper and lower hot plates was set to 150 ° C., and the treatment was performed at a pressure of 0.5 MPa and a pressurization time of 10 s. Then, the evaluation substrate 1 was removed. Subsequently, the chip C14 was immersed in a methanol solution, the fluid phase was washed and removed, and vacuum dried (at 40 ° C. for 60 minutes) to obtain an evaluation chip 79 with solder bumps.
  • VML-500 vacuum pressurizing laminator
  • step f6 solder bumps were formed in the combinations shown in Table 14 to obtain evaluation chips 80 to 96.
  • Table 14 shows the evaluation results obtained in the same manner as above.
  • Step g2 Preparation of evaluation substrate
  • Six types of substrates with gold bumps (40 ⁇ 40 mm, thickness: 0.5 mm) shown below were prepared.
  • the arrangement of the Au bumps is a position relative to the Au bumps of the chips C8 to C13, respectively, and there are three alignment marks so that the alignment can be performed.
  • the gold bumps are also formed with lead-out wiring for resistance measurement.
  • Substrate D8 Corresponding chip: Chip C8 / size 8 ⁇ 4 ⁇ m, pitch in X direction 16 ⁇ m, pitch in Y direction 8 ⁇ m, height: 3 ⁇ m, number of bumps 382000
  • Substrate D9 Preparation of evaluation substrate
  • Corresponding chip Chip C9 / size 16 ⁇ m ⁇ 8 ⁇ m, pitch in X direction 32 ⁇ m, pitch in Y direction 16 ⁇ m, height: 5 ⁇ m, number of bumps 95700 Substrate D10 ...
  • Corresponding chip Chip C10 / size 24 ⁇ m ⁇ 12 ⁇ m, pitch in X direction 48 ⁇ m, pitch in Y direction 24 ⁇ m, height: 8 ⁇ m, number of bumps 42500 Substrate D11 ...
  • Corresponding chip Chip C11 / size 72 ⁇ m ⁇ 36 ⁇ m, X-direction pitch 144 ⁇ m, Y-direction pitch 72 ⁇ m, height: 10 ⁇ m, number of bumps 4700 Substrate D12 ...
  • Corresponding chip Chip C12 / size 96 ⁇ m ⁇ 48 ⁇ m, X-direction pitch 192 ⁇ m, Y-direction pitch 96 ⁇ m, height: 13 ⁇ m, number of bumps 2600 Substrate D13 ...
  • Corresponding chip Chip C13 / size 140 ⁇ m ⁇ 70 ⁇ m, X-direction pitch 280 ⁇ m, Y-direction pitch 140 ⁇ m, height: 18 ⁇ m, number of bumps 1200
  • Step h2 Joining the electrodes
  • the evaluation chip with solder bumps produced in step f5 was used to connect the evaluation substrate with gold bumps to the evaluation substrate with solder bumps.
  • the substrate on which the gold bumps were formed was fixed to the stage of a flip chip bonder (FC3000: manufactured by Toray Industries, Inc.).
  • FC3000 manufactured by Toray Industries, Inc.
  • the evaluation chips on which the solder bumps were formed were picked up by the heating and pressurizing head and placed at positions where the gold bumps face each other from the alignment mark.
  • the substrate on which the evaluation chip was placed was placed on the lower hot plate of a formic acid reflow furnace (manufactured by Shinko Seiki Co., Ltd., batch type vacuum soldering device), and a stainless steel weight was placed on the upper part of the evaluation chip.
  • a formic acid vacuum reflow furnace manufactured by Shinko Seiki Co., Ltd., batch type vacuum soldering device
  • the formic acid vacuum reflow furnace was operated, evacuated, filled with formic acid gas, the temperature of the lower hot plate was raised to 150 ° C., and the mixture was heated for 5 minutes. Then, after discharging formic acid gas by evacuation, nitrogen substitution was performed, the lower hot plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere.
  • connection structure> A part of the obtained connection structure was subjected to a conduction resistance test and an insulation resistance test in the same manner as in Step: h1. The results are shown in Tables 15, 16 and 17.
  • Step g3 Preparation of evaluation substrate Six types of substrates with copper bumps (40 ⁇ 40 mm, thickness: 0.5 mm) shown below were prepared. The Cu bumps are arranged at positions relative to the Cu bumps of the chips C14 to C19, and there are three alignment marks so that the Cu bumps can be aligned. The Cu bumps are also formed with lead-out wiring for resistance measurement.
  • Substrate D14 Corresponding chip: Chip C14 / size 8 ⁇ 4 ⁇ m, pitch in X direction 16 ⁇ m, pitch in Y direction 8 ⁇ m, height: 3 ⁇ m, number of bumps 382000
  • Substrate D15 corresponds to Chip C14 / size 8 ⁇ 4 ⁇ m, pitch in X direction 16 ⁇ m, pitch in Y direction 8 ⁇ m, height: 3 ⁇ m, number of bumps 382000
  • Substrate D15 Substrate D15 ...
  • Corresponding chip Chip C15 / size 16 ⁇ m ⁇ 8 ⁇ m, pitch in X direction 32 ⁇ m, pitch in Y direction 16 ⁇ m, height: 5 ⁇ m, number of bumps 95700 Substrate D16 ...
  • Corresponding chip Chip C16 / size 24 ⁇ m ⁇ 12 ⁇ m, pitch in X direction 48 ⁇ m, pitch in Y direction 24 ⁇ m, height: 8 ⁇ m, number of bumps 42500 Substrate D17 ...
  • Corresponding chip Chip C17 / size 72 ⁇ m ⁇ 36 ⁇ m, X-direction pitch 144 ⁇ m, Y-direction pitch 72 ⁇ m, height: 10 ⁇ m, number of bumps 4700 Substrate D18 ...
  • Corresponding chip Chip C18 / size 96 ⁇ m ⁇ 48 ⁇ m, X-direction pitch 192 ⁇ m, Y-direction pitch 96 ⁇ m, height: 13 ⁇ m, number of bumps 2600 Substrate D19 ...
  • Corresponding chip Chip C19 / size 140 ⁇ m ⁇ 70 ⁇ m, X-direction pitch 280 ⁇ m, Y-direction pitch 140 ⁇ m, height: 18 ⁇ m, number of bumps 1200
  • Step h3 Joining the electrodes
  • the evaluation chip with solder bumps produced in step f6 was used to connect to the evaluation substrate with copper bumps via the solder bumps.
  • the evaluation substrate was set on a spin coater (SC-308S manufactured by Oshigane Co., Ltd.), and 0.5 ml of flux (WHS-003C: manufactured by Arakawa Chemical Industry Co., Ltd.) was dropped on the surface on which Cu bumps were formed.
  • a thin film flux layer was formed by treating at a rotation speed of 500 rpm for 10 s and then at 1000 rpm for 3 s.
  • the evaluation substrate was fixed to the stage of a flip chip bonder (FC3000: manufactured by Toray Industries, Inc.).
  • the evaluation chips on which the solder bumps were formed were picked up by the heating and pressurizing head and placed at positions where the bumps face each other from the alignment mark.
  • the substrate on which the evaluation chip was placed was placed on the lower heating plate of a formic acid reflow furnace (manufactured by Shinko Seiki Co., Ltd., a batch type vacuum soldering device), and a stainless steel weight was placed on the upper part of the evaluation chip.
  • the formic acid vacuum reflow furnace was operated, evacuated, filled with formic acid gas, the temperature of the lower hot plate was raised to 160 ° C., and the mixture was heated for 3 minutes. Then, after discharging formic acid gas by evacuation, nitrogen substitution was performed, the lower hot plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere.
  • An appropriate amount of underfill material (CEL series manufactured by Hitachi Kasei Co., Ltd.) whose viscosity has been adjusted is placed between the evaluation chip and the evaluation substrate, filled by vacuuming, and then cured at 125 ° C. for 4 hours to form the evaluation chip and the evaluation substrate.
  • a connection structure was prepared.
  • connection structure> A part of the obtained connection structure was subjected to a conduction resistance test and an insulation resistance test in the same manner as in Step: h1. The results are shown in Tables 18, 19 and 20.

Abstract

A solder bump forming member comprising a base having a plurality of recesses, and solder particles and a fluidizer that are located inside the recesses, the solder bump forming member being such that the average particle diameter of the solder particles is 1-35 µm, and the C.V. value is 20% or less.

Description

はんだバンプ形成用部材、はんだバンプ形成用部材の製造方法、及びはんだバンプ付き電極基板の製造方法Manufacturing method of solder bump forming member, solder bump forming member, and manufacturing method of electrode substrate with solder bump
　本発明は、はんだバンプ形成用部材、はんだバンプ形成用部材製造方法、及びはんだバンプ付き電極基板の製造方法に関する。 The present invention relates to a solder bump forming member, a method for manufacturing a solder bump forming member, and a method for manufacturing an electrode substrate with solder bumps.
　所定パターンで設けられた複数のはんだボール挿入孔を備えたマスクと、該挿入孔に収容されたはんだボールと、該挿入孔の中にはんだボールを保持する固着剤から構成されていることを特徴とするはんだボール配置シートが知られている（例えば、特許文献１参照）。 It is characterized by being composed of a mask having a plurality of solder ball insertion holes provided in a predetermined pattern, solder balls housed in the insertion holes, and a fixing agent for holding the solder balls in the insertion holes. A solder ball arrangement sheet is known (see, for example, Patent Document 1).
　下記工程を含む、所定位置にはんだボール又ははんだ粉末を保持した、はんだバンプ形成用シートの製造方法が知られている（例えば、特許文献２参照）。
　Ａ．片面に、底面が粘着剤から構成された多数の窪みを所定位置に有するシートを準備し；Ｂ．シートの各窪みにはんだ粉末を充填して、窪み底面の粘着剤によりはんだ粉末を付着保持し；Ｃ．粘着剤で保持されていないはんだ粉末をシートから除去し、そしてＤ．シートの窪み内のはんだ粉末を被覆する。 A method for manufacturing a solder bump forming sheet in which a solder ball or a solder powder is held at a predetermined position including the following steps is known (see, for example, Patent Document 2).
A. Prepare a sheet on one side with a number of recesses in place, the bottom of which is made of an adhesive; B. Each recess of the sheet is filled with solder powder, and the adhesive on the bottom of the recess adheres and holds the solder powder; The solder powder that is not held by the adhesive is removed from the sheet, and D.I. Cover the solder powder in the recesses of the sheet.
　凹溝内に配置したはんだボールを粘着ロール面に転写し、さらにこのはんだボールを電極上の粘着剤に移すことで、電極上にはんだバンプを形成する方法が知られている（例えば、特許文献３参照）。 A method of forming solder bumps on an electrode by transferring a solder ball arranged in a groove to an adhesive roll surface and further transferring the solder ball to an adhesive on an electrode is known (for example, Patent Documents). 3).
特開２００４－０８００２４号公報Japanese Unexamined Patent Publication No. 2004-080024 国際公開第２００６／０４３３７７号International Publication No. 2006/0433377 特開２０１７－１５７６２６号公報JP-A-2017-157626
　特許文献１及び２に示される転写シート及び製造方法では、はんだ粒子を保持するための粘着層が必要となっている。そのため、はんだ融点以上に加熱してはんだを溶解・合一化し、さらに電極上に転写する際の加熱により、粘着層成分が軟化・溶融・分解して夾雑物となり得る。夾雑物がはんだと電極の間に介在することで、はんだバンプの安定した形成が妨げられる虞がある。電極上にはんだバンプを転写した後、これらの夾雑物を除去する場合、電極が形成された基板及び半導体パッケージを洗浄液にさらすことになり、工程の増加、基体・半導体パッケージの不具合、洗浄不良による不具合などが発生する虞がある。 The transfer sheet and the manufacturing method shown in Patent Documents 1 and 2 require an adhesive layer for holding the solder particles. Therefore, the adhesive layer component may be softened, melted, and decomposed to become a contaminant by heating above the melting point of the solder to melt and coalesce the solder, and further to transfer the solder onto the electrode. The presence of contaminants between the solder and the electrodes may hinder the stable formation of solder bumps. When removing these impurities after transferring the solder bumps onto the electrodes, the substrate and semiconductor package on which the electrodes are formed are exposed to the cleaning liquid, resulting in an increase in processes, defects in the substrate / semiconductor package, and poor cleaning. There is a risk that problems will occur.
　特許文献３では、粘着剤を介してはんだボール（粒子）を電極上に配置していくため、粘着剤成分がはんだボール表面に残り、接合に不具合を与える虞がある。また、粘着剤の厚み及び粘着剤表面の凹凸の制御は、はんだボールの大きさが１００μｍ程度では一応可能であるが、大きさが５０μｍ、３０μｍと小さくなるに従い困難となる。そのため、３０μｍを下回るはんだボール（粒子）を粘着剤を介して転写・移動させると、転写率を上げることが困難となる。 In Patent Document 3, since the solder balls (particles) are arranged on the electrodes via the adhesive, the adhesive component may remain on the surface of the solder balls and cause a problem in joining. Further, the thickness of the pressure-sensitive adhesive and the unevenness of the surface of the pressure-sensitive adhesive can be controlled when the size of the solder ball is about 100 μm, but it becomes more difficult as the size becomes smaller as 50 μm and 30 μm. Therefore, if solder balls (particles) having a size of less than 30 μm are transferred and moved via an adhesive, it becomes difficult to increase the transfer rate.
　その他、はんだボール（粒子）同士が接触しながら基材表面に粘着剤を介して一様に配置されている転写シートが知られている。この転写シートのはんだボール面を、電極が形成された基板に押し当て加熱することで、電極上にはんだボールを転写し、その後のリフローによりバンプが形成できるとされている。しかしながら、発明者らが検討したところ、電極間隔が狭くなってくると電極間をはんだがブリッジしてしまい、ショート（短絡）不良が発生した。隣接するはんだボール同士が接触しているため、どうしても電極への転写時の熱により、はんだが溶解・合一化してしまい、隣接電極間をまたぐ部分が発生するものと推察される。このようにはんだ粒子同士が接触しながら一様に並べられたはんだ転写シートでは、数ミクロンレベルの電極間隔である場合に、短絡なくはんだバンプを形成することは難しいのが現状である。 In addition, there is known a transfer sheet in which solder balls (particles) are uniformly arranged on the surface of a base material via an adhesive while being in contact with each other. It is said that the solder ball surface of this transfer sheet is pressed against a substrate on which an electrode is formed and heated to transfer the solder ball onto the electrode, and bumps can be formed by subsequent reflow. However, as a result of the examination by the inventors, when the electrode spacing becomes narrower, the solder bridges between the electrodes, and a short circuit defect occurs. Since the adjacent solder balls are in contact with each other, it is presumed that the heat at the time of transfer to the electrodes inevitably causes the solder to melt and coalesce, resulting in a portion straddling the adjacent electrodes. In the solder transfer sheet in which the solder particles are uniformly arranged while being in contact with each other in this way, it is difficult to form solder bumps without a short circuit when the electrode spacing is on the order of several microns.
　本発明は上記事情に鑑みてなされたものであり、電気的に互いに接続すべき回路部材の接続箇所が微小であっても、絶縁信頼性及び導通信頼性の両方が優れる接続構造体を製造するのに有用なはんだバンプ形成用部材及びその製造方法を提供することを目的とする。また、本発明は当該部材を用いたはんだバンプ付き電極基板の製造方法を提供することを目的とする。 The present invention has been made in view of the above circumstances, and manufactures a connection structure having excellent insulation reliability and conduction reliability even if the connection points of circuit members to be electrically connected to each other are minute. It is an object of the present invention to provide a member for forming a solder bump and a method for manufacturing the same. Another object of the present invention is to provide a method for manufacturing an electrode substrate with solder bumps using the member.
　本発明の一側面は、複数の凹部を有する基体と、凹部内にはんだ粒子及び流動化剤と、を備え、はんだ粒子の平均粒子径が１～３５μｍであり、Ｃ．Ｖ．値が２０％以下である、はんだバンプ形成用部材に関する。 One aspect of the present invention includes a substrate having a plurality of recesses, solder particles and a fluidizing agent in the recesses, and the average particle size of the solder particles is 1 to 35 μm. V. The present invention relates to a solder bump forming member having a value of 20% or less.
　上記はんだバンプ形成用部材は、電気的に互いに接続すべき回路部材の接続箇所が微小であっても、絶縁信頼性及び導通信頼性の両方が優れる接続構造体を製造するのに有用である。 The solder bump forming member is useful for manufacturing a connection structure having excellent insulation reliability and conduction reliability even if the connection points of the circuit members to be electrically connected to each other are minute.
　はんだバンプ形成用部材の一態様において、流動化剤は、コハク酸、グルタル酸、アジピン酸、ピメリン酸、スベリン酸、安息香酸、及びリンゴ酸からなる群より選択される少なくとも一種を含んでよい。 In one aspect of the solder bump forming member, the fluidizing agent may include at least one selected from the group consisting of succinic acid, glutaric acid, adipic acid, pimelic acid, suberic acid, benzoic acid, and malic acid.
　はんだバンプ形成用部材の一態様において、はんだ粒子の表面の一部に平面部が形成されていてよい。 In one aspect of the solder bump forming member, a flat surface portion may be formed on a part of the surface of the solder particles.
　はんだバンプ形成用部材の一態様において、隣接する凹部間の距離が、はんだ粒子の平均粒子径の０．１倍以上であってよい。 In one aspect of the solder bump forming member, the distance between adjacent recesses may be 0.1 times or more the average particle size of the solder particles.
　本発明の一側面は、複数の凹部を有する基体、並びにはんだ粒子及び流動化剤を準備する前工程と、凹部に、はんだ粒子及び流動化剤を配置する配置工程と、を備える、はんだバンプ形成用部材の製造方法に関する。 One aspect of the present invention includes a substrate having a plurality of recesses, a pre-step of preparing solder particles and a fluidizing agent, and an arranging step of arranging the solder particles and the fluidizing agent in the recesses, for forming solder bumps. The present invention relates to a manufacturing method of a member.
　本発明の一側面は、複数の凹部を有する基体及びはんだ微粒子を準備する準備工程と、はんだ微粒子の少なくとも一部を、凹部に収容する収容工程と、凹部に収容されたはんだ微粒子を融合させて、凹部内にはんだ粒子を形成する融合工程と、はんだ粒子が形成された凹部内に流動化剤を配置する注入工程と、を備える、はんだバンプ形成用部材の製造方法に関する。 One aspect of the present invention is to fuse a preparatory step for preparing a substrate having a plurality of recesses and solder fine particles, a storage step for storing at least a part of the solder fine particles in the recesses, and a solder fine particles housed in the recesses. The present invention relates to a method for manufacturing a solder bump forming member, comprising a fusion step of forming solder particles in the recesses and an injection step of arranging a fluidizing agent in the recesses in which the solder particles are formed.
　はんだバンプ形成用部材の製造方法の一態様において、はんだ粒子の平均粒子径が１～３５μｍであり、Ｃ．Ｖ．値が２０％以下であってよい。 In one aspect of the method for manufacturing a member for forming a solder bump, the average particle size of the solder particles is 1 to 35 μm, and C.I. V. The value may be 20% or less.
　はんだバンプ形成用部材の製造方法の一態様において、はんだ微粒子のＣ．Ｖ．値が２０％を超えてよい。 In one aspect of the method for manufacturing a member for forming a solder bump, C.I. V. The value may exceed 20%.
　はんだバンプ形成用部材の製造方法の一態様は、融合工程の前に、凹部に収容されたはんだ微粒子を還元雰囲気に晒す還元工程を更に備えてよい。 One aspect of the method for manufacturing the solder bump forming member may further include a reduction step of exposing the solder fine particles contained in the recesses to a reducing atmosphere before the fusion step.
　はんだバンプ形成用部材の製造方法の一態様において、融合工程において、はんだ微粒子を還元雰囲気下で融合させてよい。 In one aspect of the method for manufacturing a member for forming a solder bump, the solder fine particles may be fused in a reducing atmosphere in the fusion step.
　本発明の一側面は、上記はんだバンプ形成用部材、及び複数の電極を有する基板、を準備する準備工程と、はんだバンプ形成用部材の凹部を有する面及び基板の電極を有する面を対向させて接触させる配置工程と、はんだ粒子をはんだ粒子の融点以上の温度に加熱する加熱工程と、を備える、はんだバンプ付き電極基板の製造方法に関する。 One aspect of the present invention is a preparatory step for preparing the solder bump forming member and a substrate having a plurality of electrodes, and a surface having a recess of the solder bump forming member and a surface having electrodes of the substrate are opposed to each other. The present invention relates to a method for manufacturing an electrode substrate with solder bumps, which comprises an arrangement step of contacting the solder particles and a heating step of heating the solder particles to a temperature equal to or higher than the melting point of the solder particles.
　はんだバンプ付き電極基板の製造方法の一態様における加熱工程において、はんだバンプ形成用部材及び基板を加圧状態で接触させながら、はんだ粒子をはんだ粒子の融点以上の温度に加熱してよい。 In the heating step in one aspect of the method for manufacturing an electrode substrate with solder bumps, the solder particles may be heated to a temperature equal to or higher than the melting point of the solder particles while contacting the solder bump forming member and the substrate in a pressurized state.
　はんだバンプ付き電極基板の製造方法の一態様は、配置工程の前に、はんだ粒子を還元雰囲気に晒す還元工程を更に備えてよい。 One aspect of the method for manufacturing an electrode substrate with solder bumps may further include a reduction step of exposing the solder particles to a reducing atmosphere before the placement step.
　はんだバンプ付き電極基板の製造方法の一態様は、配置工程の後であって加熱工程の前に、はんだ粒子を還元雰囲気に晒す還元工程を更に備えてよい。 One aspect of the method for manufacturing an electrode substrate with solder bumps may further include a reduction step of exposing the solder particles to a reducing atmosphere after the placement step and before the heating step.
　はんだバンプ付き電極基板の製造方法の一態様における加熱工程において、還元雰囲気下ではんだ粒子をはんだ粒子の融点以上の温度に加熱してよい。 In the heating step in one aspect of the method for manufacturing an electrode substrate with solder bumps, the solder particles may be heated to a temperature equal to or higher than the melting point of the solder particles in a reducing atmosphere.
　はんだバンプ付き電極基板の製造方法の一態様は、加熱工程の後に、はんだバンプ形成用部材を基板から除去する除去工程を更に備えてよい。 One aspect of the method for manufacturing an electrode substrate with solder bumps may further include a removal step of removing the solder bump forming member from the substrate after the heating step.
　はんだバンプ付き電極基板の製造方法の一態様は、除去工程の後に、電極に結合していないはんだ粒子を除去する洗浄工程を更に備えてよい。 One aspect of the method for manufacturing an electrode substrate with solder bumps may further include a cleaning step of removing solder particles that are not bonded to the electrodes after the removal step.
　本発明によれば、電気的に互いに接続すべき回路部材の接続箇所が微小であっても、絶縁信頼性及び導通信頼性の両方が優れる接続構造体を製造するのに有用なはんだバンプ形成用部材及びその製造方法を提供することができる。また、本発明によれば、当該部材を用いたはんだバンプ付き電極基板の製造方法を提供することができる。 According to the present invention, for forming solder bumps useful for manufacturing a connection structure having excellent insulation reliability and conduction reliability even if the connection points of circuit members to be electrically connected to each other are minute. A member and a method for manufacturing the member can be provided. Further, according to the present invention, it is possible to provide a method for manufacturing an electrode substrate with solder bumps using the member.
図１は、一実施形態に係るはんだバンプ形成用部材を模式的に示す断面図である。FIG. 1 is a cross-sectional view schematically showing a solder bump forming member according to an embodiment. 図２（ａ）は、図１における凹部の開口部と反対側からはんだ粒子を見た図であり、図２（ｂ）ははんだ粒子の投影像に外接する四角形を二対の平行線により作成した場合における、対向する辺間の距離Ｘ及びＹ（但しＹ＜Ｘ）を示す図である。FIG. 2A is a view of the solder particles viewed from the side opposite to the opening of the recess in FIG. 1, and FIG. 2B is a quadrangle circumscribing the projected image of the solder particles created by two pairs of parallel lines. It is a figure which shows the distance X and Y (where Y <X) between the opposite sides in the case of. 図３（ａ）は、基体の一例を模式的に示す平面図であり、図３（ｂ）は、図３（ａ）のＩｂ－Ｉｂ線における断面図である。FIG. 3A is a plan view schematically showing an example of the substrate, and FIG. 3B is a cross-sectional view taken along the line Ib-Ib of FIG. 3A. 図４（ａ）～（ｈ）は、基体が有する凹部の断面形状の例を模式的に示す断面図である。4 (a) to 4 (h) are cross-sectional views schematically showing an example of the cross-sectional shape of the concave portion of the substrate. 図５は、基体の凹部にはんだ微粒子が収容された状態を模式的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing a state in which solder fine particles are contained in the recesses of the substrate. 図６（ａ）及び図６（ｂ）は、はんだバンプ付き電極基板の製造過程の一例を模式的に示す断面図である。6 (a) and 6 (b) are cross-sectional views schematically showing an example of a manufacturing process of an electrode substrate with solder bumps. 図７（ａ）及び図７（ｂ）は、接続構造体の製造過程の一例を模式的に示す断面図である。7 (a) and 7 (b) are cross-sectional views schematically showing an example of a manufacturing process of the connection structure. 図８は、基体の一例を模式的に示す断面図である。FIG. 8 is a cross-sectional view schematically showing an example of the substrate.
　以下、本発明の実施形態について説明する。本発明は以下の実施形態に限定されるものではない。なお、以下で例示する材料は、特に断らない限り、一種単独で用いてもよく、二種以上を組み合わせて用いてもよい。組成物中の各成分の含有量は、組成物中に各成分に該当する物質が複数存在する場合、特に断らない限り、組成物中に存在する当該複数の物質の合計量を意味する。「～」を用いて示された数値範囲は、「～」の前後に記載される数値をそれぞれ最小値及び最大値として含む範囲を示す。本明細書中に段階的に記載されている数値範囲において、ある段階の数値範囲の上限値又は下限値は、他の段階の数値範囲の上限値又は下限値に置き換えてもよい。本明細書中に記載されている数値範囲において、その数値範囲の上限値又は下限値は、実施例に示されている値に置き換えてもよい。 Hereinafter, embodiments of the present invention will be described. The present invention is not limited to the following embodiments. Unless otherwise specified, the materials exemplified below may be used alone or in combination of two or more. The content of each component in the composition means the total amount of the plurality of substances present in the composition when a plurality of substances corresponding to each component are present in the composition, unless otherwise specified. The numerical range indicated by using "-" indicates a range including the numerical values before and after "-" as the minimum value and the maximum value, respectively. In the numerical range described stepwise in the present specification, the upper limit value or the lower limit value of the numerical range of one step may be replaced with the upper limit value or the lower limit value of the numerical range of another step. In the numerical range described in the present specification, the upper limit value or the lower limit value of the numerical range may be replaced with the value shown in the examples.
＜はんだバンプ形成用部材＞
　一態様において、はんだバンプ形成用部材は、複数の凹部を有する基体と、凹部内にはんだ粒子及び流動化剤と、を備え、はんだ粒子の平均粒子径が１～３５μｍであり、Ｃ．Ｖ．値が２０％以下である。 <Solder bump forming member>
In one aspect, the solder bump forming member includes a substrate having a plurality of recesses, solder particles and a fluidizing agent in the recesses, and the average particle size of the solder particles is 1 to 35 μm. V. The value is 20% or less.
　図１は、一実施形態に係るはんだバンプ形成用部材を模式的に示す断面図である。はんだバンプ形成用部材１０は、複数の凹部６２を有する基体６０と、凹部６２内にはんだ粒子１及び流動化剤Ｆと、を備えている。はんだバンプ形成用部材１０の所定の縦断面において、一個のはんだ粒子１は隣接する一個のはんだ粒子１と離隔した状態で横方向（図１における左右方向）に並ぶように配置されている。はんだ粒子１は、凹部６２内において、その側面及び／又は底面と接していてよい。流動化剤Ｆは、はんだ粒子１と凹部６２の底面との間に存在していてもよい。はんだバンプ形成用部材は、フィルム状（はんだバンプ形成用フィルム）、シート状（はんだバンプ形成用シート）等であってよい。 FIG. 1 is a cross-sectional view schematically showing a solder bump forming member according to an embodiment. The solder bump forming member 10 includes a substrate 60 having a plurality of recesses 62, and solder particles 1 and a fluidizing agent F in the recesses 62. In a predetermined vertical cross section of the solder bump forming member 10, one solder particle 1 is arranged so as to be arranged in a horizontal direction (horizontal direction in FIG. 1) in a state of being separated from one adjacent solder particle 1. The solder particles 1 may be in contact with the side surface and / or the bottom surface thereof in the recess 62. The fluidizing agent F may be present between the solder particles 1 and the bottom surface of the recess 62. The solder bump forming member may be in the form of a film (solder bump forming film), sheet form (solder bump forming sheet), or the like.
（はんだ粒子）
　はんだ粒子１の平均粒子径は、例えば３５μｍ以下であり、好ましくは３０μｍ以下、２５μｍ以下、２０μｍ以下、又は１５μｍ以下である。また、はんだ粒子１の平均粒子径は、例えば１μｍ以上であり、好ましくは２μｍ以上、より好ましくは３μｍ以上、さらに好ましくは５μｍ以上である。 (Solder particles)
The average particle size of the solder particles 1 is, for example, 35 μm or less, preferably 30 μm or less, 25 μm or less, 20 μm or less, or 15 μm or less. The average particle size of the solder particles 1 is, for example, 1 μm or more, preferably 2 μm or more, more preferably 3 μm or more, and further preferably 5 μm or more.
　はんだ粒子１の平均粒子径は、サイズに合わせた各種方法を用いて測定することができる。例えば、動的光散乱法、レーザー回折法、遠心沈降法、電気的検知帯法、共振式質量測定法等の方法を利用できる。さらに、光学顕微鏡、電子顕微鏡等によって得られる画像から、粒子サイズを測定する方法を利用できる。具体的な装置としては、フロー式粒子像分析装置、マイクロトラック、コールターカウンター等が挙げられる。はんだ粒子１の平均粒子径は、はんだバンプ形成用部材１０の主面に対して垂直方向からはんだ粒子１を観察した時の、投影面積円相当径（粒子の投影面積と等しい面積をもつ円の直径）とすることができる。 The average particle size of the solder particles 1 can be measured by using various methods according to the size. For example, a dynamic light scattering method, a laser diffraction method, a centrifugal sedimentation method, an electrical detection band method, a resonance type mass measurement method, or the like can be used. Further, a method of measuring the particle size from an image obtained by an optical microscope, an electron microscope, or the like can be used. Specific devices include a flow-type particle image analyzer, a microtrack, a Coulter counter, and the like. The average particle diameter of the solder particles 1 is the diameter equivalent to the projected area circle (a circle having an area equal to the projected area of the particles) when the solder particles 1 are observed from a direction perpendicular to the main surface of the solder bump forming member 10. Diameter).
　はんだ粒子１のＣ．Ｖ．値は、より優れた導電信頼性及び絶縁信頼性を実現できる観点から、好ましくは２０％以下、より好ましくは１０％以下、更に好ましくは７％以下である。また、はんだ粒子１のＣ．Ｖ．値の下限は特に限定されない。例えば、はんだ粒子１のＣ．Ｖ．値は１％以上であってよく、２％以上であってもよい。 C. of solder particles 1 V. The value is preferably 20% or less, more preferably 10% or less, still more preferably 7% or less, from the viewpoint of achieving more excellent conductivity reliability and insulation reliability. In addition, C.I. V. The lower limit of the value is not particularly limited. For example, C.I. V. The value may be 1% or more, and may be 2% or more.
　はんだ粒子１のＣ．Ｖ．値は、前述の方法によって測定された粒子径の標準偏差を平均粒子径で割った値に１００を掛けることで算出される。 C. of solder particles 1 V. The value is calculated by multiplying the value obtained by dividing the standard deviation of the particle size measured by the above method by the average particle size by 100.
　はんだ粒子の表面の一部に平面部が形成されていてよい。図２（ａ）は、図１における凹部６２の開口と反対側からはんだ粒子１を見た図である。はんだ粒子１は、直径Ｂを有する球の表面の一部に直径Ａの平面部１１が形成された形状を有している。なお、図１及び図２（ａ）に示すはんだ粒子１は、凹部６２の底部が平面であるため平面部１１を有するが、凹部６２の底部が平面以外の形状である場合は、底部の形状に対応した異なる形状の面を有するものとなる。 A flat surface may be formed on a part of the surface of the solder particles. FIG. 2A is a view of the solder particles 1 viewed from the side opposite to the opening of the recess 62 in FIG. The solder particles 1 have a shape in which a flat surface portion 11 having a diameter A is formed on a part of the surface of a sphere having a diameter B. The solder particles 1 shown in FIGS. 1 and 2A have a flat surface portion 11 because the bottom portion of the recess 62 is flat, but when the bottom portion of the recess 62 has a shape other than a flat surface, the shape of the bottom portion is formed. It will have a surface with a different shape corresponding to.
　図２（ａ）に示すように、はんだ粒子１は、表面の一部に平面部１１が形成されていてよく、このとき当該平面部１１以外の表面は、球冠状であることが好ましい。すなわち、はんだ粒子１は、平面部１１と、球冠状の曲面部と、を有するものであってよい。はんだ粒子１の直径Ｂに対する平面部１１の直径Ａの比（Ａ／Ｂ）は、例えば０．０１超１．０未満（０．０１＜Ａ／Ｂ＜１．０）であってよく、０．１～０．９であってもよい。平面部１１と凹部６２の底面とは接触していてよい。図１に示すように、はんだ粒子１が平面部１１を有しており、なおかつ当該平面部と凹部の底面が接触していることで、はんだバンプ形成用部材１０からの脱離が生じ難くなる。なお、平面部は、凹部６２の内壁部とはんだ粒子１とが接する部分にも発生することがある。ただし、はんだバンプ形成用部材を製造する際、後述のとおりはんだ粒子１を基体６０から一旦取り出し、再度基体の凹部にはんだ粒子１と流動化剤Ｆを再配置する場合などは、平面部１１と凹部６２の底面とは必ずしも接触していなくてよい。 As shown in FIG. 2A, a flat surface portion 11 may be formed on a part of the surface of the solder particles 1, and at this time, the surface other than the flat surface portion 11 is preferably spherical crown-shaped. That is, the solder particles 1 may have a flat surface portion 11 and a spherical crown-shaped curved surface portion. The ratio (A / B) of the diameter A of the flat surface portion 11 to the diameter B of the solder particles 1 may be, for example, more than 0.01 and less than 1.0 (0.01 <A / B <1.0), and is 0. It may be 1 to 0.9. The flat surface portion 11 and the bottom surface of the recess 62 may be in contact with each other. As shown in FIG. 1, since the solder particles 1 have the flat surface portion 11 and the flat surface portion and the bottom surface of the recess are in contact with each other, the solder particles 1 are less likely to be detached from the solder bump forming member 10. .. The flat surface portion may also be generated at a portion where the inner wall portion of the recess 62 and the solder particles 1 are in contact with each other. However, when manufacturing the solder bump forming member, when the solder particles 1 are once taken out from the substrate 60 and the solder particles 1 and the fluidizing agent F are rearranged in the recesses of the substrate again as described later, the flat surface portion 11 is used. It does not necessarily have to be in contact with the bottom surface of the recess 62.
　はんだ粒子１の投影像に外接する四角形を二対の平行線により作成した場合において、対向する辺間の距離をＸ及びＹ（但しＹ＜Ｘ）としたときに、Ｘに対するＹの比（Ｙ／Ｘ）は、０．８超１．０未満（０．８＜Ｙ／Ｘ＜１．０）であってよく、０．９以上１．０未満であってもよい。このようなはんだ粒子１はより真球に近い粒子ということができる。はんだ粒子１が真球に近いことで、はんだ粒子１と電極間接触にムラが生じ難く、安定した接続が得られる傾向がある。 When a quadrangle circumscribing the projected image of the solder particle 1 is created by two pairs of parallel lines, and the distance between the opposing sides is X and Y (where Y <X), the ratio of Y to X (Y). / X) may be more than 0.8 and less than 1.0 (0.8 <Y / X <1.0), and may be 0.9 or more and less than 1.0. Such solder particles 1 can be said to be particles closer to a true sphere. Since the solder particles 1 are close to a true sphere, the contact between the solder particles 1 and the electrodes is less likely to be uneven, and a stable connection tends to be obtained.
　図２（ｂ）は、はんだ粒子の投影像に外接する四角形を二対の平行線により作成した場合における、対向する辺間の距離Ｘ及びＹ（但しＹ＜Ｘ）を示す図である。例えば、任意の粒子を走査型電子顕微鏡により観察して投影像を得る。得られた投影像に対し二対の平行線を描画し、一対の平行線は平行線の距離が最小となる位置に、もう一対の平行線は平行線の距離が最大となる位置に配し、その粒子のＹ／Ｘを求める。この作業を３００個のはんだ粒子に対して行って平均値を算出し、はんだ粒子のＹ／Ｘとする。 FIG. 2B is a diagram showing distances X and Y (where Y <X) between opposite sides when a quadrangle circumscribing the projected image of the solder particles is created by two pairs of parallel lines. For example, an arbitrary particle is observed with a scanning electron microscope to obtain a projected image. Two pairs of parallel lines are drawn with respect to the obtained projected image, and the pair of parallel lines are arranged at the position where the distance between the parallel lines is the minimum, and the other pair of parallel lines are arranged at the position where the distance between the parallel lines is the maximum. , Find the Y / X of the particle. This operation is performed on 300 solder particles, the average value is calculated, and the Y / X of the solder particles is obtained.
　はんだ粒子１は、スズ又はスズ合金を含むものであってよい。スズ合金としては、例えば、Ｉｎ－Ｓｎ合金、Ｉｎ－Ｓｎ－Ａｇ合金、Ｓｎ－Ａｕ合金、Ｓｎ－Ｂｉ合金、Ｓｎ－Ｂｉ－Ａｇ合金、Ｓｎ－Ａｇ－Ｃｕ合金、Ｓｎ－Ｃｕ合金等を用いることができる。これらのスズ合金の具体例としては、下記の例が挙げられる。
・Ｉｎ－Ｓｎ（Ｉｎ５２質量％、Ｂｉ４８質量％　融点１１８℃）
・Ｉｎ－Ｓｎ－Ａｇ（Ｉｎ２０質量％、Ｓｎ７７．２質量％、Ａｇ２．８質量％　融点１７５℃）
・Ｓｎ－Ｂｉ（Ｓｎ４３質量％、Ｂｉ５７質量％　融点１３８℃）
・Ｓｎ－Ｂｉ－Ａｇ（Ｓｎ４２質量％、Ｂｉ５７質量％、Ａｇ１質量％　融点１３９℃）
・Ｓｎ－Ａｇ－Ｃｕ（Ｓｎ９６．５質量％、Ａｇ３質量％、Ｃｕ０．５質量％　融点２１７℃）
・Ｓｎ－Ｃｕ（Ｓｎ９９．３質量％、Ｃｕ０．７質量％　融点２２７℃）
・Ｓｎ－Ａｕ（Ｓｎ２１．０質量％、Ａｕ７９．０質量％　融点２７８℃） The solder particles 1 may contain tin or a tin alloy. As the tin alloy, for example, In—Sn alloy, In—Sn—Ag alloy, Sn—Au alloy, Sn—Bi alloy, Sn—Bi—Ag alloy, Sn—Ag—Cu alloy, Sn—Cu alloy and the like are used. be able to. Specific examples of these tin alloys include the following examples.
-In-Sn (In 52% by mass, Bi48% by mass, melting point 118 ° C)
-In-Sn-Ag (In 20% by mass, Sn77.2% by mass, Ag 2.8% by mass, melting point 175 ° C.)
-Sn-Bi (Sn43% by mass, Bi57% by mass, melting point 138 ° C.)
-Sn-Bi-Ag (Sn42% by mass, Bi57% by mass, Ag1% by mass, melting point 139 ° C.)
-Sn-Ag-Cu (Sn96.5% by mass, Ag3% by mass, Cu0.5% by mass, melting point 217 ° C)
-Sn-Cu (Sn99.3% by mass, Cu0.7% by mass, melting point 227 ° C)
-Sn-Au (Sn21.0% by mass, Au79.0% by mass, melting point 278 ° C.)
　はんだ粒子は、インジウム又はインジウム合金を含むものであってよい。インジウム合金としては、例えば、Ｉｎ－Ｂｉ合金、Ｉｎ－Ａｇ合金等を用いることができる。これらのインジウム合金の具体例としては、下記の例が挙げられる。
・Ｉｎ－Ｂｉ（Ｉｎ６６．３質量％、Ｂｉ３３．７質量％　融点７２℃）
・Ｉｎ－Ｂｉ（Ｉｎ３３．０質量％、Ｂｉ６７．０質量％　融点１０９℃）
・Ｉｎ－Ａｇ（Ｉｎ９７．０質量％、Ａｇ３．０質量％　融点１４５℃） The solder particles may contain indium or an indium alloy. As the indium alloy, for example, an In—Bi alloy, an In—Ag alloy, or the like can be used. Specific examples of these indium alloys include the following examples.
-In-Bi (In66.3% by mass, Bi33.7% by mass, melting point 72 ° C.)
-In-Bi (In33.0% by mass, Bi67.0% by mass, melting point 109 ° C)
-In-Ag (In97.0% by mass, Ag3.0% by mass, melting point 145 ° C)
　はんだ粒子１の用途（接続時の温度）等に応じて、上記スズ合金又はインジウム合金を選択することができる。例えば、低温での融着にはんだ粒子１を用いる場合、Ｉｎ－Ｓｎ合金、Ｓｎ－Ｂｉ合金を採用すればよく、この場合、１５０℃以下で融着させることができる。Ｓｎ－Ａｇ－Ｃｕ合金、Ｓｎ－Ｃｕ合金等の融点の高い材料を採用した場合、高温放置後においても高い信頼性を維持することができる。 The tin alloy or indium alloy can be selected according to the application (temperature at the time of connection) of the solder particles 1. For example, when the solder particles 1 are used for fusion at a low temperature, an In—Sn alloy or a Sn—Bi alloy may be adopted, and in this case, the solder particles can be fused at 150 ° C. or lower. When a material having a high melting point such as Sn—Ag—Cu alloy or Sn—Cu alloy is used, high reliability can be maintained even after being left at a high temperature.
　はんだ粒子１は、Ａｇ、Ｃｕ、Ｎｉ、Ｂｉ、Ｚｎ、Ｐｄ、Ｐｂ、Ａｕ、Ｐ及びＢから選ばれる一種以上を含んでもよい。これらの元素のうち、以下の観点からＡｇ又はＣｕを含んでもよい。すなわち、はんだ粒子１がＡｇ又はＣｕを含むことで、はんだ粒子１の融点を２２０℃程度まで低下させることができ、且つ、電極との接合強度がより向上するため、より良好な導通信頼性が得られ易くなる。 The solder particles 1 may contain one or more selected from Ag, Cu, Ni, Bi, Zn, Pd, Pb, Au, P and B. Among these elements, Ag or Cu may be contained from the following viewpoints. That is, when the solder particles 1 contain Ag or Cu, the melting point of the solder particles 1 can be lowered to about 220 ° C., and the bonding strength with the electrodes is further improved, so that better conduction reliability can be obtained. It becomes easy to obtain.
　はんだ粒子１のＣｕ含有率は例えば０．０５～１０質量％であり、０．１～５質量％又は０．２～３質量％であってもよい。Ｃｕ含有率が０．０５質量％以上であると、より良好なはんだ接続信頼性を達成し易くなる。また、Ｃｕ含有率が１０質量％以下であると、融点が低く、濡れ性に優れたはんだ粒子１となり易く、結果としてはんだ粒子１による接合部の接続信頼性が良好となり易い。 The Cu content of the solder particles 1 is, for example, 0.05 to 10% by mass, and may be 0.1 to 5% by mass or 0.2 to 3% by mass. When the Cu content is 0.05% by mass or more, it becomes easy to achieve better solder connection reliability. Further, when the Cu content is 10% by mass or less, the solder particles 1 have a low melting point and excellent wettability, and as a result, the connection reliability of the joint portion by the solder particles 1 tends to be good.
　はんだ粒子１のＡｇ含有率は例えば０．０５～１０質量％であり、０．１～５質量％又は０．２～３質量％であってもよい。Ａｇ含有率が０．０５質量％以上であると、より良好なはんだ接続信頼性を達成し易くなる。また、Ａｇ含有率が１０質量％以下であると、融点が低く、濡れ性に優れたはんだ粒子１となり易く、結果としてはんだ粒子１による接合部の接続信頼性が良好となり易い。 The Ag content of the solder particles 1 is, for example, 0.05 to 10% by mass, and may be 0.1 to 5% by mass or 0.2 to 3% by mass. When the Ag content is 0.05% by mass or more, it becomes easy to achieve better solder connection reliability. Further, when the Ag content is 10% by mass or less, the solder particles 1 have a low melting point and excellent wettability, and as a result, the connection reliability of the joint portion by the solder particles 1 tends to be good.
（流動化剤）
　流動化剤Ｆは、流動相としてリフロー時に流動して凹部６２から電極側にはんだ粒子１を押し出す作用を有する。また、流動化剤Ｆはフラックス、有機溶剤等であってよい。フラックスは、はんだ粒子表面及び電極表面の酸化物を溶解して、電極へのはんだの濡れ性を向上させる作用を有する。 (Fluidizer)
The fluidizing agent F has a function of flowing as a fluid phase during reflow and pushing out the solder particles 1 from the recess 62 toward the electrode side. Further, the fluidizing agent F may be a flux, an organic solvent, or the like. The flux has the effect of dissolving the oxides on the surface of the solder particles and the surface of the electrode to improve the wettability of the solder on the electrode.
　流動化剤Ｆとしては、各種有機溶剤が利用できる。流動化剤Ｆの沸点は、はんだの融点よりも高くてもよい。電極と凹部を対峙させ、加熱した際に流動化剤Ｆの沸点がはんだの融点より高いことで、凹部内で流動化剤Ｆが流動し、流動化剤Ｆの流動に伴い、はんだ粒子も流動する。流動化剤Ｆ及びはんだ粒子が流動することで、電極表面とはんだ粒子が接触しやすくなり、結果としてはんだバンプの形成が促進される。従って、はんだバンプ形成時に、はんだ粒子の融点よりも高く、流動化剤Ｆの軟化点又は融点よりも高く、流動化剤Ｆの沸点よりも低い加熱温度を少なくとも経ると、はんだバンプが電極上に形成されやすくなる。はんだバンプ形成が十分に行われた後に、加熱温度を流動化剤Ｆの沸点以上に上げると、基体表面及び電極表面における流動化剤Ｆ由来の残渣を少なくできる。 Various organic solvents can be used as the fluidizing agent F. The boiling point of the fluidizing agent F may be higher than the melting point of the solder. When the electrode and the recess are confronted and heated, the boiling point of the fluidizing agent F is higher than the melting point of the solder, so that the fluidizing agent F flows in the recess, and the solder particles also flow as the fluidizing agent F flows. To do. The flow of the fluidizing agent F and the solder particles facilitates contact between the electrode surface and the solder particles, and as a result, the formation of solder bumps is promoted. Therefore, when the solder bumps are formed, the solder bumps are formed on the electrodes when the heating temperature is at least higher than the melting point of the solder particles, higher than the softening point or melting point of the fluidizing agent F, and lower than the boiling point of the fluidizing agent F. It becomes easy to be formed. When the heating temperature is raised above the boiling point of the fluidizing agent F after the solder bumps are sufficiently formed, the residue derived from the fluidizing agent F on the surface of the substrate and the surface of the electrode can be reduced.
　流動化剤Ｆに利用できる各種有機溶剤としては、シクロヘキサン（沸点：８０℃）、シクロヘプタン（沸点：１１８℃）、シクロオクタン（沸点：１４９℃）、ヘプタン（沸点：９８℃）、オクタン（沸点：１２６℃）、ノナン（沸点：１５０℃）、デカン（沸点１７４℃）、ウンデカン（沸点：１９６℃）、ドデカン（沸点：２１５℃）、トリデカン（沸点：２３４℃）、テトラデカン（沸点：２５４℃）、ペンタデカン（沸点：２６９℃）、ヘキサデカン（沸点：２８７℃）、ヘプタデカン（沸点：３０２℃）、オクタデカン（沸点：３１７℃）、ノナデカン（沸点：３３０℃）等の脂肪族炭化水素が利用できる。これらの脂肪族炭化水素は、無極性であり、はんだ及びＡｕ、Ｃｕ等の電極に利用される金属の還元機能は無いが、はんだの融点以上の沸点を有する溶剤として、適宜選択でき、加熱によってはんだ粒子を流動して、はんだ粒子を電極表面に接触させる機能を有する。 Various organic solvents that can be used for the fluidizing agent F include cyclohexane (boiling point: 80 ° C.), cycloheptane (boiling point: 118 ° C.), cyclooctane (boiling point: 149 ° C.), heptane (boiling point: 98 ° C.), and octane (boiling point: boiling point). : 126 ° C), Nonan (boiling point: 150 ° C), Decane (boiling point: 174 ° C), Undecane (boiling point: 196 ° C), Dodecan (boiling point: 215 ° C), Tridecane (boiling point: 234 ° C), Tetradecane (boiling point: 254 ° C) ), Pentadecane (boiling point: 269 ° C), hexadecane (boiling point: 287 ° C), heptadecane (boiling point: 302 ° C), octadecane (boiling point: 317 ° C), nonadecan (boiling point: 330 ° C) and other aliphatic hydrocarbons can be used. .. These aliphatic hydrocarbons are non-polar and do not have a reducing function for solder and metals used for electrodes such as Au and Cu, but can be appropriately selected as a solvent having a boiling point equal to or higher than the melting point of solder, and can be appropriately selected by heating. It has the function of flowing the solder particles and bringing the solder particles into contact with the electrode surface.
　流動化剤Ｆに利用できる各種有機溶剤としては、例えば、ペンタノール、ヘキサノール、ヘプタノール、オクタノール、デカノール、エチレングリコール、ジエチレングリコール、プロピレングリコール、ブチレングリコール、α－テルピネオール、イソボルニルシクロヘキサノール（ＭＴＰＨ）等の一価及び多価アルコール類；エチレングリコールブチルエーテル、エチレングリコールフェニルエーテル、ジエチレングリコールメチルエーテル、ジエチレングリコールエチルエーテル、ジエチレングリコールブチルエーテル、ジエチレングリコールイソブチルエーテル、ジエチレングリコールヘキシルエーテル、トリエチレングリコールメチルエーテル、ジエチレングリコールジメチルエーテル、ジエチレングリコールジエチルエーテル、ジエチレングリコールジブチルエーテル、ジエチレングリコールブチルメチルエーテル、ジエチレングリコールイソプロピルメチルエーテル、トリエチレングリコールジメチルエーテル、トリエチレングリコールブチルメチルエーテル、プロピレングリコールプロピルエーテル、ジプロピレングリコールメチルエーテル、ジプロピレングリコールエチルエーテル、ジプロピレングリコールプロピルエーテル、ジプロピレングリコールブチルエーテル、ジプロピレングリコールジメチルエーテル、トリプロピレングリコールメチルエーテル、トリプロピレングリコールジメチルエーテル等のエーテル類；エチレングリコールエチルエーテルアセテート、エチレングリコールブチルエーテルアセテート、ジエチレングリコールエチルエーテルアセテート、ジエチレングリコールブチルエーテルアセテート、ジプロピレングリコールメチルエーテルアセテート（ＤＰＭＡ）、乳酸エチル、乳酸ブチル、γ－ブチロラクトン、炭酸プロピレン等のエステル類；Ｎ－メチル－２－ピロリドン、Ｎ，Ｎ－ジメチルアセトアミド、Ｎ，Ｎ－ジメチルホルムアミド等の酸アミド；シクロヘキサン、オクタン、ノナン、デカン、ウンデカン等の脂肪族炭化水素；ベンゼン、トルエン、キシレン等の芳香族炭化水素；炭素数１～１８のアルキル基を有するメルカプタン類；炭素数５～７のシクロアルキル基を有するメルカプタン類が挙げられる。炭素数１～１８のアルキル基を有するメルカプタン類としては、例えば、エチルメルカプタン、ｎ－プロピルメルカプタン、ｉ－プロピルメルカプタン、ｎ－ブチルメルカプタン、ｉ－ブチルメルカプタン、ｔ－ブチルメルカプタン、ペンチルメルカプタン、ヘキシルメルカプタン及びドデシルメルカプタンが挙げられる。炭素数５～７のシクロアルキル基を有するメルカプタン類としては、例えば、シクロペンチルメルカプタン、シクロヘキシルメルカプタン及びシクロヘプチルメルカプタンが挙げられる。他にも、有機溶剤として、モノアルキルアミン、ジアルキルアミン、トリアルキルアミン、アルカノールアミン、シクロヘキシルアミン、ジシクロヘキシルアミン等の脂環式アミン、ジフェニルアミン、トリフェニルアミン等の芳香族アミンなどが挙げられる。例えば、有機溶剤として、エチレンジエタノールアミン、ｎ－ブチルジエタノールアミン、ジエタノールアミン、Ｎ，Ｎ―ビス（２－ヒドロキシエチル）イソプロパノールアミン等が挙げられる。 Examples of various organic solvents that can be used for the fluidizing agent F include pentanol, hexanol, heptanol, octanol, decanol, ethylene glycol, diethylene glycol, propylene glycol, butylene glycol, α-terpineol, isobornylcyclohexanol (MTPH) and the like. Monovalent and polyhydric alcohols; ethylene glycol butyl ether, ethylene glycol phenyl ether, diethylene glycol methyl ether, diethylene glycol ethyl ether, diethylene glycol butyl ether, diethylene glycol isobutyl ether, diethylene glycol hexyl ether, triethylene glycol methyl ether, diethylene glycol dimethyl ether, diethylene glycol diethyl ether, Diethylene glycol dibutyl ether, diethylene glycol butyl methyl ether, diethylene glycol isopropyl methyl ether, triethylene glycol dimethyl ether, triethylene glycol butyl methyl ether, propylene glycol propyl ether, dipropylene glycol methyl ether, dipropylene glycol ethyl ether, dipropylene glycol propyl ether, dipropylene glycol Ethers such as propylene glycol butyl ether, dipropylene glycol dimethyl ether, tripropylene glycol methyl ether, tripropylene glycol dimethyl ether; ethylene glycol ethyl ether acetate, ethylene glycol butyl ether acetate, diethylene glycol ethyl ether acetate, diethylene glycol butyl ether acetate, dipropylene glycol methyl ether acetate Ethers such as (DPMA), ethyl lactate, butyl lactate, γ-butyrolactone, propylene carbonate; acid amides such as N-methyl-2-pyrrolidone, N, N-dimethylacetamide, N, N-dimethylformamide; cyclohexane, octane , Nonane, decane, undecane and other aliphatic hydrocarbons; aromatic hydrocarbons such as benzene, toluene and xylene; mercaptans having an alkyl group having 1 to 18 carbon atoms; mercaptans having a cycloalkyl group having 5 to 7 carbon atoms. Kind. Examples of mercaptans having an alkyl group having 1 to 18 carbon atoms include ethyl mercaptan, n-propyl mercaptan, i-propyl mercaptan, n-butyl mercaptan, i-butyl mercaptan, t-butyl mercaptan, pentyl mercaptan, and hexyl mercaptan. And dodecyl mercaptan. Examples of mercaptans having a cycloalkyl group having 5 to 7 carbon atoms include cyclopentyl mercaptan, cyclohexyl mercaptan and cycloheptyl mercaptan. Other examples of the organic solvent include alicyclic amines such as monoalkylamines, dialkylamines, trialkylamines, alkanolamines, cyclohexylamines and dicyclohexylamines, and aromatic amines such as diphenylamines and triphenylamines. For example, examples of the organic solvent include ethylene diethanolamine, n-butyl diethanolamine, diethanolamine, N, N-bis (2-hydroxyethyl) isopropanolamine and the like.
　流動化剤Ｆとして利用できる有機溶剤として、グリコールエーテル系の溶剤も利用できる。例えば、沸点が２００℃以下の溶剤としては、ジプロピレングリコールモノメチルエーテル、プロピレングリコールモノブチルエーテル、ジエチレングリコールジメチルエーテル、エチレングリコールモノアリルエーテル、エチレングリコールモノイソプロピルエーテルが挙げられる。沸点が２００℃を超える溶剤としては、エチレングリコールモノヘキシルエーテル、ジエチレングリコールモノヘキシルエーテル、トリエチレングリコールモノメチルエーテル、エチレングリコールモノ－２－エチルヘキシルエーテル、ジエチレングリコールモノ－２－エチルヘキシルエーテル、ジエチレングリコールジブチルエーテル、トリエチレングリコールブチルメチルエーテル、テトラエチレングリコールジメチルエーテル等が挙げられる。 As an organic solvent that can be used as the fluidizing agent F, a glycol ether-based solvent can also be used. For example, examples of the solvent having a boiling point of 200 ° C. or lower include dipropylene glycol monomethyl ether, propylene glycol monobutyl ether, diethylene glycol dimethyl ether, ethylene glycol monoallyl ether, and ethylene glycol monoisopropyl ether. Solvents having a boiling point exceeding 200 ° C. include ethylene glycol monohexyl ether, diethylene glycol monohexyl ether, triethylene glycol monomethyl ether, ethylene glycol mono-2-ethylhexyl ether, diethylene glycol mono-2-ethylhexyl ether, diethylene glycol dibutyl ether, and triethylene. Glycolbutylmethyl ether, tetraethylene glycol dimethyl ether and the like can be mentioned.
　流動化剤Ｆとして利用できるフラックスとしては、はんだ接合等に一般的に用いられているものを使用できる。フラックスは、はんだ粒子の組成、融点、表面状態、転写時の加熱・雰囲気の条件等に合わせて適宜選択することができる。例えば、塩化亜鉛、塩化亜鉛と無機ハロゲン化物との混合物、塩化亜鉛と無機酸との混合物、溶融塩、リン酸、リン酸の誘導体、有機ハロゲン化物、ヒドラジン、有機酸、松脂等が挙げられる。これらは一種を単独で用いてもよく、二種以上を併用してもよい。 As the flux that can be used as the fluidizing agent F, a flux that is generally used for solder bonding or the like can be used. The flux can be appropriately selected according to the composition of the solder particles, the melting point, the surface condition, the heating / atmosphere conditions at the time of transfer, and the like. For example, zinc chloride, a mixture of zinc chloride and an inorganic halide, a mixture of zinc chloride and an inorganic acid, a molten salt, phosphoric acid, a derivative of phosphoric acid, an organic halide, hydrazine, an organic acid, pine fat and the like can be mentioned. These may be used alone or in combination of two or more.
　溶融塩としては、塩化アンモニウム等が挙げられる。有機酸としては、乳酸、クエン酸、ステアリン酸、グルタミン酸、グルタル酸等が挙げられる。また、フラックスに利用できる有機酸として、例えば、炭素数８～１６の有機酸が挙げられる。炭素数８～１６の有機酸としては、例えば、カプリル酸、メチルヘプタン酸、エチルヘキサン酸、プロピルペンタン酸、ペラルゴン酸、メチルオクタン酸、エチルヘプタン酸、プロピルヘキサン酸、カプリン酸、メチルノナン酸、エチルオクタン酸、プロピルヘプタン酸、ブチルヘキサン酸、ウンデカン酸、メチルデカン酸、エチルノナン酸、プロピルオクタン酸、ブチルヘプタン酸、ラウリン酸、メチルウンデカン酸、エチルデカン酸、プロピルノナン酸、ブチルオクタン酸、ペンチルヘプタン酸、トリデカン酸、メチルドデカン酸、エチルウンデカン酸、プロピルデカン酸、ブチルノナン酸、ペンチルオクタン酸、ミリスチン酸、メチルトリデカン酸、エチルドデカン酸、プロピルウンデカン酸、ブチルデカン酸、ペンチルノナン酸、ヘキシルオクタン酸、ペンタデカン酸、メチルテトラデカン酸、エチルトリデカン酸、プロピルドデカン酸、ブチルウンデカン酸、ペンチルデカン酸、ヘキシルノナン酸、パルミチン酸、メチルペンタデカン酸、エチルテトラデカン酸、プロピルトリデカン酸、ブチルドデカン酸、ペンチルウンデカン酸、ヘキシルデカン酸、ヘプチルノナン酸、メチルシクロヘキサンカルボン酸、エチルシクロヘキサンカルボン酸、プロピルシクロヘキサンカルボン酸、ブチルシクロヘキサンカルボン酸、ペンチルシクロヘキサンカルボン酸、ヘキシルシクロヘキサンカルボン酸、ヘプチルシクロヘキサンカルボン酸、オクチルシクロヘキサンカルボン酸、ノニルシクロヘキサンカルボン酸等の飽和脂肪酸；オクテン酸、ノネン酸、メチルノネン酸、デセン酸、ウンデセン酸、ドデセン酸、トリデセン酸、テトラデセン酸、ミリストレイン酸、ペンタデセン酸、ヘキサデセン酸、パルミトレイン酸、サピエン酸等の不飽和脂肪酸；テレフタル酸、ピロメリット酸、ｏ－フェノキシ安息香酸、メチル安息香酸、エチル安息香酸、プロピル安息香酸、ブチル安息香酸、ペンチル安息香酸、ヘキシル安息香酸、ヘプチル安息香酸、オクチル安息香酸、ノニル安息香酸等の芳香族カルボン酸が挙げられる。有機酸は、１種を単独で使用してもよく、２種以上を組み合わせて使用してもよい。松脂としては、活性化松脂、非活性化松脂等が挙げられる。松脂はアビエチン酸を主成分とするロジン類である。フラックスとして、カルボキシル基を二個以上有する有機酸又は松脂を使用することにより、電極間の導通信頼性がより一層高くなるという効果が奏される。 Examples of the molten salt include ammonium chloride. Examples of the organic acid include lactic acid, citric acid, stearic acid, glutamic acid, glutaric acid and the like. Examples of the organic acid that can be used for the flux include an organic acid having 8 to 16 carbon atoms. Examples of organic acids having 8 to 16 carbon atoms include capric acid, methylheptanic acid, ethylhexanoic acid, propylpentanoic acid, pelargonic acid, methyloctanoic acid, ethylheptanoic acid, propylhexanoic acid, capric acid, methylnonanoic acid and ethyl. Octanoic acid, propylheptanic acid, butylhexanoic acid, undecanoic acid, methyldecanoic acid, ethylnonanoic acid, propyloctanoic acid, butylheptanic acid, lauric acid, methylundecanoic acid, ethyldecanoic acid, propylnonanoic acid, butyloctanoic acid, pentylheptanic acid, Tridecanoic acid, methyldodecanoic acid, ethylundecanoic acid, propyldecanoic acid, butylnonanoic acid, pentyloctanoic acid, myristic acid, methyltridecanoic acid, ethyldodecanoic acid, propylundecanoic acid, butyldecanoic acid, pentylnonanoic acid, hexyloctanoic acid, pentadecanoic acid , Methyltetradecanoic acid, ethyltridecanoic acid, propyldodecanoic acid, butylundecanoic acid, pentyldecanoic acid, hexylnonanoic acid, palmitic acid, methylpentadecanoic acid, ethyltetradecanoic acid, propyltridecanoic acid, butyldodecanoic acid, pentylundecanoic acid, hexyldecane Acids, heptylnonanoic acid, methylcyclohexanecarboxylic acid, ethylcyclohexanecarboxylic acid, propylcyclohexanecarboxylic acid, butylcyclohexanecarboxylic acid, pentylcyclohexanecarboxylic acid, hexylcyclohexanecarboxylic acid, heptylcyclohexanecarboxylic acid, octylcyclohexanecarboxylic acid, nonylcyclohexanecarboxylic acid, etc. Saturated fatty acids; octenoic acid, nonenic acid, methylnonenic acid, decenoic acid, undecenoic acid, dodecenoic acid, tridecenoic acid, tetradecenoic acid, myristoleic acid, pentadecenoic acid, hexadecenoic acid, palmitreic acid, sapienoic acid and other unsaturated fatty acids; terephthal Aromas such as acid, pyromellitic acid, o-phenoxy benzoic acid, methyl benzoic acid, ethyl benzoic acid, propyl benzoic acid, butyl benzoic acid, pentyl benzoic acid, hexyl benzoic acid, heptyl benzoic acid, octyl benzoic acid, nonyl benzoic acid Group carboxylic acids include. One type of organic acid may be used alone, or two or more types may be used in combination. Examples of pine fat include activated pine fat and non-activated pine fat. Pine fat is a rosin whose main component is abietic acid. By using an organic acid or pine fat having two or more carboxyl groups as the flux, the effect of further increasing the conduction reliability between the electrodes is achieved.
　フラックスの融点は、５０℃以上であってよく、７０℃以上であってよく、８０℃以上であってよい。フラックスの融点は、２００℃以下であってよく、１６０℃以下であってよく、１５０℃以下であってよく、１４０℃以下であってよい。上記フラックスの融点が上記下限以上及び上記上限以下であると、フラックス効果がより一層効果的に発揮され、はんだ粒子が電極上により一層効率的に配置される。フラックスの融点の範囲は、８０～１９０℃であってよく、８０～１４０℃以下であってよい。 The melting point of the flux may be 50 ° C. or higher, 70 ° C. or higher, or 80 ° C. or higher. The melting point of the flux may be 200 ° C. or lower, 160 ° C. or lower, 150 ° C. or lower, or 140 ° C. or lower. When the melting point of the flux is at least the above lower limit and at least the above upper limit, the flux effect is exhibited more effectively, and the solder particles are arranged more efficiently on the electrode. The melting point range of the flux may be 80 to 190 ° C. and may be 80 to 140 ° C. or lower.
　融点が８０～１９０℃の範囲にあるフラックスとしては、コハク酸（融点１８６℃）、グルタル酸（融点９６℃）、アジピン酸（融点１５２℃）、ピメリン酸（融点１０４℃）、スベリン酸（融点１４２℃）等のジカルボン酸、安息香酸（融点１２２℃）、リンゴ酸（融点１３０℃）等が挙げられる。流動化剤は、コハク酸、グルタル酸、アジピン酸、ピメリン酸、スベリン酸、安息香酸、及びリンゴ酸からなる群より選択される少なくとも一種を含んでよい。 Fluxes having a melting point in the range of 80 to 190 ° C include succinic acid (melting point 186 ° C), glutaric acid (melting point 96 ° C), adipic acid (melting point 152 ° C), pimeric acid (melting point 104 ° C), and suberic acid (melting point 104 ° C). Dicarboxylic acids such as 142 ° C., benzoic acid (melting point 122 ° C.), malic acid (melting point 130 ° C.) and the like can be mentioned. The fluidizing agent may include at least one selected from the group consisting of succinic acid, glutaric acid, adipic acid, pimelic acid, suberic acid, benzoic acid, and malic acid.
　凹部６２内に存在する流動化剤Ｆの量は特に制限されないが、適度な流動作用、フラックス効果等を得易い観点から、１００質量部のはんだ粒子１に対して１～５０質量部であってよく、１～２０質量部であってよく、２０～５０質量部であってよい。流動化剤Ｆは、溶剤又は樹脂材料との混合物であってもよい。溶剤としては、前述の各種有機溶剤が利用できる。混合物であれば、流動化剤Ｆの濃度をはんだ粒子１に合わせて適宜調整できる。リフロー時に混合物がはんだ粒子１を電極上に押し出すためには、混合物の流動性が加熱により高まるよう、軟化点又は融点を調整するとよい。軟化点又は融点が室温より高ければ、室温でははんだ粒子１が凹部６２から脱落しづらく、はんだバンプ形成工程の前の取り扱いが容易になる。混合物を構成する溶剤としては、高沸点溶剤等が挙げられる。高沸点溶剤は、はんだ粒子１を電極上に流動させた後は、再加熱で揮発するため、電極上に残存し難い。溶剤としては、アルコール系溶剤等を用いることができる。アルコール系溶剤であれば、還元性を発現することができる。 The amount of the fluidizing agent F present in the recess 62 is not particularly limited, but is 1 to 50 parts by mass with respect to 100 parts by mass of the solder particles 1 from the viewpoint of easily obtaining an appropriate fluidizing action, flux effect, and the like. It may be 1 to 20 parts by mass, and may be 20 to 50 parts by mass. The fluidizing agent F may be a mixture with a solvent or a resin material. As the solvent, the above-mentioned various organic solvents can be used. In the case of a mixture, the concentration of the fluidizing agent F can be appropriately adjusted according to the solder particles 1. In order for the mixture to push the solder particles 1 onto the electrodes during reflow, the softening point or melting point may be adjusted so that the fluidity of the mixture is increased by heating. If the softening point or melting point is higher than room temperature, the solder particles 1 are less likely to fall out of the recess 62 at room temperature, and can be easily handled before the solder bump forming step. Examples of the solvent constituting the mixture include high boiling point solvents and the like. The high boiling point solvent does not easily remain on the electrode because it volatilizes by reheating after the solder particles 1 are made to flow on the electrode. As the solvent, an alcohol solvent or the like can be used. If it is an alcohol solvent, reducing property can be exhibited.
（基体）
　基体６０を構成する材料としては、例えば、シリコン、各種セラミックス、ガラス、ステンレススチール等の金属等の無機材料、並びに、各種樹脂等の有機材料を使用することができる。これらのうち、基体６０は、はんだ微粒子の溶融温度で変質しない耐熱性を有する材質であってもよい。また、基体６０は、はんだ微粒子を溶融させる温度においても、変形しない耐熱性を有する材質であってもよい。また、基体６０は、はんだ微粒子を構成する材質と合金化したり、反応して変化しない材質であってもよい。また、基体６０の凹部６２は、切削法、フォトリソグラフ法、インプリント法等の公知の方法によって形成することができる。特に、インプリント法を用いると短い工程で、正確な大きさの凹部６２を形成できる。 (Hypokeimenon)
As the material constituting the substrate 60, for example, an inorganic material such as silicon, various ceramics, glass, a metal such as stainless steel, and an organic material such as various resins can be used. Of these, the substrate 60 may be a material having heat resistance that does not deteriorate at the melting temperature of the solder fine particles. Further, the substrate 60 may be made of a material having heat resistance that does not deform even at the temperature at which the solder fine particles are melted. Further, the substrate 60 may be a material that does not change by alloying with a material constituting the solder fine particles or by reacting with the material. Further, the recess 62 of the substrate 60 can be formed by a known method such as a cutting method, a photolithography method, or an imprint method. In particular, when the imprint method is used, the recess 62 having an accurate size can be formed in a short process.
　基体６０の表面は、被覆層を有してもよい。基体６０に使用できる材料の選択性が広がる観点から、被覆層は、はんだ微粒子を構成する材質と合金化しにくい又はしない材質であってもよい。被覆層としては、無機物又は有機物が利用できる。被覆層としては、アルミ、クロムなどの表面に強固な酸化層を有する無機物、酸化チタンなどの酸化物、窒化ホウ素などの窒化物、ダイヤモンドライクカーボン、ダイヤモンド、黒鉛などの炭素系材料、フッ素樹脂、ポリイミドなどの高耐熱樹脂などが利用できる。更に、被覆層は、はんだとの濡れ性を調整する役割があってもよい。基体６０の表面に被覆層を設けることで、使用目的に合わせて、はんだとの濡れ性を適宜調整できる。 The surface of the substrate 60 may have a coating layer. From the viewpoint of expanding the selectivity of the material that can be used for the substrate 60, the coating layer may be a material that is difficult or not alloyed with the material constituting the solder fine particles. As the coating layer, an inorganic substance or an organic substance can be used. The coating layer includes inorganic substances having a strong oxide layer on the surface such as aluminum and chromium, oxides such as titanium oxide, nitrides such as boron nitride, carbon-based materials such as diamond-like carbon, diamond and graphite, and fluororesins. Highly heat-resistant resin such as polyimide can be used. Further, the coating layer may have a role of adjusting the wettability with the solder. By providing the coating layer on the surface of the substrate 60, the wettability with the solder can be appropriately adjusted according to the purpose of use.
　被覆層を形成する方法としては、ラミネート、溶液ディップ、塗工、塗装、含浸、スパッタ、めっきなどが利用できる。 As a method for forming the coating layer, laminating, solution dipping, coating, painting, impregnation, sputtering, plating, etc. can be used.
　転写工程の条件を設定し易くする観点から、基体６０の材質は、はんだ粒子を転写する電極及び電極が形成された基板と物性が近い又は同じ材質であってもよい。例えば、熱膨張係数（ＣＴＥ）が近い又は同じ材料であると、はんだ粒子の転写時に位置ずれが起きづらい。 From the viewpoint of facilitating the setting of the conditions of the transfer process, the material of the substrate 60 may be an electrode for transferring the solder particles and a material having similar or the same physical characteristics as the substrate on which the electrode is formed. For example, if the materials have a similar coefficient of thermal expansion (CTE) or the same material, misalignment is unlikely to occur during transfer of solder particles.
　基体６０には、アライメントマークが設けられていてもよい。このアライメントマークは、カメラで読み取れるとよい。電極を有する基板側にもアライメントマークがあってもよい。基体６０及び電極を有する基板のアライメントマークが設けられることで、はんだ粒子を電極上に転写する際、位置合わせ可能な装置に搭載されたカメラにより基体６０上のアライメントマークと、電極を有する基板のアライメントマークを読み取り、はんだ粒子を有する凹部６２の位置と、はんだ粒子を転写する電極の位置とを正確に把握することが可能となる。また、基体６０及び電極を有する基板のアライメントマークが設けられることで、位置精度よくはんだ粒子を電極上に転写することができる。 The substrate 60 may be provided with an alignment mark. This alignment mark should be readable by the camera. There may also be an alignment mark on the substrate side having the electrodes. By providing the alignment mark of the base 60 and the substrate having the electrode, when the solder particles are transferred onto the electrode, the alignment mark on the base 60 and the substrate having the electrode are provided by the camera mounted on the alignable device. By reading the alignment mark, it is possible to accurately grasp the position of the recess 62 having the solder particles and the position of the electrode that transfers the solder particles. Further, by providing the alignment mark of the substrate 60 and the substrate having the electrode, the solder particles can be transferred onto the electrode with high positional accuracy.
　アライメントマークは基体６０上に１か所以上あればよい。アライメントマークが２か所以上あれば位置精度が高くなる。 There may be one or more alignment marks on the substrate 60. If there are two or more alignment marks, the position accuracy will be high.
　具体的な基体６０の構成について以下に述べる。 The specific configuration of the substrate 60 will be described below.
（有機材料　単層）
　基体６０は有機材料で構成されていてもよい。有機材料としては、高分子材料であってよく、熱可塑性、熱硬化性、光硬化性材料などが利用できる。有機材料を用いることで、物性の選択の幅が広がるため、目的に合わせた基体６０を形成しやすい。例えば、有機材料であれば、基体６０（凹部６２を含む）を曲げたり、伸ばしたりし易い。有機材料であれば、凹部６２の形成にも各種手法が利用できる。凹部６２の形成方法としては、インプリント、フォトリソグラフィー、切削加工、レーザー加工などが利用できる。特にインプリント法によれば、所望の形状を有する型（モールド）を有機材料からなる基体６０に押し付けて、表面に任意の形状を形成することができる。型（モールド）に凸型のパターンを形成して、有機材料からなる基体６０に押し付けることにより、所望のパターンを有する凹部６２を形成することができる。また、凹部６２の形成に光硬化性樹脂を用いることもでき、型（モールド）に光硬化性樹脂を塗布し、露光した後、型（モールド）を剥離すると、凹部６２を有する基体６０を形成できる。また、切削加工の場合は、ドリルなどで凹部６２を形成することができる。 (Single layer of organic material)
The substrate 60 may be made of an organic material. The organic material may be a polymer material, and thermoplastic, thermosetting, photocurable materials and the like can be used. By using an organic material, the range of choice of physical properties is widened, so that it is easy to form the substrate 60 according to the purpose. For example, in the case of an organic material, the substrate 60 (including the recess 62) can be easily bent or stretched. If it is an organic material, various methods can be used for forming the recess 62. As a method for forming the recess 62, imprint, photolithography, cutting, laser machining, or the like can be used. In particular, according to the imprint method, a mold having a desired shape can be pressed against a substrate 60 made of an organic material to form an arbitrary shape on the surface. By forming a convex pattern on the mold and pressing it against the substrate 60 made of an organic material, a concave portion 62 having a desired pattern can be formed. Further, a photocurable resin can be used to form the recess 62, and when the photocurable resin is applied to the mold (mold), exposed, and then the mold (mold) is peeled off, a substrate 60 having the recess 62 is formed. it can. Further, in the case of cutting, the recess 62 can be formed by a drill or the like.
（有機材料　複層）
　基体は複数の有機材料から構成されていてもよい。また、基体は、複数の層を有していてもよく、複数の層は、それぞれ別の有機材料で構成されていてもよい。有機材料としては、高分子材料であってよく、熱可塑性、熱硬化性、光硬化性材料などが利用できる。基体は、有機材料から構成される２層を有し、片面側の有機材料層に凹部を形成していてもよい。複層化することで、はんだと触れる凹部の材料ははんだとの濡れ性が適当な材料を選定するなど、機能を分けてそれぞれの材料を選定することができる。例えば、図８は、基体の一例を模式的に示す断面図である。基体６００はベース層６０１と、凹部層６０２を備えている。ベース層６０１は凹部層６０２を支持する層であり、凹部層６０２は加工により凹部６２が形成される層である。ベース層６０１には耐熱性及び寸法安定性に優れた樹脂材料を用い、凹部層６０２には凹部６２の加工性に優れた材料を選定することができる。例えば、ベース層６０１にポリエチレンテレフタレート、ポリイミドなどの熱可塑性樹脂を用い、凹部層６０２にインプリントモールドで凹部６２を形成可能な熱硬化性樹脂を用いることができる。例えば、ポリエチレンテレフタレートとインプリントモールドで熱硬化性樹脂を挟んで、加熱加圧することで、平坦性に優れた基体６００（凹部６２含む）が得られる。また、凹部６２を光硬化性材料を用いて形成する場合は、ベース層６０１に光透過性の高い材料を用いてもよい。光透過性の高い材料としては、例えば、ポリエチレンテレフタレート、透明（無色タイプ）のポリイミド、ポリアミド等であってよい。凹部６２を光硬化性材料を用いて形成する場合は、例えば、インプリントモールドの表面に光硬化性材料を適量塗布し、その上にポリエチレンテレフタレートのフィルムを置いて、ポリエチレンテレフタレート側からローラーで加圧しながら紫外光を照射する。そして、光硬化性材料を硬化させた後、インプリントモールドを剥がすことで、ポリエチレンテレフタレートの層と光硬化性材料の層を有し、凹部６２が光硬化性材料で形成された基体６００を得ることができる。凹部６２の内壁と底部の材料構成は変更することができる。例えば、凹部６２の内壁と底部は同じ樹脂材料の構成とすることができる。また、凹部６２の内壁と底部は異なる樹脂材料（例えば、熱硬化性材料と熱可塑性材料）の構成とすることができる。 (Multi-layer organic material)
The substrate may be composed of a plurality of organic materials. Further, the substrate may have a plurality of layers, and the plurality of layers may be made of different organic materials. The organic material may be a polymer material, and thermoplastic, thermosetting, photocurable materials and the like can be used. The substrate has two layers made of an organic material, and a recess may be formed in the organic material layer on one side. By forming multiple layers, it is possible to select each material by dividing the function, such as selecting a material having an appropriate wettability with the solder for the material of the recess that comes into contact with the solder. For example, FIG. 8 is a cross-sectional view schematically showing an example of a substrate. The substrate 600 includes a base layer 601 and a recessed layer 602. The base layer 601 is a layer that supports the recess layer 602, and the recess layer 602 is a layer on which the recess 62 is formed by processing. A resin material having excellent heat resistance and dimensional stability can be used for the base layer 601, and a material having excellent workability of the recess 62 can be selected for the recess layer 602. For example, a thermoplastic resin such as polyethylene terephthalate or polyimide can be used for the base layer 601 and a thermosetting resin capable of forming the recess 62 by an imprint mold can be used for the recess layer 602. For example, a substrate 600 (including the recess 62) having excellent flatness can be obtained by sandwiching a thermosetting resin between polyethylene terephthalate and an imprint mold and heating and pressurizing the resin. When the recess 62 is formed by using a photocurable material, a material having high light transmittance may be used for the base layer 601. The material having high light transparency may be, for example, polyethylene terephthalate, transparent (colorless type) polyimide, polyamide or the like. When the recess 62 is formed using a photocurable material, for example, an appropriate amount of the photocurable material is applied to the surface of the imprint mold, a polyethylene terephthalate film is placed on the surface, and the recess 62 is added by a roller from the polyethylene terephthalate side. Irradiate ultraviolet light while pressing. Then, after the photocurable material is cured, the imprint mold is peeled off to obtain a substrate 600 having a layer of polyethylene terephthalate and a layer of the photocurable material, and the recess 62 formed of the photocurable material. be able to. The material composition of the inner wall and the bottom of the recess 62 can be changed. For example, the inner wall and the bottom of the recess 62 may be made of the same resin material. Further, the inner wall and the bottom of the recess 62 may be made of different resin materials (for example, a thermosetting material and a thermoplastic material).
　また、有機材料として感光性材料を用いてもよい。感光性材料としては、ポジ型感光性材料、ネガ型感光性材料であってもよい。例えば、熱可塑性のポリエチレンテレフタレートフィルム表面に感光性材料を均一厚みに形成し、露光と現像を行うことで、容易に凹部６２を形成することができる。露光と現像（フォトリソグラフィー法）を用いる方法は、半導体、配線板等の製造で広く利用されており、汎用性が高い方法である。また、露光方法としてはマスクを用いた露光の他に、ダイレクトレーザー露光のような直接描画方法を用いることも可能である。 Alternatively, a photosensitive material may be used as the organic material. The photosensitive material may be a positive type photosensitive material or a negative type photosensitive material. For example, the recess 62 can be easily formed by forming a photosensitive material having a uniform thickness on the surface of a thermoplastic polyethylene terephthalate film and performing exposure and development. The method using exposure and development (photolithography method) is widely used in the manufacture of semiconductors, wiring boards, etc., and is a highly versatile method. Further, as the exposure method, in addition to the exposure using a mask, it is also possible to use a direct drawing method such as a direct laser exposure.
　凹部層６０２を形成する材料の厚みよりも、ベース層６０１の材料を厚くすることで、基体６００全体の物性をベース層６０１の材料の特性で支配的にすることができる。これにより、例えば凹部層６０２を形成する材料の特性に弱点があっても、ベース層６０１の材料によりそれを補うことができる。例えば、凹部層６０２を形成する材料が熱収縮しやすい材料であっても、ベース層６０１の材料に熱収縮し難い材料を選定し、ベース層６０１の厚みを凹部層６０２を形成する材料厚みよりも厚くすることで、加熱時の変形を抑制することができる。 By making the material of the base layer 601 thicker than the thickness of the material forming the concave layer 602, the physical characteristics of the entire substrate 600 can be dominated by the characteristics of the material of the base layer 601. As a result, even if there is a weakness in the characteristics of the material forming the concave layer 602, for example, the material of the base layer 601 can compensate for the weakness. For example, even if the material forming the concave layer 602 is easily heat-shrinkable, a material that is hard to heat-shrink is selected as the material of the base layer 601 and the thickness of the base layer 601 is set to be larger than the thickness of the material forming the concave layer 602. By making the thickness thicker, it is possible to suppress deformation during heating.
　また、耐熱性又は寸法安定性に優れた樹脂材料と、はんだ微粒子の溶融温度での成分溶出が少ない材料との組み合わせ、耐熱性又は寸法安定性に優れた樹脂材料と、はんだとの濡れ性が適当な材料との組み合わせなど、目的に合わせて有機材料を適宜選定することができる。 In addition, a combination of a resin material having excellent heat resistance or dimensional stability and a material in which components are less likely to elute at the melting temperature of solder fine particles, and a resin material having excellent heat resistance or dimensional stability and wettability with solder can be obtained. An organic material can be appropriately selected according to the purpose, such as a combination with an appropriate material.
　以上のように、基体はベース層６０１と凹部層６０２から構成される基体６００であってよい。例えば、凹部層６０２を感光性材料とすることで、フォトリソグラフィーにより凹部６２が作製できる。凹部層６０２に光又は熱硬化性材料、熱可塑性材料などを用いることで、インプリント法により、容易に凹部６２を作製できる。また、ベース層６０１の厚さを変えることで基体全体の特性を調整することも可能なため、所望の特性を併せ持つ基体を作製できる利点がある。 As described above, the substrate may be a substrate 600 composed of a base layer 601 and a recessed layer 602. For example, by using the recess layer 602 as a photosensitive material, the recess 62 can be produced by photolithography. By using a light or thermosetting material, a thermoplastic material, or the like for the recess layer 602, the recess 62 can be easily produced by the imprint method. Further, since the characteristics of the entire substrate can be adjusted by changing the thickness of the base layer 601, there is an advantage that a substrate having desired characteristics can be produced.
（無機材料　単層（不透明））
　基体６０は無機材料で構成されていてもよい。成分の溶出及び異物の発生を低く制御することが容易である観点から、例えば、無機材料として、シリコン（シリコンウエハ）、ステンレス、アルミなどが利用できる。これらの材料は、半導体の実装プロセスなどで利用する場合に、コンタミ対策が容易であり、高い歩留まりと安定した生産に寄与できる。また、例えば、シリコンウエハ上の電極に、凹部６２内に形成されたはんだ粒子を転写する場合、基体６０がシリコンウエハから作製されていれば、ＣＴＥが近い又は同じ材料が用いられることになる。これにより、位置ずれ、反り等が起きづらく、正確な位置への転写が可能となる。凹部６２の形成方法としては、レーザー、切削等による加工、ドライエッチング又はウエットエッチング法、電子線描画（例えばＦＩＢ加工）等が利用できる。ドライエッチングは、半導体、ＭＥＭＳ等の作製で広く利用されており、ミクロンオーダーからナノオーダーの高い精度で無機材料を加工できる。 (Inorganic material single layer (opaque))
The substrate 60 may be made of an inorganic material. From the viewpoint that it is easy to control the elution of components and the generation of foreign substances to a low level, for example, silicon (silicon wafer), stainless steel, aluminum and the like can be used as the inorganic material. When these materials are used in a semiconductor mounting process or the like, contamination countermeasures are easy, and they can contribute to high yield and stable production. Further, for example, when solder particles formed in the recess 62 are transferred to an electrode on a silicon wafer, if the substrate 60 is made of a silicon wafer, a material having a similar CTE or the same material will be used. As a result, misalignment, warpage, etc. are unlikely to occur, and transfer to an accurate position becomes possible. As a method for forming the recess 62, processing by laser, cutting or the like, dry etching or wet etching method, electron beam drawing (for example, FIB processing) or the like can be used. Dry etching is widely used in the production of semiconductors, MEMS, etc., and can process inorganic materials with high accuracy on the order of microns to nano.
（無機材料　単層（透明））
　基体６０として、ガラス、石英、サファイア等を用いることができる。これらの材料は透明性があるため、電極が形成された別の基板に、凹部６２内のはんだ粒子を転写する際に、容易に位置合わせができる。凹部６２の形成方法としては、レーザー、切削等による加工、ドライエッチング又はウエットエッチング法、電子線描画（例えばＦＩＢ加工）等が利用できる。 (Inorganic material single layer (transparent))
As the substrate 60, glass, quartz, sapphire or the like can be used. Since these materials are transparent, they can be easily aligned when the solder particles in the recess 62 are transferred to another substrate on which the electrodes are formed. As a method for forming the recess 62, processing by laser, cutting or the like, dry etching or wet etching method, electron beam drawing (for example, FIB processing) or the like can be used.
　無機材料を用いる利点は、有機材料と比較して寸法安定性に優れることである。凹部６２内のはんだ粒子を電極上に転写する際に、高い位置精度で転写することができる。例えば、マイクロメートルオーダーのサイズかつピッチの複数電極にはんだ粒子を転写する場合、寸法安定性に優れる無機材料を用いると、いずれの電極上にも同じ位置にはんだ粒子を転写することができる。 The advantage of using an inorganic material is that it is superior in dimensional stability compared to an organic material. When the solder particles in the recess 62 are transferred onto the electrode, they can be transferred with high positional accuracy. For example, when transferring solder particles to a plurality of electrodes having a size and pitch on the order of micrometers, if an inorganic material having excellent dimensional stability is used, the solder particles can be transferred to the same position on any of the electrodes.
（有機無機複合材料）
　基体は複数の材料から構成されていてもよい。また、基体は、複数の層を有していてもよく、複数の層は、それぞれ別の材料で構成されていてもよい。有機無機複合材料としては、例えば、無機材料と無機材料の組み合わせ、無機材料と有機材料の組み合わせが利用できる。無機材料と有機材料の組み合わせは、寸法安定性と凹部６２の加工性の両立が図れる。無機材料と有機材料の組み合わせを有する基体としては、例えば、無機材料であるシリコン、各種セラミックス、ガラス、ステンレススチール等の金属からなるベース層６０１と、有機材料からなる凹部層６０２とを備える基体が挙げられる。そのような基体は、例えば、シリコンウエハの表面に感光性材料を成膜し、露光と現像により凹部を形成する方法により得ることができる。凹部６２の内壁と底部が感光性材料で構成されていてもよく、凹部６２の内壁が感光性材料で底部がシリコンウエハで構成されていてもよい。凹部６２の構成は、凹部６２内のはんだ粒子との濡れ性、電極への転写のしやすさなどの目的に合わせ適宜選択できる。凹部６２の内壁と底部が感光性材料で構成される場合、シリコンウエハ表面に感光性材料を成膜して硬化させることで、シリコンウエハ表面に感光性材料層を一層設け、当該層の表面に再度感光性材料を成膜し、露光・現像を行うことで凹部６２を設ける方法を用いることができる。この場合、シリコンウエハ表面側の感光性材料と、更に最表層に設けた感光性材料が異なる組成であってもよい。感光性材料は、はんだ粒子の濡れ性、汚染性などを考慮し、適宜選択できる。特に、凹部６２内に形成したはんだ粒子を、電極上へ転写する際は、最表層の感光性材料層の表面が電極上または電極を有する基板の表面と接する可能性がある。そのため、電極及び基板にダメージを与えない、または電極及び基板を汚染しない感光性材料を適宜選択することができる。感光性材料は、未硬化成分の溶出、ハロゲン系材料、シリコーン系材料等による汚染を防ぐ材料であってよい。また、感光性材料は、はんだ粒子を電極に転写する時の還元雰囲気、フラックス等に対する耐性が高い材料であってよい。例えば、感光性材料は、ギ酸、水素、水素ラジカルなどの還元雰囲気に対しての耐性がある材料であってよい。更に、感光性材料は、はんだ粒子を電極に転写する時の温度に対して耐性が高い材料であってよい。具体的には、感光性材料は、１００℃以上３００℃以下の温度に対して耐性がある材料であってよい。はんだ粒子の融点はその構成材料により異なるため、感光性材料の耐熱温度も利用するはんだ材料に合わせて選択することができる。電子機器で広く利用されている鉛フリーはんだである錫―銀―銅系はんだ（例：ＳＡＣ３０５（融点２１９℃））を用いる場合、２２０℃以上の耐熱性、特にリフロープロセスで用いられる２６０℃以上の耐熱性がある材料を用いることができる。錫―ビスマス系はんだ（例：ＳｎＢｉ５８（融点１３９℃））を用いる場合、１４０℃以上の耐熱性がある材料を用いることができ、１６０℃以上の耐熱性がある材料であれば、産業上の利用尤度が広くなる。インジウムはんだ（融点１５９℃）を用いる場合、１７０℃以上の耐熱性がある材料を用いることができる。インジウム－錫はんだ（例：融点１２０℃）を用いる場合、１３０℃以上の耐熱性がある材料を用いることができる。 (Organic-inorganic composite material)
The substrate may be composed of a plurality of materials. Further, the substrate may have a plurality of layers, and the plurality of layers may be made of different materials. As the organic-inorganic composite material, for example, a combination of an inorganic material and an inorganic material, or a combination of an inorganic material and an organic material can be used. The combination of the inorganic material and the organic material can achieve both dimensional stability and workability of the recess 62. Examples of the substrate having a combination of an inorganic material and an organic material include a substrate having a base layer 601 made of a metal such as silicon, various ceramics, glass, and stainless steel, which is an inorganic material, and a concave layer 602 made of an organic material. Can be mentioned. Such a substrate can be obtained, for example, by forming a photosensitive material on the surface of a silicon wafer and forming recesses by exposure and development. The inner wall and bottom of the recess 62 may be made of a photosensitive material, or the inner wall of the recess 62 may be made of a photosensitive material and the bottom may be made of a silicon wafer. The configuration of the recess 62 can be appropriately selected according to the purpose such as wettability with the solder particles in the recess 62 and ease of transfer to the electrode. When the inner wall and the bottom of the recess 62 are made of a photosensitive material, a photosensitive material layer is further provided on the surface of the silicon wafer by forming a photosensitive material on the surface of the silicon wafer and curing it, and the surface of the layer is provided with a layer of the photosensitive material. A method of providing the recess 62 by forming a photosensitive material again and performing exposure and development can be used. In this case, the photosensitive material on the surface side of the silicon wafer and the photosensitive material provided on the outermost layer may have different compositions. The photosensitive material can be appropriately selected in consideration of the wettability and stainability of the solder particles. In particular, when the solder particles formed in the recess 62 are transferred onto the electrode, the surface of the photosensitive material layer on the outermost layer may come into contact with the electrode or the surface of the substrate having the electrode. Therefore, a photosensitive material that does not damage the electrode and the substrate or does not contaminate the electrode and the substrate can be appropriately selected. The photosensitive material may be a material that prevents elution of uncured components and contamination by halogen-based materials, silicone-based materials, and the like. Further, the photosensitive material may be a material having high resistance to a reducing atmosphere, flux, etc. when transferring solder particles to an electrode. For example, the photosensitive material may be a material that is resistant to a reducing atmosphere such as formic acid, hydrogen, and hydrogen radicals. Further, the photosensitive material may be a material having high resistance to the temperature at which the solder particles are transferred to the electrode. Specifically, the photosensitive material may be a material that is resistant to temperatures of 100 ° C. or higher and 300 ° C. or lower. Since the melting point of the solder particles differs depending on the constituent material, the heat resistant temperature of the photosensitive material can also be selected according to the solder material to be used. When tin-silver-copper solder (eg SAC305 (melting point 219 ° C)), which is a lead-free solder widely used in electronic devices, is used, it has a heat resistance of 220 ° C or higher, especially 260 ° C or higher used in the reflow process. A material having heat resistance can be used. When tin-bismuth solder (eg SnBi58 (melting point 139 ° C.)) is used, a material having a heat resistance of 140 ° C. or higher can be used, and a material having a heat resistance of 160 ° C. or higher can be used industrially. Wider usage likelihood. When indium solder (melting point 159 ° C.) is used, a material having a heat resistance of 170 ° C. or higher can be used. When indium-tin solder (eg, melting point 120 ° C.) is used, a material having a heat resistance of 130 ° C. or higher can be used.
　他の基体としては、ステンレススチール板上に熱硬化性または熱可塑性樹脂で形成された凹部６２を有する基体が挙げられる。当該基体は、ステンレススチール板とインプリントモールドで熱硬化性材料（樹脂）を挟み、加圧加熱した後、インプリントモールドを剥がす方法により得ることができる。他の基体としては、ガラス板上に光硬化性材料で形成された凹部６２を有する基体が挙げられる。当該基体は、ガラス板上に光硬化性材料を塗布し、インプリントモールドを押し付けながら露光して光硬化性材料を硬化させ、インプリントモールドを剥がす方法により得ることができる。インプリントモールドを用いて凹部６２を形成する場合、加圧条件により凹部６２の内壁と底部の材料構成を変更することができる。例えば、加圧条件を緩くした場合、凹部６２の内壁と底部は同じ樹脂材料の構成とすることができる。一方で、加圧条件を強くした場合、凹部６２の内壁は樹脂材料、底部は無機材料の構成とすることができる。 Examples of the other substrate include a substrate having a recess 62 formed of a thermosetting or thermoplastic resin on a stainless steel plate. The substrate can be obtained by sandwiching a thermosetting material (resin) between a stainless steel plate and an imprint mold, heating under pressure, and then peeling off the imprint mold. Examples of the other substrate include a substrate having a recess 62 formed of a photocurable material on a glass plate. The substrate can be obtained by applying a photocurable material on a glass plate and exposing the substrate while pressing the imprint mold to cure the photocurable material and peeling off the imprint mold. When the recess 62 is formed by using the imprint mold, the material composition of the inner wall and the bottom of the recess 62 can be changed depending on the pressurizing condition. For example, when the pressurizing condition is relaxed, the inner wall and the bottom of the recess 62 can be made of the same resin material. On the other hand, when the pressurizing condition is strengthened, the inner wall of the recess 62 can be made of a resin material and the bottom can be made of an inorganic material.
　ベース層６０１の材料として、ガラス繊維、フィラー等と、樹脂成分とを含む複合材を利用することもできる。複合材としては、配線板用銅張積層板等が挙げられる。銅張積層板の表面に感光性材料、熱硬化性樹脂、光硬化性樹脂等を塗布して、前述のように凹部６２を形成することができる。銅張積層板は主に樹脂材料分が多く含まれるが、ガラス繊維、各種フィラー等との組み合わせにより低ＣＴＥにすることができるため、前述の寸法安定性を確保することができる。また、銅張積層板上に電極を形成した場合、凹部６２も同じ銅張積層板上に形成することで、両者のＣＴＥが同じ又は近い値になり、凹部６２内のはんだ粒子の転写時に位置合わせが容易で、位置ずれが起きにくい利点がある。 As the material of the base layer 601, a composite material containing glass fiber, a filler, etc. and a resin component can also be used. Examples of the composite material include a copper-clad laminate for a wiring board and the like. A photosensitive material, a thermosetting resin, a photocurable resin, or the like can be applied to the surface of the copper-clad laminate to form the recess 62 as described above. Although the copper-clad laminate mainly contains a large amount of resin material, the CTE can be lowered by combining with glass fiber, various fillers, and the like, so that the above-mentioned dimensional stability can be ensured. Further, when the electrode is formed on the copper-clad laminate, the recess 62 is also formed on the same copper-clad laminate so that the CTEs of both become the same or close to each other, and the position at the time of transferring the solder particles in the recess 62 is obtained. It has the advantage of being easy to align and less likely to cause misalignment.
　凹部層６０２の材料として、パッケージ用封止材を利用することもできる。封止材としては固形、液状及びフィルム状のいずれも利用できる。封止材をガラス、シリコンウエハ等の上に薄層で積層し、インプリントモールドで加圧加熱することで、凹部６２を形成することができる。 A packaging encapsulant can also be used as the material for the recess layer 602. As the sealing material, any solid, liquid or film form can be used. The recess 62 can be formed by laminating a sealing material on a glass, silicon wafer, or the like in a thin layer and pressurizing and heating with an imprint mold.
＜はんだバンプ形成用部材の製造方法＞
　はんだバンプ形成用部材１０の製造方法は、複数の凹部を有する基体及びはんだ微粒子を準備する準備工程と、はんだ微粒子の少なくとも一部を、凹部に収容する収容工程と、凹部に収容されたはんだ微粒子を融合させて、凹部内にはんだ粒子を形成する融合工程と、はんだ粒子が形成された凹部内に流動化剤（流動相）を配置（注入）する注入工程と、を備える。 <Manufacturing method of solder bump forming member>
The method for manufacturing the solder bump forming member 10 includes a preparatory step of preparing a substrate having a plurality of recesses and solder fine particles, a storage step of storing at least a part of the solder fine particles in the recesses, and a solder fine particles housed in the recesses. A fusion step of forming solder particles in the recesses by fusing the solder particles and an injection step of arranging (injecting) a fluidizing agent (fluid phase) in the recesses in which the solder particles are formed are provided.
　図３～５を参照しながら、第一実施形態に係るはんだバンプ形成用部材１０の製造方法について説明する。 The method for manufacturing the solder bump forming member 10 according to the first embodiment will be described with reference to FIGS. 3 to 5.
　まず、はんだ微粒子と、はんだ微粒子を収容するための基体６０を準備する。図３（ａ）は、基体６０の一例を模式的に示す平面図であり、図３（ｂ）は、図３（ａ）のＩｂ－Ｉｂ線における断面図である。図３（ａ）に示す基体６０は、複数の凹部６２を有している。複数の凹部６２は所定のパターンで規則的に配置されていてよい。接続すべき電極の形状、サイズ及びパターン等に応じ、複数の凹部６２の位置及び個数等を設定すればよい。 First, the solder fine particles and the substrate 60 for accommodating the solder fine particles are prepared. FIG. 3A is a plan view schematically showing an example of the substrate 60, and FIG. 3B is a cross-sectional view taken along the line Ib-Ib of FIG. 3A. The substrate 60 shown in FIG. 3A has a plurality of recesses 62. The plurality of recesses 62 may be regularly arranged in a predetermined pattern. The positions and numbers of the plurality of recesses 62 may be set according to the shape, size, pattern, etc. of the electrodes to be connected.
　隣接する凹部間の距離Ｌに特に制限はないが、収容されるはんだ粒子の平均粒子径の０．１倍以上とすることができ、１倍以上であってよい。距離Ｌは、はんだバンプを形成する電極の配置によって適宜調整することができる。凹部間の距離とは凹部の中心間距離ではなく、凹部開口の縁から縁への距離である。 The distance L between adjacent recesses is not particularly limited, but can be 0.1 times or more the average particle size of the contained solder particles, and may be 1 time or more. The distance L can be appropriately adjusted by arranging the electrodes forming the solder bumps. The distance between the recesses is not the distance between the centers of the recesses, but the distance from the edge of the recess opening to the edge.
　基体６０の凹部６２は、凹部６２の底部６２ａ側から基体６０の表面６０ａ側に向けて開口面積が拡大するテーパ状に形成されていることが好ましい。すなわち、図３（ａ）及び図３（ｂ）に示すように、凹部６２の底部６２ａの幅（図３（ａ）及び図３（ｂ）における幅ａ）は、凹部６２の表面６０ａにおける開口の幅（図３（ａ）及び図３（ｂ）における幅ｂ）よりも狭いことが好ましい。そして、凹部６２のサイズ（幅ａ、幅ｂ、容積、テーパ角度及び深さ等）は、目的とするはんだ粒子のサイズに応じて設定すればよい。 The recess 62 of the base 60 is preferably formed in a tapered shape in which the opening area expands from the bottom 62a side of the recess 62 toward the surface 60a side of the base 60. That is, as shown in FIGS. 3A and 3B, the width of the bottom 62a of the recess 62 (the width a in FIGS. 3A and 3B) is the opening at the surface 60a of the recess 62. Is preferably narrower than the width of (width b in FIGS. 3 (a) and 3 (b)). The size of the recess 62 (width a, width b, volume, taper angle, depth, etc.) may be set according to the size of the target solder particles.
　なお、凹部６２の形状は図３（ａ）及び図３（ｂ）に示す形状以外の形状であってもよい。例えば、凹部６２の表面６０ａにおける開口の形状は、図３（ａ）に示すような円形以外に、楕円形、三角形、四角形、多角形等であってよい。 The shape of the recess 62 may be a shape other than the shapes shown in FIGS. 3 (a) and 3 (b). For example, the shape of the opening on the surface 60a of the recess 62 may be an ellipse, a triangle, a quadrangle, a polygon, or the like, in addition to the circular shape as shown in FIG. 3A.
　また、表面６０ａに対して垂直な断面における凹部６２の形状は、例えば、図４に示すような形状であってよい。図４（ａ）～（ｈ）は、基体が有する凹部の断面形状の例を模式的に示す断面図である。図４（ａ）～（ｈ）に示すいずれの断面形状も、凹部６２の表面６０ａにおける開口の幅（幅ｂ）が、断面形状における最大幅となっている。これにより、凹部６２内に形成されたはんだ粒子が取り出し易くなり、作業性が向上する。また、上記開口の幅（幅ｂ）が、断面形状における最大幅となっていることから、はんだ粒子１を電極上に転写する場合に、はんだ粒子１が凹部６２から抜け出し易く、転写率の向上が期待できる。また、上記開口の幅（幅ｂ）を適切に調整することで、はんだ粒子１を電極上に転写する時の位置ずれが起き難くなり、正確な位置にはんだバンプを形成し易くなる。 Further, the shape of the recess 62 in the cross section perpendicular to the surface 60a may be, for example, the shape shown in FIG. 4 (a) to 4 (h) are cross-sectional views schematically showing an example of the cross-sectional shape of the concave portion of the substrate. In each of the cross-sectional shapes shown in FIGS. 4A to 4H, the width (width b) of the opening on the surface 60a of the recess 62 is the maximum width in the cross-sectional shape. As a result, the solder particles formed in the recess 62 can be easily taken out, and workability is improved. Further, since the width (width b) of the opening is the maximum width in the cross-sectional shape, when the solder particles 1 are transferred onto the electrodes, the solder particles 1 can easily come out from the recess 62, and the transfer rate is improved. Can be expected. Further, by appropriately adjusting the width (width b) of the opening, the position shift when the solder particles 1 are transferred onto the electrodes is less likely to occur, and the solder bumps are easily formed at the correct positions.
　準備工程で準備されるはんだ微粒子は、凹部６２の表面６０ａにおける開口の幅（幅ｂ）より小さい粒子径の微粒子を含むものであればよく、幅ｂより小さい粒子径の微粒子をより多く含むことが好ましい。例えば、はんだ微粒子は、粒度分布のＤ１０粒子径が幅ｂより小さいことが好ましく、粒度分布のＤ３０粒子径が幅ｂより小さいことがより好ましく、粒度分布のＤ５０粒子径が幅ｂより小さいことが更に好ましい。 The solder fine particles prepared in the preparatory step may contain fine particles having a particle size smaller than the width (width b) of the opening on the surface 60a of the recess 62, and may contain more fine particles having a particle size smaller than the width b. Is preferable. For example, in the solder fine particles, the D10 particle size of the particle size distribution is preferably smaller than the width b, the D30 particle size of the particle size distribution is more preferably smaller than the width b, and the D50 particle size of the particle size distribution is smaller than the width b. More preferred.
　はんだ微粒子の粒度分布は、サイズに合わせた各種方法を用いて測定することができる。例えば、動的光散乱法、レーザー回折法、遠心沈降法、電気的検知帯法、共振式質量測定法等の方法を利用できる。さらに、光学顕微鏡、電子顕微鏡等によって得られる画像から、粒子サイズを測定する方法を利用できる。具体的な装置としては、フロー式粒子像分析装置、マイクロトラック、コールターカウンター等が挙げられる。 The particle size distribution of the solder fine particles can be measured using various methods according to the size. For example, a dynamic light scattering method, a laser diffraction method, a centrifugal sedimentation method, an electrical detection band method, a resonance type mass measurement method, or the like can be used. Further, a method of measuring the particle size from an image obtained by an optical microscope, an electron microscope, or the like can be used. Specific devices include a flow-type particle image analyzer, a microtrack, a Coulter counter, and the like.
　準備工程で準備されるはんだ微粒子のＣ．Ｖ．値は特に限定されないが、大小の微粒子の組み合わせによる凹部６２への充填性が向上する観点から、Ｃ．Ｖ．値は高いことが好ましい。例えば、はんだ微粒子のＣ．Ｖ．値は、２０％を超えていてよく、好ましくは２５％以上、より好ましくは３０％以上である。 C. of solder fine particles prepared in the preparation process. V. The value is not particularly limited, but from the viewpoint of improving the filling property into the recess 62 by the combination of large and small fine particles, C.I. V. The value is preferably high. For example, C.I. V. The value may exceed 20%, preferably 25% or more, more preferably 30% or more.
　はんだ微粒子のＣ．Ｖ．値は、前述の方法によって測定された粒子径の標準偏差を平均粒子径（Ｄ５０粒子径）で割った値に１００を掛けることで算出される。 C. of solder fine particles. V. The value is calculated by dividing the standard deviation of the particle size measured by the above method by the average particle size (D50 particle size) and multiplying by 100.
　はんだ微粒子は、スズ又はスズ合金を含むものであってよい。スズ合金としては、例えば、Ｉｎ－Ｓｎ合金、Ｉｎ－Ｓｎ－Ａｇ合金、Ｓｎ－Ａｕ合金、Ｓｎ－Ｂｉ合金、Ｓｎ－Ｂｉ－Ａｇ合金、Ｓｎ－Ａｇ－Ｃｕ合金、Ｓｎ－Ｃｕ合金等を用いることができる。これらのスズ合金の具体例としては、下記の例が挙げられる。
・Ｉｎ－Ｓｎ（Ｉｎ５２質量％、Ｂｉ４８質量％　融点１１８℃）
・Ｉｎ－Ｓｎ－Ａｇ（Ｉｎ２０質量％、Ｓｎ７７．２質量％、Ａｇ２．８質量％　融点１７５℃）
・Ｓｎ－Ｂｉ（Ｓｎ４３質量％、Ｂｉ５７質量％　融点１３８℃）
・Ｓｎ－Ｂｉ－Ａｇ（Ｓｎ４２質量％、Ｂｉ５７質量％、Ａｇ１質量％　融点１３９℃）
・Ｓｎ－Ａｇ－Ｃｕ（Ｓｎ９６．５質量％、Ａｇ３質量％、Ｃｕ０．５質量％　融点２１７℃）
・Ｓｎ－Ｃｕ（Ｓｎ９９．３質量％、Ｃｕ０．７質量％　融点２２７℃）
・Ｓｎ－Ａｕ（Ｓｎ２１．０質量％、Ａｕ７９．０質量％　融点２７８℃） The solder fine particles may contain tin or a tin alloy. As the tin alloy, for example, In—Sn alloy, In—Sn—Ag alloy, Sn—Au alloy, Sn—Bi alloy, Sn—Bi—Ag alloy, Sn—Ag—Cu alloy, Sn—Cu alloy and the like are used. be able to. Specific examples of these tin alloys include the following examples.
-In-Sn (In 52% by mass, Bi48% by mass, melting point 118 ° C)
-In-Sn-Ag (In 20% by mass, Sn77.2% by mass, Ag 2.8% by mass, melting point 175 ° C.)
-Sn-Bi (Sn43% by mass, Bi57% by mass, melting point 138 ° C.)
-Sn-Bi-Ag (Sn42% by mass, Bi57% by mass, Ag1% by mass, melting point 139 ° C.)
-Sn-Ag-Cu (Sn96.5% by mass, Ag3% by mass, Cu0.5% by mass, melting point 217 ° C)
-Sn-Cu (Sn99.3% by mass, Cu0.7% by mass, melting point 227 ° C)
-Sn-Au (Sn21.0% by mass, Au79.0% by mass, melting point 278 ° C.)
　はんだ微粒子は、インジウム又はインジウム合金を含むものであってよい。インジウム合金としては、例えば、Ｉｎ－Ｂｉ合金、Ｉｎ－Ａｇ合金等を用いることができる。これらのインジウム合金の具体例としては、下記の例が挙げられる。
・Ｉｎ－Ｂｉ（Ｉｎ６６．３質量％、Ｂｉ３３．７質量％　融点７２℃）
・Ｉｎ－Ｂｉ（Ｉｎ３３．０質量％、Ｂｉ６７．０質量％　融点１０９℃）
・Ｉｎ－Ａｇ（Ｉｎ９７．０質量％、Ａｇ３．０質量％　融点１４５℃） The solder fine particles may contain indium or an indium alloy. As the indium alloy, for example, an In—Bi alloy, an In—Ag alloy, or the like can be used. Specific examples of these indium alloys include the following examples.
-In-Bi (In66.3% by mass, Bi33.7% by mass, melting point 72 ° C.)
-In-Bi (In33.0% by mass, Bi67.0% by mass, melting point 109 ° C)
-In-Ag (In97.0% by mass, Ag3.0% by mass, melting point 145 ° C)
　はんだ粒子の用途（使用時の温度）等に応じて、上記スズ合金又はインジウム合金を選択することができる。例えば、低温での融着に用いるはんだ粒子を得たい場合、Ｉｎ－Ｓｎ合金、Ｓｎ－Ｂｉ合金を採用すればよく、この場合、１５０℃以下で融着可能なはんだ粒子が得られる。Ｓｎ－Ａｇ－Ｃｕ合金、Ｓｎ－Ｃｕ合金等の融点の高い材料を採用した場合、高温放置後においても高い信頼性を維持可能なはんだ粒子を得ることができる。 The above tin alloy or indium alloy can be selected according to the application (temperature at the time of use) of the solder particles. For example, when it is desired to obtain solder particles used for fusion at a low temperature, an In—Sn alloy or a Sn—Bi alloy may be adopted. In this case, solder particles that can be fused at 150 ° C. or lower can be obtained. When a material having a high melting point such as Sn—Ag—Cu alloy or Sn—Cu alloy is used, solder particles capable of maintaining high reliability even after being left at a high temperature can be obtained.
　はんだ微粒子は、Ａｇ、Ｃｕ、Ｎｉ、Ｂｉ、Ｚｎ、Ｐｄ、Ｐｂ、Ａｕ、Ｐ及びＢから選ばれる一種以上を含んでもよい。これらの元素のうち、以下の観点からＡｇ又はＣｕを含んでもよい。すなわち、はんだ微粒子がＡｇ又はＣｕを含むことで、得られるはんだ粒子の融点を２２０℃程度まで低下させることができる、電極との接合強度に優れたはんだ粒子が得られることによってより良好な導通信頼性を得られる、という効果が奏される。 The solder fine particles may contain one or more selected from Ag, Cu, Ni, Bi, Zn, Pd, Pb, Au, P and B. Among these elements, Ag or Cu may be contained from the following viewpoints. That is, when the solder fine particles contain Ag or Cu, the melting point of the obtained solder particles can be lowered to about 220 ° C., and the solder particles having excellent bonding strength with the electrode can be obtained, so that better conduction reliability can be obtained. The effect of obtaining sex is achieved.
　はんだ微粒子のＣｕ含有率は例えば０．０５～１０質量％であり、０．１～５質量％又は０．２～３質量％であってもよい。Ｃｕ含有率が０．０５質量％以上であると、良好なはんだ接続信頼性を達成可能なはんだ粒子が得られ易くなる。また、Ｃｕ含有率が１０質量％以下であると、融点が低く、濡れ性に優れたはんだ粒子が得られ易くなり、結果としてはんだバンプ付き電極の接続信頼性がより良好となり易い。 The Cu content of the solder fine particles is, for example, 0.05 to 10% by mass, and may be 0.1 to 5% by mass or 0.2 to 3% by mass. When the Cu content is 0.05% by mass or more, it becomes easy to obtain solder particles capable of achieving good solder connection reliability. Further, when the Cu content is 10% by mass or less, solder particles having a low melting point and excellent wettability can be easily obtained, and as a result, the connection reliability of the electrode with solder bumps tends to be improved.
　はんだ微粒子のＡｇ含有率は例えば０．０５～１０質量％であり、０．１～５質量％又は０．２～３質量％であってもよい。Ａｇ含有率が０．０５質量％以上であれば、良好なはんだ接続信頼性を達成可能なはんだ粒子が得られ易くなる。また、Ａｇ含油率が１０質量％以下であると、融点が低く、濡れ性に優れたはんだ粒子が得られ易くなり、結果としてはんだバンプ付き電極の接続信頼性がより良好となり易い。 The Ag content of the solder fine particles is, for example, 0.05 to 10% by mass, and may be 0.1 to 5% by mass or 0.2 to 3% by mass. When the Ag content is 0.05% by mass or more, it becomes easy to obtain solder particles capable of achieving good solder connection reliability. Further, when the Ag oil content is 10% by mass or less, solder particles having a low melting point and excellent wettability can be easily obtained, and as a result, the connection reliability of the electrode with solder bumps tends to be improved.
　収容工程では、基体６０の凹部６２のそれぞれに、準備工程で準備したはんだ微粒子を収容する。収容工程では、準備工程で準備したはんだ微粒子の全部を凹部６２に収容する工程であってよく、準備工程で準備したはんだ微粒子の一部（例えば、はんだ微粒子のうち、凹部６２の開口の幅ｂより小さいもの）を凹部６２に収容する工程であってよい。 In the accommodating step, the solder fine particles prepared in the preparatory step are accommodated in each of the recesses 62 of the substrate 60. The accommodating step may be a step of accommodating all the solder fine particles prepared in the preparatory step into the recess 62, and a part of the solder fine particles prepared in the preparatory step (for example, the width b of the opening of the recess 62 among the solder fine particles). It may be a step of accommodating a smaller particle) in the recess 62.
　図５は、基体６０の凹部６２にはんだ微粒子１１１が収容された状態を模式的に示す断面図である。図５に示すように、複数の凹部６２のそれぞれに、複数のはんだ微粒子１１１が収容される。 FIG. 5 is a cross-sectional view schematically showing a state in which the solder fine particles 111 are housed in the recess 62 of the substrate 60. As shown in FIG. 5, a plurality of solder fine particles 111 are housed in each of the plurality of recesses 62.
　凹部６２に収容されたはんだ微粒子１１１の量は、例えば、凹部６２の容積に対して２０％以上であることが好ましく、３０％以上であることがより好ましく、５０％以上であることが更に好ましく、６０％以上であることが最も好ましい。これにより、収容量のばらつきが抑えられ、粒度分布のより小さいはんだ粒子が得られ易くなる。 The amount of the solder fine particles 111 contained in the recess 62 is, for example, preferably 20% or more, more preferably 30% or more, still more preferably 50% or more, based on the volume of the recess 62. , 60% or more is most preferable. As a result, the variation in the accommodating amount is suppressed, and it becomes easy to obtain solder particles having a smaller particle size distribution.
　はんだ微粒子を凹部６２に収容する方法は特に限定されない。収容方法は、乾式、湿式のいずれであってもよい。例えば、準備工程で準備したはんだ微粒子を基体６０上に配置し、スキージを用いて基体６０の表面６０ａを擦ることで、余分なはんだ微粒子を除去しつつ、凹部６２内に十分なはんだ微粒子を収容することができる。凹部６２の開口の幅ｂが凹部６２の深さより大きい場合、凹部６２の開口からはんだ微粒子が飛び出す場合がある。スキージを用いると、凹部６２の開口から飛び出ているはんだ微粒子は除去される。余分なはんだ微粒子を除去する方法として、圧縮空気を吹き付ける、不織布又は繊維の束で基体６０の表面６０ａを擦る、等の方法も挙げられる。これらの方法は、スキージと比べて物理的な力が弱いため、変形し易いはんだ微粒子を扱う上で好ましい。また、これらの方法では、凹部６２の開口から飛び出ているはんだ微粒子を凹部内に残すこともできる。 The method of accommodating the solder fine particles in the recess 62 is not particularly limited. The accommodating method may be either dry or wet. For example, the solder fine particles prepared in the preparation step are placed on the substrate 60, and the surface 60a of the substrate 60 is rubbed with a squeegee to remove the excess solder fine particles while accommodating sufficient solder fine particles in the recess 62. can do. When the width b of the opening of the recess 62 is larger than the depth of the recess 62, solder fine particles may pop out from the opening of the recess 62. When a squeegee is used, the solder fine particles protruding from the opening of the recess 62 are removed. Examples of the method of removing the excess solder fine particles include a method of blowing compressed air, a method of rubbing the surface 60a of the substrate 60 with a non-woven fabric or a bundle of fibers, and the like. Since these methods have a weaker physical force than the squeegee, they are preferable for handling easily deformable solder fine particles. Further, in these methods, the solder fine particles protruding from the opening of the recess 62 can be left in the recess.
　融合工程は、凹部６２に収容されたはんだ微粒子１１１を（例えば１３０～２６０℃に加熱することによって）融合させて、凹部６２の内部にはんだ粒子１を形成する工程である。凹部６２に収容されたはんだ微粒子１１１は、溶融することで合一化し、表面張力によって球状化する。このとき、凹部６２の底部６２ａとの接触部では、溶融したはんだが底部６２ａに追従して平面部１１を形成する。これにより、形成されるはんだ粒子１は、表面の一部に平面部１１を有する形状となる。このようにして、図１に示すはんだバンプ形成用部材１０が得られる。 The fusion step is a step of fusing the solder fine particles 111 contained in the recess 62 (for example, by heating to 130 to 260 ° C.) to form the solder particles 1 inside the recess 62. The solder fine particles 111 housed in the recess 62 are united by melting and spheroidized by surface tension. At this time, at the contact portion of the recess 62 with the bottom portion 62a, the molten solder follows the bottom portion 62a to form the flat surface portion 11. As a result, the formed solder particles 1 have a shape having a flat surface portion 11 on a part of the surface. In this way, the solder bump forming member 10 shown in FIG. 1 is obtained.
　凹部６２に収容されたはんだ微粒子１１１を溶融させる方法としては、はんだ微粒子１１１をはんだの融点以上に加熱する方法が挙げられる。はんだ微粒子１１１は、酸化被膜の影響で融点以上の温度で加熱しても溶融しなかったり、濡れ拡がらなかったりして、合一化しない場合がある。このため、はんだ微粒子１１１を還元雰囲気下に晒し、はんだ微粒子１１１の表面酸化被膜を除去した後に、はんだ微粒子１１１の融点以上の温度に加熱することで、はんだ微粒子１１１を溶融させ、濡れ拡がり、合一化させることができる。また、はんだ微粒子１１１の溶融は、還元雰囲気下で行うことが好ましい。はんだ微粒子１１１をはんだ微粒子１１１の融点以上に加熱し、かつ還元雰囲気とすることで、はんだ微粒子１１１の表面の酸化被膜が還元され、はんだ微粒子１１１の溶融、濡れ拡がり、合一化が効率的に進行し易くなる。すなわち、はんだバンプ形成用部材の製造方法は、融合工程の前に、凹部に収容されたはんだ微粒子を還元雰囲気に晒す還元工程を更に備えてよい。また、はんだバンプ形成用部材の製造方法の融合工程において、はんだ微粒子を還元雰囲気下で融合させてよい。 Examples of the method of melting the solder fine particles 111 contained in the recess 62 include a method of heating the solder fine particles 111 to a temperature equal to or higher than the melting point of the solder. Due to the influence of the oxide film, the solder fine particles 111 may not melt or spread even when heated at a temperature equal to or higher than the melting point, and may not be united. Therefore, the solder fine particles 111 are exposed to a reducing atmosphere to remove the surface oxide film of the solder fine particles 111, and then heated to a temperature equal to or higher than the melting point of the solder fine particles 111 to melt the solder fine particles 111 and spread them wet. It can be unified. Further, it is preferable that the solder fine particles 111 are melted in a reducing atmosphere. By heating the solder fine particles 111 to a temperature equal to or higher than the melting point of the solder fine particles 111 and creating a reducing atmosphere, the oxide film on the surface of the solder fine particles 111 is reduced, and the solder fine particles 111 are efficiently melted, wetted and spread, and unified. It becomes easier to proceed. That is, the method for manufacturing the solder bump forming member may further include a reduction step of exposing the solder fine particles contained in the recesses to the reducing atmosphere before the fusion step. Further, in the fusion step of the method for manufacturing the solder bump forming member, the solder fine particles may be fused in a reducing atmosphere.
　還元雰囲気にする方法は、上述の効果が得られる方法であれば特に限定されず、例えば水素ガス、水素ラジカル、ギ酸ガス等を用いる方法がある。例えば、水素還元炉、水素ラジカル還元炉、ギ酸還元炉、又はこれらのコンベアー炉若しくは連続炉を用いることで、還元雰囲気下にはんだ微粒子１１１を溶融させることができる。これらの装置は、炉内に、加熱装置、不活性ガス（窒素、アルゴン等）を充填するチャンバー、チャンバー内を真空にする機構等を備えていてよく、これにより還元ガスの制御がより容易となる。また、チャンバー内を真空にできると、はんだ微粒子１１１の溶融及び合一化の後に、減圧によってボイドの除去を行うことができ、接続安定性に一層優れるはんだ粒子１を得ることができる。 The method for creating a reducing atmosphere is not particularly limited as long as the above effects can be obtained, and for example, there is a method using hydrogen gas, hydrogen radical, formic acid gas, or the like. For example, by using a hydrogen reduction furnace, a hydrogen radical reduction furnace, a formic acid reduction furnace, or a conveyor furnace or a continuous furnace thereof, the solder fine particles 111 can be melted in a reducing atmosphere. These devices may be equipped with a heating device, a chamber filled with an inert gas (nitrogen, argon, etc.), a mechanism for evacuating the inside of the chamber, etc., which makes it easier to control the reducing gas. Become. Further, if the inside of the chamber can be evacuated, the voids can be removed by reducing the pressure after the solder fine particles 111 are melted and united, and the solder particles 1 having further excellent connection stability can be obtained.
　はんだ微粒子１１１の還元、溶解条件、温度、炉内雰囲気調整などのプロファイルは、はんだ微粒子１１１の融点、粒度、凹部サイズ、基体６０の材質などを勘案して適宜設定されてよい。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、はんだ微粒子１１１の表面酸化被膜を除去した後、真空引きにて還元ガスを除去し、その後、はんだ微粒子１１１の融点以上に加熱して、はんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成した後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。また、例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、炉内加熱ヒーターによりはんだ微粒子１１１を加熱して、はんだ微粒子１１１の表面酸化被膜を除去した後、真空引きにて還元ガスを除去し、その後、はんだ微粒子１１１の融点以上に加熱して、はんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成した後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。還元雰囲気下で、はんだ微粒子を加熱することで、還元力が増し、はんだ微粒子の表面酸化被膜の除去が容易になる利点がある。 Profiles such as reduction, melting conditions, temperature, and atmosphere adjustment in the furnace of the solder fine particles 111 may be appropriately set in consideration of the melting point, particle size, recess size, material of the substrate 60, and the like of the solder fine particles 111. For example, the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, vacuumed, and then the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the surface oxide film of the solder fine particles 111 is formed. After removing, the reducing gas is removed by vacuuming, and then the gas is heated to a temperature equal to or higher than the melting point of the solder fine particles 111 to dissolve and coalesce the solder fine particles to form the solder particles in the recess 62. After filling with nitrogen gas, the temperature inside the furnace is returned to room temperature to obtain solder particles 1. Further, for example, the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, and after vacuuming, the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the in-core heater is used. The solder fine particles 111 are heated to remove the surface oxide film of the solder fine particles 111, then the reducing gas is removed by vacuuming, and then the solder fine particles 111 are heated to the melting point or higher to dissolve and coalesce the solder fine particles. After forming the solder particles in the recess 62, the temperature inside the furnace is returned to room temperature after filling with nitrogen gas to obtain the solder particles 1. By heating the solder fine particles in a reducing atmosphere, there is an advantage that the reducing power is increased and the surface oxide film of the solder fine particles can be easily removed.
　さらに、例えば、はんだ微粒子１１１が凹部に充填された基体６０を、炉内に挿入し、真空引きを行った後に、還元ガスを導入して、炉内を還元ガスで満たし、炉内加熱ヒーターによりはんだ微粒子１１１の融点以上に加熱して、はんだ微粒子１１１の表面酸化被膜を還元により除去すると同時にはんだ微粒子を溶解及び合一化させて、凹部６２内にはんだ粒子を形成し、真空引きにて還元ガスを除去し、さらにはんだ粒子内のボイドを減らした後、窒素ガスを充填してから炉内温度を室温に戻し、はんだ粒子１を得ることができる。この場合は、炉内温度の上昇、下降の調節がそれぞれ一回でよいため、短時間で処理できる利点がある。 Further, for example, the substrate 60 in which the solder fine particles 111 are filled in the recesses is inserted into the furnace, and after vacuuming, the reducing gas is introduced to fill the inside of the furnace with the reducing gas, and the in-core heater is used. By heating to a temperature equal to or higher than the melting point of the solder fine particles 111, the surface oxide film of the solder fine particles 111 is removed by reduction, and at the same time, the solder fine particles are melted and united to form solder particles in the recess 62, which is reduced by vacuuming. After removing the gas and further reducing the voids in the solder particles, the temperature in the furnace is returned to room temperature after filling with nitrogen gas, and the solder particles 1 can be obtained. In this case, since the temperature rise and fall in the furnace need only be adjusted once, there is an advantage that the processing can be performed in a short time.
　上述の凹部６２内にはんだ粒子を形成した後に、もう一度炉内を還元雰囲気にして、除去し切れなかった表面酸化被膜を除去する工程を加えてもよい。これにより、融合されずに残っていたはんだ微粒子、融合されずに残っていた酸化被膜の一部などの残渣を減らすことができる。 After forming the solder particles in the recess 62 described above, the inside of the furnace may be made into a reducing atmosphere again to add a step of removing the surface oxide film that could not be completely removed. As a result, it is possible to reduce residues such as solder fine particles remaining unfused and a part of the oxide film remaining unfused.
　大気圧のコンベアー炉を用いる場合は、はんだ微粒子１１１が凹部に充填された基体６０を搬送用コンベアーに載せ、複数のゾーンを連続して通過させてはんだ粒子１を得ることができる。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、一定の速度に設定したコンベアーに載せ、はんだ微粒子１１１の融点より低い温度の窒素又はアルゴンなどの不活性ガスが充満したゾーンを通過させ、続いてはんだ微粒子１１１の融点より低い温度のギ酸ガスなどの還元ガスが存在するゾーンを通過させて、はんだ微粒子１１１の表面酸化被膜を除去し、続いてはんだ微粒子１１１の融点以上の温度の窒素又はアルゴンなどの不活性ガスが充満したゾーンを通過させてはんだ微粒子１１１を溶融、合一化させ、続いて窒素又はアルゴンなどの不活性ガスが充満した冷却ゾーンを通過させて、はんだ粒子１を得ることができる。例えば、はんだ微粒子１１１が凹部に充填された基体６０を、一定の速度に設定したコンベアーに載せ、はんだ微粒子１１１の融点以上の温度の窒素又はアルゴンなどの不活性ガスが充満したゾーンを通過させ、続いてはんだ微粒子１１１の融点以上の温度のギ酸ガスなどの還元ガスが存在するゾーンを通過させて、はんだ微粒子１１１の表面酸化被膜を除去し、溶融、合一化させ、続いて窒素又はアルゴンなどの不活性ガスが充満した冷却ゾーンを通過させて、はんだ粒子１を得ることができる。前記のコンベアー炉は、大気圧での処理が可能であることから、フィルム状の材料をロールトゥロールで連続的に処理することもできる。例えば、はんだ微粒子１１１が凹部に充填された基体６０の連続ロール品を作製し、コンベアー炉の入り口側にロール巻きだし機、コンベアー炉の出口側にロール巻き取り機を設置して、一定の速度で基体６０を搬送し、コンベアー炉内の各ゾーンを通過させることで、凹部に充填されたはんだ微粒子１１１を融合させることができる。 When an atmospheric pressure conveyor furnace is used, the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on the conveyor and passed through a plurality of zones in succession to obtain the solder particles 1. For example, the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on a conveyor set at a constant speed and passed through a zone filled with an inert gas such as nitrogen or argon at a temperature lower than the melting point of the solder fine particles 111. Subsequently, the surface oxide film of the solder fine particles 111 is removed by passing through a zone in which a reducing gas such as formic acid gas having a temperature lower than the melting point of the solder fine particles 111 exists, and then nitrogen or nitrogen having a temperature equal to or higher than the melting point of the solder fine particles 111 is removed. The solder fine particles 111 are melted and coalesced by passing through a zone filled with an inert gas such as argon, and then passed through a cooling zone filled with an inert gas such as nitrogen or argon to obtain solder particles 1. be able to. For example, the substrate 60 in which the solder fine particles 111 are filled in the recesses is placed on a conveyor set at a constant speed and passed through a zone filled with an inert gas such as nitrogen or argon having a temperature equal to or higher than the melting point of the solder fine particles 111. Subsequently, the surface oxide film of the solder fine particles 111 is removed, melted and coalesced by passing through a zone in which a reducing gas such as formic acid gas having a temperature equal to or higher than the melting point of the solder fine particles 111 exists, and then nitrogen or argon or the like is used. The solder particles 1 can be obtained by passing through a cooling zone filled with the inert gas. Since the conveyor furnace can be processed at atmospheric pressure, a film-like material can be continuously processed by roll-to-roll. For example, a continuous roll product of the substrate 60 in which the solder fine particles 111 are filled in the recesses is produced, a roll unwinder is installed on the inlet side of the conveyor furnace, and a roll winder is installed on the outlet side of the conveyor furnace to maintain a constant speed. By transporting the substrate 60 and passing through each zone in the conveyor furnace, the solder fine particles 111 filled in the recesses can be fused.
　準備工程～融合工程によれば、はんだ微粒子１１１の材質及び形状によらず、均一なサイズのはんだ粒子１を形成することができる。例えば、インジウム系はんだは、めっきによる析出が可能であるが、粒子状に析出させることは難しく、柔らかくて扱いが難しい。しかし、上記方法では、インジウム系はんだ微粒子を原料として用いることで、均一な粒子径を有するインジウム系はんだ粒子を容易に製造することができる。また、形成されたはんだ粒子１は、基体６０の凹部６２に収容された状態で取り扱うことができるため、はんだ粒子１を変形させることなく運搬・保管等することができる。さらに、形成されたはんだ粒子１は、基体６０の凹部６２に収容された状態であるため、はんだ粒子を変形させることなく電極と接触させることができる。得られるはんだ粒子の平均粒子径は１～３５μｍであってよく、Ｃ．Ｖ．値は２０％以下であってよい。 According to the preparation step to the fusion step, the solder particles 1 having a uniform size can be formed regardless of the material and shape of the solder fine particles 111. For example, indium-based solder can be precipitated by plating, but it is difficult to precipitate it in the form of particles, and it is soft and difficult to handle. However, in the above method, by using indium-based solder fine particles as a raw material, indium-based solder particles having a uniform particle size can be easily produced. Further, since the formed solder particles 1 can be handled in a state of being housed in the recess 62 of the substrate 60, the solder particles 1 can be transported and stored without being deformed. Further, since the formed solder particles 1 are housed in the recesses 62 of the substrate 60, the solder particles can be brought into contact with the electrodes without being deformed. The average particle size of the obtained solder particles may be 1 to 35 μm, and C.I. V. The value may be 20% or less.
　また、はんだ微粒子１１１は、粒度分布にばらつきが大きくても、形状がいびつであってもよく、凹部６２内に収容することができれば原料として好適に用いることができる。 Further, the solder fine particles 111 may have a large variation in particle size distribution or a distorted shape, and can be suitably used as a raw material if they can be accommodated in the recess 62.
　また、上記方法において、基体６０は、リソグラフィー、機械加工、インプリント等によって凹部６２の形状を自在に設計できる。はんだ粒子１のサイズは凹部６２に収容されるはんだ微粒子１１１の量に依存するため、凹部６２の設計によりはんだ粒子１のサイズを自在に設計できる。 Further, in the above method, the shape of the recess 62 of the substrate 60 can be freely designed by lithography, machining, imprinting, or the like. Since the size of the solder particles 1 depends on the amount of the solder fine particles 111 accommodated in the recess 62, the size of the solder particles 1 can be freely designed by designing the recess 62.
　次に、流動化剤を配置する工程は、はんだ粒子１が形成された凹部６２内に流動化剤を配置する。流動化剤の配置方法としては特に限定されないが、例えば、液状の流動化剤溶液中に基体６０を浸漬して引き上げる方法、液状流動化剤を基体６０上に（特に凹部６２上に）に塗布、滴下する等の方法が挙げられる。さらに、固形の流動化剤の場合は、凹部６２の直径より小さい直径を有する流動化剤を、基体６０の表面に配置し、スキージにより凹部６２内に充填する等の方法が挙げられる。または、ＣＶＤ、蒸着、スパッタ法等によって、流動化剤を配置する方法が挙げられる。凹部６２より溢れた余分な流動化剤は除去してよい。除去の方法としては、例えば、減圧による揮発、スキージ、ふき取り、かきとり、レーザーエッチング、ブラスト等の方法が挙げられる。 Next, in the step of arranging the fluidizing agent, the fluidizing agent is arranged in the recess 62 in which the solder particles 1 are formed. The method of arranging the fluidizing agent is not particularly limited, but for example, a method of immersing the substrate 60 in a liquid fluidizing agent solution and pulling it up, or applying the liquid fluidizing agent on the substrate 60 (particularly on the recess 62). , Dropping and the like. Further, in the case of a solid fluidizing agent, a method of arranging a fluidizing agent having a diameter smaller than the diameter of the recess 62 on the surface of the substrate 60 and filling the recess 62 with a squeegee can be mentioned. Alternatively, a method of arranging the fluidizing agent by CVD, vapor deposition, sputtering, or the like can be mentioned. The excess fluidizing agent overflowing from the recess 62 may be removed. Examples of the removing method include volatilization under reduced pressure, squeegee, wiping, scraping, laser etching, and blasting.
　例えば、液状流動化剤を基体６０上（凹部６２上）に適量滴下し、スキージにより液状流動化剤を広げながら凹部６２内に充填した後、再度スキージにより凹部６２内に充填されなかった余剰な液状流動化剤を除去することができる。スキージで除去しきれない流動化剤は、例えば、無塵クリーンクロス等でふき取ることができる。 For example, an appropriate amount of the liquid fluidizing agent is dropped onto the substrate 60 (on the recess 62), the liquid fluidizing agent is spread in the recess 62 by the squeegee, and then filled in the recess 62. The liquid fluidizing agent can be removed. The fluidizing agent that cannot be completely removed by the squeegee can be wiped off with, for example, a dust-free clean cloth.
　はんだバンプ形成用部材１０の製造方法は、複数の凹部を有する基体、並びにはんだ粒子及び流動化剤を準備する前工程と、凹部に、はんだ粒子及び流動化剤を配置する配置工程と、を備えてもよい。このように、はんだ粒子１を基体６０から一旦取り出し、再度基体の凹部にはんだ粒子１と流動化剤Ｆを再配置して、はんだバンプ形成用部材を作製することができる。この方法であれば、溶融工程ではんだ粒子１にならなかったはんだ微粒子１１１、凹部６２外に存在するはんだ微粒子１１１及びその他の残渣、異物等と、はんだ粒子１とを分離することができる。具体的には、溶融工程を経て、凹部６２内にはんだ粒子１を有する基体６０を、溶剤内に浸漬し、はんだ粒子１を凹部６２から取り出す。はんだ粒子１が取り出された基体６０を溶剤から引きあげた後、フィルター、メッシュ等に溶剤を通すことで、溶剤から異物を除去する。その後、はんだ粒子１を溶剤中で一旦分散させて静置し、沈降分離を行う。沈降分離を行うことで、はんだ粒子１と残渣（例えば、はんだ微粒子１１１及び異物）とを分離して、はんだ粒子１と溶剤の混合物を得る。沈降分離を複数回行い、さらに残渣を除去した後、はんだ粒子１と溶剤の混合物を真空乾燥して、純度の高いはんだ粒子１を得る。配置工程では、このはんだ粒子１を再び、基体６０表面の凹部６２内に再配置する。その後、流動化剤を凹部６２内に配置することができる。または、流動化剤を凹部６２内へ予め配置した後、はんだ粒子１を凹部６２内へ配置してもよい。または、流動化剤とはんだ粒子１を予め混合し、その混合物を凹部６２内へ配置してもよい。はんだ粒子を再配置する基体は、はんだ粒子を作製する際に用いた基体であってもよく、それとは別の基体であってもよい。 The method for manufacturing the solder bump forming member 10 includes a pre-step of preparing a substrate having a plurality of recesses, solder particles and a fluidizing agent, and an arrangement step of arranging the solder particles and the fluidizing agent in the recesses. You may. In this way, the solder particles 1 can be once taken out from the substrate 60, and the solder particles 1 and the fluidizing agent F can be rearranged in the recesses of the substrate again to produce a solder bump forming member. According to this method, the solder particles 1 can be separated from the solder fine particles 111 that did not become the solder particles 1 in the melting step, the solder fine particles 111 existing outside the recess 62, other residues, foreign substances, and the like. Specifically, through the melting step, the substrate 60 having the solder particles 1 in the recess 62 is immersed in the solvent, and the solder particles 1 are taken out from the recess 62. After the substrate 60 from which the solder particles 1 have been taken out is pulled out from the solvent, foreign matter is removed from the solvent by passing the solvent through a filter, a mesh, or the like. Then, the solder particles 1 are once dispersed in a solvent and allowed to stand to perform sedimentation separation. By performing sedimentation separation, the solder particles 1 and the residue (for example, solder fine particles 111 and foreign matter) are separated to obtain a mixture of the solder particles 1 and the solvent. After performing sedimentation separation a plurality of times and further removing the residue, the mixture of the solder particles 1 and the solvent is vacuum-dried to obtain high-purity solder particles 1. In the arranging step, the solder particles 1 are rearranged in the recess 62 on the surface of the substrate 60. After that, the fluidizing agent can be arranged in the recess 62. Alternatively, the solder particles 1 may be arranged in the recess 62 after the fluidizing agent is arranged in the recess 62 in advance. Alternatively, the fluidizing agent and the solder particles 1 may be mixed in advance, and the mixture may be arranged in the recess 62. The substrate on which the solder particles are rearranged may be the substrate used when producing the solder particles, or may be a different substrate.
　なお、はんだ粒子１としては、上述の方法で得られたもの以外にも、アトマイズ法、水アトマイズ法、細線を切断して溶解する方法、精密吐出ヘッドを用いて微小はんだ液滴を作製する方法等の公知の方法で作製したものが利用できる。 As the solder particles 1, in addition to those obtained by the above method, an atomizing method, a water atomizing method, a method of cutting and dissolving fine wires, and a method of producing fine solder droplets using a precision ejection head. Those prepared by a known method such as, etc. can be used.
＜はんだバンプ付き電極基板の製造方法＞
　はんだバンプ付き電極基板の製造方法は、上記はんだバンプ形成用部材、及び複数の電極を有する基板、を準備する準備工程と、はんだバンプ形成用部材の凹部を有する面及び基板の電極を有する面を対向させて接触させる配置工程と、はんだ粒子をはんだ粒子の融点以上の温度に加熱する加熱工程と、を備える。 <Manufacturing method of electrode substrate with solder bumps>
The method for manufacturing an electrode substrate with solder bumps includes a preparatory step for preparing the solder bump forming member and a substrate having a plurality of electrodes, and a surface having a recess of the solder bump forming member and a surface having electrodes of the substrate. It includes an arrangement step of bringing the solder particles into contact with each other and a heating step of heating the solder particles to a temperature equal to or higher than the melting point of the solder particles.
　複数の電極を表面に有する基板（回路部材）の具体例として、ＩＣチップ（半導体チップ）、抵抗体チップ、コンデンサチップ、ドライバーＩＣ等のチップ部品；リジット型のパッケージ基板が挙げられる。これらの回路部材は、回路電極を備えており、多数の回路電極を備えているものが一般的である。複数の電極を表面に有する基板のその他の例として、金属配線を有するフレキシブルテープ基板、フレキシブルプリント配線板、インジウム錫酸化物（ＩＴＯ）が蒸着されたガラス基板等の配線基板が挙げられる。 Specific examples of substrates (circuit members) having a plurality of electrodes on the surface include chip components such as IC chips (semiconductor chips), resistor chips, capacitor chips, and driver ICs; rigid type package substrates. These circuit members are provided with circuit electrodes, and are generally provided with a large number of circuit electrodes. Other examples of substrates having a plurality of electrodes on the surface include wiring substrates such as flexible tape substrates having metal wiring, flexible printed wiring boards, and glass substrates on which indium tin oxide (ITO) is vapor-deposited.
　電極の具体例としては、銅、銅／ニッケル、銅／ニッケル／金、銅／ニッケル／パラジウム、銅／ニッケル／パラジウム／金、銅／ニッケル／金、銅／パラジウム、銅／パラジウム／金、銅／スズ、銅／銀、インジウム錫酸化物等の電極が挙げられる。電極は、無電解めっき又は電解めっき又はスパッタ又は金属箔のエッチングで形成することができる。 Specific examples of the electrodes include copper, copper / nickel, copper / nickel / gold, copper / nickel / palladium, copper / nickel / palladium / gold, copper / nickel / gold, copper / palladium, copper / palladium / gold, and copper. / Tin, copper / silver, indium tin oxide and other electrodes can be mentioned. Electrodes can be formed by electroless plating or electroplating or sputtering or etching of metal foil.
　図６（ａ）及び図６（ｂ）は、はんだバンプ付き電極基板の製造過程の一例を模式的に示す断面図である。図６（ａ）に示す基体６０は、凹部６２のそれぞれに一個のはんだ粒子１及び流動化剤Ｆが収容された状態である。一方、基板２は、複数の電極３を表面に有している。この基体６０の凹部６２の開口側の面に、基板２の電極３側の面を対向させて接触させる。個々の電極３に接触するはんだ粒子１の数は特に制限はなく、１電極に対し１粒子であってよく、１電極に対し複数粒子であってよい。なお、はんだ粒子１と凹部６２間に働く力（例えば、ｖａｎ　ｄｅｒ　Ｗａａｌｓ力のような分子間力）が、はんだ粒子１に加わる重力に比べ大きいため、基体６０の主面を下に向けたとしても、はんだ粒子１は脱落せずに凹部６２内に留まっている。また、はんだ粒子１の少なくとも一部が、凹部６２の底部及び／又は内壁部と接しており、平坦部を有する場合は、はんだ粒子１は凹部６２と密に接しており、脱落しづらい。 6 (a) and 6 (b) are cross-sectional views schematically showing an example of a manufacturing process of an electrode substrate with solder bumps. The substrate 60 shown in FIG. 6A is in a state in which one solder particle 1 and a fluidizing agent F are housed in each of the recesses 62. On the other hand, the substrate 2 has a plurality of electrodes 3 on the surface. The surface on the electrode 3 side of the substrate 2 is brought into contact with the surface of the substrate 60 on the opening side of the recess 62 so as to face each other. The number of solder particles 1 that come into contact with the individual electrodes 3 is not particularly limited, and may be one particle per electrode and may be a plurality of particles per electrode. Since the force acting between the solder particles 1 and the recess 62 (for example, an intermolecular force such as van der Waals force) is larger than the gravity applied to the solder particles 1, it is assumed that the main surface of the substrate 60 is directed downward. However, the solder particles 1 do not fall off and remain in the recess 62. Further, when at least a part of the solder particles 1 is in contact with the bottom portion and / or the inner wall portion of the recess 62 and has a flat portion, the solder particles 1 are in close contact with the recess 62 and are difficult to fall off.
　はんだ粒子と電極が接触している状態で、電極基板及び基体６０の全体をはんだ粒子１の融点よりも高い温度（例えば１３０～２６０℃）に少なくとも加熱することによって、加熱された流動化剤Ｆにより流動し易くなったはんだ粒子１が電極３に接すると共に溶融し、電極３上にはんだバンプが形成される。はんだ粒子１と電極３との接合をより好適に行う観点から、加熱工程において、はんだバンプ形成用部材１０及び基板２を加圧状態で接触させながら、はんだ粒子１をはんだ粒子の融点以上の温度に加熱してよい。加圧状態とは、はんだバンプ形成用部材１０と基板２同士を、図６（ａ）における矢印Ａ，Ｂ方向に３０～６００Ｐａ程度の力で押し付けた状態である。はんだ粒子１は、凹部６２に収容されており、なおかつ電極に対して押し付けられている。そのため、流動化剤Ｆの作用によって流動しても、隣接する凹部６２内のはんだ粒子１同士が混ざりあい難く、所望の電極上にのみ同じサイズのはんだバンプを形成できる。また、隣接する電極をはんだがブリッジしにくく、ショート不良を抑制できる。 The fluidizer F is heated by heating the entire electrode substrate and substrate 60 to a temperature higher than the melting point of the solder particles 1 (for example, 130 to 260 ° C.) while the solder particles and the electrodes are in contact with each other. The solder particles 1 that have become easier to flow come into contact with the electrode 3 and melt to form solder bumps on the electrode 3. From the viewpoint of more preferably joining the solder particles 1 and the electrode 3, in the heating step, the solder particles 1 are brought into contact with the solder bump forming member 10 and the substrate 2 in a pressurized state, and the temperature of the solder particles 1 is equal to or higher than the melting point of the solder particles. May be heated to. The pressurized state is a state in which the solder bump forming member 10 and the substrate 2 are pressed against each other with a force of about 30 to 600 Pa in the directions of arrows A and B in FIG. 6A. The solder particles 1 are housed in the recess 62 and are pressed against the electrodes. Therefore, even if the solder particles 1 flow due to the action of the fluidizing agent F, the solder particles 1 in the adjacent recesses 62 are unlikely to be mixed with each other, and solder bumps of the same size can be formed only on the desired electrodes. In addition, it is difficult for the solder to bridge the adjacent electrodes, and short-circuit defects can be suppressed.
　はんだ粒子１は、大気下では加熱によって急激に酸化が進み、電極３上への濡れ広がりが起こりにくくなるため、加熱時の雰囲気は脱酸素雰囲気が好ましい。例えば、窒素、アルゴンなどの不活性ガス雰囲気、真空雰囲気等であってよい。炉としては、はんだの接合工程に一般に使われるリフロー炉（窒素雰囲気下）、真空リフロー炉が利用でき、窒素雰囲気下のコンベアー型リフロー炉、バッチ式（チャンバー式）リフロー炉等が利用できる。これらのリフロー炉を利用する時に、はんだが溶融した後に真空にする工程が加えられると、はんだ内の気泡（ボイド）が除去できる。さらに、生産性向上の観点から、ラミネータを利用することもできる。ローラー式のラミネータであれば、加圧と加熱を同時加えることができる。さらに、真空加圧式ラミネータを利用することもできる。真空加圧式ラミネータは、チャンバー内を真空下にでき、加圧及び加熱が同時にできるため、電極３上にはんだバンプを転写しやすく好ましい。また、キャリアフィルムによる連続的な搬送が可能なため、生産性が高くできる利点もある。 The solder particles 1 are rapidly oxidized by heating in the atmosphere, and it is difficult for the solder particles 1 to spread wet on the electrode 3, so that the atmosphere at the time of heating is preferably a deoxidized atmosphere. For example, it may be an inert gas atmosphere such as nitrogen or argon, a vacuum atmosphere, or the like. As the furnace, a reflow furnace (under a nitrogen atmosphere) and a vacuum reflow furnace generally used in the solder joining process can be used, and a conveyor type reflow furnace under a nitrogen atmosphere, a batch type (chamber type) reflow furnace and the like can be used. When using these reflow furnaces, if a step of creating a vacuum after the solder is melted is added, air bubbles (voids) in the solder can be removed. Further, from the viewpoint of improving productivity, a laminator can also be used. If it is a roller type laminator, pressurization and heating can be applied at the same time. Further, a vacuum pressurizing laminator can also be used. The vacuum pressurizing laminator is preferable because the inside of the chamber can be evacuated and pressurization and heating can be performed at the same time, so that the solder bumps can be easily transferred onto the electrode 3. In addition, since continuous transportation by the carrier film is possible, there is an advantage that productivity can be increased.
　はんだ粒子１は、酸化被膜の影響で融点以上の温度で加熱しても溶融しなかったり、濡れ拡がらなかったりする場合がある。このため、はんだ粒子１を還元雰囲気下に晒し、はんだ粒子１の表面酸化被膜を除去した後に、はんだ粒子１の融点以上の温度に加熱することで、はんだ粒子１を溶融させることができる。また、はんだ粒子１の溶融は、還元雰囲気下で行うことが好ましい。はんだ粒子１をはんだ粒子１の融点以上に加熱し、かつ還元雰囲気とすることで、はんだ粒子１の表面の酸化被膜が還元され、さらに電極表面の酸化被膜が還元され、はんだ粒子１の溶融、濡れ拡がりが効率的に進行し易くなる。すなわち、はんだバンプ付き電極基板の製造方法は、配置工程の前に、あるいは配置工程の後であって加熱工程の前に、はんだ粒子（及び／又は電極）を還元雰囲気に晒す還元工程を更に備えてよい。また、はんだバンプ付き電極基板の製造方法の加熱工程において、還元雰囲気下ではんだ粒子をはんだ粒子の融点以上の温度に加熱してよい。電極上にはんだバンプを形成する加熱工程では、電極とはんだバンプ形成用部材の開口部面を（必要に応じ加圧状態で）密着させることで、電極上にのみはんだバンプが形成され、隣接電極間のはんだによるブリッジが抑制され易い。 Solder particles 1 may not melt or spread even when heated at a temperature higher than the melting point due to the influence of the oxide film. Therefore, the solder particles 1 can be melted by exposing the solder particles 1 to a reducing atmosphere, removing the surface oxide film of the solder particles 1, and then heating the solder particles 1 to a temperature equal to or higher than the melting point of the solder particles 1. Further, it is preferable that the solder particles 1 are melted in a reducing atmosphere. By heating the solder particles 1 to a temperature equal to or higher than the melting point of the solder particles 1 and creating a reducing atmosphere, the oxide film on the surface of the solder particles 1 is reduced, and the oxide film on the electrode surface is further reduced to melt the solder particles 1. Wetting and spreading can proceed efficiently. That is, the method for manufacturing an electrode substrate with solder bumps further includes a reduction step of exposing the solder particles (and / or electrodes) to a reducing atmosphere before the placement step or after the placement step and before the heating step. It's okay. Further, in the heating step of the method for manufacturing an electrode substrate with solder bumps, the solder particles may be heated to a temperature equal to or higher than the melting point of the solder particles in a reducing atmosphere. In the heating process of forming solder bumps on the electrodes, the electrodes and the opening surfaces of the solder bump forming members are brought into close contact with each other (under pressure if necessary), so that the solder bumps are formed only on the electrodes and the adjacent electrodes. Bridges due to solder between them are easily suppressed.
　還元雰囲気の詳細については、はんだバンプ形成用部材の製造方法の記載を適宜参照することができる。 For details of the reducing atmosphere, the description of the manufacturing method of the solder bump forming member can be referred to as appropriate.
　加熱工程後、全体を冷却することで、電極３上と、はんだ粒子１が溶融して形成されたはんだバンプ１Ａ同士が固着され、両者が電気的に接続される。はんだバンプ付き電極基板の製造方法は、加熱工程の後に、はんだバンプ形成用部材を基板から除去する除去工程を更に備えてよい。電極３上にはんだバンプ１Ａが形成された後は、はんだバンプ形成用部材１０を基板２から除去することで（除去工程）、はんだバンプ付き電極基板２０を得ることができる。図６（ｂ）は、このようにして得られるはんだバンプ付き電極基板２０の模式図である。 After the heating step, by cooling the whole, the solder bumps 1A formed by melting the solder particles 1 are fixed to each other on the electrode 3, and both are electrically connected. The method for manufacturing an electrode substrate with solder bumps may further include a removal step of removing the solder bump forming member from the substrate after the heating step. After the solder bump 1A is formed on the electrode 3, the solder bump forming member 10 is removed from the substrate 2 (removal step) to obtain the electrode substrate 20 with solder bumps. FIG. 6B is a schematic view of the electrode substrate 20 with solder bumps thus obtained.
　得られたはんだバンプ付き電極基板２０上には、凹部６２から脱離したものの電極３との接合に供されないはんだ粒子１が存在し得る。そのため、はんだバンプ付き電極基板の製造方法は、除去工程の後に、電極に結合していないはんだ粒子１を除去する洗浄工程を更に備えてよい。洗浄方法としては圧縮空気を吹き付ける、不織布又は繊維の束で基板表面を擦る、等の方法が挙げられる。なお、はんだバンプ付き電極基板２０上に残渣として流動化剤Ｆが存在する場合、洗浄工程により当該流動化剤も除去することができる。洗浄工程では、流動化剤Ｆが溶解し易い溶液を利用することができる。 On the obtained electrode substrate 20 with solder bumps, there may be solder particles 1 that have been separated from the recess 62 but are not used for joining with the electrode 3. Therefore, the method for manufacturing the electrode substrate with solder bumps may further include a cleaning step of removing the solder particles 1 not bonded to the electrode after the removing step. Examples of the cleaning method include blowing compressed air, rubbing the surface of the substrate with a non-woven fabric or a bundle of fibers, and the like. When the fluidizing agent F is present as a residue on the electrode substrate 20 with solder bumps, the fluidizing agent F can also be removed by the cleaning step. In the washing step, a solution in which the fluidizing agent F is easily dissolved can be used.
　はんだバンプ付き電極基板の製造方法によれば、基板２、電極３及びはんだバンプ１Ａをこの順に備える、はんだバンプ付き電極基板２０を得ることができる。 According to the method for manufacturing an electrode substrate with solder bumps, it is possible to obtain an electrode substrate 20 with solder bumps having a substrate 2, an electrode 3, and a solder bump 1A in this order.
＜接続構造体の製造方法＞
　図７（ａ）及び図７（ｂ）は、接続構造体の製造過程の一例を模式的に示す断面図である。図７（ａ）及び図７（ｂ）を参照しながら、接続構造体の製造方法について説明する。まず、図６（ｂ）に示すはんだバンプ付き電極基板２０を予め準備する。また、複数の他の電極５を表面に有する他の基板４を準備する。そして、両者を、はんだバンプ１Ａと他の電極５とが対向するように配置する。その後、これらの部材の積層体の厚さ方向（図７（ａ）に示す矢印Ａ及び矢印Ｂの方向）に加圧する。加圧する際に全体をはんだバンプ１Ａの融点よりも高い温度（例えば１３０～２６０℃）に少なくとも加熱することによって、電極３及び他の電極５の間においてはんだバンプ１Ａが溶融する。その後、全体を冷却することで、電極３及び他の電極５の間においてはんだ層１Ｂが形成され、電極間が電気的に接続される。はんだバンプ１Ａ及び電極５の酸化を抑制するため、酸素を遮断した雰囲気で加熱することが好ましい。例えば、窒素などの不活性ガス雰囲気下での加熱が好ましい。具体的には、真空リフロー炉、窒素リフロー炉等が利用できる。 <Manufacturing method of connection structure>
7 (a) and 7 (b) are cross-sectional views schematically showing an example of a manufacturing process of the connection structure. A method of manufacturing the connection structure will be described with reference to FIGS. 7 (a) and 7 (b). First, the electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance. Further, another substrate 4 having a plurality of other electrodes 5 on the surface is prepared. Then, both are arranged so that the solder bump 1A and the other electrode 5 face each other. Then, pressure is applied in the thickness direction of the laminated body of these members (directions of arrows A and B shown in FIG. 7A). By heating the whole to a temperature higher than the melting point of the solder bump 1A (for example, 130 to 260 ° C.) when pressurizing, the solder bump 1A melts between the electrode 3 and the other electrodes 5. After that, by cooling the whole, a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other. In order to suppress the oxidation of the solder bump 1A and the electrode 5, it is preferable to heat in an atmosphere in which oxygen is blocked. For example, heating in an atmosphere of an inert gas such as nitrogen is preferable. Specifically, a vacuum reflow furnace, a nitrogen reflow furnace, or the like can be used.
　さらに、加熱によってはんだバンプ１Ａを溶解して、対向する電極３と電極５をより好適に接合するために、還元雰囲気下で加熱することが好ましい。還元雰囲気とするためには、水素ガス、水素ラジカル、ギ酸などが利用できる。具体的には、水素還元炉、水素リフロー炉、水素ラジカル炉、ギ酸炉、これらの真空炉、連続炉、コンベアー炉が利用できる。還元雰囲気にすることで、はんだバンプ１Ａ表面の酸化被膜及び電極５表面の酸化被膜を還元、除去することができるため、はんだバンプ１Ａが電極５に濡れ広がり易くなり、はんだ層１Ｂを介して電極３及び電極５間でより安定した接合が達成される。 Further, it is preferable to heat the solder bump 1A in a reducing atmosphere in order to melt the solder bump 1A by heating and more preferably join the opposing electrodes 3 and 5 to each other. Hydrogen gas, hydrogen radicals, formic acid and the like can be used to create a reducing atmosphere. Specifically, a hydrogen reduction furnace, a hydrogen reflow furnace, a hydrogen radical furnace, a formic acid furnace, these vacuum furnaces, a continuous furnace, and a conveyor furnace can be used. By creating a reducing atmosphere, the oxide film on the surface of the solder bump 1A and the oxide film on the surface of the electrode 5 can be reduced and removed, so that the solder bump 1A easily wets and spreads on the electrode 5, and the electrode is passed through the solder layer 1B. A more stable bond is achieved between 3 and the electrode 5.
　さらに、安定した接続を実現するために、圧力を加えてもよい。図６（ｂ）に示すはんだバンプ付き電極基板２０を予め準備する。また、複数の他の電極５を表面に有する他の基板４を準備する。そして、両者を、はんだバンプ１Ａと他の電極５とが対向するように配置する。その後、これらの部材の積層体の厚さ方向（図７（ａ）に示す矢印Ａ及び矢印Ｂの方向）に加圧する。加圧する際に全体をはんだバンプ１Ａの融点よりも高い温度（例えば１３０～２６０℃）に少なくとも加熱することによって、電極３及び他の電極５の間においてはんだバンプ１Ａが溶融する。その後、全体を冷却することで、電極３及び他の電極５の間においてはんだ層１Ｂが形成され、電極間が電気的に接続される。この場合も、はんだバンプ１Ａ、電極５及び電極３表面の酸化を抑制するため、真空下、窒素など不活性ガス雰囲気下、還元雰囲気下で上記工程を行うことが好ましい。還元雰囲気にする方法としては、前述の水素ガス、水素ラジカル、ギ酸などが挙げられる。具体的には、水素還元炉、水素リフロー炉、水素ラジカル炉、ギ酸炉、これらの真空炉、連続炉、コンベアー炉などが利用できる。 Furthermore, pressure may be applied to achieve a stable connection. The electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance. Further, another substrate 4 having a plurality of other electrodes 5 on the surface is prepared. Then, both are arranged so that the solder bump 1A and the other electrode 5 face each other. Then, pressure is applied in the thickness direction of the laminated body of these members (directions of arrows A and B shown in FIG. 7A). By heating the whole to a temperature higher than the melting point of the solder bump 1A (for example, 130 to 260 ° C.) when pressurizing, the solder bump 1A melts between the electrode 3 and the other electrodes 5. After that, by cooling the whole, a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other. Also in this case, in order to suppress the oxidation of the surfaces of the solder bump 1A, the electrode 5, and the electrode 3, it is preferable to perform the above steps in a vacuum, an atmosphere of an inert gas such as nitrogen, and a reducing atmosphere. Examples of the method for creating a reducing atmosphere include the above-mentioned hydrogen gas, hydrogen radicals, formic acid and the like. Specifically, a hydrogen reduction furnace, a hydrogen reflow furnace, a hydrogen radical furnace, a formic acid furnace, these vacuum furnaces, a continuous furnace, a conveyor furnace, and the like can be used.
　還元雰囲気にする方法としては、還元作用がある材料を利用することができる。例えば、フラックス材料又はフラックス成分を含有する材料を、はんだバンプ１Ａ、電極５及び電極３近傍に配置することができる。フラックス材料及びフラックス成分を含有する材料を含有するペースト、フィルム等を用いることができる。まず、図６（ｂ）に示すはんだバンプ付き電極基板２０を予め準備する。電極基板２０のはんだバンプ１Ａが形成された面全体、又ははんだバンプ１Ａ及びはんだバンプ１Ａを含む電極３近傍に、フラックス材料又はフラックス成分を含有するペーストを配置する。また、複数の他の電極５を表面に有する他の基板４を準備する。そして、両者を、はんだバンプ１Ａと他の電極５とが対向するように配置する。その後、はんだバンプ１Ａと他の電極５とを、例えばフラックス材料又はフラックス成分を含有するペーストを介して接触させたまま、はんだバンプ１Ａの融点よりも高い温度（例えば、１３０℃～２６０℃）に少なくとも加熱することによって、電極３及び他の電極５の間においてはんだバンプ１Ａが溶融する。その後、全体を冷却することで、電極３及び他の電極５の間においてはんだ層１Ｂが形成され、電極間が電気的に接続される。その後、フラックス成分を洗浄除去すると、フラックス残渣による、はんだ層１Ｂ、電極３及び電極５の腐食が抑制できる。 As a method of creating a reducing atmosphere, a material having a reducing action can be used. For example, a flux material or a material containing a flux component can be arranged in the vicinity of the solder bump 1A, the electrode 5, and the electrode 3. A paste, a film or the like containing a flux material and a material containing a flux component can be used. First, the electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance. A flux material or a paste containing a flux component is arranged on the entire surface of the electrode substrate 20 on which the solder bumps 1A are formed, or in the vicinity of the electrode 3 including the solder bumps 1A and the solder bumps 1A. Further, another substrate 4 having a plurality of other electrodes 5 on the surface is prepared. Then, both are arranged so that the solder bump 1A and the other electrode 5 face each other. After that, the solder bump 1A and the other electrode 5 are brought into contact with each other through, for example, a flux material or a paste containing a flux component, and brought to a temperature higher than the melting point of the solder bump 1A (for example, 130 ° C. to 260 ° C.). At least by heating, the solder bump 1A melts between the electrode 3 and the other electrodes 5. After that, by cooling the whole, a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other. After that, when the flux component is washed and removed, corrosion of the solder layer 1B, the electrode 3 and the electrode 5 due to the flux residue can be suppressed.
　他の方法としては、図６（ｂ）に示すはんだバンプ付き電極基板２０を予め準備する。また、複数の他の電極５を表面に有する他の基板４を準備し、基板４の電極５を有する面全体、又は電極５の表面近傍にフラックス材料又はフラックス成分を含有するペーストを配置する。そして、両者を、はんだバンプ１Ａと他の電極５とが対向するように配置する。その後、はんだバンプ１Ａと他の電極５とを、例えばフラックス材料及びフラックス成分を含有するペーストを介して接触させたまま、はんだバンプ１Ａの融点よりも高い温度（例えば、１３０℃～２６０℃）に少なくとも加熱することによって、電極３及び他の電極５の間においてはんだバンプ１Ａが溶融する。その後、全体を冷却することで、電極３及び他の電極５の間においてはんだ層１Ｂが形成され、電極間が電気的に接続される。 As another method, the electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance. Further, another substrate 4 having a plurality of other electrodes 5 on the surface is prepared, and a flux material or a paste containing a flux component is arranged on the entire surface of the substrate 4 having the electrodes 5 or near the surface of the electrodes 5. Then, both are arranged so that the solder bump 1A and the other electrode 5 face each other. After that, the solder bump 1A and the other electrode 5 are brought into contact with each other via, for example, a flux material and a paste containing a flux component, and brought to a temperature higher than the melting point of the solder bump 1A (for example, 130 ° C. to 260 ° C.). At least by heating, the solder bump 1A melts between the electrode 3 and the other electrodes 5. After that, by cooling the whole, a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other.
　また、フラックス成分を含有するフィルムを用いることもできる。図６（ｂ）に示すはんだバンプ付き電極基板２０を予め準備する。電極基板２０のはんだバンプ１Ａが形成された面側にフラックス成分を含有するフィルムを配置する。また、複数の他の電極５を表面に有する他の基板４を準備する。そして、両者を、はんだバンプ１Ａと他の電極５とが対向するように配置する。その後、はんだバンプ１Ａと他の電極５とを、フラックス成分を含有するフィルムを介して接触させたまま、または、対向する電極３及び電極５間に圧力を加え、当該間からフラックス成分を含有するフィルムを押しのけるようにして、はんだバンプ１Ａと電極５を接触させた状態で、はんだバンプ１Ａの融点よりも高い温度（例えば、１３０℃～２６０℃）に少なくとも加熱することによって、電極３及び他の電極５の間においてはんだバンプ１Ａが溶融する。その後、全体を冷却することで、電極３及び他の電極５の間においてはんだ層１Ｂが形成され、電極間が電気的に接続される。 It is also possible to use a film containing a flux component. The electrode substrate 20 with solder bumps shown in FIG. 6B is prepared in advance. A film containing a flux component is arranged on the surface side of the electrode substrate 20 on which the solder bumps 1A are formed. Further, another substrate 4 having a plurality of other electrodes 5 on the surface is prepared. Then, both are arranged so that the solder bump 1A and the other electrode 5 face each other. After that, the solder bump 1A and the other electrode 5 are kept in contact with each other via a film containing a flux component, or a pressure is applied between the opposing electrodes 3 and 5 to contain the flux component between them. The electrode 3 and other parts are heated by at least heating to a temperature higher than the melting point of the solder bump 1A (for example, 130 ° C. to 260 ° C.) in a state where the solder bump 1A and the electrode 5 are in contact with each other so as to push the film away. The solder bump 1A melts between the electrodes 5. After that, by cooling the whole, a solder layer 1B is formed between the electrode 3 and the other electrodes 5, and the electrodes are electrically connected to each other.
　フラックス成分を含有するペースト及びフィルムは、熱硬化性材料を含有していてもよい。これにより、はんだバンプ１Ａの溶解と同時に、熱硬化性成分が硬化して、電極基板２０と基板４を固定することができる。熱硬化性材料の硬化は、はんだバンプ１Ａの溶解加熱とは別に、後工程で再度加熱することで実施してもよい。また、フラックス成分を含有するフィルムを、予め基板４の電極５が形成された面側に配置して置いてもよい。フラックス成分を含有するフィルムをはんだバンプ１Ａ側に配置するか、電極５を有する基板４側に配置するかの配置位置の選択は、電極の形状、はんだバンプ１Ａの形状及びサイズ、接合工程上の都合等に合わせ、適宜選択できる。 The paste and film containing the flux component may contain a thermosetting material. As a result, the thermosetting component is cured at the same time as the solder bump 1A is melted, and the electrode substrate 20 and the substrate 4 can be fixed. The curing of the thermosetting material may be carried out by heating again in a subsequent step separately from the melting and heating of the solder bump 1A. Further, the film containing the flux component may be placed on the surface side of the substrate 4 on which the electrode 5 is formed in advance. The selection of the placement position of the film containing the flux component on the solder bump 1A side or the substrate 4 side having the electrode 5 depends on the shape of the electrode, the shape and size of the solder bump 1A, and the joining process. It can be selected as appropriate according to convenience.
　はんだバンプ１Ａを溶解するための加熱方法としては、真空下では、例えばリフロー炉内の加熱板を加熱して、加熱板に接した基板２及び基板４を介してはんだバンプ１Ａに伝える方法、赤外線などの放射を用いる方法がある。また、前述の加熱板及び赤外線を用いる加熱方法に加えて、又は併用して、加熱された気体及びガスを介してはんだバンプ１Ａを加熱する方法が利用できる。具体的には、不活性ガス及び窒素、水素、水素ラジカル、ギ酸を加熱することで、はんだバンプ１Ａを加熱することができる。フラックス材料及びフラックス成分は、コハク酸、グルタル酸、アジピン酸、ピメリン酸、スベリン酸、安息香酸、及びリンゴ酸からなる群より選択される少なくとも一種を含んでよい。 As a heating method for melting the solder bump 1A, under vacuum, for example, a method of heating a heating plate in a reflow furnace and transmitting it to the solder bump 1A via a substrate 2 and a substrate 4 in contact with the heating plate, infrared rays. There is a method using radiation such as. Further, in addition to or in combination with the above-mentioned heating method using a heating plate and infrared rays, a method of heating the solder bump 1A via the heated gas and gas can be used. Specifically, the solder bump 1A can be heated by heating the inert gas, nitrogen, hydrogen, hydrogen radicals, and formic acid. The flux material and the flux component may include at least one selected from the group consisting of succinic acid, glutaric acid, adipic acid, pimelic acid, suberic acid, benzoic acid, and malic acid.
　他の方法としては、マイクロ波等の電磁波を利用する方法が挙げられる。例えば、電極３、電極５及びはんだバンプ１Ａの成分が加熱される特定の電磁波を外部から印加することができる。例えば、基板４及び基板２が樹脂基板である場合、基板４及び基板２の外側から特定の電磁波を照射すると、基板４及び基板２を電磁波が透過し、電極３及びはんだバンプ１Ａ又は電極５が電磁波により加熱される。この方法の場合、接合したい部分を選択的に加熱することができるため、余計な熱履歴が残らない利点がある。例えば、基板２及び基板４が耐熱性の低い材料であっても、はんだバンプ１Ａを溶解して電極３と電極５を確実に接合することができる。また、接合する系全体に熱履歴が残りにくいため、接合後の反り及び分解を抑制し易い利点がある。また、マイクロ波を利用する場合、前述のように加熱板、赤外線、加熱ガス等を利用するより、短時間ではんだバンプ１Ａを溶解することができるため、接合したい系全体への熱履歴を少なくできる利点があり、前述の効果が得られ易い。更に、マイクロ波を用いると、接合したい又は溶解させたい電極３、はんだバンプ１Ａ及び電極５の部分のみ、局所的に加熱することができる。従って、系全体を加熱する必要が無く、耐熱性の低い材料、他の電子部品など熱を加えたくないものが電極３及び電極５の近傍にあっても、はんだバンプ１Ａを溶解して接合することができる。 As another method, there is a method of using electromagnetic waves such as microwaves. For example, a specific electromagnetic wave that heats the components of the electrode 3, the electrode 5, and the solder bump 1A can be applied from the outside. For example, when the substrate 4 and the substrate 2 are resin substrates, when a specific electromagnetic wave is irradiated from the outside of the substrate 4 and the substrate 2, the electromagnetic wave is transmitted through the substrate 4 and the substrate 2, and the electrode 3 and the solder bump 1A or the electrode 5 are formed. It is heated by electromagnetic waves. In the case of this method, since the portion to be joined can be selectively heated, there is an advantage that an extra heat history is not left. For example, even if the substrate 2 and the substrate 4 are made of materials having low heat resistance, the solder bump 1A can be melted and the electrode 3 and the electrode 5 can be reliably joined. Further, since the heat history is unlikely to remain in the entire system to be joined, there is an advantage that warpage and decomposition after joining can be easily suppressed. Further, when microwaves are used, the solder bump 1A can be melted in a shorter time than using a heating plate, infrared rays, heating gas, etc. as described above, so that the heat history to the entire system to be joined is reduced. There is an advantage that the above-mentioned effect can be easily obtained. Further, when microwaves are used, only the portions of the electrode 3, the solder bump 1A and the electrode 5 to be joined or melted can be locally heated. Therefore, it is not necessary to heat the entire system, and even if there are materials with low heat resistance, other electronic components, etc. that do not want to be heated in the vicinity of the electrodes 3 and 5, the solder bumps 1A are melted and joined. be able to.
　他の方法としては、超音波を利用する方法が挙げられる。例えば、超音波振動子を基板２の電極３と反対側に配置し、超音波を印加すると、超音波の振動エネルギーによりはんだバンプ１Ａが溶解する。これにより、電極３と、予め電極３の対向位置に配置してあった電極５とが、はんだ層１Ｂを介して接合される。超音波による接合は、短時間ではんだバンプ１Ａを溶解することができるため、基板２及び基板４全体へ熱を掛ける必要が無く、基板２及び基板４が耐熱性の低い材料でも、確実に電極３と電極５を接合することができる。 Another method is to use ultrasonic waves. For example, when an ultrasonic vibrator is arranged on the side opposite to the electrode 3 of the substrate 2 and ultrasonic waves are applied, the solder bump 1A is melted by the vibration energy of the ultrasonic waves. As a result, the electrode 3 and the electrode 5 previously arranged at the opposite positions of the electrode 3 are joined via the solder layer 1B. Since the solder bump 1A can be melted in a short time in the bonding by ultrasonic waves, it is not necessary to apply heat to the entire substrate 2 and the substrate 4, and even if the substrate 2 and the substrate 4 are made of a material having low heat resistance, the electrodes are surely electrode. 3 and the electrode 5 can be joined.
　図７（ｂ）は、このようにして得られる接続構造体３０の模式図である。すなわち、図７（ｂ）は、基板２が有する電極３と、他の基板４が有する他の電極５が、融着して形成されたはんだ層１Ｂを介して接続された状態を模式的に示したものである。本明細書において「融着」とは、電極の少なくとも一部が熱によって融解したはんだ（はんだバンプ１Ａ）によって接合され、その後、これが固化する工程を経ることによって電極の表面にはんだが接合された状態を意味する。接続構造体３０は、基板及びその表面に複数の電極を備える第一の回路部材と、他の基板及びその表面に複数の他の電極を備える第二の回路部材と、複数の電極及び複数の他の電極間にはんだ層と、を備えるものであるということができる。なお、第一の回路部材と第二の回路部材との間の空間には、例えばエポキシ樹脂を主剤とするアンダーフィル材を充填することができる。 FIG. 7B is a schematic view of the connection structure 30 obtained in this way. That is, FIG. 7B schematically shows a state in which the electrode 3 of the substrate 2 and the other electrode 5 of the other substrate 4 are connected via a solder layer 1B formed by fusion. It is shown. As used herein, the term "fused" means that at least a part of the electrode is joined by a solder (solder bump 1A) melted by heat, and then the solder is joined to the surface of the electrode through a step of solidifying the solder. Means the state. The connection structure 30 includes a first circuit member having a plurality of electrodes on the substrate and its surface, a second circuit member having a plurality of other electrodes on the other substrate and its surface, and a plurality of electrodes and a plurality of electrodes. It can be said that a solder layer is provided between the other electrodes. The space between the first circuit member and the second circuit member can be filled with, for example, an underfill material containing an epoxy resin as a main agent.
　接続構造体の適用対象としては、半導体メモリー、半導体ロジックチップなどの接続部、半導体パッケージの一次実装及び二次実装の接続部、ＣＭＯＳ画像素子、レーザー素子、ＬＥＤ発光素子などの接合体、それらを用いたカメラ、センサー、液晶ディスプレイ、パーソナルコンピュータ、携帯電話、スマートフォン、タブレット等のデバイスが挙げられる。 Applications of the connection structure include connection parts such as semiconductor memory and semiconductor logic chips, connection parts for primary and secondary mounting of semiconductor packages, and junctions such as CMOS image elements, laser elements, and LED light emitting elements. Examples include devices such as cameras, sensors, liquid crystal displays, personal computers, mobile phones, smartphones, and tablets used.
　以上、本発明の好適な実施形態について説明したが、本発明は上記実施形態に限定されるものではない。 Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment.
　以下、実施例によって本発明を更に詳細に説明するが、本発明はこれらの実施例に限定されるものではない。 Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited to these Examples.
＜はんだバンプ形成用フィルムの作製＞
（作製例１）
工程ａ１：はんだ微粒子の分級
　Ｓｎ－Ｂｉはんだ微粒子（５Ｎ　Ｐｌｕｓ社製、融点１３９℃、Ｔｙｐｅ８）１００ｇを、蒸留水に浸漬し、超音波分散させた後、静置し、上澄みに浮遊するはんだ微粒子を回収した。この操作を繰り返して、１０ｇのはんだ微粒子を回収した。得られたはんだ微粒子の平均粒子径は１．０μｍ、Ｃ．Ｖ．値は４２％であった。
工程ｂ１：基体への配置
　表１に示す、開口径２．３μｍφ、底部径２．０μｍφ、深さ２．０μｍ（底部径２．０μｍφは、開口を上面からみると、開口径２．３μｍφの中央に位置する）の凹部を複数有する基体（ポリイミドフィルム、厚さ１００μｍ）を準備した。複数の凹部は、１．０μｍの間隔で規則的に配列させた。工程ａで得られたはんだ微粒子（平均粒子径１．０μｍ、Ｃ．Ｖ．値４２％）を基体の凹部に配置した。なお、基体の凹部が形成された面側を微粘着ローラーでこすることで余分なはんだ微粒子を取り除き、凹部内のみにはんだ微粒子が配置された基体を得た。
工程ｃ１：はんだ粒子の形成
　工程ｂ１で凹部にはんだ微粒子が配置された基体を、水素還元炉（神港精機株式会社製、真空半田付装置）に入れ、真空引き後、水素ガスを炉内に導入して炉内を水素で満たした。その後、炉内を２８０℃で２０分保った後、再び真空に引き、窒素を導入して大気圧に戻してから炉内の温度を室温まで下げることにより、凹部の内部にはんだ粒子を形成した。 <Manufacturing of film for forming solder bumps>
(Production Example 1)
Step a1: Classification of solder fine particles 100 g of Sn-Bi solder fine particles (manufactured by 5N Plus, melting point 139 ° C., Type 8) are immersed in distilled water, ultrasonically dispersed, then allowed to stand, and the solder fine particles float in the supernatant. Was recovered. This operation was repeated to recover 10 g of solder fine particles. The average particle size of the obtained solder fine particles was 1.0 μm, and C.I. V. The value was 42%.
Step b1: Arrangement on the substrate The opening diameter is 2.3 μmφ, the bottom diameter is 2.0 μmφ, and the depth is 2.0 μm (the bottom diameter of 2.0 μmφ is 2.3 μmφ when the opening is viewed from the top surface, as shown in Table 1. A substrate (polyimide film, thickness 100 μm) having a plurality of recesses (located in the center) was prepared. The plurality of recesses were regularly arranged at intervals of 1.0 μm. The solder fine particles (average particle diameter 1.0 μm, CV value 42%) obtained in step a were placed in the recesses of the substrate. By rubbing the surface side of the substrate on which the recesses were formed with a fine adhesive roller, excess solder fine particles were removed, and a substrate in which the solder fine particles were arranged only in the recesses was obtained.
Step c1: Formation of solder particles The substrate in which the solder fine particles are arranged in the recesses in step b1 is placed in a hydrogen reduction furnace (Vacuum soldering device manufactured by Shinko Seiki Co., Ltd.), evacuated, and then hydrogen gas is put into the furnace. It was introduced and the inside of the furnace was filled with hydrogen. Then, after keeping the inside of the furnace at 280 ° C. for 20 minutes, the inside of the furnace was evacuated again, nitrogen was introduced to return the pressure to atmospheric pressure, and then the temperature inside the furnace was lowered to room temperature to form solder particles inside the recesses. ..
＜はんだ粒子の評価＞
　工程ｃ１を経て得た基体の一部を、ＳＥＭ観察用台座表面に固定し、表面に白金スパッタを施した。ＳＥＭにて、はんだ粒子の直径を３００個測定し、平均粒子径及びＣ．Ｖ．値を算出した。結果を表２に示す。また、工程ｃ１を経て得た基体の一部の表面形状を、レーザー顕微鏡（オリンパス株式会社製、ＬＥＸＴ　ＯＬＳ５０００―ＳＡＦ）を用いて測定し、基体表面からのはんだ粒子の高さを測定し、３００個の平均値を算出した。結果を表２に示す。 <Evaluation of solder particles>
A part of the substrate obtained through the step c1 was fixed to the surface of the pedestal for SEM observation, and the surface was subjected to platinum sputtering. The diameter of 300 solder particles was measured by SEM, and the average particle diameter and C.I. V. The value was calculated. The results are shown in Table 2. Further, the surface shape of a part of the substrate obtained through the step c1 was measured using a laser microscope (LEXT OLS5000-SAF manufactured by Olympus Corporation), and the height of the solder particles from the surface of the substrate was measured to be 300. The average value of the pieces was calculated. The results are shown in Table 2.
工程ｄ１：フラックスの配置
　ジヒドロターピネオール９０質量部にフラックス成分としてアジピン酸２０質量部を入れ、混合し、流動相とした。この流動相を工程ｃ１で得られたはんだ粒子が配置された凹部内に配置した。その後、基体の凹部が形成された面側をゴム製スキージで擦って、凹部に充填されなかった余分な流動相（フラックス成分）を取り除いた。その後、さらに無塵クリーンクロスで基材表面を拭きあげて、はんだバンプ形成用フィルムを作製した。 Step d1: Arrangement of flux 20 parts by mass of adipic acid as a flux component was added to 90 parts by mass of dihydroterpineol and mixed to prepare a fluid phase. This flowing phase was placed in the recess in which the solder particles obtained in step c1 were placed. Then, the surface side on which the concave portion of the substrate was formed was rubbed with a rubber squeegee to remove an excess fluid phase (flux component) that was not filled in the concave portion. Then, the surface of the base material was further wiped with a dust-free clean cloth to prepare a film for forming solder bumps.
（作製例２～６）
　凹部サイズ等を表１に記載のとおり変更したこと以外は、作製例１と同様にしてはんだバンプ形成用フィルムを作製し、評価した。結果を表２に示す。 (Production Examples 2 to 6)
A film for forming solder bumps was produced and evaluated in the same manner as in Production Example 1 except that the recess size and the like were changed as shown in Table 1. The results are shown in Table 2.
（作製例７）
　工程ｃ１に代えて、以下の工程ｃ２を行ったこと以外は、作製例１と同様にしてはんだバンプ形成用フィルムを作製し、評価した。結果を表２に示す。
工程ｃ２：はんだ粒子の形成
　工程ｂ１で凹部にはんだ微粒子が配置された基体を、水素ラジカル還元炉（神港精機株式会社製、プラズマリフロー装置）に投入し、真空引き後、水素ガスを炉内に導入して、炉内を水素ガスで満たした。その後、炉内を１２０℃に調整し、５分間水素ラジカルを照射した。その後、真空引きにて炉内の水素ガスを除去し、１７０℃まで加熱した後、窒素を炉内に導入して大気圧に戻してから炉内の温度を室温まで下げることにより、はんだ粒子を形成した。 (Production Example 7)
A film for forming solder bumps was produced and evaluated in the same manner as in Production Example 1 except that the following step c2 was performed instead of step c1. The results are shown in Table 2.
Step c2: Formation of solder particles The substrate in which the solder fine particles were arranged in the recesses in step b1 was put into a hydrogen radical reduction furnace (Plasma reflow device manufactured by Shinko Seiki Co., Ltd.), evacuated, and then hydrogen gas was introduced into the furnace. The inside of the furnace was filled with hydrogen gas. Then, the inside of the furnace was adjusted to 120 ° C. and irradiated with hydrogen radicals for 5 minutes. After that, the hydrogen gas in the furnace is removed by vacuuming, and after heating to 170 ° C., nitrogen is introduced into the furnace to return it to atmospheric pressure, and then the temperature inside the furnace is lowered to room temperature to remove the solder particles. Formed.
（作製例８～１２）
　凹部サイズ等を表１に記載のとおり変更したこと以外は、作製例７と同様にしてはんだバンプ形成用フィルムを作製し、評価した。結果を表２に示す。 (Production Examples 8 to 12)
A film for forming solder bumps was produced and evaluated in the same manner as in Production Example 7, except that the recess size and the like were changed as shown in Table 1. The results are shown in Table 2.
（作製例１３）
　工程ｃ１に代えて、以下の工程ｃ３を行ったこと以外は、作製例１と同様にしてはんだバンプ形成用フィルムを作製し、評価した。結果を表２に示す。
工程ｃ３：はんだ粒子の形成
　工程ｂ１で凹部にはんだ微粒子が配置された基体を、ギ酸還元炉に投入し、真空引き後、ギ酸ガスを炉内に導入して、炉内をギ酸ガスで満たした。その後、炉内を１３０℃に調整し、５分間温度を保持した。その後、真空引きにて炉内のギ酸ガスを除去し、１８０℃まで加熱した後、窒素を炉内に導入して大気圧に戻してから炉内の温度を室温まで下げることにより、はんだ粒子を形成した。 (Production Example 13)
A film for forming solder bumps was produced and evaluated in the same manner as in Production Example 1 except that the following step c3 was performed instead of step c1. The results are shown in Table 2.
Step c3: Formation of solder particles The substrate in which the solder fine particles were arranged in the recesses in step b1 was put into a formic acid reduction furnace, evacuated, and then formic acid gas was introduced into the furnace to fill the inside of the furnace with formic acid gas. .. Then, the inside of the furnace was adjusted to 130 ° C., and the temperature was maintained for 5 minutes. After that, formic acid gas in the furnace is removed by vacuuming, and after heating to 180 ° C., nitrogen is introduced into the furnace to return it to atmospheric pressure, and then the temperature in the furnace is lowered to room temperature to remove the solder particles. Formed.
（作製例１４～１８）
　凹部サイズ等を表１に記載のとおり変更したこと以外は、作製例１３と同様にしてはんだバンプ形成用フィルムを作製し、評価した。結果を表２に示す。 (Production Examples 14 to 18)
A film for forming solder bumps was produced and evaluated in the same manner as in Production Example 13 except that the recess size and the like were changed as shown in Table 1. The results are shown in Table 2.
（作製例１９）
　工程ｃ１に代えて、以下の工程ｃ４を行ったこと以外は、作製例１と同様にしてはんだバンプ形成用フィルムを作製し、評価した。結果を表２に示す。
工程ｃ４：はんだ粒子の形成
　工程ｂ１で凹部にはんだ微粒子が配置された基体を、ギ酸コンベアーリフロー炉（Ｈｅｌｌｅｒ　Ｉｎｄｕｓｔｒｉｅｓ，　Ｉｎｃ．製、１９１３ＭＫ）に投入し、コンベアーにて搬送しながら、１９０℃に調整された窒素ゾーン、窒素及びギ酸ガス混合ゾーン、窒素ゾーンを連続して通過させた。窒素及びギ酸ガス混合ゾーンを２０分間で通過させ、凹部内にはんだ粒子を形成した。 (Production Example 19)
A film for forming solder bumps was produced and evaluated in the same manner as in Production Example 1 except that the following step c4 was performed instead of step c1. The results are shown in Table 2.
Step c4: Formation of solder particles The substrate in which the solder fine particles were arranged in the recesses in step b1 was put into a formic acid conveyor reflow furnace (Heller Industries, Inc., 1913MK) and adjusted to 190 ° C. while being conveyed by the conveyor. The soldered nitrogen zone, nitrogen and formic acid gas mixing zone, and nitrogen zone were passed continuously. The nitrogen and formic acid gas mixing zone was passed in 20 minutes to form solder particles in the recesses.
（作製例２０～２４）
　凹部サイズ等を表１に記載のとおり変更したこと以外は、作製例１９と同様にしてはんだバンプ形成用フィルムを作製し、評価した。結果を表２に示す。 (Production Examples 20 to 24)
A film for forming solder bumps was produced and evaluated in the same manner as in Production Example 19 except that the recess size and the like were changed as shown in Table 1. The results are shown in Table 2.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
＜はんだバンプ付き評価チップの作製＞
工程ｅ１：評価チップの準備
　下記に示す、７種類の金バンプ付きチップ（３．０×３．０ｍｍ、厚さ：０．５ｍｍ）を準備した。
チップＣ１…面積１００μｍ×１００μｍ、スペース４０μｍ、高さ：１０μｍ、バンプ数３６２
チップＣ２…面積７５μｍ×７５μｍ、スペース２０μｍ、高さ：１０μｍ、バンプ数３６２
チップＣ３…面積４０μｍ×４０μｍ、スペース１６μｍ、高さ：７μｍ、バンプ数３６２
チップＣ４…面積２０μｍ×２０μｍ、スペース７μｍ、高さ：５μｍ、バンプ数３６２
チップＣ５…面積１０μｍ×１０μｍ、スペース６μｍ、高さ：３μｍ、バンプ数３６２
チップＣ６…面積１０μｍ×１０μｍ、スペース４μｍ、高さ：３μｍ、バンプ数３６２
チップＣ７…面積５μｍ×１０μｍ、スペース３μｍ、高さ：２μｍ、バンプ数３６２ <Manufacturing of evaluation chips with solder bumps>
Step e1: Preparation of evaluation chip Seven types of chips with gold bumps (3.0 × 3.0 mm, thickness: 0.5 mm) shown below were prepared.
Chip C1 ... Area 100 μm × 100 μm, space 40 μm, height: 10 μm, number of bumps 362
Chip C2: Area 75 μm × 75 μm, space 20 μm, height: 10 μm, number of bumps 362
Chip C3: Area 40 μm × 40 μm, space 16 μm, height: 7 μm, number of bumps 362
Chip C4: Area 20 μm × 20 μm, space 7 μm, height: 5 μm, number of bumps 362
Chip C5: Area 10 μm × 10 μm, space 6 μm, height: 3 μm, number of bumps 362
Chip C6: Area 10 μm × 10 μm, space 4 μm, height: 3 μm, number of bumps 362
Chip C7: Area 5 μm × 10 μm, space 3 μm, height: 2 μm, number of bumps 362
工程ｆ１：はんだバンプ形成（ギ酸ガス不使用）
　以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｃ２で作製したはんだバンプ形成用フィルム（作製例７）を用いて、金バンプ付きチップ（３．０×３．０ｍｍ、厚さ：０．５ｍｍ）にはんだバンプを形成した。
ｉ）ホットプレート上に、厚さ０．３ｍｍのガラス板を置き、ガラス板上に金バンプを上にして評価チップを置いた。
ｉｉ）はんだバンプ形成用フィルムの凹部の開口面側を下に向け、評価チップの金バンプ面とはんだバンプ形成用フィルムが接触するように配置した。さらに、はんだバンプ形成用フィルムの上に厚さ０．３ｍｍのガラス板をのせ、ガラス板上にステンレス製の錘をのせてはんだバンプ形成用フィルムを金バンプに密着させた。
ｉｉｉ）窒素ガスが内部に吹き込める釣鐘型のガラスカバーを用意した。このガラスカバーで、ｉｉ）で準備した評価チップ上にはんだバンプ形成用フィルムが積層したサンプルを覆った。次に、ガラスカバー内に窒素ガスを導入して、サンプル全体を窒素雰囲気下に置いた。ホットプレートの熱板を１６０℃に昇温し、５分加熱した。その後、ホットプレートを室温にまで戻した後、窒素ガスを止めて、大気開放した。最上部の錘、ガラス板、はんだバンプ形成用フィルムの順に取り除いた。続いて、メタノール溶液中に評価チップを浸漬し、流動相を洗浄除去して、真空乾燥（４０℃で６０分）して、はんだバンプ付き評価チップを得た。 Step f1: Solder bump formation (no formic acid gas used)
Using the solder bump forming film (Production Example 7) produced in step c2 according to the procedures i) to iii) shown below, a chip with gold bumps (3.0 × 3.0 mm, thickness: 0.5 mm). ) Was formed with solder bumps.
i) A glass plate having a thickness of 0.3 mm was placed on the hot plate, and the evaluation chip was placed on the glass plate with the gold bump facing up.
ii) The solder bump forming film was arranged so that the gold bump surface of the evaluation chip and the solder bump forming film were in contact with each other so that the opening surface side of the recess of the solder bump forming film was directed downward. Further, a glass plate having a thickness of 0.3 mm was placed on the solder bump forming film, and a stainless steel weight was placed on the glass plate to bring the solder bump forming film into close contact with the gold bump.
iii) A bell-shaped glass cover that allows nitrogen gas to be blown inside was prepared. With this glass cover, a sample in which a film for forming a solder bump was laminated on the evaluation chip prepared in ii) was covered. Next, nitrogen gas was introduced into the glass cover and the entire sample was placed in a nitrogen atmosphere. The hot plate of the hot plate was heated to 160 ° C. and heated for 5 minutes. Then, after returning the hot plate to room temperature, nitrogen gas was stopped and the hot plate was opened to the atmosphere. The top weight, glass plate, and solder bump forming film were removed in this order. Subsequently, the evaluation chip was immersed in a methanol solution, the fluidized bed was washed and removed, and vacuum dried (40 ° C. for 60 minutes) to obtain an evaluation chip with solder bumps.
＜はんだバンプの評価：ギ酸ガス不使用＞
　工程ｆ１を経て得た評価チップを、ＳＥＭ観察用台座表面に固定し、表面に白金スパッタを施した。ＳＥＭにて、３０個の金バンプについて、金バンプ上に載った、はんだバンプ数を数え、一つの金バンプ上に載ったはんだバンプの平均個数を算出した。結果を表３に示す。また、レーザー顕微鏡（オリンパス株式会社製、ＬＥＸＴ　ＯＬＳ５０００―ＳＡＦ）を用いて金バンプからのはんだバンプの高さを測定し、１００個の平均値を算出した。結果を表３に示す。 <Solder bump evaluation: Formic acid gas not used>
The evaluation chip obtained in step f1 was fixed to the surface of the pedestal for SEM observation, and the surface was subjected to platinum sputtering. For 30 gold bumps, the number of solder bumps placed on the gold bumps was counted by SEM, and the average number of solder bumps placed on one gold bump was calculated. The results are shown in Table 3. Further, the height of the solder bumps from the gold bumps was measured using a laser microscope (LEXT OLS5000-SAF manufactured by Olympus Corporation), and the average value of 100 pieces was calculated. The results are shown in Table 3.
　作製例７のはんだバンプ形成用フィルムに代えて、作製例８～１２のはんだバンプ形成用フィルムを用いたこと以外は、上記と同じ方法ではんだバンプ形成及びその評価を行った。
評価結果を表３に示す。 Solder bump formation and its evaluation were carried out by the same method as described above, except that the solder bump forming film of Production Examples 8 to 12 was used instead of the solder bump forming film of Production Example 7.
The evaluation results are shown in Table 3.
（比較作製例１）
　工程ｄ１（フラックスの配置）を行わなかったこと以外は、作製例８と同様にして凹部内にはんだ粒子を有する比較用はんだバンプ形成用フィルムを作製した。この比較用はんだバンプ形成用フィルムを用いたこと以外は、工程ｆ１と同じ方法ではんだバンプ形成及びその評価を行った。結果を表３に示す。 (Comparative Production Example 1)
A comparative solder bump forming film having solder particles in the recesses was produced in the same manner as in Production Example 8 except that step d1 (flux arrangement) was not performed. Solder bump formation and its evaluation were performed by the same method as in step f1 except that the comparative solder bump forming film was used. The results are shown in Table 3.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
　作製例７～１２では、評価チップの金バンプ上にはんだバンプが形成できたが、比較作製例１ではいずれの評価チップにおいても金バンプ上にはんだバンプは観察されなかった。 In Production Examples 7 to 12, solder bumps could be formed on the gold bumps of the evaluation chips, but in Comparative Production Examples 1, no solder bumps were observed on the gold bumps of any of the evaluation chips.
　比較作製例１の凹部内には、フラックスを含む流動相が無かったことで、はんだ粒子の表面酸化被膜が還元されず、金バンプへのはんだ粒子の濡れ広がりも起こらなかった。 Since there was no fluid phase containing flux in the recess of Comparative Production Example 1, the surface oxide film of the solder particles was not reduced, and the solder particles did not wet and spread on the gold bumps.
　フラックス成分を含有する流動相が、はんだ粒子とともに凹部の中に収容されていることから、加熱によりフラックス成分がはんだ粒子表面の酸化被膜を除去するとともに、金バンプ（電極）表面の洗浄も行う。そして、はんだ粒子が溶解しながら流動相により金バンプ表面へ運ばれ、金バンプ上にはんだバンプを形成することができる。図１に示されるように、流動相が凹部内に存在しているため、流動相によって、金バンプ（電極）と対向するはんだ粒子表面近傍の酸化被膜が除去され、はんだ粒子と金バンプとの接触が活性化される。凹部の開口面が金バンプ面に接している状態で加熱するため、はんだ粒子は、金バンプ表面に接することができる。この時、凹部の壁面があるため、はんだ粒子及びフラックスのはんだバンプ形成用部材の面方向への流動が抑制されて、金バンプ上にはんだバンプを形成することができる。また、同じ理由で、隣接する凹部のはんだ粒子同士が接合しづらく、良好なはんだバンプが形成できる。バンプ形成時の加熱温度及び時間により、金バンプ表面との濡れ広がり量を制御する必要があるが、はんだ粒子とフラックスが凹部に収納された状態で、金バンプ面に押し付けられているため、上記理由で隣接間のはんだ粒子同士の結合がしづらく、加熱温度と時間における尤度が大きい。従って、産業利用上安定したはんだバンプ形成が達成される。なお、金バンプが無い部分に、フラックス成分及びはんだ粒子が少量見られたが、評価チップをメタノール中で洗浄することで、それらを取り除くことができた。金バンプ以外の評価チップ表面にも、凹部開口面が面しているが、金バンプが他の面より高いため、凹部開口面が触れにくく、はんだ粒子は評価チップ側に移動しづらい。また、部分的に凹部開口面が評価チップ側に接していても、はんだが濡れ広がる金属（電極）が無いため、その後の洗浄で簡単に取り除くことができる。また、前述で示したとおり、凹部内にはんだ粒子とフラックスがあるため、はんだバンプ形成用部材の面方向にはんだ粒子の流動が抑制されて、金バンプのショート不良等を起こしづらい。 Since the fluid phase containing the flux component is housed in the recess together with the solder particles, the flux component removes the oxide film on the surface of the solder particles by heating and also cleans the surface of the gold bump (electrode). Then, the solder particles are carried to the surface of the gold bump by the flowing phase while being melted, and the solder bump can be formed on the gold bump. As shown in FIG. 1, since the fluidized phase exists in the recess, the fluidized phase removes the oxide film near the surface of the solder particles facing the gold bumps (electrodes), and the solder particles and the gold bumps are separated from each other. Contact is activated. Since the heating is performed in a state where the opening surface of the recess is in contact with the gold bump surface, the solder particles can be in contact with the gold bump surface. At this time, since there is a wall surface of the recess, the flow of the solder particles and the flux in the surface direction of the solder bump forming member is suppressed, and the solder bump can be formed on the gold bump. Further, for the same reason, it is difficult for the solder particles of the adjacent recesses to join each other, and good solder bumps can be formed. It is necessary to control the amount of wetting and spreading with the gold bump surface by the heating temperature and time at the time of bump formation, but since the solder particles and flux are pressed against the gold bump surface in the recessed state, the above For this reason, it is difficult to bond the solder particles between adjacent solder particles, and the likelihood of heating temperature and time is high. Therefore, stable solder bump formation is achieved for industrial use. A small amount of flux components and solder particles were found in the portion where there were no gold bumps, but these could be removed by washing the evaluation chip in methanol. The concave opening surface faces the surface of the evaluation chip other than the gold bump, but since the gold bump is higher than the other surfaces, the concave opening surface is hard to touch and the solder particles are hard to move to the evaluation chip side. Further, even if the concave opening surface is partially in contact with the evaluation chip side, it can be easily removed by subsequent cleaning because there is no metal (electrode) in which the solder spreads wet. Further, as shown above, since the solder particles and the flux are present in the recesses, the flow of the solder particles is suppressed in the surface direction of the solder bump forming member, and it is difficult to cause a short-circuit defect of the gold bump.
　比較作製例１のように、流動相が無い場合、加熱してもはんだ粒子の表面酸化被膜を十分に還元できず、さらにはんだ粒子を金バンプ（電極）まで流動させることは難しく、安定してはんだバンプを形成することが困難である。 When there is no flow phase as in Comparative Production Example 1, the surface oxide film of the solder particles cannot be sufficiently reduced even when heated, and it is difficult to allow the solder particles to flow to the gold bumps (electrodes), and the solder particles are stable. It is difficult to form solder bumps.
工程ｆ２：はんだバンプ形成（ギ酸ガス使用）
　以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｃ２で作製したはんだバンプ形成用フィルム（作製例７）を用いて、金バンプ付きチップ（３．０×３．０ｍｍ、厚さ：０．５ｍｍ）にはんだバンプを形成した。
ｉ）厚さ５ｍｍのステンレス板上に、厚さ０．３ｍｍのガラス板を置き、ガラス板上に金バンプを上にして評価チップを置いた。
ｉｉ）はんだバンプ形成用フィルムの凹部の開口面側を下に向け、評価チップの金バンプ面とはんだバンプ形成用フィルムが接触するように配置した。さらに、はんだバンプ形成用フィルムの上に厚さ０．３ｍｍのガラス板をのせ、ガラス板上にステンレス製の錘をのせてはんだバンプ形成用フィルムを金バンプに密着させた。
ｉｉｉ）ギ酸リフローコンベアー炉（Ｈｅｌｌｅｒ　Ｉｎｄｕｓｔｒｉｅｓ　Ｉｎｃ．　１９３６ＭＫＶ）のベルトコンベアー上に、ｉｉ）で用意したステンレス板を載せ、４０ｍｍ／ｓの速度で流した。コンベアー炉内では、サンプルはまず窒素ガスゾーンを通過した。この際、サンプル周辺の酸素が取り除かれた。続いて１５０℃に加熱された窒素ガスのゾーンを通過し、さらに１８０℃のギ酸ガス（４％）のゾーンを通過し、その後、１６０℃に設定された真空チャンバー内に導入された。真空チャンバーが閉まった後、チャンバー内を真空に１分保ち、窒素ガスを導入して大気圧に戻した後、サンプルは真空チャンバーを出て、窒素ガス雰囲気の冷却ゾーンを通過して室温に戻された。最上部の錘、ガラス板、はんだバンプ形成用フィルムの順に取り除いた。続いて、メタノール溶液中に評価チップを浸漬し、流動相を洗浄除去して、真空乾燥（４０℃で６０分）して、はんだバンプ付き評価チップを得た。 Step f2: Solder bump formation (using formic acid gas)
Using the solder bump forming film (Production Example 7) produced in step c2 according to the procedures i) to iii) shown below, a chip with gold bumps (3.0 × 3.0 mm, thickness: 0.5 mm). ) Was formed with solder bumps.
i) A glass plate having a thickness of 0.3 mm was placed on a stainless steel plate having a thickness of 5 mm, and an evaluation chip was placed on the glass plate with a gold bump facing up.
ii) The solder bump forming film was arranged so that the gold bump surface of the evaluation chip and the solder bump forming film were in contact with each other so that the opening surface side of the recess of the solder bump forming film was directed downward. Further, a glass plate having a thickness of 0.3 mm was placed on the solder bump forming film, and a stainless steel weight was placed on the glass plate to bring the solder bump forming film into close contact with the gold bump.
iii) On the belt conveyor of the formic acid reflow conveyor furnace (Heller Industries Inc. 1936MKV), the stainless plate prepared in iii) was placed and flowed at a speed of 40 mm / s. In the conveyor furnace, the sample first passed through the nitrogen gas zone. At this time, oxygen around the sample was removed. It then passed through a zone of nitrogen gas heated to 150 ° C., further through a zone of formic acid gas (4%) at 180 ° C., and then introduced into a vacuum chamber set at 160 ° C. After the vacuum chamber is closed, the inside of the chamber is kept in a vacuum for 1 minute, nitrogen gas is introduced and the pressure is returned to atmospheric pressure, and then the sample exits the vacuum chamber and passes through the cooling zone of the nitrogen gas atmosphere to return to room temperature. Was done. The top weight, glass plate, and solder bump forming film were removed in this order. Subsequently, the evaluation chip was immersed in a methanol solution, the fluidized bed was washed and removed, and vacuum dried (40 ° C. for 60 minutes) to obtain an evaluation chip with solder bumps.
＜はんだバンプの評価：ギ酸ガス使用＞
　工程ｆ２を経て得た評価チップを、ＳＥＭ観察用台座表面に固定し、表面に白金スパッタを施した。ＳＥＭにて、３０個の金バンプについて、金バンプ上に載った、はんだバンプ数を数え、一つの金バンプ上に載ったはんだバンプの平均個数を算出した。結果を表３に示す。また、レーザー顕微鏡（オリンパス株式会社製、ＬＥＸＴ　ＯＬＳ５０００―ＳＡＦ）を用いて金バンプからのはんだバンプの高さを測定し、１００個の平均値を算出した。結果を表４に示す。 <Solder bump evaluation: Formic acid gas used>
The evaluation chip obtained in step f2 was fixed to the surface of the pedestal for SEM observation, and the surface was subjected to platinum sputtering. For 30 gold bumps, the number of solder bumps placed on the gold bumps was counted by SEM, and the average number of solder bumps placed on one gold bump was calculated. The results are shown in Table 3. Further, the height of the solder bumps from the gold bumps was measured using a laser microscope (LEXT OLS5000-SAF manufactured by Olympus Corporation), and the average value of 100 pieces was calculated. The results are shown in Table 4.
　作製例７のはんだバンプ形成用フィルムに代えて、作製例８～１２のはんだバンプ形成用フィルムを用いたこと以外は、工程ｆ２と同じ方法ではんだバンプ形成及びその評価を行った。評価結果を表４に示す。 Solder bump formation and its evaluation were performed by the same method as in step f2, except that the solder bump forming film of Production Examples 8 to 12 was used instead of the solder bump forming film of Production Example 7. The evaluation results are shown in Table 4.
　比較作製例１で得た比較用はんだバンプ形成用フィルムを用いたこと以外は、工程ｆ２と同じ方法ではんだバンプ形成及びその評価を行った。結果を表４に示す。 Solder bump formation and its evaluation were performed by the same method as in step f2, except that the comparative solder bump forming film obtained in Comparative Production Example 1 was used. The results are shown in Table 4.
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
　作製例７～１２では、金バンプ上にはんだバンプが形成できた。特に、ギ酸ガス雰囲気としなかった場合（表３）と比較して、はんだバンプ数が増える傾向にある。これは、凹部内のはんだ粒子の表面酸化被膜が、流動相に含まれるフラックス成分と、ギ酸ガスにより十分に還元されたことと、金パッド表面の有機物もギ酸ガスで除去されたため、金バンプ上にはんだバンプが形成され易かったと考えられる。ギ酸ガス雰囲気を用いて得られたはんだバンプを顕微鏡及び電子顕微鏡で観察すると、ギ酸ガス雰囲気を用いずに得られたはんだバンプより、球形のゆがみが少なかった。これは、加熱後に真空チャンバー内で真空状態になることで、はんだバンプ内の気泡が除去され、また流動相の低分子成分も十分に蒸発するため、はんだバンプがゆがみの少ない球形になったと考えられる。 In Production Examples 7 to 12, solder bumps could be formed on the gold bumps. In particular, the number of solder bumps tends to increase as compared with the case where the atmosphere is not formic acid gas (Table 3). This is because the surface oxide film of the solder particles in the recess was sufficiently reduced by the flux component contained in the fluid phase and formic acid gas, and the organic matter on the surface of the gold pad was also removed by the formic acid gas. It is probable that solder bumps were easily formed on the surface. When the solder bumps obtained using the formic acid gas atmosphere were observed with a microscope and an electron microscope, the spherical distortion was less than that of the solder bumps obtained without using the formic acid gas atmosphere. It is thought that this is because the air bubbles in the solder bumps are removed by creating a vacuum in the vacuum chamber after heating, and the low molecular weight components of the fluid phase are sufficiently evaporated, so that the solder bumps have become spherical with less distortion. Be done.
　比較作製例１では、金バンプ上にはんだバンプの形成が確認されたが、作製例７～１２と比較して、バンプ数が少ない傾向にあった。同じ比較作製例１を用いた場合であっても、ギ酸ガス雰囲気としなかったときは、はんだバンプの形成は見られなかったが、ギ酸ガス雰囲気としたときは、一部の凹部内のはんだ粒子はギ酸ガスにより表面酸化膜が除去され、金バンプ上に一定量載った。ただし、凹部の側を金バンプに押し付けているため、ギ酸ガスが凹部内のはんだ粒子の表面酸化膜を十分に除去するには至らなかったと考えられる。 In Comparative Production Example 1, formation of solder bumps was confirmed on the gold bumps, but the number of bumps tended to be smaller than that of Production Examples 7 to 12. Even when the same Comparative Production Example 1 was used, no solder bumps were formed when the formic acid gas atmosphere was not used, but when the formic acid gas atmosphere was used, the solder particles in some of the recesses were not formed. The surface oxide film was removed by formic acid gas, and a certain amount of solder was placed on the gold bumps. However, since the side of the recess is pressed against the gold bump, it is considered that the formic acid gas did not sufficiently remove the surface oxide film of the solder particles in the recess.
＜接続構造体の作製＞
工程ｇ１：評価基板の準備
　下記に示す、７種類の金バンプ付き基板（７０×２５ｍｍ、厚さ：０．５ｍｍ）を準備した。なお、これらの金バンプには抵抗測定用の引き出し配線も形成されている。
基板Ｄ１…面積１００μｍ×１００μｍ、スペース４０μｍ、高さ：４μｍ、バンプ数３６２
基板Ｄ２…面積７５μｍ×７５μｍ、スペース２０μｍ、高さ：４μｍ、バンプ数３６２
基板Ｄ３…面積４０μｍ×４０μｍ、スペース１６μｍ、高さ：４μｍ、バンプ数３６２
基板Ｄ４…面積２０μｍ×２０μｍ、スペース７μｍ、高さ：４μｍ、バンプ数３６２
基板Ｄ５…面積１０μｍ×１０μｍ、スペース６μｍ、高さ：３μｍ、バンプ数３６２
基板Ｄ６…面積１０μｍ×１０μｍ、スペース４μｍ、高さ：３μｍ、バンプ数３６２
基板Ｄ７…面積５μｍ×１０μｍ、スペース３μｍ、高さ：３μｍ、バンプ数３６２ <Manufacturing of connection structure>
Step g1: Preparation of evaluation substrate Seven types of substrates with gold bumps (70 × 25 mm, thickness: 0.5 mm) shown below were prepared. The gold bumps are also formed with lead-out wiring for resistance measurement.
Substrate D1 ... Area 100 μm × 100 μm, space 40 μm, height: 4 μm, number of bumps 362
Substrate D2: Area 75 μm × 75 μm, space 20 μm, height: 4 μm, number of bumps 362
Substrate D3: Area 40 μm × 40 μm, space 16 μm, height: 4 μm, number of bumps 362
Substrate D4: Area 20 μm × 20 μm, space 7 μm, height: 4 μm, number of bumps 362
Substrate D5: Area 10 μm × 10 μm, space 6 μm, height: 3 μm, number of bumps 362
Substrate D6: Area 10 μm × 10 μm, space 4 μm, height: 3 μm, number of bumps 362
Substrate D7: Area 5 μm × 10 μm, space 3 μm, height: 3 μm, number of bumps 362
工程ｈ１：電極の接合
　以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｆ１で作製したはんだバンプ付き評価チップを用いて、金バンプ付き評価基板とはんだバンプを介して接続した。
ｉ）ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板に、金バンプを上にして評価基板を置いた。
ｉｉ）はんだバンプが形成された評価チップのはんだバンプ面を下に向け、評価基板の金バンプ面とはんだバンプが接触するように配置し、動かないように固定した。
ｉｉｉ）ギ酸真空リフロー炉を作動させ、真空引きの後、ギ酸ガスを充填し、下部熱板を１８０℃に昇温し、５分加熱した。その後、真空引きにてギ酸ガスを排出後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気に開放した。評価チップと評価基板の間に粘度を調整したアンダーフィル材（日立化成株式会社製、ＣＥＬシリーズ）を適量入れ、真空引きにて充填後、１６５℃で２時間硬化させ、評価チップと評価基板の接続構造体を作製した。接続構造体における各材料の組合せは以下のとおりである。
（１）チップＣ１／はんだバンプ形成用フィルム／基板Ｄ１
（２）チップＣ２／はんだバンプ形成用フィルム／基板Ｄ２
（３）チップＣ３／はんだバンプ形成用フィルム／基板Ｄ３
（４）チップＣ４／はんだバンプ形成用フィルム／基板Ｄ４
（５）チップＣ５／はんだバンプ形成用フィルム／基板Ｄ５
（６）チップＣ６／はんだバンプ形成用フィルム／基板Ｄ６
（７）チップＣ７／はんだバンプ形成用フィルム／基板Ｄ７ Step h1: Joining the electrodes According to the procedures i) to iii) shown below, the evaluation chip with solder bumps produced in step f1 was used to connect to the evaluation substrate with gold bumps via the solder bumps.
i) The evaluation substrate was placed on the lower hot plate of the formic acid reflow furnace (manufactured by Shinko Seiki Co., Ltd., batch type vacuum soldering device) with the gold bumps facing up.
ii) The solder bump surface of the evaluation chip on which the solder bumps were formed was directed downward, and the gold bump surface of the evaluation substrate and the solder bumps were arranged so as to be in contact with each other and fixed so as not to move.
iii) The formic acid vacuum reflow furnace was operated, evacuated, filled with formic acid gas, the temperature of the lower hot plate was raised to 180 ° C., and the mixture was heated for 5 minutes. Then, after discharging formic acid gas by evacuation, nitrogen substitution was performed, the lower hot plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere. An appropriate amount of underfill material (CEL series manufactured by Hitachi Kasei Co., Ltd.) whose viscosity has been adjusted is placed between the evaluation chip and the evaluation substrate, filled by vacuuming, and then cured at 165 ° C. for 2 hours to form the evaluation chip and the evaluation substrate. A connection structure was prepared. The combinations of each material in the connection structure are as follows.
(1) Chip C1 / Solder bump forming film / substrate D1
(2) Chip C2 / Solder bump forming film / Substrate D2
(3) Chip C3 / Solder bump forming film / Substrate D3
(4) Chip C4 / Solder bump forming film / Substrate D4
(5) Chip C5 / Solder bump forming film / Substrate D5
(6) Chip C6 / Solder bump forming film / Substrate D6
(7) Chip C7 / Solder bump forming film / Substrate D7
＜接続構造体の評価＞
　得られた接続構造体の一部について、導通抵抗試験及び絶縁抵抗試験を以下のように行った。 <Evaluation of connection structure>
A conduction resistance test and an insulation resistance test were performed on a part of the obtained connection structure as follows.
（導通抵抗試験－吸湿耐熱試験）
　金バンプ付きチップ（バンプ）／金バンプ付き基板（バンプ）間の導通抵抗に関して、導通抵抗の初期値と吸湿耐熱試験（温度８５℃、湿度８５％の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定し、それらの平均値を算出した。
得られた平均値から下記基準に従って導通抵抗を評価した。結果を表５に示す。なお、吸湿耐熱試験１０００時間後に、下記Ａ又はＢの基準を満たす場合は導通抵抗が良好といえる。
Ａ：導通抵抗の平均値が２Ω未満
Ｂ：導通抵抗の平均値が２Ω以上５Ω未満
Ｃ：導通抵抗の平均値が５Ω以上１０Ω未満
Ｄ：導通抵抗の平均値が１０Ω以上２０Ω未満
Ｅ：導通抵抗の平均値が２０Ω以上 (Conduction resistance test-moisture absorption and heat resistance test)
Regarding the conduction resistance between the chip with gold bump (bump) and the substrate with gold bump (bump), after the initial value of the conduction resistance and the moisture absorption and heat resistance test (leaving for 100, 500, 1000 hours under the conditions of temperature 85 ° C and humidity 85%). The value of was measured for 20 samples, and the average value thereof was calculated.
From the obtained average value, the conduction resistance was evaluated according to the following criteria. The results are shown in Table 5. If the following criteria A or B are satisfied after 1000 hours of the moisture absorption and heat resistance test, it can be said that the conduction resistance is good.
A: Average value of conduction resistance is less than 2Ω B: Average value of conduction resistance is 2Ω or more and less than 5Ω C: Average value of conduction resistance is 5Ω or more and less than 10Ω D: Average value of conduction resistance is 10Ω or more and less than 20Ω E: Conduction resistance The average value of is 20Ω or more
（導通抵抗試験－高温放置試験）
　金バンプ付きチップ（バンプ）／金バンプ付き基板（バンプ）間の導通抵抗に関して、導通抵抗の初期値と高温放置試験（温度１００℃の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定した。なお、高温放置後は、落下衝撃を加え、落下衝撃後のサンプルの導通抵抗を測定した。落下衝撃は、接続構造体を、金属板にネジ止め固定し、高さ５０ｃｍから落下させることで生じさせた。落下後、最も衝撃の大きいチップコーナーのはんだ接合部（４箇所）において直流抵抗値を測定し、測定値が初期抵抗から５倍以上増加したときに破断が生じたとみなして、評価を行った。なお、各サンプルにつき４箇所で、合計８０箇所の測定を行った。結果を表６に示す。落下回数２０回後に下記Ａ又はＢの基準を満たす場合をはんだ接続信頼性が良好であると評価した。
Ａ：初期抵抗から５倍以上増加したはんだ接続部が、０箇所であった。
Ｂ：初期抵抗から５倍以上増加したはんだ接続部が、１箇所以上５箇所以下であった。
Ｃ：初期抵抗から５倍以上増加したはんだ接続部が、６箇所以上２０箇所以下であった。
Ｄ：初期抵抗から５倍以上増加したはんだ接続部が、２１箇所以上であった。 (Conduction resistance test-high temperature standing test)
Regarding the conduction resistance between the chip with gold bump (bump) and the substrate with gold bump (bump), the initial value of the conduction resistance and the value after the high temperature standing test (leaving for 100, 500, 1000 hours at a temperature of 100 ° C.) are set. 20 samples were measured. After being left at a high temperature, a drop impact was applied and the conduction resistance of the sample after the drop impact was measured. The drop impact was generated by fixing the connection structure to a metal plate with screws and dropping it from a height of 50 cm. After the drop, the DC resistance values were measured at the solder joints (4 points) at the chip corners where the impact was greatest, and when the measured values increased 5 times or more from the initial resistance, it was considered that breakage had occurred and evaluation was performed. A total of 80 points were measured at 4 points for each sample. The results are shown in Table 6. When the criteria of A or B below were satisfied after 20 drops, the solder connection reliability was evaluated as good.
A: There were no solder connections where the initial resistance increased by 5 times or more.
B: The number of solder connection portions increased by 5 times or more from the initial resistance was 1 or more and 5 or less.
C: The number of solder connection portions increased by 5 times or more from the initial resistance was 6 or more and 20 or less.
D: There were 21 or more solder connection parts that increased by 5 times or more from the initial resistance.
（絶縁抵抗試験）
　チップ電極間の絶縁抵抗に関し、絶縁抵抗の初期値とマイグレーション試験（温度６０℃、湿度９０％、２０Ｖ印加の条件で１００、５００、１０００時間放置）後の値を、２０サンプルについて測定し、全２０サンプル中、絶縁抵抗値が１０９Ω以上となるサンプルの割合を算出した。得られた割合から下記基準に従って絶縁抵抗を評価した。結果を表７に示す。なお、マイグレーション試験１０００時間後に、下記Ａ又はＢの基準を満たした場合は絶縁抵抗が良好といえる。
Ａ：絶縁抵抗値１０９Ω以上の割合が１００％
Ｂ：絶縁抵抗値１０９Ω以上の割合が９０％以上１００％未満
Ｃ：絶縁抵抗値１０９Ω以上の割合が８０％以上９０％未満
Ｄ：絶縁抵抗値１０９Ω以上の割合が５０％以上８０％未満
Ｅ：絶縁抵抗値１０９Ω以上の割合が５０％未満 (Insulation resistance test)
Regarding the insulation resistance between the chip electrodes, the initial value of the insulation resistance and the value after the migration test (standing at temperature 60 ° C., humidity 90%, 20V application for 100, 500, 1000 hours) were measured for 20 samples, and all of them were measured. of 20 samples was calculated the ratio of the sample insulation resistance is 10 9 Omega more. The insulation resistance was evaluated from the obtained ratio according to the following criteria. The results are shown in Table 7. If the following criteria A or B are satisfied after 1000 hours of the migration test, it can be said that the insulation resistance is good.
A: percentage of higher insulation resistance 10 9 Omega 100%
B: Insulation resistance value 10 9 Ω or more is 90% or more and less than 100% C: Insulation resistance value 10 9 Ω or more is 80% or more and less than 90% D: Insulation resistance value 10 9 Ω or more is 50% or more and less than 80% E: ratio of more than the insulation resistance 10 9 Omega is less than 50%
Figure JPOXMLDOC01-appb-T000005
Figure JPOXMLDOC01-appb-T000005
Figure JPOXMLDOC01-appb-T000006
Figure JPOXMLDOC01-appb-T000006
Figure JPOXMLDOC01-appb-T000007
Figure JPOXMLDOC01-appb-T000007
＜はんだバンプ形成用フィルムの作製＞
工程ｉ１：評価用基体の作製
　６インチのシリコンウエハ上に、液状感光性レジスト（日立化成株式会社製、ＡＨシリーズ）をスピンコート法にて２．３μｍの厚みに塗布した。このシリコンウエハ上の感光性レジストを露光・現像して、開口径３．１μｍφ、底部径２．０μｍφ、深さ２．３μｍ（底部径２．０μｍφは、開口を上面からみると、開口径３．１μｍφの中央に位置する）の凹部を有する評価パターンを形成した。なお、この評価パターンは、一つが２０ｍｍ×２０ｍｍのサイズであり、その中心の１０ｍｍ×１０ｍｍのエリアに前述の凹部が配置されている。凹部の位置は、後述する評価チップＣ８の電極配置パターンに相対した位置（Ｘ方向ピッチ、Ｙ方向ピッチ）に配置されており、３箇所のアライメントマークも配置した。これをダイサーにより２０ｍｍ×２０ｍｍのサイズに切り出し評価用基体１を得た。評価用基体の概要を表８に示す。 <Manufacturing of film for forming solder bumps>
Step i1: Preparation of evaluation substrate A liquid photosensitive resist (manufactured by Hitachi Kasei Co., Ltd., AH series) was applied to a thickness of 2.3 μm on a 6-inch silicon wafer by a spin coating method. The photosensitive resist on this silicon wafer is exposed and developed to have an opening diameter of 3.1 μmφ, a bottom diameter of 2.0 μmφ, and a depth of 2.3 μm (the bottom diameter of 2.0 μmφ is an opening diameter of 3 when the opening is viewed from the top surface. An evaluation pattern having a recess (located in the center of 1 μmφ) was formed. One of the evaluation patterns has a size of 20 mm × 20 mm, and the above-mentioned recess is arranged in an area of 10 mm × 10 mm at the center thereof. The positions of the recesses are arranged at positions (X-direction pitch, Y-direction pitch) relative to the electrode arrangement pattern of the evaluation chip C8, which will be described later, and three alignment marks are also arranged. This was cut out to a size of 20 mm × 20 mm by a dicer to obtain a substrate 1 for evaluation. The outline of the evaluation substrate is shown in Table 8.
Figure JPOXMLDOC01-appb-T000008
Figure JPOXMLDOC01-appb-T000008
　感光性レジストの厚み、開口径及びピッチを表８に示す値として、評価用基体２～６を作製した。 Evaluation substrates 2 to 6 were prepared with the thickness, opening diameter and pitch of the photosensitive resist as the values shown in Table 8.
＜はんだ粒子の準備＞
工程ｊ１：はんだ粒子の準備
　工程ａ１、ｂ１、ｃ１を経て、表２の作製例７～作製例１２に示す、はんだ粒子を凹部に有するはんだバンプ形成用フィルムを得た。ステンレス製バットにイソプロピルアルコールを満たし、得られたはんだバンプ形成用フィルムを浸漬し、２８ｋＨｚ、６００Ｗの超音波を５分印加した。はんだ粒子は、凹部から脱離し、イソプロピルアルコール溶剤中に分散した。このはんだ粒子が分散した溶剤を静置して、上澄みを廃棄した。その後、イソプロピルアルコールで再び満たし、はんだ粒子をよく分散させたのち、静置した。この沈降分離の操作を３回行い、粒子径の揃ったはんだ粒子１～６を得た。はんだ粒子１～６の概要を表９に示す。 <Preparation of solder particles>
Step j1: Preparation of Solder Particles Through the steps a1, b1 and c1, the solder bump forming films having the solder particles in the recesses shown in Production Examples 7 to 12 in Table 2 were obtained. A stainless steel vat was filled with isopropyl alcohol, the obtained film for forming solder bumps was immersed, and ultrasonic waves of 28 kHz and 600 W were applied for 5 minutes. The solder particles were separated from the recesses and dispersed in the isopropyl alcohol solvent. The solvent in which the solder particles were dispersed was allowed to stand, and the supernatant was discarded. Then, it was filled with isopropyl alcohol again to disperse the solder particles well, and then allowed to stand. This sedimentation separation operation was performed three times to obtain solder particles 1 to 6 having the same particle size. The outline of the solder particles 1 to 6 is shown in Table 9.
Figure JPOXMLDOC01-appb-T000009
Figure JPOXMLDOC01-appb-T000009
（作製例２５）
工程ｋ１：流動化剤とはんだ粒子の配置
　蓋つきガラス瓶にドデカンとはんだ粒子１を入れ、超音波で分散した。ガラス板上に固定した２０ｍｍ×２０ｍｍの評価用基体１表面に、分散液を垂らし、ウレタン製スキージで評価用基体１表面を擦り、はんだ粒子１とドデカンを凹部内に充填した。評価用基体１表面の余剰なはんだ粒子１及びドデカンをクリーンクロスで拭きとり、評価用基体１の凹部内にはんだ粒子１とドデカンが配置されたはんだバンプ形成用フィルムを得た。 (Production Example 25)
Step k1: Arrangement of fluidizing agent and solder particles Dodecane and solder particles 1 were placed in a glass bottle with a lid and dispersed by ultrasonic waves. The dispersion liquid was dropped on the surface of the evaluation substrate 1 of 20 mm × 20 mm fixed on the glass plate, the surface of the evaluation substrate 1 was rubbed with a urethane squeegee, and the solder particles 1 and dodecane were filled in the recesses. Excess solder particles 1 and dodecane on the surface of the evaluation substrate 1 were wiped off with a clean cloth to obtain a solder bump forming film in which the solder particles 1 and dodecane were arranged in the recesses of the evaluation substrate 1.
Figure JPOXMLDOC01-appb-T000010
Figure JPOXMLDOC01-appb-T000010
（作製例２６～４２）
　流動化剤の種類、はんだ粒子、及び評価用基体を表１０に示す組み合わせにしたこと以外は、工程ｋ１と同様にして、はんだ粒子と流動化剤を凹部内に配置した、評価用はんだバンプ形成用フィルム２６～４２を得た。なお、アジピン酸は、ジヒドロターピネオール９０質量部に対しアジピン酸２０質量部を入れ、よく混ぜて、流動相とした。 (Production Examples 26 to 42)
Forming of evaluation solder bumps in which the solder particles and the fluidizing agent are arranged in the recesses in the same manner as in step k1, except that the types of the fluidizing agent, the solder particles, and the evaluation substrate are combined as shown in Table 10. Films 26 to 42 for use were obtained. As for adipic acid, 20 parts by mass of adipic acid was added to 90 parts by mass of dihydroterpineol and mixed well to prepare a fluid phase.
＜はんだバンプ付き評価チップの作製＞
工程ｅ２：評価チップの準備
　下記に示す、６種類の金バンプ付きチップ（１０ｍｍ×１０ｍｍ、厚さ：０．５ｍｍ）を準備した。
チップＣ８…サイズ８×４μｍ、Ｘ方向ピッチ１６μｍ、Ｙ方向ピッチ８μｍ、高さ：３μｍ、バンプ数３８２０００
チップＣ９…サイズ１６μｍ×８μｍ、Ｘ方向ピッチ３２μｍ、Ｙ方向ピッチ１６μｍ、高さ：５μｍ、バンプ数９５７００
チップＣ１０…サイズ２４μｍ×１２μｍ、Ｘ方向ピッチ４８μｍ、Ｙ方向ピッチ２４μｍ、高さ：８μｍ、バンプ数４２５００
チップＣ１１…サイズ７２μｍ×３６μｍ、Ｘ方向ピッチ１４４μｍ、Ｙ方向ピッチ７２μｍ、高さ：１０μｍ、バンプ数４７００
チップＣ１２…サイズ９６μｍ×４８μｍ、Ｘ方向ピッチ１９２μｍ、Ｙ方向ピッチ９６μｍ、高さ：１３μｍ、バンプ数２６００
チップＣ１３…サイズ１４０μｍ×７０μｍ、Ｘ方向ピッチ２８０μｍ、Ｙ方向ピッチ１４０μｍ、高さ：１８μｍ、バンプ数１２００
　なお、それぞれに３箇所のアライメントマークが配置されている。 <Manufacturing of evaluation chips with solder bumps>
Step e2: Preparation of evaluation chip Six types of chips with gold bumps (10 mm × 10 mm, thickness: 0.5 mm) shown below were prepared.
Chip C8: size 8 × 4 μm, pitch in X direction 16 μm, pitch in Y direction 8 μm, height: 3 μm, number of bumps 382000
Chip C9: Size 16 μm × 8 μm, X-direction pitch 32 μm, Y-direction pitch 16 μm, height: 5 μm, number of bumps 95700
Chip C10: Size 24 μm × 12 μm, X-direction pitch 48 μm, Y-direction pitch 24 μm, height: 8 μm, number of bumps 42500
Chip C11 ... Size 72 μm × 36 μm, X-direction pitch 144 μm, Y-direction pitch 72 μm, height: 10 μm, number of bumps 4700
Chip C12: Size 96 μm × 48 μm, X-direction pitch 192 μm, Y-direction pitch 96 μm, height: 13 μm, number of bumps 2600
Chip C13: Size 140 μm × 70 μm, X-direction pitch 280 μm, Y-direction pitch 140 μm, height: 18 μm, number of bumps 1200
In addition, three alignment marks are arranged in each.
＜はんだバンプ形成＞
工程ｆ３：はんだバンプ形成：窒素雰囲気
　以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｋ１で作製した評価用はんだバンプ形成用フィルム２５を用いて、金バンプ付きチップ（１０ｍｍ×１０ｍｍ、厚さ：０．５ｍｍ）にはんだバンプを形成した。
ｉ）３０ｍｍ×３０ｍｍ（厚み０．５ｍｍ）のガラス板上に、金バンプを上にしてチップＣ８を固定した。これをフリップチップボンダー（ＦＣ３０００：東レ製）のステージに吸着固定した。
ｉｉ）加熱加圧用ヘッドにて２０ｍｍ×２０ｍｍの評価用基体１をピックアップし、カメラによりアライメントマークを読み取り、チップＣ８の電極位置と評価用基体１の凹部を対向させ、仮置きした。
ｉｉｉ）窒素ガスが内部に吹き込める釣鐘型のガラスカバーを用意した。このガラスカバーで、ホットプレート全体を覆い、ホットプレートの熱板を１５０℃に昇温した。ｉｉ）で準備したサンプルをホットプレート上に載せ、最上段の評価用基体１の上に、ステンレス製の錘を載せ、窒素雰囲気下で３分加熱した。その後、最上部の錘、評価用基体１の順に取り除いた。続いて、メタノール溶液中にチップＣ８を浸漬し、流動相を洗浄除去して、真空乾燥（４０℃で６０分）して、はんだバンプ付き評価用チップ２５を得た。 <Solder bump formation>
Step f3: Solder bump formation: Nitrogen atmosphere Using the evaluation solder bump forming film 25 produced in step k1 according to the procedures i) to iii) shown below, a chip with gold bumps (10 mm × 10 mm, thickness: Solder bumps were formed at 0.5 mm).
i) The chip C8 was fixed on a glass plate of 30 mm × 30 mm (thickness 0.5 mm) with the gold bump facing up. This was adsorbed and fixed to the stage of a flip chip bonder (FC3000: manufactured by Toray Industries, Inc.).
ii) The evaluation substrate 1 having a size of 20 mm × 20 mm was picked up by the heating and pressurizing head, the alignment mark was read by the camera, the electrode position of the chip C8 and the recess of the evaluation substrate 1 were opposed to each other, and the evaluation substrate 1 was temporarily placed.
iii) A bell-shaped glass cover that allows nitrogen gas to be blown inside was prepared. The entire hot plate was covered with this glass cover, and the temperature of the hot plate of the hot plate was raised to 150 ° C. The sample prepared in ii) was placed on a hot plate, a stainless steel weight was placed on the evaluation substrate 1 on the uppermost stage, and the sample was heated in a nitrogen atmosphere for 3 minutes. Then, the uppermost weight and the evaluation substrate 1 were removed in this order. Subsequently, the chip C8 was immersed in a methanol solution, the fluidized bed was washed and removed, and vacuum dried (at 40 ° C. for 60 minutes) to obtain an evaluation chip 25 with solder bumps.
＜はんだバンプの評価：ギ酸ガス不使用＞
　工程ｆ１を経て得た評価用チップ２５を、ＳＥＭ観察用台座表面に固定し、表面に白金スパッタを施した。ＳＥＭにて、３００個の金バンプについて、金バンプ上にはんだバンプが形成された数を数え、はんだバンプ形成率を算出し、以下の評価基準で評価した。結果を表１１に示す。なお、はんだバンプ形成率の評価がＡ又はＢの基準を満たす場合に良好といえる。
Ａ：はんだバンプ形成率が９割以上
Ｂ：はんだバンプ形成率が８割以上９割未満
Ｃ：はんだバンプ形成率が７割以上８割未満
Ｄ：はんだバンプ形成率が６割以上７割未満
Ｅ：はんだバンプ形成率が６割未満 <Solder bump evaluation: Formic acid gas not used>
The evaluation chip 25 obtained in step f1 was fixed to the surface of the SEM observation pedestal, and the surface was subjected to platinum sputtering. For 300 gold bumps, the number of solder bumps formed on the gold bumps was counted by SEM, the solder bump formation rate was calculated, and the evaluation was performed according to the following evaluation criteria. The results are shown in Table 11. It can be said that the evaluation of the solder bump formation rate is good when the criteria of A or B are satisfied.
A: Solder bump formation rate is 90% or more B: Solder bump formation rate is 80% or more and less than 90% C: Solder bump formation rate is 70% or more and less than 80% D: Solder bump formation rate is 60% or more and less than 70% E : Solder bump formation rate is less than 60%
　さらに、レーザー顕微鏡（オリンパス株式会社製、ＬＥＸＴ　ＯＬＳ５０００―ＳＡＦ）を用いて金バンプからのはんだバンプの高さを測定し、１００個の平均値を算出した。結果を表１１に示す。 Furthermore, the height of the solder bumps from the gold bumps was measured using a laser microscope (LEXT OLS5000-SAF manufactured by Olympus Corporation), and the average value of 100 pieces was calculated. The results are shown in Table 11.
　次に、作製例２５の評価用はんだバンプ形成用フィルム２５に代えて、作製例２６～４２の評価用はんだバンプ形成用フィルム２６～４２を用いたこと、それぞれの金バンプ（電極）と凹部の位置に対応したチップＣ８～１３を用いたこと以外は、上記と同じ方法ではんだバンプ形成及びその評価を行った。評価結果を表１１に示す。
Figure JPOXMLDOC01-appb-T000011
 Next, instead of the evaluation solder bump forming film 25 of the production example 25, the evaluation solder bump forming films 26 to 42 of the production examples 26 to 42 were used, and the gold bumps (electrodes) and the recesses of each were used. Solder bump formation and its evaluation were performed by the same method as described above except that the chips C8 to 13 corresponding to the positions were used. The evaluation results are shown in Table 11.
Figure JPOXMLDOC01-appb-T000011
　評価用チップ２５～４２は、いずれも金バンプ上にはんだバンプが十分に形成された。はんだバンプは、電極上にのみ形成され、電極間にはんだ粒子は存在しなかった。電極表面にはんだバンプ形成用フィルムの凹部の開口部面を押し付けているため、流動相があっても、溶解したはんだが電極表面から漏れる可能性が低く、安定してはんだバンプが形成できる。 In each of the evaluation chips 25 to 42, solder bumps were sufficiently formed on the gold bumps. Solder bumps were formed only on the electrodes and no solder particles were present between the electrodes. Since the opening surface of the recess of the solder bump forming film is pressed against the electrode surface, there is a low possibility that the melted solder leaks from the electrode surface even if there is a fluid phase, and the solder bump can be stably formed.
＜はんだバンプ形成＞
工程ｆ４：はんだバンプ形成：ギ酸雰囲気
　工程ｆ３のｉｉｉ）を以下の方法に代えたこと以外は、工程ｆ３と同じ方法を用いてはんだバンプを形成し、評価した。評価結果を表１２に示す。
ｉｉｉ）チップＣ８上に評価用基体１が載ったガラス板を、ギ酸炉（神港精機株式会社製）の熱板上に配置固定し、評価用基体１の上にステンレス製の錘を載せた。炉内を真空脱気した後、ギ酸雰囲気下で１５０℃３分処理し、大気圧に戻した。その後、最上部の錘、評価用基体１の順に取り除いた。続いて、メタノール溶液中にチップＣ８を浸漬し、流動相を洗浄除去して、真空乾燥（４０℃で６０分）して、はんだバンプ付きの評価用チップ４３を得た。 <Solder bump formation>
Step f4: Solder bump formation: Formic acid atmosphere Solder bumps were formed and evaluated using the same method as in step f3, except that iii) in step f3 was replaced with the following method. The evaluation results are shown in Table 12.
iii) A glass plate on which the evaluation base 1 was placed on the chip C8 was placed and fixed on a hot plate of a formic acid furnace (manufactured by Shinko Seiki Co., Ltd.), and a stainless steel weight was placed on the evaluation base 1. .. After vacuum degassing the inside of the furnace, the treatment was carried out at 150 ° C. for 3 minutes in a formic acid atmosphere, and the pressure was returned to atmospheric pressure. Then, the uppermost weight and the evaluation substrate 1 were removed in this order. Subsequently, the chip C8 was immersed in a methanol solution, the fluid phase was washed and removed, and vacuum dried (at 40 ° C. for 60 minutes) to obtain an evaluation chip 43 with solder bumps.
Figure JPOXMLDOC01-appb-T000012
Figure JPOXMLDOC01-appb-T000012
　工程ｆ４の方法を用い、表１２に示す組み合わせではんだバンプの形成を行い、評価用チップ４４～６０を得た。上記と同様に行った評価結果を表１２に示す。 Using the method of step f4, solder bumps were formed in the combinations shown in Table 12 to obtain evaluation chips 44 to 60. Table 12 shows the evaluation results obtained in the same manner as above.
　評価用チップ４３～６０では、いずれも良好なはんだバンプが形成できた。ギ酸により還元雰囲気としたため良好な結果となった。 Good solder bumps could be formed in all of the evaluation chips 43 to 60. Good results were obtained because the atmosphere was reduced by formic acid.
＜はんだバンプ形成＞
工程ｆ５：はんだバンプ形成：真空加圧
　工程ｆ３のｉｉｉ）を以下の方法に代えたこと以外は、工程ｆ３と同じ方法ではんだバンプを形成し、評価した。評価結果を表１３に示す。
ｉｉｉ）チップＣ８上に評価用基体１が載ったガラス板を、真空加圧式ラミネータ（ＭＶＬ－５００：株式会社日本製鋼所製）のキャリアフィルム上に配置した。上下加熱板温度を１４５℃に設定し、圧力０．５ＭＰａ、加圧時間３ｓで処理した。その後、評価用基体１を取り除いた。続いて、メタノール溶液中にチップＣ８を浸漬し、流動相を洗浄除去して、真空乾燥（４０℃で６０分）して、はんだバンプ付きの評価用チップ６１を得た。結果を表１３に示す。 <Solder bump formation>
Step f5: Solder bump formation: Vacuum pressurization Solder bumps were formed and evaluated by the same method as in step f3, except that iii) in step f3 was replaced with the following method. The evaluation results are shown in Table 13.
iii) A glass plate on which the evaluation substrate 1 was placed on the chip C8 was placed on a carrier film of a vacuum pressurizing laminator (MVL-500: manufactured by Japan Steel Works, Ltd.). The upper and lower heating plate temperature was set to 145 ° C., and the treatment was performed at a pressure of 0.5 MPa and a pressurization time of 3 s. Then, the evaluation substrate 1 was removed. Subsequently, the chip C8 was immersed in a methanol solution, the fluid phase was washed and removed, and vacuum dried (at 40 ° C. for 60 minutes) to obtain an evaluation chip 61 with solder bumps. The results are shown in Table 13.
Figure JPOXMLDOC01-appb-T000013
Figure JPOXMLDOC01-appb-T000013
　工程ｆ５の方法を用い、表１３に示す組み合わせではんだバンプの形成を行い、評価用チップ６２～７８を得た。上記と同様に行った評価結果を表１３に示す。 Using the method of step f5, solder bumps were formed in the combinations shown in Table 13 to obtain evaluation chips 62 to 78. Table 13 shows the evaluation results obtained in the same manner as above.
　評価用チップ６１～７８では、いずれも良好なはんだバンプが形成できた。真空加圧により、圧力が面内に均一に掛かるため良好な結果となった。 Good solder bumps could be formed in all of the evaluation chips 61 to 78. Good results were obtained because the pressure was evenly applied in the plane by vacuum pressurization.
＜はんだバンプ付き評価チップの作製＞
工程ｅ３：評価チップの準備
　下記に示す、６種類の銅バンプ付きチップ（１０ｍｍ×１０ｍｍ、厚さ：０．５ｍｍ）を準備した。
チップＣ１４…サイズ８×４μｍ、Ｘ方向ピッチ１６μｍ、Ｙ方向ピッチ８μｍ、高さ：３μｍ、バンプ数３８２０００
チップＣ１５…サイズ１６μｍ×８μｍ、Ｘ方向ピッチ３２μｍ、Ｙ方向ピッチ１６μｍ、高さ：５μｍ、バンプ数９５７００
チップＣ１６…サイズ２４μｍ×１２μｍ、Ｘ方向ピッチ４８μｍ、Ｙ方向ピッチ２４μｍ、高さ：８μｍ、バンプ数４２５００
チップＣ１７…サイズ７２μｍ×３６μｍ、Ｘ方向ピッチ１４４μｍ、Ｙ方向ピッチ７２μｍ、高さ：１０μｍ、バンプ数４７００
チップＣ１８…サイズ９６μｍ×４８μｍ、Ｘ方向ピッチ１９２μｍ、Ｙ方向ピッチ９６μｍ、高さ：１３μｍ、バンプ数２６００
チップＣ１９…サイズ１４０μｍ×７０μｍ、Ｘ方向ピッチ２８０μｍ、Ｙ方向ピッチ１４０μｍ、高さ：１８μｍ、バンプ数１２００
　なお、それぞれに３箇所のアライメントマークが配置されている。 <Manufacturing of evaluation chips with solder bumps>
Step e3: Preparation of evaluation chip Six types of copper bumped chips (10 mm × 10 mm, thickness: 0.5 mm) shown below were prepared.
Chip C14 ... Size 8 x 4 μm, X-direction pitch 16 μm, Y-direction pitch 8 μm, height: 3 μm, number of bumps 382000
Chip C15 ... Size 16 μm × 8 μm, X-direction pitch 32 μm, Y-direction pitch 16 μm, height: 5 μm, number of bumps 95700
Chip C16 ... Size 24 μm × 12 μm, X-direction pitch 48 μm, Y-direction pitch 24 μm, height: 8 μm, number of bumps 42500
Chip C17: Size 72 μm × 36 μm, X-direction pitch 144 μm, Y-direction pitch 72 μm, height: 10 μm, number of bumps 4700
Chip C18: size 96 μm × 48 μm, X-direction pitch 192 μm, Y-direction pitch 96 μm, height: 13 μm, number of bumps 2600
Chip C19: Size 140 μm × 70 μm, X-direction pitch 280 μm, Y-direction pitch 140 μm, height: 18 μm, number of bumps 1200
In addition, three alignment marks are arranged in each.
＜はんだバンプ形成＞
工程ｆ６：はんだバンプ形成：真空加圧
　工程ｆ３のｉｉｉ）を以下の方法に代えたこと以外は、工程ｆ３と同じ方法ではんだバンプを形成し、評価した。評価結果を表１４に示す。
ｉｉｉ）チップＣ１４上に評価用基体１が載ったガラス板を、真空加圧式ラミネータ（ＭＶＬ－５００：株式会社日本製鋼所製）のキャリアフィルム上に配置した。上下加熱板温度を１５０℃に設定し、圧力０．５ＭＰａ、加圧時間１０ｓで処理した。その後、評価用基体１を取り除いた。続いて、メタノール溶液中にチップＣ１４を浸漬し、流動相を洗浄除去して、真空乾燥（４０℃で６０分）して、はんだバンプ付きの評価用チップ７９を得た。 <Solder bump formation>
Step f6: Solder bump formation: Vacuum pressurization Solder bumps were formed and evaluated by the same method as in step f3, except that iii) in step f3 was replaced with the following method. The evaluation results are shown in Table 14.
iii) A glass plate on which the evaluation substrate 1 was placed on the chip C14 was placed on a carrier film of a vacuum pressurizing laminator (MVL-500: manufactured by Japan Steel Works, Ltd.). The temperature of the upper and lower hot plates was set to 150 ° C., and the treatment was performed at a pressure of 0.5 MPa and a pressurization time of 10 s. Then, the evaluation substrate 1 was removed. Subsequently, the chip C14 was immersed in a methanol solution, the fluid phase was washed and removed, and vacuum dried (at 40 ° C. for 60 minutes) to obtain an evaluation chip 79 with solder bumps.
Figure JPOXMLDOC01-appb-T000014
Figure JPOXMLDOC01-appb-T000014
　工程ｆ６の方法を用い、表１４に示す組み合わせではんだバンプの形成を行い、評価用チップ８０～９６を得た。上記と同様に行った評価結果を表１４に示す。 Using the method of step f6, solder bumps were formed in the combinations shown in Table 14 to obtain evaluation chips 80 to 96. Table 14 shows the evaluation results obtained in the same manner as above.
　Ｃｕバンプ（電極）を有する評価用チップ７９～９６でも、良好なはんだバンプ形成ができた。 Good solder bumps could be formed even with the evaluation chips 79 to 96 having Cu bumps (electrodes).
＜接続構造体の作製＞
工程ｇ２：評価基板の準備
　下記に示す、６種類の金バンプ付き基板（４０×４０ｍｍ、厚さ：０．５ｍｍ）を準備した。このＡｕバンプの配置は、それぞれがチップＣ８～Ｃ１３のＡｕバンプに相対した位置となっており、位置合わせができるように、３箇所のアライメントマークがある。なお、これらの金バンプには抵抗測定用の引き出し配線も形成されている。
基板Ｄ８…対応するチップ：チップＣ８／サイズ８×４μｍ、Ｘ方向ピッチ１６μｍ、Ｙ方向ピッチ８μｍ、高さ：３μｍ、バンプ数３８２０００
基板Ｄ９…対応するチップ：チップＣ９／サイズ１６μｍ×８μｍ、Ｘ方向ピッチ３２μｍ、Ｙ方向ピッチ１６μｍ、高さ：５μｍ、バンプ数９５７００
基板Ｄ１０…対応するチップ：チップＣ１０／サイズ２４μｍ×１２μｍ、Ｘ方向ピッチ４８μｍ、Ｙ方向ピッチ２４μｍ、高さ：８μｍ、バンプ数４２５００
基板Ｄ１１…対応するチップ：チップＣ１１／サイズ７２μｍ×３６μｍ、Ｘ方向ピッチ１４４μｍ、Ｙ方向ピッチ７２μｍ、高さ：１０μｍ、バンプ数４７００
基板Ｄ１２…対応するチップ：チップＣ１２／サイズ９６μｍ×４８μｍ、Ｘ方向ピッチ１９２μｍ、Ｙ方向ピッチ９６μｍ、高さ：１３μｍ、バンプ数２６００
基板Ｄ１３…対応するチップ：チップＣ１３／サイズ１４０μｍ×７０μｍ、Ｘ方向ピッチ２８０μｍ、Ｙ方向ピッチ１４０μｍ、高さ：１８μｍ、バンプ数１２００ <Manufacturing of connection structure>
Step g2: Preparation of evaluation substrate Six types of substrates with gold bumps (40 × 40 mm, thickness: 0.5 mm) shown below were prepared. The arrangement of the Au bumps is a position relative to the Au bumps of the chips C8 to C13, respectively, and there are three alignment marks so that the alignment can be performed. The gold bumps are also formed with lead-out wiring for resistance measurement.
Substrate D8 ... Corresponding chip: Chip C8 / size 8 × 4 μm, pitch in X direction 16 μm, pitch in Y direction 8 μm, height: 3 μm, number of bumps 382000
Substrate D9 ... Corresponding chip: Chip C9 / size 16 μm × 8 μm, pitch in X direction 32 μm, pitch in Y direction 16 μm, height: 5 μm, number of bumps 95700
Substrate D10 ... Corresponding chip: Chip C10 / size 24 μm × 12 μm, pitch in X direction 48 μm, pitch in Y direction 24 μm, height: 8 μm, number of bumps 42500
Substrate D11 ... Corresponding chip: Chip C11 / size 72 μm × 36 μm, X-direction pitch 144 μm, Y-direction pitch 72 μm, height: 10 μm, number of bumps 4700
Substrate D12 ... Corresponding chip: Chip C12 / size 96 μm × 48 μm, X-direction pitch 192 μm, Y-direction pitch 96 μm, height: 13 μm, number of bumps 2600
Substrate D13 ... Corresponding chip: Chip C13 / size 140 μm × 70 μm, X-direction pitch 280 μm, Y-direction pitch 140 μm, height: 18 μm, number of bumps 1200
工程ｈ２：電極の接合
　以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｆ５で作製したはんだバンプ付きの評価用チップを用いて、金バンプ付き評価基板とはんだバンプを介して接続した。
ｉ）金バンプが形成された基板をフリップチップボンダー（ＦＣ３０００：東レ株式会社製）のステージに固定した。加熱加圧用ヘッドではんだバンプが形成された評価用チップをピックアップし、アライメントマークから互いの金バンプが対向する位置に配置した。
ｉｉ）評価用チップが載った基板を、ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板上に置き、評価用チップ上部にステンレス製の錘を置いた。
ｉｉｉ）ギ酸真空リフロー炉を作動させ、真空引きの後、ギ酸ガスを充填し、下部熱板を１５０℃に昇温し、５分加熱した。その後、真空引きにてギ酸ガスを排出後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気に開放した。評価チップと評価基板の間に粘度を調整したアンダーフィル材（日立化成株式会社製、ＣＥＬシリーズ）を適量入れ、真空引きにて充填後、１２５℃で４時間硬化させ、評価チップと評価基板の接続構造体を作製した。 Step h2: Joining the electrodes According to the procedures i) to iii) shown below, the evaluation chip with solder bumps produced in step f5 was used to connect the evaluation substrate with gold bumps to the evaluation substrate with solder bumps.
i) The substrate on which the gold bumps were formed was fixed to the stage of a flip chip bonder (FC3000: manufactured by Toray Industries, Inc.). The evaluation chips on which the solder bumps were formed were picked up by the heating and pressurizing head and placed at positions where the gold bumps face each other from the alignment mark.
ii) The substrate on which the evaluation chip was placed was placed on the lower hot plate of a formic acid reflow furnace (manufactured by Shinko Seiki Co., Ltd., batch type vacuum soldering device), and a stainless steel weight was placed on the upper part of the evaluation chip.
iii) The formic acid vacuum reflow furnace was operated, evacuated, filled with formic acid gas, the temperature of the lower hot plate was raised to 150 ° C., and the mixture was heated for 5 minutes. Then, after discharging formic acid gas by evacuation, nitrogen substitution was performed, the lower hot plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere. An appropriate amount of underfill material (CEL series manufactured by Hitachi Kasei Co., Ltd.) whose viscosity has been adjusted is placed between the evaluation chip and the evaluation substrate, filled by vacuuming, and then cured at 125 ° C. for 4 hours to form the evaluation chip and the evaluation substrate. A connection structure was prepared.
＜接続構造体の評価＞
　得られた接続構造体の一部について、工程：ｈ１と同様に導通抵抗試験及び絶縁抵抗試験を行った。結果を表１５、１６、１７に示す。 <Evaluation of connection structure>
A part of the obtained connection structure was subjected to a conduction resistance test and an insulation resistance test in the same manner as in Step: h1. The results are shown in Tables 15, 16 and 17.
Figure JPOXMLDOC01-appb-T000015
Figure JPOXMLDOC01-appb-T000015
Figure JPOXMLDOC01-appb-T000016
Figure JPOXMLDOC01-appb-T000016
Figure JPOXMLDOC01-appb-T000017
Figure JPOXMLDOC01-appb-T000017
＜接続構造体の作製＞
工程ｇ３：評価基板の準備
　下記に示す、６種類の銅バンプ付き基板（４０×４０ｍｍ、厚さ：０．５ｍｍ）を準備した。このＣｕバンプの配置は、それぞれがチップＣ１４～Ｃ１９のＣｕバンプに相対した位置となっており、位置合わせができるように、３箇所のアライメントマークがある。なお、これらのＣｕバンプには抵抗測定用の引き出し配線も形成されている。
基板Ｄ１４…対応するチップ：チップＣ１４／サイズ８×４μｍ、Ｘ方向ピッチ１６μｍ、Ｙ方向ピッチ８μｍ、高さ：３μｍ、バンプ数３８２０００
基板Ｄ１５…対応するチップ：チップＣ１５／サイズ１６μｍ×８μｍ、Ｘ方向ピッチ３２μｍ、Ｙ方向ピッチ１６μｍ、高さ：５μｍ、バンプ数９５７００
基板Ｄ１６…対応するチップ：チップＣ１６／サイズ２４μｍ×１２μｍ、Ｘ方向ピッチ４８μｍ、Ｙ方向ピッチ２４μｍ、高さ：８μｍ、バンプ数４２５００
基板Ｄ１７…対応するチップ：チップＣ１７／サイズ７２μｍ×３６μｍ、Ｘ方向ピッチ１４４μｍ、Ｙ方向ピッチ７２μｍ、高さ：１０μｍ、バンプ数４７００
基板Ｄ１８…対応するチップ：チップＣ１８／サイズ９６μｍ×４８μｍ、Ｘ方向ピッチ１９２μｍ、Ｙ方向ピッチ９６μｍ、高さ：１３μｍ、バンプ数２６００
基板Ｄ１９…対応するチップ：チップＣ１９／サイズ１４０μｍ×７０μｍ、Ｘ方向ピッチ２８０μｍ、Ｙ方向ピッチ１４０μｍ、高さ：１８μｍ、バンプ数１２００ <Manufacturing of connection structure>
Step g3: Preparation of evaluation substrate Six types of substrates with copper bumps (40 × 40 mm, thickness: 0.5 mm) shown below were prepared. The Cu bumps are arranged at positions relative to the Cu bumps of the chips C14 to C19, and there are three alignment marks so that the Cu bumps can be aligned. The Cu bumps are also formed with lead-out wiring for resistance measurement.
Substrate D14 ... Corresponding chip: Chip C14 / size 8 × 4 μm, pitch in X direction 16 μm, pitch in Y direction 8 μm, height: 3 μm, number of bumps 382000
Substrate D15 ... Corresponding chip: Chip C15 / size 16 μm × 8 μm, pitch in X direction 32 μm, pitch in Y direction 16 μm, height: 5 μm, number of bumps 95700
Substrate D16 ... Corresponding chip: Chip C16 / size 24 μm × 12 μm, pitch in X direction 48 μm, pitch in Y direction 24 μm, height: 8 μm, number of bumps 42500
Substrate D17 ... Corresponding chip: Chip C17 / size 72 μm × 36 μm, X-direction pitch 144 μm, Y-direction pitch 72 μm, height: 10 μm, number of bumps 4700
Substrate D18 ... Corresponding chip: Chip C18 / size 96 μm × 48 μm, X-direction pitch 192 μm, Y-direction pitch 96 μm, height: 13 μm, number of bumps 2600
Substrate D19 ... Corresponding chip: Chip C19 / size 140 μm × 70 μm, X-direction pitch 280 μm, Y-direction pitch 140 μm, height: 18 μm, number of bumps 1200
工程ｈ３：電極の接合
　以下に示すｉ）～ｉｉｉ）の手順に従い、工程ｆ６で作製したはんだバンプ付きの評価用チップを用いて、銅バンプ付き評価基板とはんだバンプを介して接続した。
ｉ）評価基板をスピンコーター（ＳＣ－３０８Ｓ　有限会社押鐘製）にセットし、Ｃｕバンプが形成された表面にフラックス（ＷＨＳ－００３Ｃ：荒川化学工業製製）を０．５ｍｌ垂らした。回転数５００ｒｐｍで１０ｓ、その後１０００ｒｐｍで３ｓ処理して、薄膜のフラックス層を形成した。
ｉｉ）評価基板をフリップチップボンダー（ＦＣ３０００：株式会社東レ製）のステージに固定した。加熱加圧用ヘッドではんだバンプが形成された評価用チップをピックアップし、アライメントマークから互いのバンプが対向する位置に配置した。評価用チップが載った基板を、ギ酸リフロー炉（神港精機株式会社製、バッチ式真空半田付装置）の下部熱板上に置き、評価用チップ上部にステンレス製の錘を置いた。
ｉｉｉ）ギ酸真空リフロー炉を作動させ、真空引きの後、ギ酸ガスを充填し、下部熱板を１６０℃に昇温し、３分加熱した。その後、真空引きにてギ酸ガスを排出後、窒素置換を行い、下部熱板を室温まで戻し、炉内を大気に開放した。評価チップと評価基板の間に粘度を調整したアンダーフィル材（日立化成株式会社製、ＣＥＬシリーズ）を適量入れ、真空引きにて充填後、１２５℃で４時間硬化させ、評価チップと評価基板の接続構造体を作製した。 Step h3: Joining the electrodes According to the procedures i) to iii) shown below, the evaluation chip with solder bumps produced in step f6 was used to connect to the evaluation substrate with copper bumps via the solder bumps.
i) The evaluation substrate was set on a spin coater (SC-308S manufactured by Oshigane Co., Ltd.), and 0.5 ml of flux (WHS-003C: manufactured by Arakawa Chemical Industry Co., Ltd.) was dropped on the surface on which Cu bumps were formed. A thin film flux layer was formed by treating at a rotation speed of 500 rpm for 10 s and then at 1000 rpm for 3 s.
ii) The evaluation substrate was fixed to the stage of a flip chip bonder (FC3000: manufactured by Toray Industries, Inc.). The evaluation chips on which the solder bumps were formed were picked up by the heating and pressurizing head and placed at positions where the bumps face each other from the alignment mark. The substrate on which the evaluation chip was placed was placed on the lower heating plate of a formic acid reflow furnace (manufactured by Shinko Seiki Co., Ltd., a batch type vacuum soldering device), and a stainless steel weight was placed on the upper part of the evaluation chip.
iii) The formic acid vacuum reflow furnace was operated, evacuated, filled with formic acid gas, the temperature of the lower hot plate was raised to 160 ° C., and the mixture was heated for 3 minutes. Then, after discharging formic acid gas by evacuation, nitrogen substitution was performed, the lower hot plate was returned to room temperature, and the inside of the furnace was opened to the atmosphere. An appropriate amount of underfill material (CEL series manufactured by Hitachi Kasei Co., Ltd.) whose viscosity has been adjusted is placed between the evaluation chip and the evaluation substrate, filled by vacuuming, and then cured at 125 ° C. for 4 hours to form the evaluation chip and the evaluation substrate. A connection structure was prepared.
＜接続構造体の評価＞
　得られた接続構造体の一部について、工程：ｈ１と同様に導通抵抗試験及び絶縁抵抗試験を行った。結果を表１８、１９、２０に示す。 <Evaluation of connection structure>
A part of the obtained connection structure was subjected to a conduction resistance test and an insulation resistance test in the same manner as in Step: h1. The results are shown in Tables 18, 19 and 20.
Figure JPOXMLDOC01-appb-T000018
Figure JPOXMLDOC01-appb-T000018
Figure JPOXMLDOC01-appb-T000019
Figure JPOXMLDOC01-appb-T000019
Figure JPOXMLDOC01-appb-T000020
Figure JPOXMLDOC01-appb-T000020
　Ｃｕ電極へ形成したはんだバンプを介してＣｕ電極同士を接合した場合も、安定した接続特性を示した。 Stable connection characteristics were also shown when the Cu electrodes were joined to each other via solder bumps formed on the Cu electrodes.
　１…はんだ粒子、１Ａ…はんだバンプ、１Ｂ…はんだ層、２…基板、３…電極、４…他の基板、５…他の電極、１０…はんだバンプ形成用部材、２０…はんだバンプ付き電極基板、３０…接続構造体、６０…基体、６２…凹部、１１１…はんだ微粒子、Ｆ…流動化剤、６００…基体、６０１…ベース層、６０２…凹部層。

  1 ... Solder particles, 1A ... Solder bumps, 1B ... Solder layer, 2 ... Substrate, 3 ... Electrodes, 4 ... Other substrates, 5 ... Other electrodes, 10 ... Solder bump forming members, 20 ... Electrode substrates with solder bumps , 30 ... Connection structure, 60 ... Base, 62 ... Recess, 111 ... Solder fine particles, F ... Fluidizer, 600 ... Base, 601 ... Base layer, 602 ... Recess layer.

Claims (18)

  1. 　複数の凹部を有する基体と、前記凹部内にはんだ粒子及び流動化剤と、を備え、
    　前記はんだ粒子の平均粒子径が１～３５μｍであり、Ｃ．Ｖ．値が２０％以下である、はんだバンプ形成用部材。     A substrate having a plurality of recesses, and solder particles and a fluidizing agent in the recesses are provided.
    The average particle size of the solder particles is 1 to 35 μm, and C.I. V. A member for forming solder bumps having a value of 20% or less.
  2. 　前記流動化剤が、コハク酸、グルタル酸、アジピン酸、ピメリン酸、スベリン酸、安息香酸、及びリンゴ酸からなる群より選択される少なくとも一種を含む、請求項１に記載のはんだバンプ形成用部材。 The solder bump forming member according to claim 1, wherein the fluidizing agent contains at least one selected from the group consisting of succinic acid, glutaric acid, adipic acid, pimelic acid, suberic acid, benzoic acid, and malic acid. ..
  3. 　前記はんだ粒子の表面の一部に平面部が形成されている、請求項１又は２に記載のはんだバンプ形成用部材。 The solder bump forming member according to claim 1 or 2, wherein a flat surface portion is formed on a part of the surface of the solder particles.
  4. 　隣接する前記凹部間の距離が、前記はんだ粒子の平均粒子径の０．１倍以上である、請求項１～３のいずれか一項に記載のはんだバンプ形成用部材。 The solder bump forming member according to any one of claims 1 to 3, wherein the distance between the adjacent recesses is 0.1 times or more the average particle diameter of the solder particles.
  5. 　複数の凹部を有する基体、並びにはんだ粒子及び流動化剤を準備する前工程と、
    　前記凹部に、前記はんだ粒子及び前記流動化剤を配置する配置工程と、
    を備える、はんだバンプ形成用部材の製造方法。     A pre-process for preparing a substrate having a plurality of recesses, solder particles, and a fluidizing agent, and
    An arrangement step of arranging the solder particles and the fluidizing agent in the recess, and
    A method for manufacturing a member for forming a solder bump.
  6. 　前記はんだ粒子の平均粒子径が１～３５μｍであり、Ｃ．Ｖ．値が２０％以下である、請求項５に記載の製造方法。 The average particle size of the solder particles is 1 to 35 μm, and C.I. V. The production method according to claim 5, wherein the value is 20% or less.
  7. 　複数の凹部を有する基体及びはんだ微粒子を準備する準備工程と、
    　前記はんだ微粒子の少なくとも一部を、前記凹部に収容する収容工程と、
    　前記凹部に収容された前記はんだ微粒子を融合させて、前記凹部内にはんだ粒子を形成する融合工程と、
    　前記はんだ粒子が形成された前記凹部内に流動化剤を配置する注入工程と、
    を備える、はんだバンプ形成用部材の製造方法。     A preparatory process for preparing a substrate having a plurality of recesses and solder fine particles, and
    An accommodating step of accommodating at least a part of the solder fine particles in the recess,
    A fusion step of fusing the solder fine particles contained in the recess to form solder particles in the recess.
    An injection step of arranging a fluidizing agent in the recess in which the solder particles are formed, and
    A method for manufacturing a member for forming a solder bump.
  8. 　前記はんだ粒子の平均粒子径が１～３５μｍであり、Ｃ．Ｖ．値が２０％以下である、請求項７に記載の製造方法。 The average particle size of the solder particles is 1 to 35 μm, and C.I. V. The production method according to claim 7, wherein the value is 20% or less.
  9. 　前記はんだ微粒子のＣ．Ｖ．値が２０％を超える、請求項７又は８に記載の製造方法。 C. of the solder fine particles. V. The production method according to claim 7 or 8, wherein the value exceeds 20%.
  10. 　前記融合工程の前に、前記凹部に収容された前記はんだ微粒子を還元雰囲気に晒す還元工程を更に備える、請求項７～９のいずれか一項に記載の製造方法。 The production method according to any one of claims 7 to 9, further comprising a reduction step of exposing the solder fine particles contained in the recesses to a reducing atmosphere before the fusion step.
  11. 　前記融合工程において、前記はんだ微粒子を還元雰囲気下で融合させる、請求項７～１０のいずれか一項に記載の製造方法。 The production method according to any one of claims 7 to 10, wherein in the fusion step, the solder fine particles are fused in a reducing atmosphere.
  12. 　請求項１～４のいずれか一項に記載のはんだバンプ形成用部材、及び複数の電極を有する基板、を準備する準備工程と、
    　前記はんだバンプ形成用部材の前記凹部を有する面及び前記基板の前記電極を有する面を対向させて接触させる配置工程と、
    　前記はんだ粒子をはんだ粒子の融点以上の温度に加熱する加熱工程と、
    を備える、はんだバンプ付き電極基板の製造方法。     A preparatory step for preparing the solder bump forming member according to any one of claims 1 to 4 and a substrate having a plurality of electrodes.
    An arrangement step in which the surface of the solder bump forming member having the recess and the surface of the substrate having the electrode are brought into contact with each other so as to face each other.
    A heating step of heating the solder particles to a temperature equal to or higher than the melting point of the solder particles,
    A method for manufacturing an electrode substrate with solder bumps.
  13. 　前記加熱工程において、前記はんだバンプ形成用部材及び前記基板を加圧状態で接触させながら、前記はんだ粒子をはんだ粒子の融点以上の温度に加熱する、請求項１２に記載の製造方法。 The manufacturing method according to claim 12, wherein in the heating step, the solder particles are heated to a temperature equal to or higher than the melting point of the solder particles while the solder bump forming member and the substrate are brought into contact with each other in a pressurized state.
  14. 　前記配置工程の前に、前記はんだ粒子を還元雰囲気に晒す還元工程を更に備える、請求項１２又は１３に記載の製造方法。 The manufacturing method according to claim 12 or 13, further comprising a reduction step of exposing the solder particles to a reducing atmosphere before the placement step.
  15. 　前記配置工程の後であって前記加熱工程の前に、前記はんだ粒子を還元雰囲気に晒す還元工程を更に備える、請求項１２～１４のいずれか一項に記載の製造方法。 The production method according to any one of claims 12 to 14, further comprising a reduction step of exposing the solder particles to a reducing atmosphere after the placement step and before the heating step.
  16. 　前記加熱工程において、還元雰囲気下で前記はんだ粒子をはんだ粒子の融点以上の温度に加熱する、請求項１２～１５のいずれか一項に記載の製造方法。 The production method according to any one of claims 12 to 15, wherein in the heating step, the solder particles are heated to a temperature equal to or higher than the melting point of the solder particles in a reducing atmosphere.
  17. 　前記加熱工程の後に、前記はんだバンプ形成用部材を前記基板から除去する除去工程を更に備える、請求項１２～１６のいずれか一項に記載の製造方法。 The manufacturing method according to any one of claims 12 to 16, further comprising a removing step of removing the solder bump forming member from the substrate after the heating step.
  18. 　前記除去工程の後に、前記電極に結合していない前記はんだ粒子を除去する洗浄工程を更に備える、請求項１７に記載の製造方法。

          The manufacturing method according to claim 17, further comprising a cleaning step of removing the solder particles not bonded to the electrode after the removing step.
PCT/JP2020/046731 2019-12-27 2020-12-15 Solder bump forming member, method for manufacturing solder bump forming member, and method for manufacturing electrode substrate provided with solder bump WO2021131897A1 (en)

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JPH05235061A (en) * 1991-08-28 1993-09-10 Hitachi Ltd Electronic circuit joining device and method, solder ball, and aligning mark
JPH07249631A (en) * 1994-01-20 1995-09-26 Fujitsu Ltd Manufacture of solder bumps and solder ball and manufacture of semiconductor device
JPH1079404A (en) * 1996-09-03 1998-03-24 Ngk Spark Plug Co Ltd Wiring board having solder bump and manufacturing method thereof
WO2006043377A1 (en) * 2004-10-19 2006-04-27 Senju Metal Industry Co., Ltd. Sheet for forming solder bump and method for manufacture thereof
JP2010036234A (en) * 2008-08-07 2010-02-18 Mitsui Mining & Smelting Co Ltd Solder powder and solder paste
WO2010125753A1 (en) * 2009-04-30 2010-11-04 昭和電工株式会社 Process for production of circuit board

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JPH0523887A (en) * 1991-07-19 1993-02-02 Matsushita Electric Ind Co Ltd Method for forming metal ball
JPH05235061A (en) * 1991-08-28 1993-09-10 Hitachi Ltd Electronic circuit joining device and method, solder ball, and aligning mark
JPH07249631A (en) * 1994-01-20 1995-09-26 Fujitsu Ltd Manufacture of solder bumps and solder ball and manufacture of semiconductor device
JPH1079404A (en) * 1996-09-03 1998-03-24 Ngk Spark Plug Co Ltd Wiring board having solder bump and manufacturing method thereof
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