WO2021131760A1

WO2021131760A1 - Semiconductor photodetection element

Info

Publication number: WO2021131760A1
Application number: PCT/JP2020/046133
Authority: WO
Inventors: 晃永山本; 隆裕近藤; 弘典園部; 輝昌永野; 龍太郎土屋; 守弘幸田; 鈴木　義之
Original assignee: 浜松ホトニクス株式会社
Priority date: 2019-12-26
Filing date: 2020-12-10
Publication date: 2021-07-01
Also published as: JP2021106196A

Abstract

A semiconductor photodetection element (1) comprises: a first-conductivity-type silicon substrate (11) comprising a first main surface (11a) and second main surface (11b) that are opposite from each other, and a polysilicon layer (19) comprising a third main surface (19a) and fourth main surface (19b) that are opposite from each other. The polysilicon layer (19) is disposed on the silicon substrate (11) such that the third main surface (19a) faces the first main surface (11a). The silicon substrate (11) comprises a first area (R1) including a part of the first main surface (11a), and a second area (R2) including another part of the first main surface (11a). A second-conductivity-type first semiconductor area (13) is formed in the first area (R1). A first-conductivity-type second semiconductor area (15) is formed in the second area (R2). A plurality of depressions (21) that are open at the fourth main surface (19b) are formed in the polysilicon layer (19).

Description

Semiconductor photodetector

The present invention relates to a semiconductor photodetector.

A known semiconductor photodetector includes a silicon substrate having a first main surface and a second main surface facing each other (see, for example, Patent Document 1). Irregular irregularities are formed on the silicon substrate included in this semiconductor photodetector. In Patent Document 1, irregular irregularities are formed by irradiating a silicon substrate with a laser beam.

The light incident on the semiconductor photodetector is reflected, scattered, or diffused in the region where irregular irregularities are formed, and travels a long distance in the silicon substrate. Most of the light incident on the semiconductor photodetector is difficult to pass through the silicon substrate and is absorbed by the silicon substrate. The mileage of the light incident on the semiconductor photodetector becomes longer, and the distance at which the light is absorbed also becomes longer. Therefore, the semiconductor photodetector improves the spectral sensitivity characteristic in the near infrared wavelength band.

Japanese Unexamined Patent Publication No. 2010-226071

Crystal damage (crystal defects) may occur in the region where irregular irregularities are formed on the silicon substrate, and the crystallinity of the silicon substrate may deteriorate. When the crystallinity of the silicon substrate deteriorates, electric charges may be generated on the silicon substrate regardless of the incident of light. The electric charge generated regardless of the incident of light may generate a dark current.

One aspect of the present invention is to provide a semiconductor photodetector that improves the spectral sensitivity characteristics in the near infrared wavelength band and suppresses the generation of dark current.

The semiconductor photodetector according to one embodiment includes a first conductive silicon substrate having a first main surface and a second main surface facing each other, and a third main surface and a second main surface facing each other. It is provided with a polysilicon layer having four main surfaces. The polysilicon layer is arranged on the silicon substrate so that the third main surface faces the first main surface. The silicon substrate includes a first region including a part of the first main surface and a second region including another part of the first main surface. A second conductive type first semiconductor region is formed in the first region. In the second region, a first conductive type second semiconductor region is formed. The polysilicon layer is arranged on a part of the first main surface included in the first region. The polysilicon layer is formed with a plurality of depressions that open on the fourth main surface.

In the above one aspect, when light is incident on the fourth main surface, the light is scattered on the fourth main surface of the polysilicon layer in which a plurality of depressions are formed. The scattered light travels in the polysilicon layer, enters the silicon substrate from the first main surface, and travels in various directions in the silicon substrate. Therefore, the above one aspect increases the mileage of light in the silicon substrate as compared with the configuration in which the polysilicon layer is not arranged. Since the light incident on the silicon substrate travels a long distance in the silicon substrate, more light is converted into electric charges. As a result, the above-mentioned one aspect improves the spectral sensitivity characteristics in the near-infrared wavelength band.

In the above one aspect, crystal damage due to the formation of a plurality of depressions is unlikely to occur on the silicon substrate. Therefore, the crystallinity of the silicon substrate is unlikely to deteriorate. As a result, the above-mentioned one aspect suppresses the generation of dark current.

In the above one aspect, in the first region, the first conductive type third semiconductor region having a higher impurity concentration than the silicon substrate contained in the first region is closer to the second main surface than the first semiconductor region. It may be formed.

In the above one aspect, the silicon substrate is located between the first conductive type epitaxial semiconductor region including the first region and the second region, and the second main surface and the axial semiconductor region. It may have a conductive type fourth semiconductor region. In this case, the fourth semiconductor region has a higher impurity concentration than the epitaxial semiconductor region.

In one aspect described above, the plurality of depressions may be formed in the polysilicon layer so as to be regularly arranged.
When irregular irregularities are formed on the polysilicon layer, the shape or size of the irregularities may differ from product to product. If the shape or size of the unevenness is different, the spectral sensitivity characteristics may vary between products.
The configuration in which the plurality of depressions are regularly arranged in the polysilicon layer is unlikely to cause variations in the spectral sensitivity characteristics.

In the above one aspect, the polysilicon layer may be of the second conductive type, and the first semiconductor region and the polysilicon layer may be in contact with each other. In this case, the polysilicon layer can function as an electrode. Therefore, the need to newly provide an electrode for extracting the electric charge from the first semiconductor region is reduced. A portion of the charge generated by the polysilicon layer can be included in the output signal. Therefore, the configuration in which the polysilicon layer is the second conductive type and the first semiconductor region and the polysilicon layer are in contact with each other improves the spectral sensitivity characteristics in the near infrared wavelength band.

One aspect described above may include an insulating layer arranged between the silicon substrate and the polysilicon layer. In this case, the formation of a plurality of depressions in the polysilicon layer can be easily performed while further suppressing the influence on the silicon substrate.

In the above one aspect, the plurality of depressions may also be open to the third main surface, and a part of the insulating layer may be exposed in the plurality of depressions. In this case, since the depth of each recess is defined by the thickness of the polysilicon layer, the depth of each recess is controlled with high accuracy.

In the above one aspect, each surface of the plurality of depressions may be curved.

In the above one aspect, the plurality of depressions may be formed by isotropic etching.

The above one aspect may include a reflective film arranged on the second main surface. In this case, the light traveling through the silicon substrate and reaching the second main surface is incident on the reflective film and reflected by the reflective film. The light reflected by the reflective film travels further in the silicon substrate. Therefore, the mileage of light in the silicon substrate is further increased, and more light is converted into electric charges. As a result, the configuration in which the reflective film is arranged on the second main surface further improves the spectral sensitivity characteristics in the near-infrared wavelength band.

The above one aspect may include a support substrate arranged so as to face the second main surface. In this case, the support substrate improves the mechanical strength of the semiconductor photodetector.

In the above one aspect, the silicon substrate may have a plurality of cells including a first region and a second region, and the plurality of cells may be electrically connected in parallel.

In the above one aspect, trenches for physically separating adjacent cells among a plurality of cells may be formed in a grid pattern on the silicon substrate when viewed from a direction orthogonal to the first main surface. , The polysilicon layer does not have to be located on the trench.

One or more aspects of the present invention provide a semiconductor photodetector that improves spectral sensitivity characteristics in the near-infrared wavelength band and suppresses the generation of dark current.

FIG. 1 is a diagram showing a cross-sectional configuration of a semiconductor photodetector according to the first embodiment. FIG. 2 is a diagram showing an example of an arrangement of a plurality of depressions. FIG. 3 is a diagram showing an example of an arrangement of a plurality of depressions. FIG. 4 is a diagram showing a process of forming a plurality of depressions. FIG. 5 is a diagram showing a cross-sectional configuration of the semiconductor photodetector according to the first modification of the first embodiment. FIG. 6 is a diagram showing a cross-sectional configuration of a semiconductor photodetector according to a second modification of the first embodiment. FIG. 7 is a diagram showing a cross-sectional configuration of a semiconductor photodetector according to a third modification of the first embodiment. FIG. 8 is a diagram showing a cross-sectional configuration of a semiconductor photodetector according to a third modification of the first embodiment. FIG. 9 is a diagram showing a cross-sectional configuration of the semiconductor photodetector according to the second embodiment. FIG. 10 is a plan view showing a semiconductor photodetector according to the second embodiment. FIG. 11 is a diagram showing a cross-sectional configuration of the semiconductor photodetector. FIG. 12 is a diagram showing a cross-sectional configuration of the semiconductor photodetector. FIG. 13 is a diagram showing a cross-sectional configuration of the semiconductor photodetector. FIG. 14 is a diagram showing a cross-sectional configuration of the semiconductor photodetector.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals will be used for the same elements or elements having the same function, and duplicate description will be omitted.

(First Embodiment)
The configuration of the semiconductor photodetector 1 according to the first embodiment will be described with reference to FIG. FIG. 1 is a diagram showing a cross-sectional configuration of a semiconductor photodetector according to the first embodiment. In the first embodiment, the semiconductor photodetector 1 is, for example, a surface incident type avalanche photodiode.

As shown in FIG. 1, the semiconductor photodetector 1 includes a semiconductor substrate 11. The semiconductor substrate 11 is a substrate made of silicon (Si). The semiconductor substrate 11 has a main surface 11a and a main surface 11b facing each other. The main surface 11a is a light incident surface on the semiconductor substrate 11. The main surface 11a is the front surface and the main surface 11b is the back surface. In the present embodiment, the main surface 11a and the main surface 11b are flat surfaces. The thickness of the semiconductor substrate 11 is, for example, 100 to 625 μm. For example, when the main surface 11a constitutes the first main surface, the main surface 11b constitutes the second main surface.

The semiconductor substrate 11 has a first conductive type epitaxial semiconductor region 12a and a first conductive type semiconductor region 12b. The semiconductor region 12b constitutes the substrate of the semiconductor substrate 11. The epitaxial semiconductor region 12a is formed on the semiconductor region 12b by the epitaxial growth method. The epitaxial semiconductor region 12a is a region including the main surface 11a. The semiconductor region 12b is located closer to the main surface 11b than the epitaxial semiconductor region 12a. The semiconductor region 12b is located between the epitaxial semiconductor region 12a and the main surface 11b. In the present embodiment, the semiconductor region 12b is a region including the main surface 11b. In the present embodiment, the semiconductor substrate 11 is composed of an epitaxial semiconductor region 12a and a semiconductor region 12b.

The first conductive type is, for example, the p type. The second conductive type is, for example, n type. When the semiconductor substrate 11 is made of Si, the p-type impurity contains, for example, a Group 13 element, and the n-type impurity contains, for example, a Group 15 element. The n-type impurities are, for example, nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). The p-type impurity is, for example, boron (B) or aluminum (Al). The first conductive type may be n type, and the second conductive type may be p type.
The impurity concentration in the semiconductor region 12b is higher than the impurity concentration in the epitaxial semiconductor region 12a. The impurity concentration in the semiconductor region 12b is, for example, 1 × 10 ¹⁸ cm ^-3 . The impurity concentration in the epitaxial semiconductor region 12a is, for example, 1 × 10 ¹⁴ cm ^-3 .

The semiconductor substrate 11 has a second conductive type semiconductor region 13, a first conductive type semiconductor region 15, and a first conductive type semiconductor region 17. The

semiconductor regions

13, 15 and 17 are formed in the epitaxial semiconductor region 12a. The semiconductor region 13 and the semiconductor region 15 are arranged on the main surface 11a side of the semiconductor substrate 11. The semiconductor region 13 and the semiconductor region 15 are regions including the main surface 11a. The semiconductor region 17 is located closer to the main surface 11b than the semiconductor region 13. The semiconductor region 13 and the semiconductor region 17 are formed so as to be separated from each other. The semiconductor region 13 and the semiconductor region 17 may be formed so as to be in contact with each other.

Each of the

semiconductor regions

13, 15 and 17 has a high impurity concentration. Each of the

semiconductor regions

13, 15 and 17 has a higher impurity concentration than the epitaxial semiconductor region 12a. The impurity concentration of the semiconductor region 13 is, for example, 1 × 10 ¹⁹ cm ^-3 . The impurity concentration of the semiconductor region 15 is, for example, 1 × 10 ¹⁹ cm ^-3 . The impurity concentration of the semiconductor region 17 is, for example, 1 × 10 ¹⁶ cm ^-3 . The thickness of the semiconductor region 13 is, for example, 0.5 μm. The thickness of the semiconductor region 15 is, for example, 1.0 μm. The thickness of the semiconductor region 17 is, for example, 2.0 μm.

The epitaxial semiconductor region 12a and the semiconductor region 13 form a pn junction. The pn junction is formed at the boundary between the epitaxial semiconductor region 12a and the semiconductor region 13. In the configuration in which the semiconductor region 13 and the semiconductor region 17 are formed so as to be in contact with each other, the semiconductor region 13 and the semiconductor region 17 form a pn junction. The semiconductor region 13 and the semiconductor region 15 are separated from each other. When viewed from the direction orthogonal to the main surface 11a, the semiconductor region 15 is located outside the semiconductor region 13 so as to surround the semiconductor region 13. The semiconductor region 15 is formed continuously or intermittently outside the semiconductor region 13. The semiconductor region 15 is formed in a region on the main surface 11a side of the semiconductor substrate 11 where the semiconductor region 13 is not formed.

The semiconductor substrate 11 includes a region R1 in which the

semiconductor regions

13 and 17 are formed and a region R2 in which the semiconductor region 15 is formed. Region R1 includes a part of the main surface 11a. The region R2 includes another part of the main surface 11a that is different from the part of the main surface 11a included in the region R1. The epitaxial semiconductor region 12a includes a region R1 and a region R2. For example, when the region R1 constitutes the first region, the region R2 constitutes the second region. For example, when the semiconductor region 13 constitutes the first semiconductor region, the semiconductor region 15 constitutes the second semiconductor region, the semiconductor region 17 constitutes the third semiconductor region, and the semiconductor region 12b constitutes the fourth semiconductor region. .. The semiconductor photodetector 1 includes an electrode electrically connected to the semiconductor region 13 (not shown) and an electrode electrically connected to the semiconductor region 15 (not shown).

The semiconductor light detection element 1 includes a polysilicon layer 19. The polysilicon layer 19 has a main surface 19a and a main surface 19b facing each other. The polysilicon layer 19 is arranged on the semiconductor substrate 11 so that the main surface 19a faces the main surface 11a. In this embodiment, the polysilicon layer 19 is arranged directly on the semiconductor substrate 11. For example, when the main surface 19a constitutes the third main surface, the main surface 19b constitutes the fourth main surface. In this embodiment, the main surface 19a is a flat surface. The thickness of the polysilicon layer 19 is, for example, 0.1 to 1.0 μm.

The polysilicon layer 19 is arranged on a part of the main surface 11a included in the region R1. The polysilicon layer 19 is arranged on the semiconductor region 13. The polysilicon layer 19 is not disposed on another part of the main surface 11a included in the region R2. In this embodiment, the polysilicon layer 19 is in contact with the main surface 11a. The polysilicon layer 19 is in contact with the semiconductor region 13. In a configuration in which the polysilicon layer 19 is in contact with the semiconductor region 13, the polysilicon layer 19 may be of the second conductive type. In this case, for example, phosphorus (P) may be added to the polysilicon layer 19.

A plurality of recesses 21 are formed in the polysilicon layer 19. Each recess 21 is open to the main surface 19b. The plurality of recesses 21 are formed in the polysilicon layer 19 so as to be regularly arranged. The depth of the recess 21 is, for example, 0.1 to 1.0 μm. In the present embodiment, the depth of the recess 21 may be smaller than the maximum thickness of the polysilicon layer 19.
The semiconductor substrate 11 (semiconductor region 13) may be formed with a recess continuous with the recess 21. In this case, the recess formed in the semiconductor substrate 11 does not have to reach the interface between the semiconductor region 13 and the epitaxial semiconductor region 12a. That is, the depth of the recess formed in the semiconductor substrate 11 may be less than the thickness of the semiconductor region 13. In the configuration in which the recess 21 continuous with the recess 21 is formed in the semiconductor region 13, the depth of the recess formed over the polysilicon layer 19 and the semiconductor region 13 is larger than the maximum thickness of the polysilicon layer 19.
The thickness of the polysilicon layer 19 varies according to the surface shape of the plurality of recesses 21. The region of the main surface 19b where the recess 21 is not formed is flat.

The plurality of recesses 21 may be arranged two-dimensionally, for example, as shown in FIGS. 2 and 3. In this case, the plurality of recesses 21 may be arranged at equal intervals in two directions orthogonal to each other. The plurality of depressions 21 shown in FIGS. 2 and 3 are arranged at equal intervals in the X and Y directions orthogonal to each other. A flat surface formed by the main surface 19b may be located between the recesses 21 adjacent to each other. The flat surface may be continuous so as to surround the opening of each recess 21. In this case, the flat surface has a substantially grid pattern. 2 and 3 are diagrams showing an example of an arrangement of a plurality of depressions. FIG. 3 is an observation of the main surface 19b in which the plurality of recesses 21 are formed from an angle of 65 ° when the direction orthogonal to the plane (main surface 11a) of the semiconductor substrate 11 is defined as 0 °. It is an SEM image.

The surface of each recess 21 may be curved, as shown in FIG. That is, the surface of each recess 21 may have a concave shape. The shape of the inner space of the recess 21 is a partial sphere. Each recess 21 has the same shape. Deepest position of the recesses 21 adjacent to each other, i.e., the apex of the inner space of the recess 21, the spacing in the X direction (pitch) _{P X} is, for example, 0.1 ~ 2.0 .mu.m. The deepest position of the recesses 21 adjacent to each other, that is, the interval (pitch) P _Y of the vertices of the inner space of the recesses 21 in the Y direction is, for example, 0.1 to 2.0 μm. In the present embodiment, the distance P _X and spacing P _Y, are equivalent. The interval _{P X} and spacing _{P Y,} may be different.

Each recess 21 may be formed by, for example, the following process. In the following process, each recess 21 is formed by isotropic etching.

A mask MK is formed on the main surface 19b of the polysilicon layer 19 (see (a) in FIG. 4). In the mask MK, an opening MKa is formed at a position corresponding to a region to be formed of each recess 21. The mask MK is, for example, a hard mask. The hard mask is made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ). The mask MK may be, for example, a resist mask. The resist mask is made of a resist material. FIG. 4 is a diagram showing a process of forming a plurality of depressions. In FIG. 4, hatching representing a cross section is omitted.

The polysilicon layer 19 (semiconductor substrate 11) on which the mask MK is formed is arranged in the chamber of the chemical dry etching (CDE) apparatus. Then, the polysilicon layer 19 is subjected to isotropic etching (isotropic dry etching) by the etching gas. When the etching gas reaches the polysilicon layer 19 through the opening MKa, the etching gas erodes the polysilicon layer 19 (see FIG. 4B). In this case, the etching proceeds isotropically. The region of the polysilicon layer 19 immediately below the mask MK remains unetched. As a result, a plurality of recesses 21 are formed in the polysilicon layer 19 (see (c) of FIG. 4). The surface of the recess 21 is curved. The etching gas is, for example, SF ₆ , C ₂ F ₆ , NF ₂ , or Cl _{F 3} .

After the plurality of recesses 21 are formed in the polysilicon layer 19, the mask MK is removed (see (d) in FIG. 4). The region of the polysilicon layer 19 immediately below the mask MK includes a flat surface. By removing the mask MK, the main surface 19b of the polysilicon layer 19 is exposed as a flat surface. The width of the flat surface is adjusted, for example, by the etching time. The longer the etching time, the smaller the width of the flat surface. Each recess 21 may be formed by anisotropic dry etching. In this case, the etching gas is, for example, Cl ₂ or HBr.

The semiconductor photodetector 1 includes an insulating layer 23. The insulating layer 23 is arranged on the main surface 11a except for a part of the main surface 11a included in the region R1. The semiconductor substrate 11 and the insulating layer 23 are in contact with each other. The insulating layer 23 is, for example, an oxide film. In the present embodiment, the insulating layer 23 is made of silicon oxide (SiO ₂ ). The insulating layer 23 may be made of silicon nitride (Si ₃ N ₄ ). The thickness of the insulating layer 23 is, for example, 0.2 μm.

As described above, in the first embodiment, the polysilicon layer 19 is arranged on a part of the main surface 11a included in the region R1. The polysilicon layer 19 is formed with a plurality of recesses 21 that open to the main surface 19b.
When the light is incident on the main surface 19b of the polysilicon layer 19, the light is scattered on the main surface 19b of the polysilicon layer 19 in which the plurality of recesses 21 are formed. The scattered light travels in the polysilicon layer 19 and enters the semiconductor substrate 11 from the main surface 11a. The light that has entered the semiconductor substrate 11 travels in the semiconductor substrate 11 in various directions. Therefore, in the semiconductor photodetector 1, the mileage of light in the semiconductor substrate 11 increases as compared with the configuration in which the polysilicon layer 19 is not arranged. The light incident on the semiconductor substrate 11 travels a long distance in the semiconductor substrate 11. Therefore, more light is converted into electric charge. As a result, the semiconductor photodetector 1 improves the spectral sensitivity characteristics in the near-infrared wavelength band. The semiconductor photodetector 1 also improves the spectral sensitivity characteristic in the wavelength band of visible light.

In the semiconductor photodetector 1, a plurality of recesses 21 are formed in the polysilicon layer 19. Therefore, the semiconductor substrate 11 is unlikely to suffer crystal damage due to the formation of the plurality of recesses 21. That is, the crystallinity of the semiconductor substrate 11 is unlikely to deteriorate. As a result, the semiconductor photodetector 1 suppresses the generation of dark current. In the present embodiment, since the semiconductor substrate 11 does not have a recess, the crystallinity of the semiconductor substrate 11 is less likely to deteriorate. Even when a plurality of recesses are formed on the main surface 11a of the semiconductor substrate 11, the crystallinity of the semiconductor substrate 11 is deteriorated as compared with the configuration in which the plurality of recesses are directly formed on the main surface 11a of the semiconductor substrate 11. It's hard. In the present embodiment, since the semiconductor substrate 11 does not have a recess, the crystallinity of the semiconductor substrate 11 is less likely to deteriorate.

In the semiconductor photodetector 1, as described above, a plurality of recesses 21 are formed in the polysilicon layer 19. Therefore, the semiconductor photodetector 1 suppresses the influence of the formation of the plurality of recesses 21 on the pn junction. As a result, the semiconductor photodetector 1 not only suppresses the generation of dark current, but also suppresses the deterioration of withstand voltage characteristics.

When irregular irregularities are formed on the polysilicon layer 19, the shape or size of the irregularities may differ from product to product. If the shape or size of the unevenness is different, the spectral sensitivity characteristics may vary between products.
In the semiconductor photodetector 1, the plurality of recesses 21 are formed in the polysilicon layer 19 so as to be regularly arranged. Therefore, the semiconductor photodetector 1 is unlikely to cause variations in spectral sensitivity characteristics.

The configuration in which irregular irregularities are formed on the polysilicon layer 19 makes it difficult to control the shape of the irregularities. On the other hand, the configuration in which the plurality of recesses 21 are regularly arranged makes it easy to control the shape of each recess 21. Therefore, the semiconductor photodetector 1 can easily control the optical characteristics for a specific wavelength by controlling the shape of each recess 21. The shape of the recess 21 includes the depth of the recess 21, the width of the recess 21, or the spacing of the recess 21.

In a configuration in which the second conductive type polysilicon layer 19 and the semiconductor region 13 are in contact with each other, the polysilicon layer 19 can function as an electrode. Therefore, the need to newly provide an electrode for extracting the electric charge from the semiconductor region 13 is reduced. A part of the electric charge generated in the polysilicon layer 19 may be included in the output signal. Therefore, the semiconductor photodetector 1 improves the spectral sensitivity characteristic in the near infrared wavelength band. The charge may be extracted only from the polysilicon layer 19 without newly providing an electrode for extracting the charge from the semiconductor region 13.

Even when the semiconductor substrate 11 has a semiconductor region 12b and an epitaxial semiconductor region 12a laminated on the semiconductor region 12b, the charge absorbed by the semiconductor region 12b is in the near-infrared wavelength band. It is difficult to contribute to spectral sensitivity.
The configuration in which the polysilicon layer 19 in which the plurality of recesses 21 are formed is provided on the main surface 11a reduces the electric charge generated near the main surface 11b of the semiconductor substrate 11. Since the charge absorbed by the semiconductor region 12b is reduced, the spectral sensitivity in the near-infrared wavelength band is improved.

Subsequently, a method of manufacturing the semiconductor photodetector 1 will be described.
First, a semiconductor substrate 11 having an epitaxial semiconductor region 12a and a first conductive type semiconductor region 12b is prepared.

Next, the semiconductor region 13, the semiconductor region 15, and the semiconductor region 17 are formed in the epitaxial semiconductor region 12a.
The semiconductor region 17 is formed by implanting impurities into the epitaxial semiconductor region 12a from the main surface 11a at a high concentration by using a mask having an open central portion or the like. The semiconductor region 15 is formed by diffusing impurities from the main surface 11a into the epitaxial semiconductor region 12a at a high concentration by using another mask or the like having an open peripheral portion. The semiconductor region 13 is formed by implanting impurities into the epitaxial semiconductor region 12a from the main surface 11a at a high concentration by using another mask having an open central portion or the like.

Next, the insulating layer 23 is formed on the main surface 11a of the semiconductor substrate 11. After that, the portion of the insulating layer 23 corresponding to the region to be formed of the polysilicon layer 19 is removed. The region to be formed of the polysilicon layer 19 includes the above-mentioned part of the main surface 11a included in the region R1. The insulating layer 23 is removed by etching, for example.

Next, the polysilicon layer 19 is formed on the semiconductor region 13. In this process, n-type impurities may be added to the polysilicon layer 19. After that, a plurality of recesses 21 are formed in the polysilicon layer 19. The plurality of recesses 21 are formed by isotropic etching as described above.
Through these processes, the semiconductor photodetector 1 is obtained.

Next, the configuration of the first modification of the first embodiment will be described with reference to FIG. FIG. 5 is a diagram showing a cross-sectional configuration of the semiconductor photodetector according to the first modification of the first embodiment. The first modification is generally similar to or the same as the first embodiment, but the present modification is different from the first embodiment with respect to the insulating layer 23. Hereinafter, the differences between the first embodiment and the first modification will be mainly described.

In this modification, the insulating layer 23 is also arranged on a part of the main surface 11a included in the region R1. For example, the insulating layer 23 is formed on the entire main surface 11a. The polysilicon layer 19 is arranged on the insulating layer 23. The polysilicon layer 19 is indirectly arranged on the semiconductor substrate 11 so that the insulating layer 23 is located between the semiconductor substrate 11 and the polysilicon layer 19. The semiconductor substrate 11 and the insulating layer 23 are in contact with each other, and the insulating layer 23 and the polysilicon layer 19 are in contact with each other.

In this modification, the insulating layer 23 is arranged between the semiconductor substrate 11 and the polysilicon layer 19. Therefore, the formation of the plurality of recesses 21 in the polysilicon layer 19 can be easily performed while further suppressing the influence on the semiconductor substrate 11.

Next, the configuration of the second modification of the first embodiment will be described with reference to FIG. FIG. 6 is a diagram showing a cross-sectional configuration of a semiconductor photodetector according to a second modification of the first embodiment. The second modification is generally similar to or the same as the first modification, but this modification is different from the first modification in terms of the shape of each recess 21. Hereinafter, the differences between the first modification and the second modification will be mainly described.

In this modification, as shown in FIG. 6, the plurality of recesses 21 are also open to the main surface 19a. Each recess 21 is formed so as to penetrate the polysilicon layer 19. Therefore, a part of the insulating layer 23 is exposed in the plurality of recesses 21.
When each recess 21 is formed so as to penetrate the polysilicon layer 19, the depth of each recess 21 is defined by the thickness of the polysilicon layer 19. Therefore, the depth of each recess 21 is accurately controlled. The shape of the recess 21 shown in FIG. 6 is easily realized by the insulating layer 23 made of silicon oxide functioning as an etching stop layer.

In this modification, the polysilicon layer 19 may be a first conductive type or a second conductive type. The first conductive type polysilicon layer 19 is realized, for example, by adding boron (B) to the polysilicon layer 19.

Next, the configuration of the third modification of the first embodiment will be described with reference to FIG. 7. FIG. 7 is a diagram showing a cross-sectional configuration of a semiconductor photodetector according to a third modification of the first embodiment. The third modification is generally similar to or the same as the first embodiment, but this modification is different from the first embodiment with respect to the support substrate 31. Hereinafter, the differences between the first embodiment and the third modification will be mainly described.

In this modification, as shown in FIG. 7, the semiconductor photodetector 1 includes a support substrate 31. The support substrate 31 has a main surface 31a and a main surface 31b facing each other. The support substrate 31 is arranged on the semiconductor substrate 11 so as to face the main surface 11b. The main surface 31a and the main surface 11b face each other. The support substrate 31 is, for example, a silicon substrate or a glass substrate. In this modification, the semiconductor region 12b is thinned from the main surface 11b side. A resin layer RL is arranged between the semiconductor substrate 11 and the support substrate 31. The resin layer RL is composed of, for example, a resin whose main component is any one of propylene glycol monomethyl ether acetate (PGMEA), polyethylene terephthalate (PET), and an epoxy resin. The support substrate 31 is adhered to the semiconductor substrate 11 by the resin layer RL. The resin layer RL is optically transparent. Instead of the resin layer RL, a dielectric layer may be arranged between the semiconductor substrate 11 and the support substrate 31. The dielectric layer is made of, for example, silicon oxide (SiO ₂ ).

A reflective film RF is arranged on the main surface 31a of the support substrate 31. The reflective film RF is in contact with the resin layer RL. The reflective film RF is made of, for example, metal. The reflective film RF is composed of, for example, a metal whose main component is either C aluminum (Al), silver (Ag), or gold (Au). In this modification, the support substrate 31 is indirectly arranged on the semiconductor substrate 11 in a state where the resin layer RL and the reflective film RF are located between the support substrate 31 and the semiconductor substrate 11. The reflective film RF is indirectly arranged on the semiconductor substrate 11 in a state where the resin layer RL is located between the reflective film RF and the semiconductor substrate 11. The main surface 31a and the main surface 11b indirectly face each other with the resin layer RL and the reflective film RF sandwiched between the main surface 31a and the main surface 11b.

The semiconductor region 12b may be thinned by, for example, the following process.
The temporary support substrate is temporarily bonded to the main surface 11a side of the semiconductor substrate 11 on which the

semiconductor regions

13, 15, 17, the polysilicon layer 19, and the insulating layer 23 are formed. The temporary support substrate is bonded to the semiconductor substrate 11 with an adhesive resin. After that, the semiconductor region 12b is thinned from the main surface 11b side. The thinning of the semiconductor region 12b is performed, for example, by mechanical polishing (grinding) with a grindstone, chemical mechanical polishing (CMP), or etching.
After the semiconductor region 12b is thinned, n-type impurities may be diffused to a high concentration from the main surface 11b in the semiconductor region 12b.

Next, the support substrate 31 is joined to the semiconductor substrate 11. The support substrate 31 is joined to the semiconductor substrate 11 by the resin layer RL in a state where the reflective film RF faces the main surface 11b. After that, the temporary support substrate is peeled off from the semiconductor substrate 11.
Through these processes, the semiconductor photodetector 1 shown in FIG. 7 is obtained.

In this modification, the semiconductor photodetector 1 includes a support substrate 31. The support substrate 31 improves the mechanical strength of the semiconductor photodetector 1.
The semiconductor photodetector 1 includes a reflective film RF arranged on the main surface 11b. Light traveling through the semiconductor substrate 11 and reaching the main surface 11b is incident on the reflective film RF and reflected by the reflective film RF. The light reflected by the reflective film RF further travels in the semiconductor substrate 11. Therefore, the mileage of light in the semiconductor substrate 11 is further increased, and more light is converted into electric charges. As a result, the semiconductor photodetector 1 further improves the spectral sensitivity characteristics in the near-infrared wavelength band.

As shown in FIG. 8, a plurality of recessed RFa may be formed on the surface of the reflective film RF. The plurality of recesses RFa are formed, for example, by etching the reflective film RF using a mask in which a plurality of openings are formed. The plurality of recesses RFa may be formed so as to be arranged regularly, or may be formed so as to be arranged irregularly.

In the semiconductor photodetector 1 shown in FIG. 8, the light incident on the reflective film RF is diffusely reflected by the reflective film RF in which a plurality of recesses RFa are formed. The diffusely reflected light travels in the semiconductor substrate 11 in various directions. Therefore, the mileage of light in the semiconductor substrate 11 is further increased. As a result, the semiconductor photodetector 1 further improves the spectral sensitivity characteristics in the near-infrared wavelength band.

(Second Embodiment)
The configuration of the semiconductor photodetector 2 according to the second embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is a diagram showing a cross-sectional configuration of the semiconductor photodetector according to the second embodiment. FIG. 10 is a plan view showing a semiconductor photodetector according to the second embodiment. In the second embodiment, the semiconductor photodetector 2 is, for example, a surface incident type avalanche photodiode array. In FIG. 9, hatching representing a cross section is omitted. In FIG. 10, a part of the insulating layer 63, which will be described later, has been removed.

The semiconductor light detection element 2 includes a semiconductor substrate 41. The semiconductor substrate 41 is a substrate made of silicon (Si). The semiconductor substrate 41 has a main surface 41a and a main surface 41b facing each other. The main surface 41a is a light incident surface on the semiconductor substrate 41. The main surface 41a is the front surface, and the main surface 41b is the back surface. In the present embodiment, the main surface 41a and the main surface 41b are flat surfaces. The thickness of the semiconductor substrate 41 is, for example, 100 to 625 μm. For example, when the main surface 41a constitutes the first main surface, the main surface 41b constitutes the second main surface.

The semiconductor substrate 41 has a first conductive type epitaxial semiconductor region 42a and a second conductive type semiconductor region 42c. The semiconductor region 42c constitutes the substrate of the semiconductor substrate 41. The epitaxial semiconductor region 42a is formed on the semiconductor region 42c by the epitaxial growth method. The epitaxial semiconductor region 42a is a region including the main surface 41a. The semiconductor region 42c is a region including the main surface 41b. The semiconductor region 42c is located between the epitaxial semiconductor region 42a and the main surface 41b. In the present embodiment, the semiconductor substrate 41 is composed of an epitaxial semiconductor region 42a and a semiconductor region 42c. Also in the second embodiment, the first conductive type is, for example, p type, and the second conductive type is, for example, n type. The impurity concentration in the epitaxial semiconductor region 42a is, for example, 1 × 10 ¹⁴ cm ^-3 . The semiconductor region 42c has a high impurity concentration. The impurity concentration in the semiconductor region 42c is, for example, 1 × 10 ¹⁸ cm ^-3 .

The semiconductor substrate 41 has a plurality of cells U. The plurality of cells U are arranged two-dimensionally in a matrix, for example. The plurality of cells U may be arranged one-dimensionally. In the semiconductor substrate 41, a signal corresponding to the incident light incident on each cell U is output from each cell U. Each cell U contains one or more avalanche photodiodes. In this embodiment, each cell U includes one avalanche photodiode APD. The avalanche photodiode APD may have, for example, the same configuration as the semiconductor photodetector 2 shown in the first embodiment.

The avalanche photodiode APD included in each cell U includes a semiconductor region 43 and a semiconductor region 45. The

semiconductor regions

43 and 45 are formed in the epitaxial semiconductor region 42a. The semiconductor region 43 is arranged on the main surface 41a side of the semiconductor substrate 41. The semiconductor region 43 is a region including the main surface 41a. The semiconductor region 45 is located closer to the main surface 41b than the semiconductor region 43. The semiconductor region 43 and the semiconductor region 45 are formed so as to be separated from each other. The semiconductor region 43 and the semiconductor region 45 may be formed so as to be in contact with each other.

The semiconductor region 43 is a second conductive type. The semiconductor region 45 is a first conductive type. The semiconductor region 43 and the semiconductor region 45 form a pn junction. The pn junction is formed at the boundary between the semiconductor region 43 and the semiconductor region 45. The semiconductor region 43 and the semiconductor region 45 form a light-sensitive region. The light-sensitive region is a region in which an electric charge is generated according to the incident light. The light-sensitive region also includes a region in the epitaxial semiconductor region 42a that becomes depleted when a bias voltage is applied.

Each of the

semiconductor regions

43 and 45 has a high impurity concentration. Each of the

semiconductor regions

43 and 45 has a higher impurity concentration than the epitaxial semiconductor region 42a. The impurity concentration of the semiconductor region 43 is, for example, 1 × 10 ¹⁹ cm ^-3 . The impurity concentration in the semiconductor region 45 is, for example, 1 × 10 ¹⁷ cm ^-3 . The thickness of the semiconductor region 43 is, for example, 0.5 μm. The thickness of the semiconductor region 45 is, for example, 1.5 μm.

A trench TR is formed on the semiconductor substrate 41. The trench TR is open to the main surface 41a. The depth direction of the trench TR is the thickness direction of the semiconductor substrate 41. The trench TR physically separates cells U adjacent to each other among the plurality of cells U. The trench TR surrounds each cell U when viewed from a direction orthogonal to the main surface 41a. The cells U adjacent to each other are electrically separated from each other by the trench TR. In the present embodiment, the trench TR is formed in a grid pattern on the semiconductor substrate 41 when viewed from a direction orthogonal to the main surface 41a.

A light-shielding member 53 is arranged in the trench TR. The light-shielding member 53 is made of a material that reflects light. The light-shielding member 53 may be made of a material that absorbs light. The light-shielding member 53 is made of, for example, tungsten (W). The light-shielding member 53 is formed by filling the trench TR with a material that reflects or absorbs light. The light-shielding member 53 has a surface exposed to the main surface 41a at the opening of the trench TR. The surface of the light-shielding member 53 is covered with an insulating layer 55. The light-shielding member 53 is formed in the trench TR by, for example, low-pressure chemical vapor deposition (LP-CVD).

The side surface and the bottom surface of the trench TR are composed of the semiconductor region 47. The semiconductor region 47 is a first conductive type. The semiconductor region 47 has a higher impurity concentration than the epitaxial semiconductor region 42a. The impurity concentration of the semiconductor region 47 is, for example, 1 × 10 ¹⁷ cm ^-3 . The semiconductor region 47 is formed, for example, by ion-implanting a first conductive type impurity at a high concentration from the surface of the epitaxial semiconductor region 42a exposed in the trench TR. The depth of the trench TR may be equal to or greater than the thickness of the epitaxial semiconductor region 42a.

The semiconductor substrate 41 has a semiconductor region 49. The semiconductor region 49 is formed in the epitaxial semiconductor region 42a. The semiconductor region 49 is a region including the main surface 41a. The semiconductor region 49 is arranged along the edge of the semiconductor substrate 41 so as to surround a region in which a plurality of cells U are located. The semiconductor region 49 is continuously formed so as to surround the entire region in which the plurality of cells U are located when viewed from a direction orthogonal to the main surface 41a. The semiconductor region 49 has a higher impurity concentration than the epitaxial semiconductor region 42a. The impurity concentration of the semiconductor region 49 is, for example, 1 × 10 ¹⁷ cm ^-3 .

The semiconductor region 43 and the semiconductor region 47 are separated from each other. The semiconductor region 47 is located outside the semiconductor region 43 so as to surround the semiconductor region 43 when viewed from a direction orthogonal to the main surface 41a. The semiconductor region 47 is continuously formed outside the semiconductor region 43. The semiconductor region 47 is formed in a region on the main surface 41a side of the semiconductor substrate 41 where the semiconductor region 43 is not formed.

The semiconductor substrate 41 includes a region R1 in which the

semiconductor regions

43 and 45 are formed and a region R2 in which the semiconductor region 47 is formed. Region R1 includes a part of the main surface 41a. The region R2 includes another part of the main surface 41a that is different from the part of the main surface 41a included in the region R1. The epitaxial semiconductor region 42a includes a region R1 and a region R2. For example, when the region R1 constitutes the first region, the region R2 constitutes the second region. For example, when the semiconductor region 43 constitutes the first semiconductor region, the semiconductor region 47 constitutes the second semiconductor region, the semiconductor region 45 constitutes the third semiconductor region, and the semiconductor region 42c constitutes the fourth semiconductor region. .. Each cell U includes a region R1 and a region R2.

The semiconductor light detection element 2 includes a wiring layer 61. The wiring layer 61 is arranged on the main surface 41a of the semiconductor substrate 41. The wiring layer 61 includes an insulating layer 63, a polysilicon layer 19, a plurality of connecting conductors 65, a plurality of quenching resistors 67, and a common conductor 69. The insulating layer 63 is made of a material that has electrical insulation and transmits light to be detected. The insulating layer 63 is made of, for example, silicon oxide (SiO ₂ ).

Each connecting conductor 65 is arranged in the insulating layer 63 and has one end and the other end. One end of the connecting conductor 65 is connected to the semiconductor region 43 included in the corresponding cell U among the plurality of cells U. The other end of the connecting conductor 65 is connected to the corresponding quenching resistor 67 among the plurality of quenching resistors 67. Each connecting conductor 65 electrically connects the semiconductor region 43 and the quenching resistor 67 corresponding to each other.

The quenching resistor 67 is formed in the insulating layer 63. The quenching resistor 67 is arranged along the peripheral edge of the semiconductor region 43 when viewed from a direction orthogonal to the main surface 41a. Each quenching resistor 67 has one end connected to the corresponding connecting conductor 65 and the other end electrically connected to the common conductor 69. The common conductor 69 is electrically connected to each other end of the plurality of quenching resistors 67. The common conductor 69 is electrically connected to an electrode pad 71 arranged so as to be exposed from the insulating layer 63. The electrode pad 71 is electrically connected to the semiconductor region 43 included in each cell U through a common conductor 69, each quenching resistor 67, and each connection conductor 65. The plurality of cells U are electrically connected in parallel through the common conductor 69. A bonding wire configured to take out a signal is connected to the electrode pad 71, for example. The semiconductor region 43 constitutes a cathode in an avalanche photodiode APD.

The wiring layer 61 includes a conducting wire 73 that is electrically connected to the semiconductor region 49. The conductor 73 is electrically connected to an electrode pad 75 that is arranged so as to be exposed from the insulating layer 63. The conductor 73 has one end that is electrically connected to the semiconductor region 49 and the other end that is electrically connected to the electrode pad 75. A bonding wire configured to apply a bias voltage is connected to the electrode pad 75, for example. The electrode pad 75 is electrically connected to the epitaxial semiconductor region 42a through the conducting wire 73 and the semiconductor region 49. The semiconductor region 49 constitutes an anode in an avalanche photodiode APD.

Each of the conducting

wires

65, 69, 73 and each of the

electrode pads

71, 75 is made of, for example, a metal material. The

conductors

65, 69, 73 and the

electrode pads

71, 75 are made of, for example, aluminum (Al), copper (Cu), titanium (Ti), nickel (Ni), gold (Au), or platinum (Pt). .. The quenching resistor 67 is made of a material having a higher electrical resistance than the metal material constituting each of the conducting

wires

65, 69, 73 and each of the

electrode pads

71, 75. The quenching resistor 67 is made of, for example, silicon chromium (SiCr), polysilicon, nickel chromium (NiCr), or ferrochrome (FeCr).

In the semiconductor photodetector 2, the polysilicon layer 19 is arranged in the insulating layer 63. The polysilicon layer 19 is in contact with the insulating layer 63. The polysilicon layer 19 is arranged on the semiconductor substrate 41 so that the main surface 19a faces the main surface 41a. The polysilicon layer 19 is indirectly arranged on the semiconductor substrate 41 so that a part of the insulating layer 63 is located between the semiconductor substrate 41 and the polysilicon layer 19. The above-mentioned part of the insulating layer 63 exists between the polysilicon layer 19 and the semiconductor substrate 41, and the polysilicon layer 19 is not in contact with the semiconductor substrate 41. The polysilicon layer 19 may be in contact with the semiconductor substrate 41. The polysilicon layer 19 is arranged on a part of the main surface 41a included in the region R1. The polysilicon layer 19 is arranged on the semiconductor region 43.

As shown in FIG. 10, the polysilicon layer 19 is located inside the quenching resistor 67 when viewed from the direction orthogonal to the main surface 41a. The polysilicon layer 19 is separated from the quenching resistor 67. The polysilicon layer 19 is not arranged on another part of the main surface 41a included in the region R2. The polysilicon layer 19 is not located on the trench TR. The semiconductor region 43 has a region to which the connecting conductor 65 is connected. The polysilicon layer 19 is located so as to overlap the semiconductor region 43 when viewed from the direction orthogonal to the main surface 41a, except for the region to which the connecting conductor 65 is connected. The polysilicon layer 19 is separated from the semiconductor region 43. In the semiconductor photodetector 2, the polysilicon layer 19 is electrically insulated from the semiconductor region 43 and the polysilicon layer 19.

When the quenching resistor 67 is made of polysilicon, impurities may be added to the polysilicon constituting the quenching resistor 67 in order to adjust the resistance value of the quenching resistor 67. When the quenching resistor 67 and the polysilicon layer 19 are formed at the same time, the same impurities as those added to the polysilicon layer 19 may be added to the polysilicon layer 19. Impurities may not be added to the polysilicon layer 19. The impurities are, for example, phosphorus (P) or boron (B). The quenching resistor 67 and the polysilicon layer 19 may be formed individually.

The polysilicon layer 19 may be formed so as to be in contact with the semiconductor substrate 41 (semiconductor region 43). In this case, impurities may not be added to the polysilicon layer 19.

A plurality of recesses 21 are formed in the polysilicon layer 19 as in each polysilicon layer 19 included in the semiconductor photodetector 1. Since the above-mentioned part of the insulating layer 63 exists between the polysilicon layer 19 and the semiconductor substrate 41, each recess 21 may penetrate the polysilicon layer 19.

As described above, in the second embodiment, the polysilicon layer 19 is arranged on a part of the main surface 41a included in the region R1. The polysilicon layer 19 is formed with a plurality of recesses 21 that open to the main surface 19b.
When the light is incident on the main surface 19b of the polysilicon layer 19, the light is scattered on the main surface 19b of the polysilicon layer 19 in which the plurality of recesses 21 are formed. The scattered light travels in the polysilicon layer 19 and enters the semiconductor substrate 41 from the main surface 41a. The light that has entered the semiconductor substrate 41 travels in the semiconductor substrate 41 in various directions. Therefore, in the semiconductor photodetector 2, the mileage of light in the semiconductor substrate 41 is increased as compared with the configuration in which the polysilicon layer 19 is not arranged. The light incident on the semiconductor substrate 41 travels a long distance in the semiconductor substrate 41. Therefore, more light is converted into electric charge. As a result, the semiconductor photodetector 2 improves the spectral sensitivity characteristics in the near-infrared wavelength band. The semiconductor photodetector 2 also improves the spectral sensitivity characteristic in the wavelength band of visible light.

In the semiconductor light detection element 2, as in the semiconductor light detection element 1, a plurality of recesses 21 are formed in the polysilicon layer 19. Therefore, as described above, the semiconductor photodetector 2 suppresses the generation of dark current and suppresses the deterioration of withstand voltage characteristics. Even in this embodiment, since the semiconductor substrate 41 does not have a recess, the crystallinity of the semiconductor substrate 41 is less likely to deteriorate.

When a plurality of recesses 21 are formed in the polysilicon layer 19 so as to be regularly arranged, as described above, the semiconductor photodetector 2 is unlikely to cause variations in spectral sensitivity characteristics. The semiconductor photodetector 2 can also easily control the optical characteristics for a specific wavelength by controlling the shape of each recess 21.

In the configuration in which a plurality of depressions are formed on the main surface 41b of the semiconductor substrate 41, when the light traveling in the semiconductor substrate 41 reaches the region where the plurality of depressions are formed, the light is formed with the plurality of depressions. It is diffusely reflected in the area where it is. In this case, the diffusely reflected light may enter the adjacent cells U without being blocked by the trench TR, and optical crosstalk may occur between the adjacent cells U.
In the semiconductor photodetector 2, the polysilicon layer 19 in which a plurality of recesses 21 are formed is arranged on the main surface 41a, and the polysilicon layer 19 is relatively close to the pn junction. Therefore, even when the light is scattered by the polysilicon layer 19, the spread of the light is relatively small. As a result, the semiconductor photodetector 2 is unlikely to cause the above-mentioned optical crosstalk. In the semiconductor photodetector 2, the trench TR is formed on the semiconductor substrate 41 from the main surface 41a. Therefore, the semiconductor photodetector 2 is less likely to cause optical crosstalk on the main surface 41a side.

When it is stated in the specification that an element is placed on another element, the element may be placed directly on the other element or indirectly placed on the other element. It may have been done. When an element is indirectly placed on another element, an intervening element exists between one element and another. If one element is placed directly on top of another, the intervening element does not exist between one element and another.
When it is described herein that an element is located on another element, the element may be located directly on the other element or indirectly on the other element. You may be doing it. When an element is indirectly located on another element, an intervening element exists between one element and another. If one element is located directly on another, the intervening element does not exist between one element and another.

Although the embodiments of the present invention have been described above, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.

The plurality of recesses 21 may be formed so as to be irregularly arranged in the polysilicon layer 19. The fact that a plurality of dents 21 are formed so as to be irregularly means that the distance between the deepest positions of the dents 21 adjacent to each other is irregularly changed, and that the depth of the dents 21 is irregularly changed. Includes at least one of what you are doing. A configuration in which the plurality of recesses 21 are formed so as to be irregularly arranged can be realized, for example, by forming the recesses 21 as follows. The polysilicon layer 19 is etched using masks in which the positions and sizes of the openings are irregularly different.

The plurality of recesses 21 may include recesses having different depths.
For example, the plurality of depressions 21 may include a plurality of first depressions having a first depth and a plurality of second depressions having a second depth larger than the first depth. In this case, the width of the first recess and the width of the second recess may be different. When the plurality of recesses 21 include the plurality of first recesses and the plurality of second recesses, the plurality of first recesses and the plurality of second recesses are formed so as to be regularly arranged. For example, the plurality of first depressions and the plurality of second depressions may be alternately located. For example, the region where the first depression of the first number is continuously located and the region where the second depression of the second number is continuously located may be alternately located. The first number is a value greater than or equal to "2", and the second number is greater than the first number.
For example, the plurality of depressions 21 may include a plurality of depressions having different depths.

In the semiconductor photodetector elements 1 and 2, the p-type and n-type conductive types may be interchanged so as to be opposite to the above-mentioned conductive type.

The present specification discloses the following additional notes.
(Appendix 1)
A silicon substrate having a pn junction composed of a first conductive type semiconductor region and a second conductive type semiconductor region,
A support substrate arranged so as to face the silicon substrate is provided.
A semiconductor photodetector element characterized in that a plurality of recesses are regularly arranged on a surface of the support substrate facing the silicon substrate.

Appendix 1 above includes the following plurality of aspects. In each of the following embodiments, the same reference numerals are used for the same elements or elements having the same function, and duplicate description will be omitted. Each aspect is generally similar to or the same as the semiconductor photodetector described in Patent Document 1.

The semiconductor photodetector shown in FIG. 11 includes a silicon substrate 101 and a support substrate 111. This semiconductor photodetector is, for example, a front-mounted or back-mounted photodiode.

The silicon substrate 101 has a main surface 101a and a main surface 101b that face each other. The main surface 101a and the main surface 101b are flat surfaces. The silicon substrate 101 has a first conductive type semiconductor region 103 and a second conductive type semiconductor region 105. The semiconductor region 103 and the semiconductor region 105 form a pn junction. Therefore, the silicon substrate 101 has a pn junction. The silicon substrate 101 has a first conductive type semiconductor region 107. The semiconductor region 107 is located outside the semiconductor region 105 so as to surround the semiconductor region 105 when viewed from a direction orthogonal to the main surface 101a. The semiconductor photodetector includes an insulating film 109 arranged on the main surface 101a of the silicon substrate 101. The semiconductor photodetector includes an electrode E1 that is electrically connected to the semiconductor region 105 and an electrode E2 that is electrically connected to the semiconductor region 107.

The silicon substrate 101 has an accumulation layer 108. The accumulation layer 108 is arranged on the main surface 101b side of the silicon substrate 101. The surface of the accumulation layer 108 constitutes the main surface 101b. The accumulation layer 108 is the same conductive type as the semiconductor region 103. The impurity concentration of the accumulation layer 108 is higher than the impurity concentration of the semiconductor region 103.

The support substrate 111 has a main surface 111a and a main surface 111b facing each other. The support substrate 111 is arranged on the silicon substrate 101 so as to face the main surface 101b. The main surface 111a faces the silicon substrate 101 (main surface 101b). A resin layer 113 is arranged between the silicon substrate 101 and the support substrate 111. The support substrate 111 is adhered to the silicon substrate 101 by the resin layer 113. The resin layer 113 is optically transparent.

A plurality of recesses 121 are formed on the main surface 111a. The plurality of recesses 121 are formed in 111a so as to be regularly arranged. The surface of each recess 121 may include, for example, a plurality of inclined surfaces. The surface of each recess 121 may be curved, for example. The plurality of recesses 121 may be formed by, for example, an etch. The plurality of recesses 121 may be formed, for example, by an isotropic etch. The plurality of recesses 121 may be formed, for example, by anisotropic etching. Light incident on a region where a plurality of depressions 121 are formed is diffusely reflected or scattered in the region. Therefore, the mileage of light in the silicon substrate 101 increases. The semiconductor photodetector shown in FIG. 11 improves the spectral sensitivity characteristics in the near infrared wavelength band. The plurality of recesses 121 may be formed so as to be arranged irregularly.

The semiconductor photodetector shown in FIG. 12 includes a silicon substrate 131 and a support substrate 111. This semiconductor photodetector is, for example, a front-mounted or back-mounted avalanche photodiode.

The silicon substrate 131 has a main surface 131a and a main surface 131b facing each other. The main surface 131a and the main surface 131b are flat surfaces. The silicon substrate 131 has a first conductive type semiconductor region 133, a second conductive type semiconductor region 135, a first conductive type semiconductor region 137, and a first conductive type semiconductor region 139. .. The semiconductor region 135 and the semiconductor region 137 form a pn junction. Therefore, the silicon substrate 131 has a pn junction. When viewed from the direction orthogonal to the main surface 101a, the semiconductor region 139 is located outside the semiconductor region 135 so as to surround the semiconductor region 135. The semiconductor photodetector includes an insulating film 140 arranged on the main surface 131a of the silicon substrate 131. The semiconductor photodetector includes an electrode E11 electrically connected to the semiconductor region 135 and an electrode E21 electrically connected to the semiconductor region 139.

The silicon substrate 131 has an accumulation layer 138. The accumulation layer 138 is arranged on the main surface 131b side of the silicon substrate 131. The surface of the accumulation layer 138 constitutes the main surface 131b. The accumulation layer 138 is the same conductive type as the semiconductor region 133. The impurity concentration of the accumulation layer 138 is higher than the impurity concentration of the semiconductor region 133.

The support substrate 111 is arranged on the silicon substrate 131 so as to face the main surface 131b. The main surface 111a faces the silicon substrate 131 (main surface 131b). A resin layer 113 is arranged between the silicon substrate 131 and the support substrate 111. The support substrate 111 is adhered to the silicon substrate 131 by the resin layer 113.
A plurality of recesses 121 are formed on the main surface 111a of the support substrate 111. As described above, the light incident on the region where the plurality of depressions 121 are formed is diffusely reflected or scattered in the region. Therefore, the mileage of light in the silicon substrate 131 increases. The semiconductor photodetector shown in FIG. 12 improves the spectral sensitivity characteristics in the near infrared wavelength band.

The semiconductor photodetector shown in FIG. 13 includes a silicon substrate 141 and a support substrate 111. This semiconductor photodetector is, for example, a front-mounted or back-mounted avalanche photodiode array.

The silicon substrate 141 has a main surface 141a and a main surface 141b facing each other. The silicon substrate 141 has a first conductive type semiconductor layer 143, a second conductive type semiconductor layer 145, and a second conductive type plurality of semiconductor regions 147. The semiconductor layer 143 and the semiconductor layer 145 form a pn junction. Therefore, the silicon substrate 141 has a pn junction. The silicon substrate 141 has a first conductive type separating portion 149 that separates the semiconductor layer 145. The semiconductor photodetector includes an insulating film 151 arranged on the main surface 141a of the silicon substrate 141. The semiconductor photodetector includes a plurality of connecting conductors 153 and a plurality of resistors 155 arranged on the insulating film 151. The semiconductor layer 145 and the resistor 155 corresponding to each other are connected to each other via the connecting conductor 153. Each resistor 155 is connected to a common conductor (not shown). Each semiconductor layer 145 is electrically connected in parallel through a corresponding connecting wire 153, a corresponding resistor 155, and a common wire.

The support substrate 111 is arranged on the silicon substrate 141 so as to face the main surface 141b. The main surface 111a faces the silicon substrate 141 (main surface 141b). A resin layer 113 is arranged between the silicon substrate 141 and the support substrate 111. The support substrate 111 is adhered to the silicon substrate 131 by the resin layer 113.
A plurality of recesses 121 are formed on the main surface 111a of the support substrate 111. As described above, the light incident on the region where the plurality of depressions 121 are formed is diffusely reflected or scattered in the region. Therefore, the mileage of light in the silicon substrate 141 increases. The semiconductor photodetector shown in FIG. 13 improves the spectral sensitivity characteristics in the near infrared wavelength band.

The semiconductor photodetector shown in FIG. 14 includes a silicon substrate 161 and a support substrate 111. This semiconductor photodetector is, for example, a front-side incident type or back-side incident type solid-state image sensor.

The silicon substrate 161 has a main surface 161a and a main surface 161b that face each other. The silicon substrate 161 has a first conductive type semiconductor region 163 and a second conductive type semiconductor region 165. The semiconductor region 163 and the semiconductor region 165 form a pn junction. Therefore, the silicon substrate 161 has a pn junction. The semiconductor photodetector includes an insulating film 167 arranged on the main surface 161a of the silicon substrate 161 and a plurality of charge transfer electrodes 169 arranged on the insulating film 167.

The silicon substrate 161 has an accumulation layer 168. The accumulation layer 168 is arranged on the main surface 161b side of the silicon substrate 161. The surface of the accumulation layer 168 constitutes the main surface 161b. The accumulation layer 168 is the same conductive type as the semiconductor region 163. The impurity concentration of the accumulation layer 168 is higher than the impurity concentration of the semiconductor region 163.

The support substrate 111 is arranged on the silicon substrate 161 so as to face the main surface 161b. The main surface 111a faces the silicon substrate 161 (main surface 161b). A resin layer 113 is arranged between the silicon substrate 161 and the support substrate 111. The support substrate 111 is adhered to the silicon substrate 161 by the resin layer 113.
A plurality of recesses 121 are formed on the main surface 111a of the support substrate 111. As described above, the light incident on the region where the plurality of depressions 121 are formed is diffusely reflected or scattered in the region. Therefore, the mileage of light in the silicon substrate 161 increases. The semiconductor photodetector shown in FIG. 14 improves the spectral sensitivity characteristics in the near infrared wavelength band.

The present invention can be used for a semiconductor photodetector element provided with a silicon substrate.

1,2 ... Semiconductor photodetector, 11,41 ... Semiconductor substrate, 11a, 11b, 41a, 41b ... Main surface, 12a, 42a ... Epitaxial semiconductor region, 12b, 13, 15, 17, 42c, 43, 45, 47 ... Semiconductor region, 19 ... Polysilicon layer, 19a, 19b ... Main surface, 21 ... Depression, 23 ... Insulation layer, 31 ... Support substrate, R1, R2 ... Region included in semiconductor substrate, RF ... Reflective film, TR ... Trench , U ... cell.

Claims

It is a semiconductor photodetector
A first conductive silicon substrate having a first main surface and a second main surface facing each other,
A polysilicon layer having a third main surface and a fourth main surface facing each other and arranged on the silicon substrate so that the third main surface faces the first main surface. And with
The silicon substrate is
A first region including a part of the first main surface and forming a second conductive type first semiconductor region,
Including another part of the first main surface and a second region in which a first conductive type second semiconductor region is formed.
The polysilicon layer is arranged on the part of the first main surface included in the first region.
The polysilicon layer is formed with a plurality of recesses that open to the fourth main surface.
The semiconductor photodetector according to claim 1.
In the first region, a first conductive type third semiconductor region having a higher impurity concentration than the silicon substrate contained in the first region is formed closer to the second main surface than the first semiconductor region. Has been done.
The semiconductor photodetector according to claim 2.
The silicon substrate is
A first conductive type epitaxial semiconductor region including the first region and the second region,
It is located between the second main surface and the epitaxial semiconductor region, and has a first conductive type fourth semiconductor region having a higher impurity concentration than the epitaxial semiconductor region.
The semiconductor photodetector according to any one of claims 1 to 3.
The plurality of recesses are formed in the polysilicon layer so as to be regularly arranged.
The semiconductor photodetector according to any one of claims 1 to 4.
The polysilicon layer is a second conductive type and has a second conductive type.
The first semiconductor region and the polysilicon layer are in contact with each other.
The semiconductor photodetector according to any one of claims 1 to 5.
An insulating layer arranged between the silicon substrate and the polysilicon layer is further provided.
The semiconductor photodetector according to claim 6.
The plurality of depressions are also open to the third main surface.
A part of the insulating layer is exposed in the plurality of recesses.
The semiconductor photodetector according to any one of claims 1 to 7.
Each surface of the plurality of depressions is curved.
The semiconductor photodetector according to any one of claims 1 to 8.
The plurality of recesses are formed by isotropic etching.
The semiconductor photodetector according to any one of claims 1 to 9.
It further includes a reflective film arranged on the second main surface.
The semiconductor photodetector according to any one of claims 1 to 10.
Further, a support substrate arranged so as to face the second main surface is provided.
The semiconductor photodetector according to any one of claims 1 to 11.
The silicon substrate has a plurality of cells including the first region and the second region, respectively.
The plurality of cells are electrically connected in parallel.
The semiconductor photodetector according to claim 12.
On the silicon substrate, trenches for physically separating cells adjacent to each other among the plurality of cells are formed in a grid pattern when viewed from a direction orthogonal to the first main surface.
The polysilicon layer is not located on the trench.